Display panel and display apparatus

Abstract

A display panel (PNL) and a display apparatus, relating to the technical field of display. The display panel (PNL) comprises a base substrate (SBT), a driving layer (DRL), and a pixel layer (PIXL) which are arranged in a stacked manner. The display panel (PNL) is provided with a plurality of sub-circuit areas (PDCAs) distributed in an array in a display area (AA). The driving layer (DRL) is provided with a pixel driving circuit (PDC) for driving sub-pixels (PIXs) in each sub-circuit area (PDCA). The ratio of the size of each sub-circuit area (PDCA) in the row direction (DH) to the size thereof in the column direction (DV) is not less than 3:4. Thus, the PPI of the display panel (PNL) can be improved.

Description

Display panel and display device

[0001] Cross-references

[0002] This disclosure claims priority to Chinese patent application number 202410046904.1, filed on January 11, 2024, entitled “Display Panel and Display Device,” and the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0004] In recent years, the metaverse has grown rapidly, and AR (Augmented Reality) and VR (Virtual Reality) have become key technology drivers and have become a hot topic. As near-eye displays, AR / VR require optimization of display algorithms and higher pixel density requirements for achieving higher clarity, enhanced visual quality, and a more immersive experience.

[0005] Currently, LCD (liquid crystal display) type display devices used for AR / VR can achieve more than 1500PPI. OLED / MLED have better performance in response time, brightness, etc., but due to their driving principle, Vth (threshold voltage of the driving transistor) compensation is usually required. Conventional methods include internal compensation circuits (such as 7T1C) and external compensation circuits (such as 3T1C). Due to the demand for high PPI, the size of a single pixel is constantly compressed. The internal compensation circuit is difficult to meet the requirements due to the large number of devices. The external compensation circuit is also difficult to increase PPI (Pixel Per Inch, PPI for short, pixels per inch) under the current glass-based / PI-based process capabilities.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0007] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art, provide a display panel and a display device, and improve PPI.

[0008] According to one aspect of the present disclosure, there is provided a display panel comprising a base substrate, a driving layer, and a pixel layer stacked in layers;

[0009] The display panel is provided with a plurality of sub-circuit areas distributed in an array in the display area;

[0010] The driving layer is provided with a pixel driving circuit for driving a sub-pixel in each sub-circuit area;

[0011] The ratio of the size of the sub-circuit area in the row direction to the size in the column direction is not less than 3:4.

[0012] In an example of the present disclosure, the sub-circuit areas constitute a circuit area distributed in an array, and each circuit area includes six sub-circuit areas; the six pixel driving circuits in the six sub-circuit areas respectively drive the sub-pixels of two pixels.

[0013] In an example of the present disclosure, the ratio of the size of the sub-circuit area in the row direction to the size in the column direction is equal to 3:4.

[0014] In an example of the present disclosure, the six sub-circuit areas in the circuit area are arranged in three rows and two columns.

[0015] In an example of the present disclosure, the pixel layer has six adjacent pixel electrodes in the circuit area, and the six pixel electrodes are electrically connected to the six pixel driving circuits in the circuit area in a one-to-one correspondence;

[0016] The six pixel electrodes in the circuit area are arranged in two rows and three columns;

[0017] Alternatively, the six pixel electrodes in the circuit area are arranged in three rows and two columns.

[0018] In an example of the present disclosure, the ratio of the size of the sub-circuit area in the row direction to the size in the column direction is equal to 4:3.

[0019] In an example of the present disclosure, the six sub-circuit areas in the circuit area are arranged in two rows and three columns.

[0020] In an example of the present disclosure, the pixel layer is provided with six pixel electrodes in the circuit area, and the six pixel electrodes are electrically connected to the six pixel driving circuits in the circuit area in a one-to-one correspondence;

[0021] The six pixel electrodes in the circuit area are arranged in a row and six columns;

[0022] Alternatively, the six pixel electrodes in the circuit area are arranged in two rows and three columns.

[0023] In an example of the present disclosure, the sub-circuit areas located in the same column are arranged in a staggered manner.

[0024] In one example of the present disclosure, the pixel driving circuit includes a data writing transistor, a sensing transistor, a driving transistor, and a storage capacitor;

[0025] The first electrode of the data writing transistor is used to load a data voltage, and the second electrode of the data writing transistor, the gate of the driving transistor, and the first electrode plate of the storage capacitor are electrically connected; the gate of the data writing transistor is used to load a scan signal;

[0026] The first electrode of the sensing transistor is used to load a reference voltage, and the second electrode of the sensing transistor, the second electrode plate of the storage capacitor, the pixel electrode of the sub-pixel, and the first electrode of the driving transistor are electrically connected; the gate of the sensing transistor is used to load the scanning signal;

[0027] The second electrode of the driving transistor is used to apply a driving voltage.

[0028] In one example of the present disclosure, the driving layer includes a semiconductor layer, and the semiconductor layer includes an active layer of the data writing transistor, an active layer of the sensing transistor, and an active layer of the driving transistor;

[0029] Any two of the active layer of the data write transistor, the active layer of the sensing transistor, and the active layer of the driving transistor are located in the same row.

[0030] In one example of the present disclosure, the active layer of the data writing transistor and the active layer of the sensing transistor are arranged along a row direction, and the active layer of the driving transistor and the active layer of the sensing transistor are arranged along a column direction;

[0031] There is a gap between the orthographic projection of the active layer of the driving transistor in the row direction and the orthographic projection of the active layer of the data writing transistor in the row direction;

[0032] A gap is formed between an orthographic projection of the active layer of the driving transistor in the column direction and an orthographic projection of the active layer of the sensing transistor in the column direction.

[0033] In an example of the present disclosure, the length direction of the active layer of the data writing transistor, the length direction of the active layer of the driving transistor, and the length direction of the active layer of the sensing transistor are all column directions.

[0034] In an example of the present disclosure, the length direction of the active layer of the data writing transistor is the column direction, and the length directions of the active layers of the driving transistor and the sensing transistor are both the row directions.

[0035] In an example of the present disclosure, the driving layer further includes a gate layer, the gate layer being provided with a scan line for loading the scan signal, and a first electrode plate of the storage capacitor being provided as a gate of the driving transistor;

[0036] The orthographic projections of the active layer of the data writing transistor and the active layer of the sensing transistor on the gate layer are completely located within the scanning line;

[0037] The orthographic projection of the active layer of the driving transistor on the first electrode plate of the storage capacitor is completely located within the first electrode plate of the storage capacitor.

[0038] In one example of the present disclosure, the driving layer further includes a semiconductor layer, a first source-drain metal layer, and a second source-drain metal layer located on a side of the gate layer away from the base substrate;

[0039] The second source-drain metal layer has a conductive portion, which serves as a second electrode plate of the storage capacitor and is arranged to overlap with the first electrode plate of the storage capacitor.

[0040] According to another aspect of the present disclosure, a display device is provided, including the above-mentioned display panel.

[0041] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0043] FIG1 is a schematic diagram of a display panel structure in one embodiment of the present disclosure.

[0044] FIG2 is a schematic diagram of the layer structure of a display panel in one embodiment of the present disclosure.

[0045] FIG3 is a schematic diagram of the layer structure of a display panel in one embodiment of the present disclosure.

[0046] FIG4 is a schematic structural diagram of a pixel layer in one embodiment of the present disclosure.

[0047] FIG5 is a schematic structural diagram of a pixel layer in one embodiment of the present disclosure.

[0048] FIG6 is a schematic diagram showing the arrangement principle of a pixel driving circuit in the first related technology disclosed in the present invention.

[0049] FIG7 is a schematic structural diagram of a display panel in a pixel area in the first related technology disclosed in the present invention.

[0050] FIG8 is a schematic diagram showing the arrangement principle of a pixel driving circuit in the second related technology disclosed in the present invention.

[0051] FIG9 is a schematic structural diagram of a display panel in a pixel area in a second related technology disclosed in the present invention.

[0052] FIG10 is a schematic diagram of an equivalent circuit of a pixel driving circuit in one embodiment of the present disclosure.

[0053] FIG11 is a schematic diagram showing the arrangement principle of a pixel driving circuit in one embodiment of the present disclosure.

[0054] FIG12 is a schematic structural diagram of a display panel in a pixel area in one embodiment of the present disclosure.

[0055] FIG13 is a schematic diagram of the membrane structure of the driving layer in one embodiment of the present disclosure.

[0056] FIG14 is a schematic diagram of a partial structure of a display panel at a gate layer in one embodiment of the present disclosure.

[0057] FIG15 is a schematic diagram of a partial structure of a display panel at a semiconductor layer in one embodiment of the present disclosure.

[0058] FIG16 is a schematic diagram of a partial structure of a display panel at the first source / drain metal layer in one embodiment of the present disclosure.

[0059] FIG17 is a schematic diagram of a partial structure of a display panel where a first source / drain metal layer and a semiconductor layer overlap, in one embodiment of the present disclosure.

[0060] FIG18 is a schematic diagram of a partial structure of a display panel at the second source-drain metal layer in one embodiment of the present disclosure.

[0061] FIG19 is a schematic diagram of a partial structure of a display panel at the third source / drain metal layer in one embodiment of the present disclosure.

[0062] FIG20 is a schematic diagram showing the arrangement principle of a pixel driving circuit in one embodiment of the present disclosure.

[0063] FIG21 is a schematic structural diagram of a display panel in a pixel area in one embodiment of the present disclosure.

[0064] FIG22 is a schematic diagram of the membrane structure of the driving layer in one embodiment of the present disclosure.

[0065] FIG23 is a schematic diagram of a partial structure of a display panel at a gate layer in one embodiment of the present disclosure.

[0066] FIG24 is a schematic diagram of the local structure of the semiconductor layer of the display panel in one embodiment of the present disclosure.

[0067] FIG25 is a schematic diagram of the partial structure of the display panel at the first source-drain metal layer in one embodiment of the present disclosure.

[0068] FIG26 is a schematic diagram of a partial structure of a display panel where the first source / drain metal layer and the semiconductor layer overlap, in one embodiment of the present disclosure.

[0069] FIG27 is a schematic diagram of the partial structure of the display panel at the second source / drain metal layer in one embodiment of the present disclosure.

[0070] FIG28 is a schematic diagram of the local structure of the display panel at the third source / drain metal layer in one embodiment of the present disclosure.

[0071] FIG29 is a schematic diagram showing the arrangement principle of a pixel driving circuit in one embodiment of the present disclosure.

[0072] FIG30 is a schematic diagram of the arrangement principle of a pixel driving circuit in one embodiment of the present disclosure.

[0073] FIG31 is a schematic diagram of the arrangement principle of a pixel driving circuit in one embodiment of the present disclosure.

[0074] FIG32 is a schematic diagram of the arrangement principle of the pixel driving circuit in one embodiment of the present disclosure.

[0075] FIG33 is a schematic diagram of the anode arrangement structure in one embodiment of the present disclosure.

[0076] FIG34 is a schematic diagram of the anode arrangement structure in one embodiment of the present disclosure.

[0077] FIG35 is a schematic diagram of the anode arrangement structure in one embodiment of the present disclosure.

[0078] FIG36 is a schematic diagram of the anode arrangement structure in one embodiment of the present disclosure.

[0079] FIG37 is a schematic diagram of the anode arrangement structure in one embodiment of the present disclosure.

[0080] FIG38 is a schematic diagram of the anode arrangement structure in one embodiment of the present disclosure.

[0081] FIG39 is a schematic diagram of the anode arrangement structure in one embodiment of the present disclosure.

[0082] FIG40 is a schematic diagram of the anode arrangement structure in one embodiment of the present disclosure.

[0083] FIG41 is a schematic diagram of the anode arrangement structure in one embodiment of the present disclosure.

[0084] FIG42 is a schematic diagram of the anode arrangement structure in one embodiment of the present disclosure.

[0085] FIG43 is a schematic diagram of the membrane structure of the driving layer in one embodiment of the present disclosure.

[0086] FIG44 is a schematic diagram of the arrangement principle of the pixel driving circuit in one embodiment of the present disclosure.

[0087] FIG45 is a schematic diagram of the arrangement principle of the pixel driving circuit in one embodiment of the present disclosure.

[0088] FIG46 is a schematic diagram of the anode arrangement structure in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0089] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0090] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0091] The terms "a", "an", "the", and "said" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second", and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0092] Structural layer A is located on the side of structural layer B facing away from the base substrate, which means that structural layer A is formed on the side of structural layer B facing away from the base substrate. When structural layer B is a patterned structure, part of the structure of structural layer A may also be located at the same physical height as structural layer B or lower than the physical height of structural layer B, wherein the base substrate serves as a height reference.

[0093] A transistor refers to an element that includes at least three terminals: a gate, a drain, and a source. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. The channel region refers to the region where the current mainly flows. In the embodiment of the present disclosure, when using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source" and the "drain" are sometimes interchanged, that is, the "source" and the "drain" can be interchanged. In the embodiment of the present disclosure, for any transistor, one of the "source" and the "drain" is referred to as the first pole of the transistor, and the other is referred to as the second pole of the transistor.

[0094] In an embodiment of the present disclosure, a thin film transistor (TFT) includes an active layer, a gate insulating layer and a gate that are stacked. The active layer is located in the semiconductor layer, and the active layer includes a channel region and a source and a drain located on both sides of the channel region. The channel region maintains semiconductor properties, and the source and the drain are both conductive. In an embodiment of the present disclosure, when using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source" and the "drain" are sometimes interchanged, that is, the "source" and the "drain" can be interchanged. In an embodiment of the present disclosure, for any transistor, one of the "source" and the "drain" is referred to as the first electrode of the transistor, and the other is referred to as the second electrode of the transistor.

[0095] In the present disclosure, the length direction of the active layer refers to the arrangement direction of the source region, the channel region and the drain region.

[0096] In the present disclosure, when describing the overlapping arrangement of structure C and structure D, it means that structure C and structure D are respectively in different film layers, but the orthographic projection of structure C on the substrate and the orthographic projection of structure D on the substrate at least partially overlap.

[0097] The present disclosure provides a display panel and a display device using the same, which improves the pixel driver circuit arrangement and optimizes the layout and wiring to improve the pixel pixel intensity (PPI). Referring to FIG1 , the display panel PNL includes a display area AA and a peripheral area BB located on at least one side of the display area AA. Within the display area AA, the display panel PNL is provided with an array of display units UU, each including sub-pixels PIX and pixel driver circuits PDC that drive the sub-pixels PIX. The display panel PNL does not have display units UU in the peripheral area BB, or the provided display units UU are not used for displaying images.

[0098] Referring to FIG. 1 , the display panel PNL is provided with a plurality of scan lines GL extending along the row direction DH in the display area AA, and each scan line GL is provided in a one-to-one correspondence with each display unit row. The pixel driving circuit PDC of each display unit UU in the display unit row is electrically connected to the corresponding scan line GL, and the scan line GL is used to load a scan signal to the pixel driving circuit PDC. The display panel PNL is also provided with a plurality of data lines DL extending along the column direction DV in the display area AA, and each data line DL is provided in a one-to-one correspondence with each display unit column. The pixel driving circuit PDC of each display unit UU in the display unit column is electrically connected to the corresponding data line DL, and the data line DL is used to load a data voltage VDA to the pixel driving circuit PDC. In this way, the pixel driving circuit PDC of each display unit UU is connected to one scan line GL and one data line DL. When a scan signal is loaded on the scan line GL, the voltage loaded on the data line DL can be written into the pixel driving circuit PDC, thereby enabling the pixel driving circuit PDC to control the brightness of the sub-pixel PIX according to the written voltage.

[0099] In one disclosed embodiment, the display panel PNL is further provided with a plurality of sensing traces extending along a column direction DV. The pixel driver circuit PDC of each display unit UU in the display unit row is electrically connected to a corresponding sensing trace. The sensing trace is configured to transmit a sensing signal to the pixel driver circuit PDC. Optionally, in certain operating states, the sensing trace may also apply a reference voltage to the pixel driver circuit PDC.

[0100] In one disclosed embodiment, the display panel PNL is further provided with drive voltage traces extending in the row direction DH. The pixel drive circuit PDC of each display unit UU in the display unit row is electrically connected to a corresponding drive voltage trace, and the drive voltage trace is used to apply a drive voltage to the pixel drive circuit PDC. Thus, the pixel drive circuit PDC of each display unit UU is connected to a drive voltage trace.

[0101] Optionally, the pixel drive circuit PDC includes at least a data write transistor, a drive transistor, and a storage capacitor, and the gate of the drive transistor can be electrically connected to an electrode plate of the storage capacitor. The first electrode of the data write transistor can be electrically connected to the data line DL, and the gate of the data write transistor can be electrically connected to the scan line GL. The pixel drive circuit PDC is configured such that when a scan signal is loaded on the scan line GL, the data write transistor is turned on, thereby causing the drive voltage on the data line DL to be written to the gate of the drive transistor and the storage capacitor. When the data write transistor is turned off, the drive voltage can be maintained by the storage capacitor. The drive transistor can output a drive current to drive the sub-pixel PIX to emit light under the control of the voltage on its gate. It is understandable that the pixel drive circuit PDC of the embodiment of the present disclosure may also include other transistors or capacitors to enable the pixel drive circuit PDC to have better driving performance. For example, the pixel drive circuit PDC can be a pixel drive circuit of 3T1C (3 thin film transistors and a storage capacitor), 7T1C (7 thin film transistors and a storage capacitor), 8T1C (8 thin film transistors and a storage capacitor), or other architectures.

[0102] In one example, the display panel PNL is provided with an array of sub-circuit areas PDCA in the display area AA. The present disclosure defines the area for configuring the transistors and storage capacitors of the pixel driver circuit PDC as a sub-circuit area PDCA. The sub-circuit areas PDCA in the display area AA form an array-distributed circuit area AS, with each circuit area AS including six sub-circuit areas PDCA. Thus, the circuit area AS includes six sub-circuit areas PDCA: a first sub-circuit area PDCA1 for configuring the transistors and storage capacitors of the first pixel driver circuit PDC1; a second sub-circuit area PDCA2 for configuring the transistors and storage capacitors of the second pixel driver circuit PDC2; a third sub-circuit area PDCA3 for configuring the transistors and storage capacitors of the third pixel driver circuit PDC3; a fourth sub-circuit area PDCA4 for configuring the transistors and storage capacitors of the fourth pixel driver circuit PDC4; a fifth sub-circuit area PDCA5 for configuring the transistors and storage capacitors of the fifth pixel driver circuit PDC5; and a sixth sub-circuit area PDCA6 for configuring the transistors and storage capacitors of the sixth pixel driver circuit PDC6.

[0103] Accordingly, the circuit area AS is provided with six sub-pixels PIX, each corresponding to a pixel driver circuit PDC. The six pixel driver circuits PDC in the six sub-circuit areas PDCA drive the sub-pixels PIX of two pixels, respectively. In one example, a pixel includes sub-pixels of three different colors, for example, a red sub-pixel PIX, a green sub-pixel PIX, and a blue sub-pixel PIX. In the present disclosure, the color of the sub-pixel PIX is determined based on the color of the final light emitted from the display panel PNL, rather than based on the color of the light emitted from the sub-pixel PIX.

[0104] It is understandable that in other embodiments of the present disclosure, the number of sub-pixels PIX in a pixel may also be other numbers, such as one, two, four, etc.

[0105] 2 , the display panel PNL includes a base substrate SBT, a driving layer DRL, and a pixel layer PIXL that are stacked.

[0106] The substrate SBT may be a substrate SBT of an inorganic material, or a substrate SBT of an organic material, or a substrate SBT in which organic and inorganic materials are alternately stacked. For example, in one embodiment of the present disclosure, the material of the substrate SBT may be a glass material such as soda-lime glass, quartz glass, or sapphire glass. In another embodiment of the present disclosure, the material of the substrate SBT may be polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or a combination thereof. In another embodiment of the present disclosure, the substrate SBT may be a flexible substrate SBT, for example, the substrate SBT may be made of polyimide (PI). The substrate SBT may also be a composite of multiple layers. For example, in one embodiment of the present disclosure, the substrate SBT may include a bottom film layer, a pressure-sensitive adhesive layer, a first polyimide layer, and a second polyimide layer stacked in sequence.

[0107] Referring to Figure 3, the pixel driving circuit PDC is arranged in the driving layer DRL, and the driving layer DRL has only one pixel driving circuit PDC in each of the sub-circuit areas PDCA. The pixel layer PIXL can be provided with a light-emitting element LD electrically connected to the pixel driving circuit PDC. The light-emitting element LD can serve as a sub-pixel PIX of the display panel PNL. In this way, the pixel layer PIXL is provided with an array-distributed light-emitting element LD, and each light-emitting element LD emits light under the control of the pixel driving circuit PDC. The pixel driving circuit PDC is used to drive the corresponding sub-pixel PIX so that the display panel PNL displays the picture.

[0108] In one disclosed embodiment, the light-emitting element LD may be an organic light-emitting diode (OLED), a micro light-emitting diode (Micro LED), a quantum dot-organic light-emitting diode (QD-OLED), a quantum dot light-emitting diode (QLED), or other types of light-emitting elements.

[0109] As shown in Figures 4 and 5 , the light-emitting element LD in the pixel layer PIXL may include two stacked electrodes and a light-emitting functional unit (EFU) sandwiched between the two electrodes. For example, the pixel layer PIXL may include a pixel electrode layer, a light-emitting functional layer, and a common electrode layer stacked in sequence. The pixel electrode layer comprises multiple pixel electrodes in the display area of ​​the display panel; the portion of the light-emitting functional layer connected to the pixel electrodes serves as the light-emitting functional unit of the light-emitting element LD; and the common electrode layer serves as a common electrode electrically connected to the light-emitting functional units of each light-emitting element LD.

[0110] Furthermore, the pixel layer PIXL may also include a pixel definition layer located between the pixel electrode layer and the light-emitting functional layer. The pixel definition layer has a plurality of through pixel openings arranged in a one-to-one correspondence with the plurality of pixel electrodes, and any pixel opening exposes at least a portion of the corresponding pixel electrode. For example, the pixel definition layer covers the edge of the pixel electrode and exposes at least a portion of the internal area of ​​the pixel electrode, so that the pixel definition layer can effectively define the actual effective area of ​​the pixel electrode (the area directly connected to the light-emitting functional unit), thereby defining the light-emitting area and light-emitting area of ​​the light-emitting element LD. The light-emitting functional layer at least covers the pixel electrode exposed by the pixel definition layer. The common electrode layer can cover the light-emitting functional layer in the display area. The pixel electrode and the common electrode layer provide carriers such as electrons and holes to the light-emitting functional layer so that the light-emitting functional layer emits light. The portion of the light-emitting functional layer located between the pixel electrode and the common electrode layer can serve as a light-emitting functional unit. The pixel electrode, the common electrode layer, and the light-emitting functional unit form the light-emitting element LD. Among them, one of the pixel electrode and the common electrode layer serves as the anode AE ​​of the light-emitting element LD, and the other serves as the cathode CE of the light-emitting element LD.

[0111] In one example, the pixel electrode serves as the anode AE ​​of the light emitting element LD, and the common electrode layer serves as the cathode CE of the light emitting element LD. For example, magnesium-silver alloy is used as the cathode CE of the light emitting element.

[0112] In an example, the pixel layer PIXL may further include an organic cover layer located on a side of the common electrode layer away from the substrate SBT.

[0113] It is understandable that the types of light-emitting elements are different, and the materials and film layers of the light-emitting functional units EFU are different.

[0114] For example, referring to FIG4 , when the light-emitting element is an OLED or MLED (Micro LED), the light-emitting functional unit EFU may include an organic light-emitting layer EML, and may include one or more of a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL. Furthermore, the organic light-emitting layer EML may include a light-emitting layer host material and a light-emitting layer guest material, and the light-emitting layer guest material may be a fluorescent dopant or a phosphorescent dopant, in particular, a thermally activated delayed fluorescent material. When the OLED or MLED adopts a stacked structure, a charge generation layer may also be provided in the light-emitting functional layer EFL.

[0115] For another example, referring to FIG5 , when the light-emitting element is a QLED, the light-emitting functional unit EFU may include a quantum dot layer QDL, and may include one or more of a hole injection layer HIL, an electron transport layer ETL, an electron blocking layer EBL, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL. Furthermore, the quantum dot layer QDL may include quantum dot particles, and the quantum dot particles may be interconnected via surface modification groups. When the QLED adopts a stacked structure, a charge generation layer may also be provided in the light-emitting functional unit EFU.

[0116] In the embodiments of the present disclosure, the light-emitting functional unit (EFU) may include a single light-emitting stack structure or a stacked multi-layer light-emitting stack structure. When the light-emitting functional unit (EFU) includes a multi-layer light-emitting stack structure, a charge generation layer may be provided between two adjacent light-emitting stack structures. Each light-emitting stack structure may include one or more light-emitting layers, which may be either an organic light-emitting layer (EML) or a quantum dot layer (QDL).

[0117] In the first related technology, referring to FIG6 , the six sub-pixels PIX in two pixels (pixel one and pixel two) are arranged in two rows and three columns, wherein the three sub-pixels PIX of the same pixel are arranged along the same row direction DH. Correspondingly, referring to FIG7 , the first pixel driving circuit PDC1, the second pixel driving circuit PDC2, the third pixel driving circuit PDC3, the fourth pixel driving circuit PDC4, the fifth pixel driving circuit PDC5 and the sixth pixel driving circuit PDC6 are arranged in two rows and three columns.

[0118] In the second related technology, referring to FIG8 , the six sub-pixels PIX in two pixels (pixel one and pixel two) are arranged in a row and six columns. Correspondingly, referring to FIG9 , the first pixel driving circuit PDC1, the second pixel driving circuit PDC2, the third pixel driving circuit PDC3, the fourth pixel driving circuit PDC4, the fifth pixel driving circuit PDC5 and the sixth pixel driving circuit PDC6 are arranged in a row and six columns.

[0119] In the two related technologies mentioned above, the pixel drive circuit includes a data write transistor, a sensing transistor, a drive transistor, and a storage capacitor. The drive layer includes a gate layer, a gate insulating layer, and a semiconductor layer stacked in sequence on one side of a substrate. The semiconductor layer has an active layer of the data write transistor, an active layer of the drive transistor, and an active layer of the sensing transistor. The gate of the data write transistor and the gate of the sensing transistor are each connected to a scanning line. The design of the two scanning lines allows the active layers of the data write transistor, the drive transistor, and the sensing transistor to be arranged in a column direction. The length direction of the active layer of the data write transistor, the length direction of the active layer of the drive transistor, and the length direction of the active layer of the sensing transistor are in the row direction. The sub-circuit area where the pixel drive circuit is located has a size in the row direction and a size in the column direction in a ratio of 1:3. The lateral space is too small, which is not conducive to layout and wiring. If the Oxide BCE process is used, the minimum Pixel Pitch (sub-pixel setting spacing) = 28.2um, which is approximately 901PPI (process capability: TFT W / L = 2.0 / 3.0um, critical dimension of via = 1.8um, metal layer w / s = 2.0 / 1.8um), and the pixel density is low.

[0120] It is understandable that the six pixel driving circuits PDC are not arranged in the order of first, second, etc. The description of the number of pixel driving circuits PDC, the number of sub-pixels PIX, and the colors in the above embodiment is merely an example of an embodiment of the present disclosure. In other embodiments of the present disclosure, the display area AA may be provided with other numbers of pixel driving circuits PDC and sub-pixels PIX, and may also be provided with sub-pixels PIX of other colors.

[0121] In order to solve the above problems, the present disclosure optimizes the arrangement of the above pixel driving circuit PDC.

[0122] In an embodiment of the present disclosure, any two of the active layer of the data writing transistor T1, the active layer of the sensing transistor T2, and the active layer of the driving transistor T3 are arranged in the same row. For example:

[0123] In a first embodiment, referring to FIG10 , the pixel driving circuit PDC includes a data writing transistor T1, a sensing transistor T2, a driving transistor T3 and a storage capacitor CST; the first electrode of the data writing transistor T1 is used to connect to the data line DL and load the data voltage VDA, the second electrode of the data writing transistor T1, the gate of the driving transistor T3 and the first electrode plate CP1 of the storage capacitor are electrically connected to the first node N1, and the gate of the data writing transistor T1 is used to connect to the scanning line GL and load the scanning signal GS; the second electrode of the driving transistor T3 is used to connect to the driving voltage line VDDL and load the driving voltage VDD, the first electrode of the driving transistor T3, the pixel electrode PIXP of the sub-pixel PIX, the second electrode of the sensing transistor T2, the second electrode plate CP2 of the storage capacitor are electrically connected to the second node N2, the first electrode of the sensing transistor T2 is used to connect to the sensing line SSL and load the reference voltage VREF, the gate of the sensing transistor T2 is used to connect to the scanning line GL and load the scanning signal GS, one end of the reset switch S_REF is connected to the first electrode of the sensing transistor T2, and the other end of the reset switch S_REF is connected to the reset line Ref. One end of the sampling switch S_SAMP is connected to the sensing trace SSL, and the other end of the sampling switch S_SAMP is connected to the charge detection device.

[0124] In the pre-charge phase, the reset switch S_REF is closed, and the data write transistor T1 and the sense transistor T2 are both turned on by the first scan voltage provided by the scan line GL, the data voltage VDA provided by the data line DL, and the reference voltage VREF provided by the sense line SSL, thereby turning on the drive transistor T3; in the detection phase, the reset switch S_REF is opened, so that the scan line GL changes from providing the first scan voltage to providing the second scan voltage, so that the sense transistor T2 is turned on, and the data write transistor T1 is turned off, so that the gate and the second electrode of the drive transistor T3 are in a suspended state. In this way, when the drive voltage VDD is input through the drive voltage line VDDL to increase the potential of the second electrode of the drive transistor T3, the storage capacitor Due to the coupling effect of CST, the gate potential of the driving transistor T3 increases, and the potential difference Vgs between the gate and the second electrode of the driving transistor T3 remains stable, so that the current flowing between the source and the second electrode of the driving transistor T3 can also remain stable, thereby accurately detecting the mobility of the driving transistor T3 and further accurately compensating the mobility of the driving transistor T3; in the sampling phase, the sampling switch S_SAMP is closed, the reset switch S_REF is kept disconnected, the data writing transistor T1 is kept closed, and the driving transistor T3 and the sensing transistor T2 are kept open. The processing unit collects the threshold voltage of the driving transistor T3 through the sensing trace SSL, and obtains the mobility of the driving transistor T3 based on the current flowing through the driving transistor T3.

[0125] In this disclosed embodiment, the data writing transistor T1, the sensing transistor T2, and the driving transistor T3 are all thin film transistors TFT, and the thin film transistor TFT can be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a dual-gate thin film transistor; the material of the active layer of the thin film transistor TFT can be amorphous silicon semiconductor material, low-temperature polycrystalline silicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, carbon nanotube semiconductor material, or other types of semiconductor materials; the thin film transistor TFT can be an N-type thin film transistor or a P-type thin film transistor.

[0126] In one disclosed embodiment, referring to Figures 11 and 12 , the six pixel driving circuits PDC corresponding to the six sub-pixels PIX of two pixels are arranged in a three-row, two-column arrangement instead of two rows. The three sub-pixels PIX of each pixel are arranged in two rows. A pixel includes three sub-pixels: R (red sub-pixel), G (green sub-pixel), and B (blue sub-pixel).

[0127] In one disclosed embodiment, referring to FIG13 , the drive layer DRL includes a gate layer GT, a gate insulating layer GI, a semiconductor layer SCL, a first source / drain metal layer SD1, a first interlayer dielectric layer ILD1, a second source / drain metal layer SD2, a second interlayer dielectric layer ILD2, and a third source / drain metal layer SD3, stacked sequentially on one side of a substrate SBT. The scan lines GL may be provided on the gate layer GT, the drive voltage lines VDDL may be provided on the first source / drain metal layer SD1, and the data lines DL and the sense lines SSL may be provided on the third source / drain metal layer SD3.

[0128] Figure 14 is a schematic diagram of the partial structure of the display panel PNL in the gate layer GT in the first disclosed embodiment. Figure 15 is a schematic diagram of the partial structure of the display panel PNL in the semiconductor layer SCL in the first disclosed embodiment. Figure 16 is a schematic diagram of the partial structure of the display panel PNL in the first source-drain metal layer SD1 in the first disclosed embodiment. Figure 17 is a schematic diagram of the partial structure of the display panel PNL in the first disclosed embodiment where the semiconductor layer SCL and the first source-drain metal layer SD1 overlap. Figure 18 is a schematic diagram of the partial structure of the display panel PNL in the second source-drain metal layer SD2 in the first disclosed embodiment. Figure 19 is a schematic diagram of the partial structure of the display panel PNL in the third source-drain metal layer SD3 in the first disclosed embodiment.

[0129] Referring to Figure 15 , the display area AA includes four pixel arrangement areas PDCA: a first pixel arrangement area PDCA1, a second pixel arrangement area PDCA2, a third pixel arrangement area PDCA3, and a fourth pixel arrangement area PDCA4. Each pixel arrangement area PDCA includes an active layer for a sensing transistor T2, an active layer for a driving transistor T3, and an active layer for a data write transistor T1. Each active layer includes a channel region and a source and drain located on either side of the channel region.

[0130] The data write transistor T1 and the sensing transistor T2 are arranged sequentially along the row direction DH, and the drive transistor T3 and the sensing transistor T2 are arranged sequentially along the column direction DV. A gap exists between the orthogonal projection of the active layer of the drive transistor T3 in the row direction DH and the orthogonal projection of the active layer of the data write transistor T1 in the row direction DH; a gap exists between the orthogonal projection of the active layer of the drive transistor T3 in the column direction DV and the orthogonal projection of the active layer of the sensing transistor T2 in the column direction DV. The length directions of the active layers of the data write transistor T1, the drive transistor T3, and the sensing transistor T2 are all in the column direction DV.

[0131] Referring to Figure 15 , the active layer of the data write transistor T1 includes a channel region T1A of the data write transistor T1 and a first electrode and a second electrode located on either side of the channel region T1A of the data write transistor T1. The first electrode of the data write transistor T1 is electrically connected to a data line DL located on the third source-drain metal layer SD3. The second electrode of the data write transistor T1 is electrically connected to a first node N1. The active layer of the drive transistor T3 includes a channel region T3A of the drive transistor T3 and a first electrode and a second electrode located on either side of the channel region T3A of the drive transistor T3. The second electrode of the drive transistor T3 is electrically connected to a drive voltage line VDDL located on the first source-drain metal layer SD1. The first electrode of the drive transistor T3 is electrically connected to a second node N2. The active layer of the sensing transistor T2 includes a channel region T2A of the sensing transistor T2 and a first electrode and a second electrode located on both sides of the channel region T2A of the sensing transistor T2; the first electrode of the sensing transistor T2 is used to be electrically connected to the sensing trace SSL located on the third source-drain metal layer SD3, and the second electrode of the sensing transistor T2 is used to be electrically connected to the second node N2.

[0132] 14 and 18 , the storage capacitor CST includes a first electrode plate CP1 of the storage capacitor located in the gate layer Gate and a second electrode plate CP2 of the storage capacitor located in the second source / drain metal layer SD2; the second electrode plate CP2 of the storage capacitor overlaps with the first electrode plate CP1 of the storage capacitor, and the overlapping portion of the first electrode plate CP1 of the storage capacitor and the channel region T3A of the driving transistor T3 is reused as the gate of the driving transistor T3.

[0133] In this exemplary display panel, as shown in FIG16 , the first source-drain metal layer SD1 includes a first conductive portion ML1, a second conductive portion ML2, a third conductive portion ML3, a fourth conductive portion ML4, and a drive voltage trace VDDL. Two adjacent first conductive portions ML1 along the column direction are electrically connected to form a first conductive group, and four adjacent second conductive portions ML2 are electrically connected to form a second conductive group. Partial areas of the first conductive portion ML1 are electrically connected to the first electrode of the data write transistor T1, partial areas of the fourth conductive portion ML4 are electrically connected to the second electrode of the data write transistor T1, and partial areas of the second conductive portion ML2 are electrically connected to the first electrode of the sensing transistor T2. Partial areas of the third conductive portion ML3 are electrically connected to the second electrode of the sensing transistor T2, and partial areas of the third conductive portion ML3 are electrically connected to the first electrode of the drive transistor T3. Thus, the second electrode of the sensing transistor T2 and the first electrode of the drive transistor T3 are electrically connected via the third conductive portion ML3.

[0134] In this exemplary display panel, the drive voltage VDD can be applied to the second electrode of each drive transistor T3 via a drive voltage line VDDL. The drive voltage line VDDL is disposed on the first source-drain metal layer SD1. Exemplarily, the drive voltage line VDDL has a raised portion corresponding to each drive transistor T3. The raised portion is electrically connected to the second electrode of the drive transistor T3, thereby enabling the drive voltage VDD to be applied to the second electrode of the drive transistor T3.

[0135] In this exemplary display panel, referring to Figures 14, 16 and 17, a fourth bottom via area HA4 is provided on the first electrode plate CP1 of the storage capacitor of the gate layer Gate, and a fourth top via area HB4 is provided on the fourth conductive portion ML4. The fourth bottom via area HA4 and the fourth top via area HB4 are overlapped and connected through vias. In this way, the second electrode of the data writing transistor T1 and the first electrode plate CP1 of the storage capacitor are electrically connected through the fourth conductive portion ML4, and they serve as the first node N1 together.

[0136] In this exemplary display panel, referring to Figures 16, 17 and 18, a third top via area HB3 is provided on the second electrode plate CP2 of the storage capacitor of the second source-drain metal layer SD2, and a third bottom via area HA3 is provided on the third conductive portion ML3. The third top via area HB3 and the third bottom via area HA3 are overlapped and connected through vias. In this way, the second electrode of the sensing transistor T2, the first electrode of the driving transistor T3 and the second electrode plate CP2 of the storage capacitor are electrically connected through the third conductive portion ML3, and together serve as the second node N2.

[0137] In this exemplary display panel, as shown in Figures 16, 17, and 19, a data voltage VDA can be applied to the first electrode of each data write transistor T1 via a data line DL. The data line DL is disposed on the third source-drain metal layer SD3, and pixel driver circuits PDC in the same column share a single data line DL. The data line DL has a raised portion near the data write transistor T1, on which a first top via region HB1 is formed. A first bottom via region HA1 is formed on the first conductive group. The first top via region HB1 and the first bottom via region HA1 overlap and are connected via vias. Thus, the data line DL is electrically connected to the first electrodes of two adjacent data write transistors T1 via the first conductive group, enabling the data voltage VDA to be applied to the first electrodes of the two adjacent data write transistors T1. Furthermore, two adjacent pixel driver circuits PDC share the same set of first top via region HB1 and first bottom via region HA1, reducing the area occupied by the pixel driver circuit PDC.

[0138] In this exemplary display panel, as shown in Figures 16, 17, and 19, a reference voltage VREF is applied to the first electrode of each sensing transistor T2 via a sensing trace SSL. The sensing trace SSL is disposed on the third source / drain metal layer SD3. The sensing trace SSL has a raised portion at the location of the sensing transistor T2, with a second top via region HB2 formed on the raised portion. A second bottom via region HA2 is formed on the second conductive group. The second top via region HB2 and the second bottom via region HA2 overlap and are connected via vias. Thus, the sensing trace SSL is electrically connected to the first electrodes of four adjacent sensing transistors T2 via the second conductive group, enabling the reference voltage VREF to be applied to the first electrodes of the four adjacent sensing transistors T2. Furthermore, the four adjacent sensing transistors T2 share the same set of second top via region HB2 and second bottom via region HA2, thereby reducing the area occupied by the pixel driver circuit PDC.

[0139] The driving layer DRL adopts the above-mentioned arrangement, see Figure 11, the ratio of the size of the sub-circuit area PDCA in the row direction DH to the size in the column direction DV can be changed from 1:3 to 3:4. Before and after optimization, the occupied area of ​​the sub-circuit area PDCA can remain unchanged; two pixels are grouped together, and the shape, area, and number of sub-pixels PIX are the same as the conventional arrangement (that is, the present disclosure is a method of making the spatial layout and wiring more reasonable by changing the pixel aspect ratio without reducing the number of sub-pixels, thereby improving the density of layout and wiring and achieving high PPI). The driving architecture changes from two row scan signals and three column scan signals to three row scan signals and two column scan signals, which is equivalent to a 1:1.5mux effect. Under the same process capability conditions, the Pixel Pitch is further compressed to 25.4um, reaching 1000PPI.

[0140] In the embodiment of the present disclosure, a left-right symmetrical and top-bottom symmetrical structural design is adopted during the layout. Two pixel driving circuits PDC adjacent to each other on the left and right share a sensing trace SSL. The left-right symmetrical structure allows two horizontally adjacent pixel driving circuits PDC to share the driving voltage trace VDDL, and the top-bottom symmetrical structure allows two vertical pixel driving circuits PDC to share the driving voltage trace VDDL, the connecting vias of the data trace DL, and the connecting vias of the sensing trace SSL, wherein the sensing trace SSL is shared by left and right and top and bottom, so that four pixel driving circuits PDC share one connecting via. In summary, the maximum sharing of vias and traces has been considered during the layout and wiring, which reduces the occupied area and improves the PPI. A high PPI means an increase in the number of pixels and the required scanning signals. Row scanning signals are provided by the backplane GOA, so this increase in number does not increase costs. Column scanning signals are provided by ICs. The arrangement proposed in this disclosure can reduce the number of column scanning signals from 3 to 2, and the number of ICs is reduced by 1 / 3, thus achieving low costs. This also reduces the cost of the display module and backplane, reducing the number of backplane process masks from 13 to 11, while also reducing the number of stacked film layers and improving yield. This arrangement increases the aperture ratio, improves brightness, reduces power consumption, and enhances the core competitiveness of the product.

[0141] In a second embodiment, referring to FIG. 20 and FIG. 21 , the six sub-pixels PIX of two pixels are arranged in a row of six columns, which is optimized to an arrangement of two rows and three columns, wherein the three sub-pixels PIX of each pixel are arranged in two rows.

[0142] In one disclosed embodiment, referring to FIG22 , the drive layer DRL includes a gate layer GT, a gate insulating layer GI, a semiconductor layer SCL, a first source / drain metal layer SD1, a first interlayer dielectric layer ILD1, a second source / drain metal layer SD2, a second interlayer dielectric layer ILD2, and a third source / drain metal layer SD3, stacked sequentially on one side of a substrate SBT. The scan lines GL may be provided on the gate layer GT, the drive voltage lines VDDL may be provided on the second source / drain metal layer SD2, and the data lines DL and the sense lines SSL may be provided on the third source / drain metal layer SD3.

[0143] Figure 23 shows a schematic diagram of the partial structure of the display panel PNL in the gate layer GT in the second embodiment. Figure 24 shows a schematic diagram of the partial structure of the display panel PNL in the semiconductor layer SCL in the second embodiment. Figure 25 shows a schematic diagram of the partial structure of the display panel PNL in the first source / drain metal layer SD1 in the second embodiment. Figure 26 shows a schematic diagram of the partial structure of the display panel PNL in the second embodiment where the first source / drain metal layer SD1 and the semiconductor layer SCL are superimposed. Figure 27 shows a schematic diagram of the partial structure of the display panel PNL in the second source / drain metal layer SD2 in the second embodiment. Figure 28 shows a schematic diagram of the partial structure of the display panel PNL in the third source / drain metal layer SD3 in the second embodiment.

[0144] Referring to Figure 24 , the display area AA includes four pixel arrangement areas PDCA: a first pixel arrangement area PDCA1, a second pixel arrangement area PDCA2, a third pixel arrangement area PDCA3, and a fourth pixel arrangement area PDCA4. Each pixel arrangement area PDCA includes an active layer for a sensing transistor T2, an active layer for a driving transistor T3, and an active layer for a data write transistor T1. Each active layer includes a channel region and first and second electrodes located on either side of the channel region.

[0145] The active layer of the data write transistor T1 and the active layer of the sensing transistor T2 are arranged along the row direction DH, and the active layer of the drive transistor T3 and the active layer of the sensing transistor T2 are arranged along the column direction DV. A gap exists between the orthogonal projection of the active layer of the drive transistor T3 in the row direction DH and the orthogonal projection of the active layer of the data write transistor T1 in the row direction DH; a gap exists between the orthogonal projection of the active layer of the drive transistor T3 in the column direction DV and the orthogonal projection of the active layer of the sensing transistor T2 in the column direction DV. The length direction of the active layer of the data write transistor T1 is the column direction DV, and the length direction of the active layer of the drive transistor T3 and the length direction of the active layer of the sensing transistor T2 are the row direction DH.

[0146] Referring to Figure 24 , the active layer of the data write transistor T1 includes a channel region T1A of the data write transistor T1 and a first electrode and a second electrode located on either side of the channel region T1A of the data write transistor T1. The first electrode of the data write transistor T1 is electrically connected to a data line DL located on the third source-drain metal layer SD3. The second electrode of the data write transistor T1 is electrically connected to a first node N1. The active layer of the drive transistor T3 includes a channel region T3A of the drive transistor T3 and a first electrode and a second electrode located on either side of the channel region T3A of the drive transistor T3. The second electrode of the drive transistor T3 is electrically connected to a drive voltage line VDDL located on the second source-drain metal layer SD2. The first electrode of the drive transistor T3 is electrically connected to a second node N2. The active layer of the sensing transistor T2 includes a channel region T2A of the sensing transistor T2 and a first electrode and a second electrode located on both sides of the channel region T2A of the sensing transistor T2; the first electrode of the sensing transistor T2 is used to be electrically connected to the sensing trace SSL located on the third source-drain metal layer SD3, and the second electrode of the sensing transistor T2 is used to be electrically connected to the second node N2.

[0147] 23 and 27 , the storage capacitor CST includes a first electrode plate CP1 of the storage capacitor located in the gate layer Gate and a second electrode plate CP2 of the storage capacitor located in the second source / drain metal layer SD2; the second electrode plate CP2 of the storage capacitor overlaps with the first electrode plate CP1 of the storage capacitor, and the overlapping portion of the first electrode plate CP1 of the storage capacitor and the channel region T3A of the driving transistor T3 is reused as the gate of the driving transistor T3.

[0148] 25 , the first source / drain metal layer SD1 includes a first conductive portion ML1, a second conductive portion ML2, a third conductive portion ML3, a fourth conductive portion ML4, and a sixth conductive portion ML6. Four adjacent first conductive portions ML1 are electrically connected to form a first conductive group. Two adjacent second conductive portions ML2 along a column are electrically connected to form a second conductive group. Four adjacent sixth conductive portions ML6 are electrically connected to form a sixth conductive group.

[0149] Referring to Figure 26, a partial area of ​​the first conductive part ML1 is electrically connected to the first electrode of the sensing transistor T2, a partial area of ​​the fourth conductive part ML4 is electrically connected to the second electrode of the sensing transistor T2, a partial area of ​​the second conductive part ML2 is electrically connected to the first electrode of the data writing transistor T1, a partial area of ​​the third conductive part ML3 is electrically connected to the second electrode of the data writing transistor T1, a partial area of ​​the fourth conductive part ML4 is electrically connected to the first electrode of the driving transistor T3, and a partial area of ​​the sixth conductive part ML6 is electrically connected to the second electrode of the driving transistor T3.

[0150] Referring to Figures 23 and 25, the first electrode plate CP1 of the storage capacitor of the gate layer GT has a fourth bottom via area HA4, and the third conductive part ML3 has a fourth top via area HB4. The fourth bottom via area HA4 and the fourth top via area HB4 are both long strip holes. The second source and drain metal layer SD2 has an eighth conductive part ML8, and the eighth conductive part ML8 extends to the fourth top via area HB4 and the fourth bottom via area HA4. In this way, the second electrode of the data write transistor T1 and the first electrode plate CP1 of the storage capacitor are electrically connected through the eighth conductive part ML8, and they jointly serve as the first node N1.

[0151] In this exemplary display panel, referring to Figures 27 and 25, a third top via area HB3 is provided on the second electrode plate CP2 of the storage capacitor, and a third bottom via area HA3 is provided on the fourth conductive portion ML4. The third top via area HB3 and the third bottom via area HA3 are overlapped and connected through vias. In this way, the second electrode of the sensing transistor T2, the first electrode of the driving transistor T3 and the second electrode plate CP2 of the storage capacitor are electrically connected through the fourth conductive portion ML4 and serve as the second node N2.

[0152] In this exemplary display panel, the drive voltage VDD can be applied to the second electrode of each drive transistor T3 via a drive voltage trace VDDL. The drive voltage trace VDDL is disposed on the second source / drain metal layer SD2. Exemplarily, the drive voltage trace VDDL includes a raised portion corresponding to each drive transistor T3. The raised portion includes a sixth top via region HB6. The sixth conductive group includes a sixth bottom via region HA6. The sixth top via region HB6 and the sixth bottom via region HA6 overlap and are connected via vias. Thus, the drive voltage trace VDDL is electrically connected to the second electrode of the drive transistor T3 via the sixth conductive group, enabling the drive voltage VDD to be applied to the second electrode of the drive transistor T3. The drive voltage trace VDDL includes a clearance gap to avoid the sensing trace SSL.

[0153] In this exemplary display panel, a data voltage VDA can be applied to the first electrode of each data write transistor T1 via a data line DL. The data line DL is disposed on the third source-drain metal layer SD3, and pixel drive circuits PDC in the same column share one data line DL. The data line DL has a raised portion, which has a second top via region HB2. The second conductive group has a second bottom via region HA2. The second top via region HB2 and the second bottom via region HA2 overlap and are connected via vias. Thus, the data line DL is electrically connected to the first electrode of the data write transistor T1 via the second conductive group, enabling the data voltage VDA to be applied to the first electrodes of two adjacent data write transistors T1.

[0154] In this exemplary display panel, the reference voltage VREF is loaded to the first electrode of each sensing transistor T2 through the sensing trace SSL, wherein the sensing trace SSL is arranged on the third source-drain metal layer SD3, and has a raised portion on the sensing trace SSL, and has a first top via area HB1 on the raised portion, and has a first bottom via area HA1 on the first conductive group, and the first top via area HB1 and the first bottom via area HA1 are overlapped and connected through vias. In this way, the sensing trace SSL is electrically connected to the first electrodes of the four adjacent sensing transistors T2 through the first conductive group, so that the reference voltage VREF can be loaded to the first electrodes of the four adjacent sensing transistors T2.

[0155] In this embodiment, using the above arrangement, the ratio of the size of the sub-circuit area PDCA in the row direction DH to the size in the column direction DV can be changed from 1:3 to 4:3. Before and after optimization, the area occupied by the sub-circuit area PDCA can remain unchanged; two pixels are grouped together, and the shape, area, and number of sub-pixels PIX are the same as those in the conventional arrangement. The driving architecture changes from one row scan signal and six column scan signals to two row scan signals and three column scan signals, which is equivalent to a 1:2 mux or dual gate driving mode. Under the same process capability conditions, the Pixel Pitch is further compressed to 26.34um, reaching 964PPI. The number of masks is reduced from 13 to 10, and the cost is greatly reduced.

[0156] The layout adopts a left-right and top-bottom symmetric design. Two adjacent pixel drive circuits (PDCs) on the left and right share a sensing trace SSL and a driving voltage trace VDDL. The left-right symmetric structure allows the two horizontal pixel drive circuits (PDCs) to share the connection vias for the driving voltage trace VDDL, while the top-bottom symmetric structure allows the two vertical pixel drive circuits (PDCs) to share the connection vias for the data trace DL and the connection vias for the sensing trace SSL. By sharing the sensing trace SSL left-right and top-bottom, four pixel drive circuits (PDCs) share one via. This arrangement takes into account the maximum possible sharing of vias and traces during layout and wiring, thus reducing the occupied area. At the same time, a high PPI means an increase in the number of pixels and the required scanning signals. However, the row scanning signals are provided by the backplane GOA, so the increase in number does not result in a cost increase. The column scanning signals are provided by the IC. The solution proposed in this patent can reduce the number of column scanning signals from six to three, reducing the number of ICs by 1 / 2, thereby achieving low costs.

[0157] In a disclosed embodiment, the orthographic projections of the active layer of the data write transistor T1 and the active layer of the sensing transistor T2 on the gate layer GT are completely located within the scanning line GL; the orthographic projection of the active layer of the driving transistor T3 on the first electrode plate CP1 of the storage capacitor is completely located within the first electrode plate CP1 of the storage capacitor. There is no need to reserve additional space to avoid the active layer of the data write transistor T1, the active layer of the sensing transistor T2, and the active layer of the driving transistor T3, thereby reducing the space occupied by the pixel driving circuit PDC and improving the PPI.

[0158] In one disclosed embodiment, the arrangement shown in FIG. 44 and FIG. 45 can be obtained by changing the definition of pixels.

[0159] In a disclosed embodiment, referring to FIG. 29 , FIG. 30 , FIG. 31 and FIG. 32 , the PDCAs of the sub-circuit areas in the same row are staggered.

[0160] In a disclosed embodiment, referring to FIG. 13 and FIG. 22 , the driving layer DRL further includes a planarization layer PLN stacked on the third source / drain metal layer SD3 .

[0161] In a third embodiment, the light-emitting element may be an organic light-emitting diode (OLED). Referring to Figures 13, 18, and 19, the device further includes a pixel layer PIXL stacked above the drive layer DRL, the pixel layer PIXL including a pixel electrode layer disposed above the planarization layer PLN, the pixel electrode layer having a pixel electrode PIXP therein. The third source-drain metal layer SD3 includes a fifth conductive portion ML5, the fifth conductive portion ML5 having a fifth top via region HA5 thereon, and the second electrode plate CP2 of the storage capacitor located on the second source-drain metal layer SD2 having a fifth bottom via region HB5 thereon. The fifth top via region HA5 and the fifth bottom via region HB5 are overlapped and connected via vias. In this way, the pixel electrode PIXP can be electrically connected to the second electrode plate CP2 of the storage capacitor via the fifth conductive portion ML5, and further electrically connected to the first electrode of the drive transistor T3.

[0162] In a fourth embodiment, the light-emitting element may be an organic light-emitting diode (OLED). Referring to Figures 22, 27, and 28, the device further includes a pixel layer PIXL stacked above the drive layer DRL. The pixel layer PIXL includes a pixel electrode layer sequentially stacked above the planarization layer PLN, and the pixel electrode layer includes a pixel electrode PIXP. The third source-drain metal layer SD3 includes a seventh conductive portion ML7, which includes a seventh top via region HA7. The second electrode plate CP2 of the storage capacitor located on the second source-drain metal layer SD2 includes a seventh bottom via region HB7. The seventh top via region HA7 and the seventh bottom via region HB7 overlap and are connected via vias. In this way, the pixel electrode PIXP can be electrically connected to the second electrode plate CP2 of the storage capacitor through the seventh conductive portion ML7, and further electrically connected to the first electrode of the driving transistor T3.

[0163] In a fifth embodiment, the light-emitting element may be a micro-light-emitting diode (Micro LED). Referring to FIG. 43 , the drive layer DRL further includes a passivation layer PVX and a fourth source / drain metal layer SD4, which are sequentially stacked on the planarization layer PLN. The fourth source / drain metal layer SD4 can serve as a pad for bonding the pixel layer. In this case, the common voltage trace is provided on the third source / drain metal layer SD3. The pixel electrode is directly electrically connected to the second source / drain metal layer SD2 via the fourth source / drain metal layer SD4. This reduces the space occupied by the third source / drain metal layer SD3 and allows for the arrangement of the common voltage trace.

[0164] In one disclosed embodiment, the pixel layer PIXL further includes a pixel definition layer PDL located above the pixel electrode layer. The pixel definition layer PDL has a plurality of through-going pixel openings in the display area AA, corresponding to the plurality of pixel electrodes PIXP. Each pixel opening exposes at least a portion of the corresponding pixel electrode PIXP. It is understood that in other embodiments of the present disclosure, the pixel electrode layer may also have other structures.

[0165] In a sixth embodiment, the driving layer DRL may further include a third interlayer dielectric layer ILD3 and a fourth source / drain metal layer SD4 stacked on the third source / drain metal layer SD3, and the sensing line SSL is arranged on the fourth source / drain metal layer SD4. This method can still increase the pixel density.

[0166] In one disclosed embodiment, the pixel electrodes PIXP can be arranged in a conventional RGB strip configuration. For example, as shown in FIG33 , the six pixel electrodes PIXP of two pixels are arranged in two rows and three columns, with the three pixel electrodes PIXP of the same pixel arranged in the same row. The drive layer DRC further includes a third interlayer dielectric layer and a fourth source / drain metal layer located between the third source / drain metal layer SD3 and the planarization layer PLN. The third interlayer dielectric layer is located between the third source / drain metal layer SD3 and the fourth source / drain metal layer. The fourth source / drain metal layer includes a ninth conductive portion ML9. The pixel electrode PIXP is electrically connected to the fifth conductive portion ML5 of the third source / drain metal layer SD3 via the ninth conductive portion ML9 and a connection via in the third interlayer dielectric layer. It can be understood that, referring to Figures 38 and 46, the six pixel electrodes PIXP of the two pixels are arranged in a row and six columns (wherein, the pixel driving circuits in the same column may be staggered or not), and the pixel electrode PIXP is electrically connected to the seventh conductive part ML7 on the third source and drain metal layer SD3 through the connecting via on the planarization layer PLN. Using the above method, the display effect is better.

[0167] In a disclosed embodiment, the six pixel electrodes PIXP can be arranged in the same manner as the six pixel driving circuits PDC. For example, referring to FIG34 , the six pixel electrodes PIXP of two pixels are arranged in three rows and two columns, and referring to FIG39 , the six pixel electrodes PIXP of two pixels are arranged in two rows and three columns. Referring to FIG35 , the six pixel electrodes PIXP of two pixels are arranged in three rows and two columns, and the pixel electrodes PIXP of the same column are staggered. Referring to FIG40 , the six pixel electrodes PIXP of two pixels are arranged in two rows and three columns, and the pixel electrodes PIXP of the same column are staggered. In the above manner, there is no need to use the fourth source and drain metal layer, the number of mask plates is reduced from 13 to 11, the cost is reduced, and the opening area is increased.

[0168] In a disclosed embodiment, referring to FIG36 , three sub-pixels PIX of the same pixel may be located in the same row, that is, the three sub-pixels PIX in the areas where the first sub-circuit area PDCA1, the second sub-circuit area PDCA2, and the fifth sub-circuit area PDCA5 are located are defined as the same pixel, and the three sub-pixels PIX in the areas where the third sub-circuit area PDCA3, the fourth sub-circuit area PDCA4, and the sixth sub-circuit area PDCA6 are defined as the same pixel.

[0169] In a disclosed embodiment, referring to FIG. 37 , three sub-pixels PIX of a same pixel may be located in a same row, and three sub-pixels PIX of a same column may be arranged in an alternating manner.

[0170] In a disclosed embodiment, referring to FIG. 39 , the arrangement of one row and six columns can be optimized to three rows and two columns, wherein the three sub-pixels PIX corresponding to each pixel are arranged in two rows.

[0171] In a disclosed embodiment, referring to FIG. 40 , the arrangement of one row and six columns can be optimized to three rows and two columns, wherein the three sub-pixels PIX corresponding to each pixel are arranged in two rows, and the three sub-pixels PIX in the same column are staggered.

[0172] In a disclosed embodiment, referring to FIG. 41 , the definition of pixel points can be changed, and the three sub-pixels PIX in the areas where the first sub-circuit area PDCA1, the second sub-circuit area PDCA2, and the third sub-circuit area PDCA3 are located can be regarded as the same pixel, and the three sub-pixels PIX in the areas where the fourth sub-circuit area PDCA4, the fifth sub-circuit area PDCA5, and the sixth sub-circuit area PDCA6 are located can be regarded as the same pixel.

[0173] In one disclosed embodiment, referring to FIG. 42 , sub-pixels PIX in the same column may be arranged in an alternating manner.

[0174] In summary, the arrangement of the pixel driving circuit proposed in the present disclosure improves the PPI, expands the core competitiveness of glass-based / PI-based OLED / Micro LED in the VR market; reduces the cost of the display module; reduces the backplane cost, and can reduce the number of backplane process masks from 13 to 11, while reducing the number of stacked film layers and improving the yield. The aperture ratio is increased, the brightness is improved, the power consumption is reduced, and the core competitiveness of the product is improved. At the same time, the arrangement proposed in the present disclosure is not limited to the backplane process preparation method of the above example. For example, other device structures such as Top Gate, etc., or stacking processes such as LTPO, etc. can also be selected. The active layer material is not limited to IGZO, and other materials such as LTPS, etc. can be used. The present disclosure can also be used for any other driving circuits, such as 4T2C, 5T1C, 7T1C, etc., not limited to NMOS / PMOS circuits.

[0175] In one disclosed embodiment, the gate layer GT may be made of a metal material such as Mo, Cu, or Ti. The gate insulating layer GI may include a silicon nitride layer and a silicon oxide layer stacked on the gate layer GT, with the silicon oxide layer located on the side of the silicon nitride layer facing away from the substrate. The active layer may be IGZO, the source / drain metal layer may be made of a metal material such as Mo, Cu, or Ti, the first interlayer dielectric layer ILD1 may be a silicon oxide layer or a silicon oxide layer and a silicon nitride layer stacked in sequence on the first source / drain metal layer, the second interlayer dielectric layer ILD2 may be a silicon oxide layer or a silicon nitride layer, the planarization layer PLN may be an organic film layer, and the passivation layer PVX may be a silicon oxide layer or a silicon nitride layer.

[0176] Optionally, referring to Figures 2 and 3, the display panel PNL may further include a thin film encapsulation layer TFE. The thin film encapsulation layer TFE is provided on the surface of the pixel layer away from the base substrate SBT, and may include an inorganic encapsulation layer and an organic encapsulation layer that are alternately stacked. Among them, the inorganic encapsulation layer can effectively block external moisture and oxygen, and prevent water and oxygen from invading the organic light-emitting layer of the pixel layer and causing material degradation. Optionally, the edge of the inorganic encapsulation layer may be located in the light-transmitting area. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve flattening and reduce the stress between the inorganic encapsulation layers. Among them, the edge of the organic encapsulation layer may be located between the edge of the display area and the edge of the inorganic encapsulation layer. Exemplarily, the thin film encapsulation layer TFE includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer sequentially stacked on the side of the pixel layer away from the base substrate SBT.

[0177] Optionally, referring to FIG. 2 and FIG. 3 , the display panel may further include a touch function layer, which is disposed on a side of the thin film encapsulation layer TFE away from the base substrate SBT, for implementing touch operation of the display panel.

[0178] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A display panel, wherein: It includes a base substrate, a driving layer and a pixel layer that are stacked; The display panel is provided with a plurality of sub-circuit areas distributed in an array in the display area; The driving layer is provided with a pixel driving circuit for driving a sub-pixel in each sub-circuit area; The ratio of the size of the sub-circuit area in the row direction to the size in the column direction is not less than 3:

4.

2. The display panel according to claim 1, wherein The sub-circuit areas constitute a circuit area distributed in an array, and each circuit area includes six sub-circuit areas; the six pixel driving circuits in the six sub-circuit areas respectively drive the sub-pixels of two pixels.

3. The display panel according to claim 2, wherein: The ratio of the size of the sub-circuit area in the row direction to the size in the column direction is equal to 3:

4.

4. The display panel according to claim 3, wherein: The six sub-circuit areas in the circuit area are arranged in three rows and two columns.

5. The display panel according to claim 4, wherein: The pixel layer has six pixel electrodes arranged adjacent to each other in the circuit area, and the six pixel electrodes are electrically connected to the six pixel driving circuits in the circuit area in a one-to-one correspondence; The six pixel electrodes in the circuit area are arranged in two rows and three columns; Alternatively, the six pixel electrodes in the circuit area are arranged in three rows and two columns. The display panel according to claim 2 , wherein: The ratio of the size of the sub-circuit area in the row direction to the size in the column direction is equal to 4:

3.

7. The display panel according to claim 6, wherein: The six sub-circuit areas in the circuit area are arranged in two rows and three columns.

8. The display panel according to claim 7, wherein: The pixel layer is provided with six pixel electrodes in the circuit area, and the six pixel electrodes are electrically connected to the six pixel driving circuits in the circuit area respectively in a one-to-one correspondence; The six pixel electrodes in the circuit area are arranged in a row and six columns; Alternatively, the six pixel electrodes in the circuit area are arranged in two rows and three columns.

9. The display panel according to any one of claims 1 to 8, wherein: The sub-circuit areas in the same column are arranged in a staggered manner.

10. The display panel according to any one of claims 1 to 8, wherein: The pixel driving circuit includes a data writing transistor, a sensing transistor, a driving transistor and a storage capacitor; The first electrode of the data writing transistor is used to load a data voltage, and the second electrode of the data writing transistor, the gate of the driving transistor, and the first electrode plate of the storage capacitor are electrically connected; the gate of the data writing transistor is used to load a scan signal; The first electrode of the sensing transistor is used to load a reference voltage, and the second electrode of the sensing transistor, the second electrode plate of the storage capacitor, the pixel electrode of the sub-pixel, and the first electrode of the driving transistor are electrically connected; the gate of the sensing transistor is used to load the scanning signal; The second electrode of the driving transistor is used to apply a driving voltage.

11. The display panel according to claim 10, wherein: The driving layer includes a semiconductor layer, and the semiconductor layer includes an active layer of the data writing transistor, an active layer of the sensing transistor, and an active layer of the driving transistor; Any two of the active layer of the data write transistor, the active layer of the sensing transistor, and the active layer of the driving transistor are located in the same row.

12. The display panel according to claim 11, wherein: The active layer of the data writing transistor and the active layer of the sensing transistor are arranged along a row direction, and the active layer of the driving transistor and the active layer of the sensing transistor are arranged along a column direction; There is a gap between the orthographic projection of the active layer of the driving transistor in the row direction and the orthographic projection of the active layer of the data writing transistor in the row direction; A gap is formed between an orthographic projection of the active layer of the driving transistor in the column direction and an orthographic projection of the active layer of the sensing transistor in the column direction.

13. The display panel according to claim 12, wherein: A length direction of the active layer of the data writing transistor, a length direction of the active layer of the driving transistor, and a length direction of the active layer of the sensing transistor are all column directions.

14. The display panel according to claim 12, wherein: The length direction of the active layer of the data writing transistor is a column direction, and the length directions of the active layer of the driving transistor and the active layer of the sensing transistor are both row directions.

15. The display panel according to claim 11, wherein The driving layer further includes a gate layer, the gate layer being provided with a scanning line for loading the scanning signal, and a first electrode plate of the storage capacitor being provided as a gate of the driving transistor; The orthographic projections of the active layer of the data writing transistor and the active layer of the sensing transistor on the gate layer are completely located within the scanning line; The orthographic projection of the active layer of the driving transistor on the first electrode plate of the storage capacitor is completely located within the first electrode plate of the storage capacitor.

16. The display panel according to claim 15, wherein: The driving layer further comprises a semiconductor layer, a first source-drain metal layer and a second source-drain metal layer located on a side of the gate layer away from the base substrate; The second source-drain metal layer has a conductive portion, which serves as a second electrode plate of the storage capacitor and is arranged to overlap with the first electrode plate of the storage capacitor.

17. A display device, wherein: A display panel comprising any one of claims 1-16.

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