Digital integrator

Abstract

A digital integrator (100) arranged to receive a digital input (102) as a plurality of bits, each bit capable of being in a first state or a second state, the digital integrator comprising: for each input bit: i) a counter circuit (110) arranged to operate at a first clock rate and arranged to receive the input bit, count when the input bit is in the first state, and provide a counter output (114) based on the present count; ii) a weighting unit (130) having an associated weighting value, the weighting unit arranged to operate at a second clock rate, arranged to receive the counter output (114), and arranged such that when the counter output (114) indicates a change of count by at least a threshold amount, the weighting unit (130) outputs a multiple of the weighting value as a weighted output; the digital integrator further comprising: a summation unit (140) arranged to operate at the second clock rate and arranged to sum the weighted outputs from the plurality of weighting units (130) to produce a summation output; and an integrator unit (150) arranged to operate at the second clock rate and arranged to integrate over time a plurality of summation outputs to produce an integrated value; wherein the first clock rate is faster than the second clock rate. This arrangement splits the integration of digital inputs into two stages, the first stage in the counters and the second stage in the integrator unit. The two stage approach has the benefit that the two stages operate at different clock rates with the counters operating at a faster clock rate than the summation unit and the integrator unit.

Description

[0001] Digital integrator

[0002] Background of Invention

[0003] The invention relates to digital integration. For example, it is often desirable to integrate, or accumulate, a series of digital values. Such series of digital values can arise in various applications, especially where there are repeated measurements of the same or a similar item or event. Several such scenarios occur in digital processing of radio frequency signals, either for communication or sensing (e.g. radar). In particular, in most radio frequency applications, transmissions may be restricted by regulations to be below a certain power level and / or within a certain frequency band and / or transmitted in restricted times, locations and / or directions. This power level can be so low that noise is significant, or even the dominant part of any received signal. However, by making repeated measurements of a desired signal, even such signals transmitted below the noise level can be successfully received and processed as the repeated measurements of the desired signal add up while the random noise signals average out. Processing of such signals generally involves taking a repeated series of measurements and integrating them (accumulating them or summing them up). To give one specific example, ultrawideband impulse radar systems transmit a large number of pulses at very low power such that received reflections of those pulses are typically below the noise floor. By sending multiple identical pulses and integrating the corresponding multiple echoes over time, the reflected signal can be identified and a distance can be calculated to the object that reflected the pulses. Normally other characteristics such as a velocity can also be obtained, and with multi-antenna systems, angle to target can be obtained. Another specific example of accumulating repeated signals is the reception of global satellite navigation system transmissions from a satellite. The limited power transmitted by the satellite combined with the large distance from satellite to receiver results in very weak signals at the receiver which are much lower than the noise level. However, by appropriate integration of multiple measurements, the low power signal can be recovered. of Invention According to a first aspect, there is provided a digital integrator arranged to receive a digital input as a plurality of bits, each bit capable of being in a first state or a second state, the digital integrator comprising: for each input bit: i) a counter circuit arranged to operate at a first clock rate and arranged to receive the input bit, count when the input bit is in the first state, and provide a counter output based on the present count; ii) a weighting unit having an associated weighting value, the weighting unit arranged to operate at a second clock rate, arranged to receive the counter output, and arranged such that when the counter output indicates a change of count by at least a threshold amount, the weighting unit outputs a multiple of the weighting value as a weighted output; the digital integrator further comprising: a summation unit arranged to operate at the second clock rate and arranged to sum the weighted outputs from the plurality of weighting units to produce a summation output; and an integrator unit arranged to operate at the second clock rate and arranged to integrate over time a plurality of summation outputs to produce an integrated value; wherein the first clock rate is faster than the second clock rate.

[0004] This arrangement splits the integration of digital inputs into two stages. The first stage takes place in the counters. The second stage takes place in the integrator unit. This differs from a standard digital integrator with a single stage in which input values are simply passed in sequence to a summation unit which stores a running total and adds the new value to the running total when it becomes available. The two stage approach of this invention has a particular benefit that the two stages operate at different clock rates. In particular, the counters operate at a faster clock rate than the summation unit and the integrator unit. The integrator unit (often implemented in an SRAM memory) tends to have a high power consumption, so by allowing this part of the integrator to run at a slower clock rate, the power consumption of the integrator as a whole can be reduced. The counters of the first stage can be implemented in a more power efficient manner so that they can be run at the full clock rate, but with a reduced power consumption compared to more typical integrator designs.

[0005] Another notable difference between this invention and existing designs is that the first stage of integration (the counters) is done on a bit-wise basis, i.e. each bit of the digital input is integrated separately (each bit goes to a different counter). Counter-intuitively, this results in the individual bits of one particular digital input not passing through the integrator at the same rate. For example, when one counter output (corresponding to integrations of one bit) passes the threshold amount and is fed to the second stage, there is no guarantee (or even likelihood) that the other bits of that particular digital input will also be fed to the second stage. Instead, they will filter through from the first stage to the second stage at different times. Allowing the input values to separate in this manner allows the first stage to be implemented in a power efficient manner. As all bits will eventually pass through the second stage and be duly processed, the end result of the integration (the integrated value) is still correct, provided that the counters are not allowed to cycle through a complete loop without being duly processed by the second stage.

[0006] In some implementations, the counters could each be a single bit counter. Such implementations would reduce peak power consumption by splitting the overall power requirements into two stages which no longer need to operate simultaneously. The front-end part, i.e. the first stage, which counts the input bits could be operated (and consume power) while the second stage is dormant (or at low power consumption). The second stage could then operate (and consume power) while the first stage goes dormant (or low power). The second stage would simply read the values of all counters that have performed a count (i.e. that have a count of one). Thus in this embodiment, the threshold amount is one. It should be noted that in this special case, the second clock rate would need to operate at the same speed as the first clock rate.

[0007] However, in many other embodiments, power consumption can be reduced by using larger counters that are capable of accumulating multiple input bits before it becomes necessary to pass them to the second stage. Thus, in some embodiments, each counter is an N-bit counter, where N is greater than or equal to two. It will be appreciated that an N-bit counter can count from zero to 2AN-1. Thus, such multi-bit counters can integrate digital input bits from several digital inputs before it becomes necessary to pass them to the second stage. This allows the second stage to operate at a lower clock frequency.

[0008] It will be appreciated that the number of bits in the N-bit counters determines how high each counter can count before it loops back zero. If a counter loops back to zero before it has been passed to the second stage then counts can be missed and the final integrated value will not be accurate. Therefore the system should be designed to avoid this by ensuring that the counters are read out frequently enough. Larger counters (more bits) will allow more integration in the first (lower power) stage and allow the clock rate of the second stage to be slower (thus saving power). However, larger counters take up more area and therefore represent a cost that must be balanced against the power saving. As there is one counter for each bit of the digital input value, the size of the counters can mount up quickly. In some cases, several such systems need to operate in parallel to accumulate (integrate) multiple values of a received signal. For example, this can be the case for radar systems where a received signal is sampled at multiple points in time to detect objects at several potential ranges (the samples are usually referred to as sampling multiple range bins). As each range bin may need to accumulate signal from multiple transmissions (to be detectable above the noise floor), each range bin needs its own integrated value and thus its own set of counters (one counter for each bit in the digital input. Thus, for example, in a radar system with 192 range bins and with a 10-bit ADC outputting a 10-bit digital input value for each sample, 1920 counters will be required. It will therefore be appreciated that the size of the counters can quickly become an area constraint. The counter size is therefore a trade-off between power and area. In some embodiments, N is between three and ten. In some embodiments N is between four and eight. In some particular examples, N is six, i.e. each counter is a six-bit counter (capable of counting from 0 to 63).

[0009] The counters need not all be of the same type. All that matters is that they are capable of counting the digital input bits reliably as they are received. However, in general it will be convenient to design all counters to be of the same type. Any type of counter can be used (e.g. a multi-bit register, a thermometer coded counter, a shift register, etc.). However, as area is often a constraint, as discussed above, an area efficient counter is desirable. Further, power efficient counters improve the power efficiency of the first stage of the integrator. In some embodiments therefore each counter is a ripple counter. Ripple counters have a low power consumption and can be implemented efficiently with a series of flip flops. In particular, ripple counters are asynchronous counters in which each bit feeds into the next bit such that the effect of a new count at the input (the least significant bit, LSB) ripples through the counter towards the most significant bit, MSB. One example implementation of a ripple counter is a series of toggle flip flops, the output of each toggle flip flop feeding into the clock input of the next flip flop. As each flip flop triggers only on one edge (rising edge or falling edge), each flip flop in the chain toggles at half the speed of the preceding one. This results in the input (toggle input of the LSB flip flop) rippling through the chain to form a binary count of the number of times the input flip flop has toggled.

[0010] Thus, in some embodiments each ripple counter comprises a set of series- connected toggle flip flops such that each bit of the counter is represented by the state of one toggle flip flop. It will be appreciated that the present count of the counter can be obtained by reading the states at the output of each flip flop.

[0011] As discussed above, larger counters can hold larger counts and thus do not need to be read out as frequently as they will not overflow or loop round as often. It is important not to let a counter loop round in value by a full cycle as counts may then be lost (in a six-bit counter, 66 counts is indistinguishable from 2 counts. Therefore the counter must not be allowed to count more than 63 times before it is processed by the weighting unit). Thus the second clock rate must operate fast enough to ensure that no counter counts through a full loop. In some implementations, this puts a restriction on the second clock rate that the ratio of the first clock rate to the second clock rate is less than or equal to the maximum positive integer that can be represented by the counter (e.g. a ratio of 63 for a 6 bit counter). However, as will be discussed further below, for certain particularly convenient implementations, a faster second clock rate is desirable (or equivalently a larger counter for a given second clock rate). Thus, in some embodiments the ratio of the first clock rate to the second clock rate is less than half the maximum positive integer that can be represented by the counter. Expressed in an alternative fashion, the ratio of the first clock rate to the second clock rate is less than 2A(N-1), where N is the number of bits in the counter. Expressed in another manner, the ratio of the first clock rate to the second clock rate is less than the binary value represented by the most significant bit of the counter (32 for a six-bit counter). It may be noted that while a ratio of 2A(N-1) is feasible in theory, it is generally preferred to keep the ratio less than this so as to allow a margin in case of some clock jitter. Any clock jitter that could push two consecutive read-outs longer than 32 digital input values could result in missed counts in certain implementations.

[0012] There are many ways in which the counter values may be used to determine a change of count by at least a threshold amount. In some embodiments each time the counter value is read (by the weighting unit) it is stored. The next time the counter is read, its value can be compared to the stored value to determine the difference and the difference can be compared with the threshold. It may be that there is a power saving to be made by avoiding further processing when the difference is below the threshold value, i.e. it may be beneficial to wait until the counter has accumulated at least a certain amount before engaging the next level of processing. As noted above, it is important to avoid the risk of a counter looping, so the threshold value in such cases may be set as half the maximum counts of the counter. This is because it is generally more power efficient to avoid checking the counter value when it cannot have reached the threshold. However, the counter must then be unable to cycle round in less than two checking periods. Thus, a second clock frequency operating at ratio more than (i.e. faster than) 1 in 2A(N-1) combined with a threshold value of half the maximum value meets this criterion with good power efficiency.

[0013] In some embodiments, when a full counter value (i.e. all bits of the counter) is read and passed to the weighting unit, the counter may be reset to zero (as all counts have now been processed). This avoids the need to store a previously read value of the counter and thus saves on the area needed for storage (but requires the extra complexity of a reset mechanism). When the counter is reset to zero, there is also no need for further processing of the counter value (e.g. calculating a difference from a previous value). Instead, the counter value can simply be passed as is to the weighting unit. In some embodiments each counter output is a single bit of the respective counter. Using only a single bit of the counter value rather than the whole (multi-bit) value allows for further simplifications in the processing circuitry and further power savings. It will be appreciated from the following that in principle any bit of the counter value can be used as the single bit, but in general the best efficiency gains will be made with more significant bits and therefore in some embodiments the counter output is the most significant bit of the respective counter.

[0014] As the counter counts up in value, each bit toggles state once every 2An counts, where n is the bit position of the bit in question. Therefore, watching for a change of state of a single bit is equivalent to detecting a change of count by a threshold of 2An. Using the most significant bit in a six-bit counter as an example, as the counter counts up, the MSB will change state every 2A(N-1) = 32 counts. Therefore taking the MSB as the counter output makes it very easy to check whether the counter value has changed by at least a threshold amount of 32.

[0015] Accordingly, in some embodiments each weighting unit is arranged to check for a change of state of its respective counter output bit.

[0016] As above, checking for a change of state of the bit requires storing the previous state of the bit (at the time at which it was last checked). However, this storage is now only a single bit and is thus only a small area penalty. In one implementation, the digital integrator comprises a toggle state detector arranged to monitor the single counter bit for a change of state and to operate the weighting unit each time the single bit toggles state.

[0017] Also as above, the storage requirement for a previous state (and any associated toggle state detector) can also be avoided by resetting the single bit each time it toggles. Thus, in some embodiments when a change of state of the counter output bit is detected, the weighting unit resets that bit of the counter. Essentially, every time the bit toggles from a 0 to a 1 (indicating a count of at least 32 for the MSB of a 6-bit counter), the bit is reset to a 0. This resetting is equivalent to a subtraction of 2An from the counter value where n is the bit position (e.g. a subtraction of 32 for the MSB (bit position 5 of a six bit counter in which n ranges from 0 to 5). This arrangement simplifies the onwards processing such that the weighting unit is operated every time it receives a 1 on the counter output bit. This is very simple and power efficient. It will be appreciated that the weighting unit could equivalently be operated when a bit is 0, with appropriate adjustment to the rest of the processing (e.g. the MSB would not to be initialised to a ‘T). In general each weighting unit is arranged to check if its respective counter output bit is in a predefined state.

[0018] Where the output from the counter is a single bit, the respective weighting unit only has a single bit to process. That bit represents a particular number of counts from the corresponding digital input bit that need to be accumulated (integrated), so the weighting unit can multiply its weighting value by that number and pass the product to the summation unit so as to contribute a total weighted value to the running total. However, the multiplication (and the power required for it) can be avoided. In particular, providing that each counter output is the same counter bit (e.g. they are all the MSB) then the multiplier is common to all weighting units and the multiplication can be delayed until later. Therefore, in some embodiments the weighting unit is arranged to output a single multiple of its weighting value upon detection of a change of state. Thus when, for example, the MSB (as the counter output) toggles, the weighting unit detects the change of state and determines that (at least) 32 counts have taken place which have not yet been processed.

[0019] However, rather than outputting 32 multiplied by the weighting value (which is a viable implementation), the weighting unit outputs a single weighting value to the summation unit for integration. Later in the process the total in the integrator unit can be multiplied by 32 (or another appropriate value depending on the counter size I counter output bit) in a single operation which is more power efficient. This arrangement is particularly convenient as the single bit output from a binary counter always results in a multiplier which is a power of two. The final multiply operation on the integrated value can therefore be accomplished with a simple (and power efficient) bit shift operation by a number of bits corresponding to the bit position of the counter output bit (e.g. left shift five bits to multiply by 32 for the MSB of a six-bit counter).

[0020] The weighting value of each weighting unit may include various factors that can be applied to ensure that the respective bit being processed contributes the correct amount to the final integrated value. At one basic level, each bit of the digital input carries a different weight due to its bit-position in that digital input. For example, if the bits of the digital input are a binary representation of a number, then each bit of that number carries a weight of 2An, where n is the bit-position (i.e. weights of 1, 2, 4, 8 ... for bit positions, n = 0, 1 , 2, 3 ... ). These weights can be applied by the weighting units. The outputs of the various weighting units can then simply be added up by the summation unit to produce a summation output that can be directly added to the running total of the integrated value. Accordingly, in some embodiments the weighting value for each weighting unit includes a bit-value multiplier equal to the radix of the digital input raised to the power of the corresponding digital input bit position.

[0021] However, in some implementations, the bits of the digital input do not represent a binary number in the sense that they are not a base-2 representation, i.e. not a number with radix 2. This can for example be beneficial when the digital input is the output from an ADC, the internal workings of which may suffer from process variations that can cause problematic outputs. For example, with a SAR ADC that uses a capacitive DAC to determine the digital output, the capacitors of the DAC array would normally be sized with ratios of two for a binary output. However, process variations can cause those capacitors to be larger or smaller than intended which can result in the ADC comparisons not providing correct outputs for a given input. One mechanism to improve accuracy is to undersize the capacitors so that they have a size ratio of less than two. This provides some redundancy in the conversion process that accommodates the process variations, but a consequence is that the ADC output is now a number with a radix less than 2. When the output of such an ADC provides the digital input, the weighting values in the weighting units can simply be adjusted to compensate for the ADC design by including a weighting factor with the appropriate multiplier. Thus, in some embodiments the radix of the digital input is less than two. By way of example, where the digital inputs are from an ADC with a radix of 1.8 to accommodate process variations, the weighting units can have weighting values that include a factor of 1 (for the weighting unit corresponding to digital input bit position 0), a factor of 1.8 (for the weighting unit corresponding to digital input bit position 1), a factor of 1.8A2 = 3.24 (for the weighting unit corresponding to digital input bit position 2), etc. The weighting value can include other correction factors as well as a radix-based multiplier. For example, taking the example of the SAR ADC with capacitors subject to process variation, a calibration process can be used to determine the actual sizes (or capacitances) of the capacitors and how much they deviate from their intended sizes (or capacitances). When the capacitor values are known more precisely, their influence on the digital output of the ADC is known more precisely. Effectively, the radix multipliers for each bit of the digital input are no longer a simple geometric series, but are calibrated values. For example, instead of the ideal values of 1 , 1.8, 3.24, ... as discussed above, an individual implementation may have values (due to process variation) of 0.95 (0.05 too low), 1.82 (0.02 too high), 3.30 (0.06 too high), etc. By determining these values (through calibration), the appropriate (and more accurate) weighting values can be used by the weighting units so as to produce a digital representation of the analogue input that more accurately reflects that analogue value.

[0022] It should be noted that the capacitor sizes in an ADC are not the only cause of inaccuracy in the digital input. The charges on the capacitors in an ADC are also dependent on the reference voltages applied to those capacitors in the conversion process. Not all ADCs use the same reference voltage for each capacitor, but may instead reduce the larger capacitor sizes by applying higher reference voltages to them. The reference voltages may also be subject to process variations or the like that can be identified and therefore corrected. Therefore more generally, in some embodiments, the weighting value for each weighting unit includes a correction factor to correct for process variation in a component upstream of the digital integrator. The component may be any analogue or digital component and it may be an active or passive component.

[0023] The weighting values may additionally correct for other factors (which may or may not be bit-specific). For example, the weighting values may include a correction factor to compensate for CDAC mismatches between different sub-ADCs and / or to compensate for differing gains in different sub-ADCs.

[0024] It has been recognised that the above processes can be incorporated into the two- stage integrator arrangement of this invention despite the separation (and processing asynchrony) of the various bit streams as the operations on each bit are still linear and can thus be reordered without affecting the final result.

[0025] As discussed above, in some embodiments the upstream component is a capacitor and / or a voltage source in an analogue to digital converter. Specifically, in some embodiments the capacitor may be a capacitor of a capacitive DAC in a SAR ADC. In some embodiments the voltage source may be the voltage source for a capacitive DAC in a SAR ADC. In other embodiments the SAR ADC may have a different topology, e.g. a current-steering DAC and the upstream component may be a current source. In yet further embodiments the ADC may be a resistive ladder ADC or a delta-sigma ADC. Process variations or device mismatch in any of these topologies could result in errors which can be corrected in the weighting units. It will be appreciated that different variation mechanisms will dominate in different architectures and implementations.

[0026] The processes described above can be continued as long as the digital inputs are to be integrated. The integrator unit will accumulate the values from the counters and the weighting units as they become available. At any given time during this process there will be an error in the integrator unit due to any uncounted values in the counters. Uncounted values may be present for various reasons depending on the implementation choices, but may for example be present due to the slower second clock rate (the counters operate at the faster clock rate and may have made further counts since the last second clock rate operations), or due to counter values having not exceeded the threshold amount for processing (e.g. where the counter output is a single bit, only that bit is processed by the weighting units. Any other bits in the counter remain unprocessed at that time). The digital integrator may be used to provide a rolling average of the digital input continuously in time (i.e. for a continuous stream of digital inputs). After sufficient operations the error due to uncounted bits in the counters may become small enough to be inconsequential. However, in other implementations there is a finite number of digital input values to be integrated and an accurate total is desired. In such cases, after the last digital input has arrived, the final uncounted bits in the counters can be extracted and processed and added to the integrator unit to produce an accurate total of all digital inputs. Thus in some embodiments the digital integrator is arranged to carry out a final integration step after all digital inputs have been processed, in which all unprocessed counts in the present count value of each counter are output to the respective weighting units, multiplied by the respective weighting values and combined with the integrated value.

[0027] It should be noted that the method of combining with the integrated value will depend on implementation choices discussed above. For example, where the weighting units have extracted and processed full counter values, or where they have multiplied up a single bit counter input according to its bit-position, the final stage can be simple processing of counter values (multiply by weight and add, as in all previous processing steps). However, where the weighting units have processed single bit counter outputs without any further multiplication (e.g. where they outputted a single weighting value), the integrated value needs to be multiplied up appropriately before the final addition (because the final addition processes a full counter value rather than a single bit). For example, in the examples discussed above where the MSB of a six-bit counter was used as the input to the weighting units, the integrated value should be multiplied by 32 (easily accomplished with a 5 place bit-shift) to scale it up appropriately before adding the final weighted counter values.

[0028] As discussed above, the digital integrator described here may be used in many different implementations. However, it has been found to be particularly beneficial in an impulse radar system where a defined stream of pulses needs to be integrated for improved signal to noise ratio and where power consumption can be an extremely important consideration (especially for instance for battery-powered devices such as portable computing devices or wearable devices).

[0029] Therefore, in some embodiments the invention provides an impulse radar system comprising an analogue to digital converter and a digital integrator as described above (optionally including any of the optional features discussed above); wherein the analogue to digital converter is arranged to digitise a radar receive signal; and wherein the output of the analogue to digital converter provides the digital input to the digital integrator. The impulse radar system may be an ultrawideband impulse radar system. Operation in the ultrawideband spectrum requires very low power transmission and a consequent need for coherent integration of the received range profile for adequate signal to noise ratio and thus the invention is particularly beneficial.

[0030] For various reasons, one of which is improved spectrum compliance (e.g. in the areas of the spectrum where UWB transmissions are allowed) and another of which is for DC offset cancellation in other system components (e.g. an ADC), the transmitted series of pulses in an impulse radar system may be modulated, e.g. for spectrum spreading which can improve coexistence and link budget. One typical method is biphase modulation where pulses are transmitted with either a positive polarity or a negative polarity according to a pseudorandom sequence that achieves spectrum spreading, but which can be used to recover the transmitted pulses as they are received. Similar modulation schemes are also used in other technologies such as global satellite navigation system signals and IEEE 802.15.4z UWB communications.

[0031] The corresponding despreading mechanism (which is required to allow coherent integration of both positive and negative transmissions) can be incorporated into the digital integrator. Moreover, due to the linearity of the decoding, it can be done at the bit level in the same way as the counters of the digital integrator. For example, each bit can be inverted or not inverted according to a polarity signal (the pseudorandom sequence used for transmission) so as to allow all pulses (positive and negative polarity) to be coherently integrated. In some embodiments the impulse radar system is arranged to transmit a plurality of pulses, each pulse having a positive or negative polarity; wherein each bit of the output of the analogue to digital converter is combined in a logic gate with a polarity signal indicative of the transmitted pulse polarity so as to remove the effect of the transmitted polarity and the outputs of the logic gates provide the digital input to the digital integrator. The logic gate may be an XOR or XNOR gate which makes for a very simple and power efficient decoding scheme which is integrated with the digital integrator.

[0032] As discussed above, a radar system typically samples a range profile at a number of time points to produce a number of range bins. Each range bin generally needs to be accumulated over several pulse transmissions until the signal to noise ratio is sufficient to recover the signal adequately. Therefore an integrator is needed for each range bin. Accordingly, in some embodiments the analogue to digital converter is arranged to process a time sequence of samples of the radar receive signal, each corresponding to a different radar range, and wherein the impulse radar system comprises a digital integrator as described above (optionally including any of the optional features discussed above) for each radar range.

[0033] When operating at high speed, the speed of an individual analogue to digital converter can become a limiting factor. To overcome this, several ADCs are sometimes operated in parallel with the samples being divided between the ADCs is sequence. This arrangement may be referred to as a single time-interleaved ADC comprising a plurality of sub-ADCs. When several such sub-ADCs are in use, it will be appreciated that each has its own individual process variations. Therefore, the calibration process discussed above, whereby the weighting units can correct for process variation, must be done on a per-sub-ADC basis. The weighting units need to know which sub-ADC will provide digital inputs to them and then correct for that sub-ADC. As noted above, a counter must be provided for each bit in the digital input for each range bin in the range profile. In some embodiments, a weighting unit is provided for each counter. In such arrangements, the radar system can be designed such that each counter and each weighting unit always receive digital inputs from the same sub-ADC (e.g. if the number of range bins is an exact multiple of the number of sub-ADCs). Each weighting unit will then only need a single weighting value which is always applicable to all inputs that it receives. However, in other implementations it may be desirable (e.g. from an area saving perspective) to reuse the weighting units such that at least some weighting units handle multiple range bins. In such cases, the weighting units may receive digital inputs from different sub-ADCs and will need to store weighting values for those different sub-ADCs and select the appropriate weighting value accordingly. Thus, in some embodiments the analogue to digital converter is a time-interleaved ADC comprising a plurality of sub-ADC units that each sample and quantise the analogue input signal in sequence, and provide digitised values to the digital integrators for the plurality of range points in sequence; and wherein each weighting unit of each digital integrator has an appropriately calibrated weighting value for each sub-ADC from which it may receive a digital input and wherein each weighting unit is arranged to select the calibrated weighting value according to the sub-ADC that provided the current digital input.

[0034] By way of example, in a radar system with 192 range bins in the range profile, and with a time-interleaved ADC having 16 sub-ADCs, each range point will always receive digital inputs from the same sub-ADC (because 192 is a multiple of 16). With 10-bit ADCs, such a system requires 1920 counters. However, if the weighting units are reused, then fewer than 1920 weighting units are needed, saving area. For example, if each weighting unit is used to cover counters from four sub-ADCs, then only 480 weighting units are required, but each needs to store four sets of weighting values if it is to correct for process variations in each of the four sub-ADCs that it serves. In total, there will be sixteen sets of weighting values, one set for each sub-ADC, each set comprising a weighting value for each input bit (e.g. weights wO to w9 for a ten bit digital input value). These weighting values can be shared amongst the instantiations of the weighting units as required, each weighting unit having four sets of weighting values corresponding to the sub-ADCs that it serves. In fact, weighting units can be reused much more than this. In some examples, only two sets of weighting units are provided, each serving eight of the sixteen sub-ADCs. Each set of weighting units comprises one weighting unit per bit of the digital input, so in the example of 10-bit inputs, such examples have only 2 * 10 = 20 weighting units.

[0035] Accordingly, it will be appreciated that in some embodiments, each weighting unit has a memory to store a weighting value. In some embodiments the memory may store a plurality of weighting values.

[0036] In some embodiments the impulse radar system is arranged to transmit a sequence of pulses and wherein the impulse radar system is arranged to carry out the final integration step discussed above after all transmitted pulses have been received and processed.

[0037] According to a second aspect, the invention provides a method of digitally integrating a series of digital inputs, each digital input comprising a plurality of bits, each bit capable of being in a first state or a second state, the method comprising: for each input bit: receiving the input bit and counting in a counter at a first clock rate when the input bit is in the first state; providing a counter output based on the present count from the counter to a weighting unit operating at a second clock rate and having an associated weighting value; and when the counter output indicates a change of count by at least a threshold amount, the weighting unit outputting a multiple of the weighting value as a weighted output; summing the weighted outputs at the second clock rate to produce a summation output; and integrating over time at the second clock rate a plurality of summation outputs to produce an integrated value; wherein the first clock rate is faster than the second clock rate.

[0038] It will be appreciated that all of the optional features discussed above in relation to the first aspect are equally applicable to the second aspect. It will also be appreciated that in some embodiments the method according to the second aspect may be carried out using a digital integrator according to the first aspect (optionally including any of its optional features).

[0039] The concept of bitwise integration of a digital input is considered to be separately inventive. Such bitwise integration can be accomplished fully within the counters (providing they are large enough) without requiring the second integrating stage. Such integration could all be carried out at a single clock rate.

[0040] An alternative way of considering the first aspect of the invention is as a digital integrator arranged to receive a digital input as a plurality of bits, each bit capable of being in a first state or a second state, the digital integrator comprising: for each input bit: i) a counter circuit arranged to operate at a first clock rate and arranged to receive the input bit, count when the input bit is in the first state, and provide a counter output based on the present count; ii) a weighting unit having an associated weighting value, the weighting unit arranged to operate at a second clock rate, arranged to receive the counter output, and arranged such that when the counter output indicates that a predetermined change has occurred, the weighting unit outputs a multiple of the weighting value as a weighted output; the digital integrator further comprising: a summation unit arranged to operate at the second clock rate and arranged to sum the weighted outputs from the plurality of weighting units to produce a summation output; and an integrator unit arranged to operate at the second clock rate and arranged to integrate over time a plurality of summation outputs to produce an integrated value; wherein the first clock rate is faster than the second clock rate.

[0041] Likewise, an alternative way of considering the second aspect is as a method of digitally integrating a series of digital inputs, each digital input comprising a plurality of bits, each bit capable of being in a first state or a second state, the method comprising: for each input bit: receiving the input bit and counting in a counter at a first clock rate when the input bit is in the first state; providing a counter output based on the present count from the counter to a weighting unit operating at a second clock rate and having an associated weighting value; and when the counter output indicates that a predetermined change has occurred, the weighting unit outputting a multiple of the weighting value as a weighted output; summing the weighted outputs at the second clock rate to produce a summation output; and integrating over time at the second clock rate a plurality of summation outputs to produce an integrated value; wherein the first clock rate is faster than the second clock rate.

[0042] According to a third aspect of the invention, there is provided a digital integrator arranged to receive a digital input as a plurality of bits, each bit capable of being in a first state or a second state, the digital integrator comprising: for each input bit: i) a counter circuit arranged to receive the input bit, count when the input bit is in the first state, and provide a counter output based on the present count; and ii) a weighting unit having an associated weighting value, the weighting unit arranged to receive the counter output, and arranged to output a product of the counter output and the weighting value as a weighted output; the digital integrator further comprising: a summation unit arranged to sum the weighted outputs from the plurality of weighting units to produce an integrated value.

[0043] It will be appreciated that this third aspect of the invention shares much in common with the first aspect and in particular, the additional features that are present in the first aspect that are not present in the third aspect can be added to the third aspect if desired. In the same way, all optional features that are described above in relation to the first aspect can optionally be applied to the third aspect.

[0044] The bitwise integration has particularly simple application when the digital inputs are radix-2, i.e. binary number inputs. In such cases, the weighting units simply have to multiply by powers of two which can be done by bit shifting without the need for complicated multiplication. The shifted results from the weighting units can then simply be added for the final total. Thus, in some embodiments of the third aspect, the weighting unit is arranged to output a product of the counter output by bit shifting the counter output according to the weighting value.

[0045] It will also be appreciated that the bitwise integration is also particularly interesting for non-radix 2 applications for a different reason. Non-radix-2 outputs from an ADC are still represented by binary style Ts and ‘0’s and cannot simply be added or multiplied by the same standard addition or multiplication processes that are used for binary numbers. Therefore, standard accumulation techniques are not normally applicable until after the non-radix-2 number has been converted to a standard binary (radix-2) representation. This would require multiplications to be performed on each non-radix-2 input before it can be accumulated (integrated). This is also a power hungry process. The bitwise integration process allows the non-radix-2 number to be accumulated (integrated) before any correction factors are applied. This allows the power hungry multiplication operations to be performed after accumulation, and thus less frequently. It will be appreciated that this is a particular benefit of this arrangement.

[0046] According to a fourth aspect of the invention, there is provided a method of digitally integrating a series of digital inputs, each digital input comprising a plurality of bits, each bit capable of being in a first state or a second state, the method comprising: for each input bit: receiving the input bit and counting in a counter when the input bit is in the first state; providing a counter output based on the present count from the counter to a weighting unit having an associated weighting value; and the weighting unit outputting a product of the counter output and the weighting value as a weighted output; and summing the weighted outputs to produce an integrated value.

[0047] It will be appreciated that all of the optional features discussed above in relation to the first and third aspects are equally applicable to the fourth aspect. It will also be appreciated that in some embodiments the method according to the fourth aspect may be carried out using a digital integrator according to the first aspect or third aspect (optionally including any of its optional features).

[0048] Certain embodiments of the invention will now be described, by way of example only, and with reference to the accompanying drawings, in which:

[0049] Figure 1 shows a digital integrator according to the invention;

[0050] Figure 2 shows the main signal processing components of an impulse radar system for processing the digital output samples from an ADC;

[0051] Figure 3 illustrates a bit skimming process according to some embodiments; and Figure 4 illustrates the number of bits (or bit width) involved in various stages of the digital integrator shown in Figure 1.

[0052] Figure 1 shows a digital integrator 100. The particular example shown in Figure 1 is for processing the range profile of an impulse radar system. In this example, the range profile has 192 range bins (distinct samples of the receive signal sampled at different times). As indicated by the annotation “x192” in the bottom right, the hardware of the digital integrator 100 is repeated 192 times in this example so as to process all 192 range bins. However, it will be appreciated that other embodiments may include only a single digital integrator 100 as shown.

[0053] The digital integrator 100 shown in Figure 1 receives a digital input signal 102 which in this case comprises 10 bits (as indicated by the 710” marker). The digital input in this example is passed into a set of XOR gates 106. There is one XOR gate for each bit of the digital input (i.e 10 XOR gates 106 in this example as indicated by the “x10” annotation). The other input to the XOR gates 106 is a pulse phase input 104. This pulse phase input 104 is common to all bits, i.e. common to all ten XOR gates. The pulse phase input 104 depends on the polarity of the pulse that was transmitted. The transmitted pulses in this example were transmitted using Binary Phase Shift Keying (BPSK) which modulates the outgoing transmit pulses as positive polarity or negative polarity according to a pseudorandom number (PRN) sequence. The purpose of this is for spectrum spreading so as to avoid spectrum violations that may otherwise occur with repeated pulse transmissions. The XOR gates 106 despread the signal in the receiver by removing the modulation of the PRN. The pulse phase input 104 is based on the PRN used for transmission. For example, the pulse phase input 104 may be a ‘0’ for a positive pulse and a T for a negative pulse. The XOR gate 106 therefore either inverts the incoming bit of the digital input 102 (if the pulse phase input 104 is a ‘T) or passes the incoming bit uninverted (if the pulse phase input 104 is a ‘0’). It will be appreciated that not all embodiments will receive a modulated signal and may therefore not require the XOR gates 106 and the pulse phase input 104. Instead, the digital input 102 can simply be passed straight to the ripple counters 110. In other examples, some alternative dispreading or decoding device can be used in place of the XOR gates 106.

[0054] The XOR gates 106 each output a modified (despread or demodulated) bit that corresponds to a bit of the digital input 102. Each of these bits are passed to a ripple counter 110. There are therefore ten ripple counters 110 in this example (one for each bit of the digital input), all operating in parallel on one bit of the digital input 102 (as denoted by the annotation “x10”). In embodiments which do not have any demodulation, the bits of the digital input may each be passed directly to a ripple counter 110.

[0055] Each ripple counter 110 comprises six toggle flip flops 112a-f connected in series (of which three are shown in Figure 1 , 112a, 112b, 112f). The first toggle flip flop 112a receives the data bit that is to be counted, i.e. the (demodulated) bit of the digital input 102. The clock input of the first toggle flip flop 112a (although not shown) is driven by the same clock as the PRF used to transmit the pulses. Therefore the first toggle flip flop 112a will operate on each new digital input that is to be processed.

[0056] If the toggle input T of the first toggle flip flop 112a is a T, then the ripple counter 110 should increment its counter value. If the toggle input T is a ‘O’, then the ripple counter 110 should not increment its counter value. If the toggle input T of the first toggle flip flop 112a is a T then the output of that toggle flip flop 112a changes state (toggles). This output is fed into the clock input of the next (second) toggle flip flop 112b via an inverter. The second toggle flip flop 112b receives a T at its toggle input T so that its output always toggles whenever it receives a clock input. The same applies for all subsequent toggle flip flops 112c-f. If the toggle flip flops 112a-f are arranged to process their toggle inputs T on a rising edge at the clock input, then the first toggle flip flop 112a operates once per clock cycle of the main clock (at a first clock rate). The rate at which subsequent toggle flips flops 112b-f operate is dependent on the original input, but as each receives a T at its input, each operates at half the rate of the previous one. For example, if the output of toggle flip flop 112a toggles from a ‘0’ to a ‘T (a rising edge), the inverter changes this to a falling edge and the second toggle flip flop 112b does not operate. When the next count arrives and the first toggle flip flop toggles from a T to a ‘0’ (a falling edge), the inverter changes this to a rising edge and the second toggle flip flop toggles its output. Thus, this arrangement ensures that each toggle flip flop 112b-f toggles for every two toggles of the preceding flip flop. In this one, the outputs of the toggle flip flops 112 of ripple counter 110 represent a rolling binary count that increases by one every time the first toggle flip flop 112a receives a T with its clock trigger. If the ripple counter 110 reaches the maximum positive integer that it can represent (63 for a six bit, i.e. six flip flop counter) then the next count causes it to loop back to zero. It will be appreciated that ripple counters 110 could be arranged to operate on falling edges rather than rising edges. More generally, the invention does not depend on the counters being ripple counters 110. In other embodiments any other form of counter can be used that counts the number of times the input bit is in a certain state (e.g. a ‘1’ or high state). However, ripple counters are simple and power efficient in operation, hence their use in this embodiment.

[0057] As can be seen in Figure 1 , the counter output 114 of each ripple counter 110 is taken from its most significant bit (MSB) which in this case is the output of the sixth toggle flip flop 112f. As there are ten parallel ripple counters 110, each ripple counter 110 has its own counter output 114 based on its own MSB. Thus there are ten ripple counter outputs as denoted by the ‘710” marker.

[0058] As will be discussed further below, the counter output 114 does not necessarily need to be the MSB of the counter 110. It could be a different single bit from the counter (e.g. the bit MSB-1) or it could be all bits or a combination of bits of the counter. For example, the counter output 114 could be the full value of the counter in its present state. The following discussion and Figure 1 are on the basis that the output 114 is a single bit, the MSB.

[0059] The set of ripple counter outputs 114 (ten in this example) are all passed to toggle checkers 120. In this example, there are ten toggle checkers (as indicated by the “x10” annotation), although it will be appreciated that a single multi-bit toggle checker could be implemented instead if desired. Each toggle checker 120 receives a single ripple counter output 114. It will be appreciated that this input is just a single bit (i.e. a T or a ‘0’) depending on the current state of the MSB of the respective counter 110. The toggle checker 120 monitors this bit and detects when it changes state (toggles), i.e. it monitors for a change from ‘0’ to T and also for a change from T to ‘O’. It will be appreciated that in other embodiments it could monitor for only one of these transitions, with suitable adaptions to ensure appropriate counting. Each time the output bit 114 changes state, this is indicative of the MSB of the respective counter 110 having counted 2A(N-1) times, where N is the number of bits in the counter 110. Thus, in this example, where N is 6, a change of state of the MSB (and of the counter output 114) occurs every time the counter 110 has counted 32 times. Thus, the MSB can only toggle its state at a maximum rate of 1 / 32 (more generally at a rate of 1 / 2A(N-1)) of the first clock rate. Thus, the toggle checkers 120 and all subsequent processing parts can be clocked at a lower rate (second clock rate) which allows a significant power saving. As noted in the figure, the XOR gates 106 and the ripple counters 110 (strictly the first toggle flip flop 112a of each ripple counter 110) are clocked at the main (first) clock rate as indicated by the dotted box 125. In this example, the main clock rate is indicated as the PRF (pulse repetition frequency) as a new digital input will be acquired for each range bin with each transmitted pulse of the impulse radar system. However, it will be appreciated that different clock rates may apply in other implementations. The toggle checkers 120 and all subsequent processing elements discussed below and shown in Figure 1 are clocked at a second, lower, clock rate as indicated by dotted box 127 which, as indicated, is at PRF 130, i.e. it is 1 / 30thof the PRF clock rate. It may be noted that this is slightly faster than the theoretical limit of 1 / 32ndof the PRF clock rate. This is because it is important to avoid missing counts due to clock jitter or minor processing delays. Therefore a small margin is desirable in order to ensure that proper operation occurs and that no counts are missed in the slower processing stage.

[0060] When a toggle checker 120 determines that its input 114 has toggled, it sends a trigger to a corresponding weighting unit 130-0, 130-1 , ... 130-9. It will be appreciated that, although the weighting units 130-0 to 130-9 are displayed in a slightly different manner in Figure 1 (each shown separately side by side rather than indicated as a set of stacked boxes), there is one weighting unit 130-0 to 130-9 for each toggle checker 120. Thus, a first ripple counter 110 for the first bit of the digital input (least significant bit, LSB) feeds its output 114 into a first toggle checker 120 which sends a trigger to a first weighting unit 130-0. A second ripple counter 110 for the second bit of the digital input (second least significant bit) feeds its output 114 into a second toggle checker 120 (different from the first toggle checker) which sends a trigger to a second weight unit 130-1 , and so on for each bit of the digital input (i.e. ten such processing chains are present in this embodiment).

[0061] The weighting units 130-0 to 130-9 all operate in substantially the same manner, but each has its own stored weighting value (or possibly several as discussed below) that it uses in its processing. Thus detailed operation of only one weighting unit 130-0 will be discussed below, but is representative of all weighting units 130-0 to 130-9.

[0062] The weighting unit 130-0 has a stored weighting value Wo. This weighting value may be stored in the weighting unit 130-0 or otherwise provided to it as an input. The weighting unit 130-0 may operate in a number of different ways. Two examples are set out below, but in each case the output is a multiple (which may be one) of its input.

[0063] In one example (as is illustrated in Figure 1), the weighting unit 130-0 multiplies its input from the toggle checker 120 by its weighting value Wo. In this example, the trigger input from the toggle checker is a T when it detects that a toggle has occurred and a ‘0’ otherwise. Thus, in this example, the weighting unit 130-0 receives a single bit input and multiplies it by a multi-bit weighting value Wo. It will be appreciated that multiplication is not strictly necessary in this example as the weighting unit 130-0 can simply output its weighting value Wo when it receives the trigger from the toggle checker.

[0064] In other examples, the counter output 114 could be more than just a single bit. For example, it could be several bits of the counter 110 and could even be a full counter value representing the present counter state. The toggle checkers 120 could in this case be difference checkers that store the last known value of the counter output 114 and output the difference, i.e. the number of counts that have taken place since the last processing. In this case, the output from the toggle checkers 120 would be a multi-bit value that would be passed to the weighting unit 130-0. The weighting unit 130-0 would then multiply this multi-bit input by its weighting value Wo and output this product (this being a multiple of the weighting value that is not necessarily one).

[0065] The outputs of each of the weighting units 130-0 to 130-9 are all passed into a single summation unit 140 that adds together all of the inputs that it receives and outputs the sum to an SRAM integrator 150 that keeps a running total of the outputs from summation unit 140 that it receives over time. Thus, each output from the summation unit 140 is S = Wo + Wi + ... + Wg. With each clock cycle of the second clock rate (PRF / 30 in this example), the SRAM integrator 150 receives a new value of S and adds it to its running total which is thus an accumulated or integrated value for the whole process.

[0066] As discussed above, the output of each weighting unit 130 is a multi-bit value. The sum of a plurality of such multi-bit values (ten in this example) will have more bits than any of its individual components. Hence the output of the summation unit is potentially a larger number (in terms of number of bits). In this example the output of the summation unit is 15 bits as denoted by the marker 715”. The same applies to the SRAM integrator 150 which sums up multiple outputs from the summation unit and thus likewise needs to be able to process larger numbers. Thus, in this example the SRAM integrator will store a number with more than 15 bits. The number of bits required will depend on implementation and purpose and in particular on the number of digital inputs that are to be accumulated in the SRAM integrator without it overflowing or wrapping. By way of example, in an impulse radar system, a very large number of pulses may be transmitted and accumulated as part of a single measurement, e.g. potentially several tens or hundreds of thousands in some use cases. Therefore the SRAM integrator may store a significantly larger number, e.g. in excess of 30 bits. It will be appreciated that these numbers are given purely by way of example for illustrating the processing.

[0067] The weighting values Wo to Wg are used to weight each processed bit according to its original bit position in the digital input 102. For example, if the digital input 102 is a simple binary output from an ADC then for one particular digital input, the LSB is worth 1, the next bit is worth 2, the next 4, etc., increasing in powers of two. In other words, the radix (or base) of the number is two (a straightforward binary number). In such cases, the weights Wo to Wg include the corresponding weighting component, i.e. the weighting value Wo of weighting unit 130-0 includes a weight of

[0068] 1 (for the LSB), the weighting value Wi of weighting unit 130-1 includes a weight of

[0069] 2 (for the second bit), the weighting value W2 of weighting unit 130-2 includes a weight of 4 (for the third bit), etc.

[0070] However, the radix of the incoming digital input 102 is not necessarily two, but for reasons of ADC design (e.g. to provide overlap and thus mitigate process variations in capacitor sizes, especially in a capacitive DAC of a SAR ADC) the radix of the incoming digital input 102 may be less than two. For example, the radix may be 1 .8. For such digital inputs, the LSB is worth 1 , the second bit is worth 1 .8, the third bit is worth 1.8A2 = 3.24, etc. Therefore the weighting values Wo to Wg can include these weights of 1 , 1 .8, 3.24 etc. so that they give appropriate weight to those bits before they are added together in the summation unit 140.

[0071] The weights Wo to Wg in the weighting units 130-0 to 130-9 need not be based solely on the theoretical radix weights, but can also include other correction factors if desired. One reason why additional correction factors are beneficial is to adjust for process variation in the ADC (or other analogue components that may have affected the digital input). To give one example, in a SAR ADC with a capacitive DAC, the digital output of the ADC typically depends on using the DAC to cancel out a sampled input voltage. The DAC does this by switching each capacitor in an array to either a high reference voltage or a low reference voltage. The capacitors in the array are sized in multiples of a chosen radix (two in many cases, less than two, e.g. 1.8 in others as discussed above). As each capacitor is switched, it contributes a charge to the process of balancing the input voltage that depends on both its capacitance and the reference voltage. Therefore, although a capacitor array may be designed with a certain radix in mind, the actual capacitors vary due to process variations. Similarly, the reference voltages may deviate from their ideal values with process variations. However, the charge contributed by these process variations still contributes to cancelling the ADC sample voltage and therefore affects the meaning of the digital output obtained. By performing a calibration process on the ADC (or more generally on whichever component or circuit is introducing an error that is to be cancelled), the actual contribution of each ADC bit can be ascertained which may not be the exact radix value of the design. For example, in a simple radix 2 system, process variations in capacitor sizes may result in capacitors having sizes of C, 2.05C, 4.03C, 7.99C, etc. instead of 1 , 2, 4 and 8. The weighting values Wo to Wg can be adjusted appropriately (i.e. they can include the calibration correction factor) so that they reflect these calibrated values. This effectively makes the digital input values 102 reflect more accurately the DAC voltage that cancelled the input sample of the ADC and thus makes the digital values 102 more representative of the received signal.

[0072] In a further (and optional) development, the weights Wo to Wg of the weighting units 130-0 to 130-9 may be selectable by the weighting unit (or by some other component of the system) so that each weighting unit 130-0 to 130-9 can handle inputs from different sources. For example, a weighting unit 130-9 (just to pick one as an example, but they all operate the same) could include calibrated radix weights W9 for eight different ADCs that may provide digital inputs 102 to the digital integrator 100. The weighting unit 130-9 in this example needs to be provided with the appropriate weighting value W9 to compensate for whichever ADC supplied the digital input 102 (each ADC being subject to its own specific process variations and thus its own specific calibration). In some embodiments, the weighting unit 130-9 itself may store all the weighting values W9 that it needs and can be provided with a selector input indicating which weight W9 should be used. One reason why multiple ADCs may provide an input to the weighting unit is where the weighting units are reused to save area. For example, in a radar system, each range bin must be integrated separately which means that each range bin needs its own counter 110. However, as the weighting units are clocked at a lower clock speed they can be used to process multiple counters 110 if it is desirable to save area (as fewer weighting units are then required). If a time-interleaved ADC is used to produce the digital inputs 102 then each sub-ADC within the time-interleaved ADC will have its own calibration values and thus the weighting unit 130-9 needs to be able to handle digital inputs from several such sub-ADCs.

[0073] Figure 2 illustrates the process in a more schematic manner in the context of an impulse radar frame (one frame being made up of multiple pulses) which reuses the weighting units 130-0 to 130-9 as described above.

[0074] The overall input to the radar processing system 200 is the input 202 mframejn which is a data stream containing 10 bit numbers, each representing a digital output from a time-interleaved ADC. In this example the time-interleaved ADC has sixteen sub-ADCs, hence the indicator “10b x 16” indicating that the stream contains 16 ADC values each of 10 bits. It will be appreciated that the input stream will in fact contain more than 16 10-bit inputs if it has more than 16 range bins, but the processing is simply multiplied up as the sub-ADCs are reused.

[0075] The pulse phase input 104 is provided to demodulator 204 to despread the signal and allow subsequent processing of positive and negative pulses identically. The output of the demodulator 204 is still sixteen 10-bit numbers. The ripple counter array 220 includes ten ripple counters 110 for each range bin (one for each input bit for each range bin). In this system 200, the weighting units 130-0 to 130-9 are reused so that each can process eight different ADC calibrations. It may be noted that this is eight rather than sixteen (the actual number of sub-ADCs) because the design ensures that only half the sub-ADCs will ever be fed to each weighting unit 130-0 to 130-9. Thus, to accommodate all sixteen ADCs, there are two of each weighting unit 130-0 to 130-9 (i.e. two weighting units 130-0, two weighting units 130-1 , etc.) each handling eight sub-ADCs, hence the indicator “10b x 2” indicating that there are now two 10-bit processing pathways.

[0076] The ADC correction 230 includes the weighting units 130-0 to 130-9 as described above (two of each). The coefficients for the sixteen sub-ADCs (each coefficient correcting for the radix weight and the process variation) are stored in memory 232 and fed in to the weighting units 130-0 to 130-9 according to the sub-ADC associated with the current input being processed. As discussed above, the weighting units 130-0 to 130-9 multiply their input by a weighting value and thus increase the number of bits required, hence the output of the ADC correction 230 is indicated as “15b x 2” to show two groups of weighted values (one for each of the two input streams) each group holding 15 bits worth of data. The weighted outputs of each group are added together in summation unit 240 (the weights of the first group are added together to produce a first sum and the weights of the second group are added together to produce a second sum, these two sums representing different range bins) and then the summed outputs are provided to the SRAM integrator 250 which accumulates each summed output to the appropriate running total. The SRAM integrator 250 holds a running total for each range bin so that over time, a full range profile can be built up with improved signal to noise ratio.

[0077] The arrangement described here with respect to Figures 1 and 2 is very power efficient, at least in part due to the splitting of the integration into two stages - a first stage in the ripple counters 110 and a second stage in the SRAM integrator 150, the second of these stages being operated at a much slower clock rate. The power savings with this arrangement compared with a typical one stage integrator are significant. One implementation of this two-stage design was found to reduce the power consumption of the integration process from 10 milliwatts down to less than 1 milliwatt. Such power savings are of significant value when implemented in battery powered devices such as mobile devices or wearable devices or battery-powered sensors that cannot be wired into a continuous power source.

[0078] A modification that can be made to the operations discussed above involves resetting at least some parts of the counters 110 after they have been read. For example, where the full counter value is read out as the counter output 114, the procedure described above involved storing the previous counter value and checking for a difference. This allows the further processing of the counter data to be made dependent on the difference exceeding a threshold amount (if desired) which may save further power. However, if the counter 110 is reset each time the counter value is processed (e.g. each time it is above the threshold amount) then the counter 110 can be reset so that its count is zero. There is then no need to store a previous value of the counter as any counter value already represents the difference since the last processing. This approach saves the memory and processing requirements of storing and comparing previous counter values. However, it introduces a complexity of resetting the counters 110. The counters 110 would need to be reset at high speed (e.g. within a single clock cycle of the first clock rate) so as not to interfere with new incoming counts. In some counter implementations this functionality may already be present and could readily be used without increased complexity. Accordingly there would be an overall reduction in complexity. In other embodiments, the addition of the reset functionality may be less complex than the storing and comparing functionality.

[0079] Similarly, where the counter output 114 is a single bit, e.g. the MSB, as depicted in Figure 1 , that bit can be reset every time it is processed. It will be appreciated that the complexity of resetting a single bit is minimal and thus can make a significant improvement. Resetting a bit is effectively equivalent to subtracting an amount equal to the binary value of the bit. For example, in the six bit counter 110 shown in Figure 1, the MSB is worth 2A(N-1) = 32, so resetting the MSB is equivalent to subtracting 32 from the counter 110. With this arrangement, the toggle checker 120 only ever expects to see a change from ‘0’ to ‘T in the MSB. When that happens, the weighting units 130-0 to 130-9 are triggered as described above. Then the MSB of the counter 110 is reset back to ‘0’ so that the next state change will again be from ‘0’ to T. Thus the toggle checkers 120 in such embodiments are simplified such that they only need to check for the presence of a T on the MSB rather than checking for a change of state.

[0080] In some embodiments, the toggle checkers 120 can in fact be eliminated altogether by simply passing the MSB state directly as the input to the respective weighting unit 130. The weighting unit 130 can simply multiply the MSB by its weighting value to produce its output. It may be noted that a multiplication by 1 or 0 is fast and efficient and can be accomplished with a single bitwise AND operation. In such implementations, care needs to be taken with the resetting of the MSB discussed above. The resetting must be conditional upon the output being read as a T (i.e. ensuring that the read operation, i.e. the processing of the MSB, has occurred before applying a reset operation. If the read and reset operations are not linked and there is the possibility of a delay between them then a read operation could read a ‘O’, then the counter 110 could flip the MSB to a T before the reset set it back to ‘O’. A conditional reset approach (where the reset is conditional upon a T being read) avoids this situation.

[0081] It is important that resetting is done carefully in such embodiments. For example, it is important to avoid a further count being processed by the counter 110 that would once again toggle the MSB state. If such a case were to occur, the reset would not have the effect of subtracting 32 and there would be an error in the final total. It will be appreciated that if the second clock rate is close to 1 / 2A(N-1) of the first clock rate then such events can occur within one clock cycle of the first clock rate. For example, if the counter 110 is checked by the toggle checker 120 when its value is 31, its MSB is ‘0’ and no action is taken. If the counter 110 then processes 32 ‘1’s at its input over the next 32 clock cycles, then the next check by the toggle checker 120 occurs at a counter value of 63, where the MSB is found to be T and the appropriate weighting unit 130 is triggered. Once further clock cycle of the first clock rate, with a ‘T at the counter input can result in the counter 110 rolling round to a value of 0 (with the MSB at ‘0’). With certain delays in processing, and delays in counter values rippling through the rippling counter, care must be taken to avoid this possibility. If the second clock rate is faster than the theoretical limit described here by a suitable margin, then there should not be any possibility of reset errors. Figure 3 illustrates the processing of a four bit ripple counter (with bits identified as bit 0, bit 1 , bit 2 and bit 3) and how the MSB reset technique works. In the figure, the counter value is shown as a column of four bits. The development of the counter with time is shown by moving to the right in the figure. The counter value increases by 1 in each time step (as if the counter continually received a T value as its digital input bit at the first toggle flip flop 112a in Figure 1). After 7 time steps have occurred (7 time steps representing the slower second clock rate which has a ratio of less than 1 in 2A(N-1)=8 of the first clock rate), the counter value has reached 6 and the MSB remains at ‘O’. This is multiplied by the weight wo so that a total of 0 is added to the final integrator. No reset operation is performed as the MSB is ‘O’. Next time the second clock cycles round, i.e. another 7 time steps later, the counter value has reached 13 and the MSB is T. This T is passed to the weighting unit which multiplies the counter value of the MSB (2A3 = 8 in this case) by the weighting value wo and thus adds 8*wo to the final integrator. The MSB is then reset to 0 so that the counter value drops from 13 to 5 (i.e. subtracting 8). This state is not visible in figure 3 as it happens before the next time step, but the next time step shows the incremented counter value of 6 rather than 14, demonstrating that the reset took place (and accordingly the MSB is then ‘0’). 7 more time steps later, the counter value has increased from 5 to 12 and the MSB is once again T, so the weighting unit again multiplies the counter value of the MSB by the weighting value wo and thus adds 8*wo to the final integrator.

[0082] Six time steps later in Figure 3, the digital inputs stop, i.e. all inputs have reached the counters and have been accumulated in the ripple counters, the final value of the counters being 10. Therefore processing of the MSB by the weighting units can cease. Instead, a final integration step takes place to add in the residual values of the counters. This final operation takes into account all bits of the counter, not just the MSB so that all information in the digital inputs has been duly processed and added to the final integrator. Although this final integration step could be done at the usual time point in the sequence, i.e. seven time steps on from the last check of the MSB, it is shown later in this embodiment of Figure 3 as it is a slightly different process. In particular, this final process has to process all bits rather than just the MSB. As the counter values are no longer changing, a time delay in initiating this process is not problematic. Therefore, as shown in Figure 3, the final integration step takes place 11 time steps after the last MSB check. At this point, the full remaining counter value of 10 is multiplied by the weighting value and added to the final integrator, i.e. adding 1O*wo. The digital integration is now complete.

[0083] In alternative embodiments, instead of the weighting units multiplying the weighting value wo by the counter value of the MSB (8 in this example), the weighting units can simply output 1* wo for each of the normal checks (excluding the final integration step). Providing the same approach is taken across all counters 110, the result of this simplification is that the final integrator value has simply been downscaled by a factor equal to the counter value of the MSB (i.e. it as one eighth of the intended value in this example). In such embodiments, a further processing step is required before the final integration step to multiply the digital integrator by the scaling factor, i.e. in this example to multiply it by 8 (e.g. by bit shifting the final integrator by 3 places). The final addition of the final integration step based on a full counter value can then be added and is appropriately scaled relative to the previously accumulated values.

[0084] Figure 4 illustrates the way that the bits of the digital input values 102 are handled through the processing techniques described above. At the far left, the 10 bits of the original digital input value 102 (i.e. the raw ADC output) are represented as a column with a height of 10. The next ten columns represent the ten ripple counters, each of which accumulates one bit of the input digital value 102. Each ripple counter has a height of 6 because it is a six bit counter and therefore accumulates six bits worth of data. These ten columns are offset from each other as they each represent different bit values in the overall sum. Thus the second column from the left is highest as it represents an accumulation of MSBs from the digital input 102. On the other hand, the 11thcolumn from the left represents the ripple counter for the LSB of the digital input 102 and is thus lower in the figure. The twelfth column from the left represents the skimmed bits from each of the ten MSBs of the ten ripple counters (i.e. the single bit values that are passed to the weighting units as illustrated in Figure 3). The thirteenth column is not a value that is actually processed anywhere within the system, but it represents the real value of the twelfth column due to the fact that the bits up to this point are from an ADC which uses a radix of 1.8. Thus the thirteenth column has a height 0.9 times that of the twelfth column, just for illustrative purposes. The fourteenth column shows the sum of the ten weighting units all added together (i.e. the ten bits of the twelfth column multiplied by the ten corresponding weighting values). The weights in this case are shown as adding fractional bits so that the total bar extends lower on the graph than the twelfth column, but it will be appreciated that this is just an implementation detail. This summed value now occupies 15 bits due to the fact that it has summed 10 numbers, each of which was effectively a 10-bit number multiplied by a weighting value. Finally, the values from the fourteenth column are accumulated (integrated) over time to produce the fifteenth column in the SRAM integrator which is capable of accumulating up to a 33 bit number so that it can accumulate a very large number of digital inputs without overflow. It will be appreciated that the choice of 33 bits is just another implementation detail. The sixteenth column shows the final value after the final integration step has added on the residual bits from the counter values (thus adding an extra 5 bits in this example).

[0085] While the above description of Figures 1 to 4 has been provided for the full two stage integration technique (the first stage being the ripple counters at the first clock rate and the second stage being in the SRAM integrator at the second clock rate), the bitwise integration of the digital inputs in the ripple counters followed by weighting to correct for radix value may be sufficient in some embodiments. That is, some embodiments need not include the SRAM integrator. If the ripple counters 110 are themselves large enough to accumulate all the digital inputs 102, then the weighting by the weighting units 130-0 to 130-9 and the summation in the summation unit 140 are sufficient to produce a final value without needing further time integration.

[0086] The separation of the digital inputs into individual bits and individual counters is counter-intuitive as it means that each counter accumulates at a different rate, depending on how often a particular input bit is a T. Thus the individual bits of the digital inputs 102 get separated from one another in time before they are processed into the final integration value. This is particularly counter-intuitive when dealing with digital outputs that represent a non-radix 2 number in a binary format (i.e. using only Ts and ‘0’s) as such numbers must normally be weighted and summed to convert to radix 2 before any further processing can be performed. The processing here recognises that there is linearity in a lot of the processing that is not impacted by separating the bits and processing them individually in this manner. All multiplications and additions still happen, but in a different order and with several operations able to operate at a slower clock frequency, thereby making power savings. In particular, the multiplications (weightings) for the radix adjustment can be performed at a slower clock frequency and can also conveniently be combined (if desired) with corrections for process variations in the same operation.

[0087] It will be appreciated by those skilled in the art that the disclosure has been illustrated by describing one or more specific aspects thereof, but is not limited to these aspects; many variations and modifications are possible, within the scope of the accompanying claims.

Claims

Claims1 . A digital integrator arranged to receive a digital input as a plurality of bits, each bit capable of being in a first state or a second state, the digital integrator comprising: for each input bit: i) a counter circuit arranged to operate at a first clock rate and arranged to receive the input bit, count when the input bit is in the first state, and provide a counter output based on the present count; ii) a weighting unit having an associated weighting value, the weighting unit arranged to operate at a second clock rate, arranged to receive the counter output, and arranged such that when the counter output indicates a change of count by at least a threshold amount, the weighting unit outputs a multiple of the weighting value as a weighted output; the digital integrator further comprising: a summation unit arranged to operate at the second clock rate and arranged to sum the weighted outputs from the plurality of weighting units to produce a summation output; and an integrator unit arranged to operate at the second clock rate and arranged to integrate over time a plurality of summation outputs to produce an integrated value; wherein the first clock rate is faster than the second clock rate.

2. A digital integrator as claimed in claim 1 , wherein each counter is an N-bit counter, where N is greater than or equal to two.

3. A digital integrator as claimed in claim 2, wherein N is between three and ten.

4. A digital integrator as claimed in claim 1 , 2 or 3, wherein each counter is a ripple counter.

5. A digital integrator as claimed in claim 4, wherein each ripple counter comprises a set of series-connected toggle flip flops such that each bit of the counter is represented by the state of one toggle flip flop.

6. A digital integrator as claimed in any preceding claim, wherein the ratio of the first clock rate to the second clock rate is less than half the maximum positive integer that can be represented by the counter.

7. A digital integrator as claimed in any preceding claim, wherein each counter output is a single bit of the respective counter.

8. A digital integrator as claimed in claim 7, wherein the counter output is the most significant bit of the respective counter.

9. A digital integrator as claimed in claim 7 or 8, wherein each weighting unit is arranged to check for a change of state of its respective counter output bit.

10. A digital integrator as claimed in claim 9, wherein when a change of state of the counter output bit is detected, the weighting unit resets that bit of the counter.

11. A digital integrator as claimed in claim 9 or 10, wherein the weighting unit is arranged to output a single multiple of its weighting value upon detection of a change of state.

12. A digital integrator as claimed in any preceding claim, wherein the weighting value for each weighting unit includes a bit-value multiplier equal to the radix of the digital input raised to the power of the corresponding digital input bit position.

13. A digital integrator as claimed in claim 12, wherein the radix of the digital input is less than two.

14. A digital integrator as claimed in claim 12 or 13, wherein the weighting value for each weighting unit includes a correction factor to correct for process variation in a component upstream of the digital integrator.

15. A digital integrator as claimed in claim 14, wherein the analogue component is a capacitor and / or a voltage source in an analogue to digital converter.

16. A digital integrator as claimed in any preceding claim, arranged to carry out a final integration step after all digital inputs have been processed, in which all unprocessed counts in the present count value of each counter are output to the respective weighting units, multiplied by the respective weighting values and combined with the integrated value.

17. An impulse radar system comprising an analogue to digital converter and a digital integrator as claimed in any preceding claim; wherein the analogue to digital converter is arranged to digitise a radar receive signal; and wherein the output of the analogue to digital converter provides the digital input to the digital integrator.

18. An impulse radar system as claimed in claim 17, wherein the impulse radar system is arranged to transmit a plurality of pulses, each pulse having a positive or negative polarity; wherein each bit of the output of the analogue to digital converter is combined in a logic gate with a polarity signal indicative of the transmitted pulse polarity so as to remove the effect of the transmitted polarity and the outputs of the logic gates provide the digital input to the digital integrator.

19. An impulse radar system as claimed in claim 17 or 18, wherein the analogue to digital converter is arranged to process a time sequence of samples of the radar receive signal, each corresponding to a different radar range, and wherein the impulse radar system comprises a digital integrator as claimed in any of claims 1 to 16 for each radar range.

20. An impulse radar system as claimed in claim 19, wherein the analogue to digital converter is a time-interleaved ADC comprising a plurality of sub-ADC units that receive signal samples in sequence, and provide digitised values to the digital integrators for the plurality of range points in sequence; andwherein each weighting unit of each digital integrator has an appropriately calibrated weighting value for each sub-ADC from which it may receive a digital input and wherein each weighting unit is arranged to select the calibrated weighting value according to the sub-ADC that provided the current digital input.

21. An impulse radar system as claimed in any of claims 17 to 20, wherein the impulse radar system is arranged to transmit a sequence of pulses and wherein the impulse radar system is arranged to carry out the final integration step of claim 16 after all transmitted pulses have been received and processed.

22. A method of digitally integrating a series of digital inputs, each digital input comprising a plurality of bits, each bit capable of being in a first state or a second state, the method comprising: for each input bit: receiving the input bit and counting in a counter at a first clock rate when the input bit is in the first state; providing a counter output based on the present count from the counter to a weighting unit operating at a second clock rate and having an associated weighting value; and when the counter output indicates a change of count by at least a threshold amount, the weighting unit outputting a multiple of the weighting value as a weighted output; summing the weighted outputs at the second clock rate to produce a summation output; and integrating over time at the second clock rate a plurality of summation outputs to produce an integrated value; wherein the first clock rate is faster than the second clock rate.

23. A digital integrator arranged to receive a digital input as a plurality of bits, each bit capable of being in a first state or a second state, the digital integrator comprising: for each input bit: i) a counter circuit arranged to receive the input bit, count when the input bit is in the first state, and provide a counter output based on the present count; andii) a weighting unit having an associated weighting value, the weighting unit arranged to receive the counter output, and arranged to output a product of the counter output and the weighting value as a weighted output; the digital integrator further comprising: a summation unit arranged to sum the weighted outputs from the plurality of weighting units to produce an integrated value.

24. A digital integrator as claimed in claim 23, wherein the weighting unit is arranged to output a product of the counter output by bit shifting the counter output according to the weighting value.

25. A method of digitally integrating a series of digital inputs, each digital input comprising a plurality of bits, each bit capable of being in a first state or a second state, the method comprising: for each input bit: receiving the input bit and counting in a counter when the input bit is in the first state; providing a counter output based on the present count from the counter to a weighting unit having an associated weighting value; and the weighting unit outputting a product of the counter output and the weighting value as a weighted output; and summing the weighted outputs to produce an integrated value.

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