Light detection device

Abstract

Provided is a light detection device comprising: a photoelectric conversion unit that converts light into a charge; a charge accumulation unit that accumulates the charge from the photoelectric conversion unit; an amplifying transistor that converts the charge accumulated in the charge accumulation unit into a pixel signal; a first additional capacitive unit that adds capacitance to the charge accumulation unit; and an additional transistor that switches conversion efficiency by switching between enabling and disabling addition to the charge accumulation unit by the first additional capacitive unit, said light detection device being formed by lamination of a first layer, which has the photoelectric conversion unit, the charge accumulation unit, and the first additional capacitive unit, and a second layer, which has the amplifying transistor and which is laminated on the first layer.

Description

Photodetector

[0001] The present disclosure relates to a light detection device.

[0002] In recent years, imaging devices with a two-layer stacked structure have been proposed to further reduce the size of imaging devices (photodetection devices). An example of such a device is the imaging device disclosed in Patent Document 1. The technology disclosed in Patent Document 1 achieves the miniaturization of the imaging device by stacking and bonding a first layer including a plurality of imaging elements (photodetection elements) and a second layer including a readout circuit including a plurality of pixel transistors that read pixel signals from each imaging element.

[0003] International Publication No. 2020 / 105713

[0004] Furthermore, in recent years, it has been proposed to provide an imaging device (photodetector device) with a conversion efficiency switching transistor (additional transistor) and an additional capacitance section, thereby switching the size of the capacitance section that stores the charge generated within the device depending on the amount of light during shooting. By performing such switching, when shooting in a bright location, the capacitance section can be made larger to receive all of the charge generated within the device, preventing the voltage when the charge is converted into a signal from becoming too large. On the other hand, when shooting in a dark location, the capacitance section can be made smaller to prevent the voltage when the charge is converted into a signal from becoming too small.

[0005] However, in conventional imaging devices, it is difficult to secure a large area for providing such an additional capacitance section, and therefore it is difficult to increase the capacitance value of the additional capacitance section.

[0006] Therefore, the present disclosure proposes a technique that utilizes a two-stage pixel structure to enable the imaging device (photodetector) to be miniaturized while increasing the capacitance value of the additional capacitance section.

[0007] According to the present disclosure, there is provided a photodetector device comprising: a photoelectric conversion unit that converts light into an electric charge; a charge accumulation unit that accumulates the electric charge from the photoelectric conversion unit; an amplifying transistor that converts the electric charge accumulated in the charge accumulation unit into a pixel signal; a first additional capacitance unit that adds capacitance to the charge accumulation unit; and an additional transistor that switches conversion efficiency by switching between enabling and disabling the addition of the first additional capacitance unit to the charge accumulation unit, the photodetector device being formed by stacking a first layer having the photoelectric conversion unit, the charge accumulation unit, and the first additional capacitance unit, and a second layer having the amplifying transistor and stacked on the first layer.

[0008] 6A . A plan view showing an example of a planar configuration of an imaging device 30 according to an embodiment of the present disclosure. An equivalent circuit diagram of a pixel 10a according to a comparative example. An equivalent circuit diagram of a pixel 10 according to the first embodiment of the present disclosure. A plan view showing an example of a planar configuration of a pixel 10 according to the first embodiment of the present disclosure. A cross-sectional view showing an example of a cross-sectional configuration of a pixel 10 according to the first embodiment of the present disclosure. A cross-sectional view of a semiconductor substrate 200 taken along line A-A' shown in FIG. 4A. A cross-sectional view (part 1) showing an example of a modified example of an additional capacitance section 433. A plan view showing an example of a planar configuration of a pixel 10 according to a modified example 1 of the first embodiment of the present disclosure. A cross-sectional view of a semiconductor substrate 200 taken along line B-B' shown in FIG. 6A. A plan view showing an example of a planar configuration of a pixel 10 according to a modified example 2 of the first embodiment of the present disclosure. A cross-sectional view of a semiconductor substrate 200 taken along line L-L' shown in FIG. 7A. A plan view showing an example of a planar configuration of a pixel 10 according to a modified example 3 of the first embodiment of the present disclosure. A plan view showing an example of a planar configuration of a pixel 10 according to a modified example 4 of the first embodiment of the present disclosure. 16A . FIG. 16B is a plan view illustrating an example of a planar configuration of a pixel 10 according to Modification 5 of the first embodiment of the present disclosure. FIG. 17A is a cross-sectional view illustrating an example of Modification 6 of the separation section 440. FIG. 17B is a cross-sectional view illustrating an example of Modification 7 of the amplification transistor 422. FIG. 17C is a cross-sectional view illustrating an example of a pixel 10 according to Modification 8 of the first embodiment of the present disclosure. FIG. 17D is a cross-sectional view illustrating an example of a manufacturing method for the pixel 10 according to the first embodiment of the present disclosure. FIG. 17E is an equivalent circuit diagram of the pixel 10 according to a second embodiment of the present disclosure. FIG. 17F is a cross-sectional view illustrating an example of a planar configuration of the pixel 10 according to the second embodiment of the present disclosure. FIG. 17G is a cross-sectional view illustrating an example of a planar configuration of the pixel 10 according to Modification 1 of the second embodiment of the present disclosure. 18A is a cross-sectional view of the semiconductor substrate 200 taken along the line J-J' shown in Fig. 18A. Fig. 18B is a cross-sectional view of the semiconductor substrate 200 taken along the line K-K' shown in Fig. 18A. Fig. 18C is a block diagram showing an example of a schematic functional configuration of a smartphone.Fig. 1 is a diagram showing an example of a schematic configuration of an endoscopic surgery system. Fig. 2 is a block diagram showing an example of a functional configuration of a camera head and a CCU. Fig. 3 is a block diagram showing an example of a schematic configuration of a vehicle control system. Fig. 4 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit.

[0009] Preferred embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant description will be omitted. Furthermore, in this specification and the drawings, multiple components having substantially the same or similar functional configurations may be distinguished by adding different letters after the same reference numeral. However, when there is no particular need to distinguish between multiple components having substantially the same or similar functional configurations, only the same reference numerals will be used.

[0010] The drawings referred to in the following description are for explaining and facilitating understanding of the embodiments of the present disclosure, and for the sake of clarity, the shapes, dimensions, ratios, etc. shown in the drawings may differ from the actual ones. Furthermore, the design of the devices shown in the drawings may be modified as appropriate, taking into consideration the following description and known technologies.

[0011] In the following description of circuits (electrical connections), unless otherwise specified, "electrically connected" means connecting multiple elements so that electricity (signals) is conducted between them. In addition, in the following description, "electrically connected" includes not only cases where multiple elements are directly and electrically connected, but also cases where elements are indirectly and electrically connected via other elements.

[0012] In the following description, "sharing" means that different elements (e.g., photodiodes, pixel units, etc.) share one other element (e.g., on-chip lenses, floating diffusions, etc.).

[0013] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order: 1. Background leading to the creation of embodiments of the present disclosure 1.1 Example of a schematic configuration of an imaging device 1.2 Example of a configuration of a pixel circuit according to a comparative example 1.3 Background 2. First embodiment 2.1 Overview 2.2 Equivalent circuit 2.3 Detailed configuration 2.4 Modified example 2.5 Manufacturing method 3. Second embodiment 3.1 Overview 3.2 Equivalent circuit 3.3 Detailed configuration 3.4 Modified example 4. Summary 5. Application examples 5.1 Application example to a smartphone 5.2 Application example to an endoscopic surgery system 5.3 Application example to a mobile object 6. Supplementary information

[0014] <<1. Background to the Creation of the Embodiments of the Present Disclosure>> <1.1 Example of Schematic Configuration of Imaging Device> First, before describing the embodiments of the present disclosure, the background to the creation of the embodiments of the present disclosure by the inventors will be described. First, a schematic configuration of an imaging device (photodetection device) 30 according to an embodiment of the present disclosure will be described with reference to FIG. 1 . FIG. 1 is a plan view showing an example of the planar configuration of the imaging device 30 according to an embodiment of the present disclosure. As shown in FIG. 1 , the imaging device 30 according to this embodiment includes, for example, a pixel array unit 12, a vertical drive circuit unit 32, a column signal processing circuit unit 34, a horizontal drive circuit unit 36, an output circuit unit 38, and a control circuit unit 44, which are provided on a semiconductor substrate 200 made of silicon (Si). Each block of the imaging device 30 according to this embodiment will be described in detail below.

[0015] (Pixel Array Section 12) The pixel array section 12 has a plurality of pixels 10 arranged two-dimensionally in a matrix (row and column rows and columns) on the semiconductor substrate 200. Each pixel 10 has a photoelectric conversion section (photodiode PD) (not shown) that converts light into electric charges (e.g., electrons), and a plurality of pixel transistors (e.g., MOS (Metal-Oxide-Semiconductor) transistors) (not shown). In other words, the pixel array section 12 has a plurality of pixels 10 that photoelectrically convert incident light and output signals corresponding to the resulting electric charges. The pixel transistors may include transistors with various functions, such as a transfer transistor, a selection transistor, a reset transistor, and an amplification transistor. Details of the equivalent circuits of the pixels 10 will be described later.

[0016] Here, the row direction refers to the horizontal arrangement direction of the pixels 10, and the column direction refers to the vertical arrangement direction of the pixels 10. The row direction is the left-right direction in FIG. 1, and the column direction is the up-down direction in FIG. 1. In the pixel array section 12, pixel drive wiring 42 is wired along the row direction for each row of the matrix-like arrangement of pixels 10, and vertical signal lines 48 are wired along the column direction for each column. For example, the pixel drive wiring 42 transmits drive signals for driving the pixels 10 when signals are read out.

[0017] (Vertical Drive Circuit Unit 32) The vertical drive circuit unit 32 is formed by, for example, a shift register, an address decoder, etc., selects pixel drive wirings 42, supplies pulses for driving the pixels 10 to the selected pixel drive wirings 42, and drives all of the pixels 10 simultaneously or row by row. For example, the vertical drive circuit unit 32 selects and scans each pixel 10 in the pixel array unit 12 row by row in the vertical direction (up and down in FIG. 1 ), and supplies pixel signals based on charges generated in accordance with the amount of light received by the photoelectric conversion unit of each pixel 10 to a column signal processing circuit unit 34 (described later) via vertical signal lines 48.

[0018] (Column Signal Processing Circuit Unit 34) The column signal processing circuit unit 34 is arranged for each column of pixels 10, and performs signal processing such as noise removal for each column on signals output from one row of pixels 10. For example, the column signal processing circuit unit 34 performs signal processing such as CDS (Correlated Double Sampling) and AD (Analog-Digital) conversion in order to remove fixed pattern noise specific to the pixels 10.

[0019] (Horizontal drive circuit unit 36) The horizontal drive circuit unit 36 ​​is formed, for example, by a shift register or an address decoder, and by sequentially outputting horizontal scanning pulses, it can select each of the above-mentioned column signal processing circuit units 34 in turn and output a signal from each column signal processing circuit unit 34 to the horizontal signal line 46.

[0020] (Output Circuit Unit 38) The output circuit unit 38 can process and output signals sequentially supplied from each of the column signal processing circuits 34 via the horizontal signal line 46. The output circuit unit 38 may function as a functional unit that performs buffering, or may perform processing such as column variation correction and various digital signal processing. Buffering refers to temporarily storing signals to compensate for differences in processing speed and transfer speed when exchanging signals.

[0021] (Control Circuit Unit 44) The control circuit unit 44 receives an input clock and data instructing the operation mode and the like, and can also output data such as internal information of the pixel 10. That is, the control circuit unit 44 generates clock signals and control signals that serve as references for the operation of the vertical drive circuit unit 32, the column signal processing circuit unit 34, the horizontal drive circuit unit 36, etc., based on a vertical synchronization signal, a horizontal synchronization signal, and a master clock. The control circuit unit 44 then outputs the generated clock signals and control signals to the vertical drive circuit unit 32, the column signal processing circuit unit 34, the horizontal drive circuit unit 36, etc.

[0022] It should be noted that the imaging device 30 according to the embodiment of the present disclosure is not limited to the example shown in FIG.

[0023] 1.2 Example of Pixel Circuit Configuration According to Comparative Example Next, an example of the configuration of a pixel circuit of a pixel 10a according to a comparative example will be described with reference to Fig. 2. Fig. 2 is an equivalent circuit diagram of the pixel 10a according to the comparative example. Here, the comparative example refers to the pixel 10a that the inventors of the present disclosure had studied before creating the embodiments of the present disclosure.

[0024] Each pixel 10 a has common components, such as a photoelectric conversion unit 101, a transfer transistor 102 electrically connected to the photoelectric conversion unit 101, and a floating diffusion (charge storage unit) 103 that temporarily stores the charge output from the photoelectric conversion unit 101 via the transfer transistor 102.

[0025] The photoelectric conversion unit 101 performs photoelectric conversion on incident light and generates charges according to the amount of light received. One terminal of the photoelectric conversion unit 101 is electrically connected to one of the source and drain of the transfer transistor 102, and the other terminal of the photoelectric conversion unit 101 is electrically connected to a reference potential line (e.g., ground). The other of the source and drain of the transfer transistor 102 is electrically connected to a floating diffusion 103. When the transfer transistor 102 is turned on, it can transfer charges generated in the photoelectric conversion unit 101 to the floating diffusion 103. The floating diffusion 103 then accumulates the transferred charges. The transfer transistor 102 is, for example, a complementary metal oxide semiconductor (CMOS) transistor.

[0026] Furthermore, each pixel 10 a has, for example, a reset transistor 201 , an amplification transistor 202 , and a selection transistor 203 .

[0027] One of the source or drain of the reset transistor 201 is electrically connected to the floating diffusion 103, and the other of the source or drain of the reset transistor 201 is electrically connected to the power supply line VDD. The reset transistor 201 can reset the potential of the floating diffusion 103 to a predetermined potential. Specifically, when the reset transistor 201 is turned on, the potential of the floating diffusion 103 is reset to the potential of the power supply line VDD, and the charge accumulated in the floating diffusion 103 is reset.

[0028] The gate of the amplification transistor 202 is electrically connected to the floating diffusion 103, and a signal (pixel signal) having a voltage corresponding to the amount of charge accumulated in the floating diffusion 103 can be generated. One of the source and drain of the amplification transistor 202 is connected to one of the source and drain of the selection transistor 203, and the other of the source and drain of the amplification transistor 202 is electrically connected to the power supply line VDD. The other of the source and drain of the selection transistor 203 is electrically connected to the vertical signal line 48. The selection transistor 203 can control the output timing of the pixel signal. Specifically, when the selection transistor 203 is turned on, the amplification transistor 202 outputs the pixel signal to the vertical signal line 48. The reset transistor 201, the amplification transistor 202, and the selection transistor 203 are, for example, CMOS transistors.

[0029] The equivalent circuit of the pixel circuit of the pixel 10a according to the comparative example is not limited to the example shown in FIG. 2, and may include, for example, other elements.

[0030] <1.3 Background> Next, the background that led the inventors to create the embodiments according to the present disclosure will be described.

[0031] When shooting in a dark place, the amount of light incident on the image capture device 30 is small, and therefore the amount of charge (Q) generated by the image capture device 30 is small. Furthermore, when converting the amount of charge accumulated in the floating diffusion 103 (capacitance value: C) into a voltage (pixel signal), the voltage (V) is determined based on Q = CV. Therefore, when shooting in a dark place, if the capacitance (C) of the floating diffusion 103 is large, the voltage (V) generated after conversion will be small.

[0032] On the other hand, when photographing in a bright place, a large amount of light is incident on the imaging device 30, and therefore a large amount of charge (Q) is generated in the imaging device 30. Therefore, when photographing in a dark place, unless the capacitance (C) of the floating diffusion 103 is large, the floating diffusion 103 cannot receive all of the charge generated in the photoelectric conversion unit 101. Furthermore, it is necessary to increase the capacitance (C) of the floating diffusion 103 so that the voltage value (V) upon conversion does not become too large.

[0033] Therefore, in recent years, it has been proposed to provide the pixel 10 a with a conversion efficiency switching transistor (additional transistor) and an additional capacitance unit, thereby switching the size of the capacitance unit that accumulates the charge generated in the photoelectric conversion unit 101 depending on the amount of light during shooting. Specifically, when the conversion efficiency switching transistor is turned on, the addition of the additional capacitance unit to the floating diffusion 103 is enabled, and the capacitance of the capacitance unit that accumulates the charge generated in the photoelectric conversion unit 101 increases. Therefore, when shooting in a bright location, turning on the conversion efficiency switching transistor allows the charge generated in the photoelectric conversion unit 101 to be received by the floating diffusion 103 and the additional capacitance unit, and further prevents the voltage (V) upon conversion from becoming too large. On the other hand, when the conversion efficiency switching transistor is turned off, the addition of the additional capacitance unit to the floating diffusion 103 is disabled, and the additional capacitance unit is disconnected from the floating diffusion 103, thereby reducing the capacitance of the capacitance unit that accumulates the charge generated in the photoelectric conversion unit 101. Therefore, when shooting in a dark place, by turning off the conversion efficiency switching transistor, it is possible to prevent the voltage (V) at the time of conversion from becoming small. In this way, according to the pixel 10a proposed in recent years, by switching the conversion efficiency switching transistor on and off, it is possible to change the capacitance of the capacitance section and switch the conversion efficiency.

[0034] However, if a conversion efficiency switching transistor and an additional capacitance unit are to be provided on a single substrate that already includes the photoelectric conversion unit 101, transfer transistor 102, floating diffusion 103, and amplification transistor 202, the area of ​​the substrate would increase, resulting in increased costs. Furthermore, it would become difficult to miniaturize the imaging device 30. Even if these components could be mounted on a single substrate, there would be a limit to how much the capacitance value of the additional capacitance unit could be increased due to the limited area of ​​the substrate.

[0035] In particular, when considering the operation of the pixel 10a, it is difficult to reduce the number of pixel transistors, such as the transfer transistor 102, reset transistor 201, amplifying transistor 202, selection transistor 203, and conversion efficiency switching transistor. Furthermore, since the amplifying transistor 202 has the function of generating a pixel signal, reducing its gate length increases random noise in the pixel signal. Therefore, there is a limit to how much the area of ​​the amplifying transistor 202 can be reduced (shrinked). Therefore, there is a limit to how much the capacitance value of the additional capacitance section can be increased.

[0036] In this situation, the present inventors have realized that the capacitance value of the additional capacitance section can be increased by using a pixel 10 having a two-tier pixel structure. The two-tier pixel structure is a pixel structure consisting of two stacked layers, which has been proposed to achieve further miniaturization of the imaging device 30. A photoelectric conversion section 101 and a floating diffusion 103 are provided in a first layer, and a pixel transistor is provided in a second layer stacked on the first layer. By utilizing such a two-tier pixel structure, the present inventors have come up with an embodiment of the present disclosure that can increase the capacitance value of the additional capacitance section while miniaturizing the imaging device 30. Details of the embodiment of the present disclosure created by the present inventors will be described below.

[0037] <<2. First Embodiment>> <2.1 Overview> In the first embodiment of the present disclosure created by the present inventors, as described above, a two-tier pixel structure is used to increase the capacitance of the additional capacitance section. In this embodiment, the two-tier pixel structure enables pixel transistors to be distributed across two layers. Furthermore, in this embodiment, the additional capacitance section is disposed in the space in the first layer that is freed up by moving the pixel transistors to the second layer, thereby enabling the capacitance value of the additional capacitance section to be increased. In this embodiment, all pixel transistors may be disposed in the second layer. However, in order to shorten the wiring length or increase the area of ​​the amplifier transistor 202, some of the pixel transistors may be disposed in the second layer and the remaining pixel transistors may be disposed in the first layer. Furthermore, this configuration improves the degree of freedom in layout. Details of the first embodiment of the present disclosure will be described below.

[0038] <2.2 Equivalent Circuit> First, an equivalent circuit of the pixel 10 according to the first embodiment will be described with reference to Fig. 3. Fig. 3 is an equivalent circuit diagram of the pixel 10 according to this embodiment.

[0039] 3 , in the same manner as in the comparative example, the pixel 10 includes a photoelectric conversion unit 101, a transfer transistor 102 electrically connected to the photoelectric conversion unit 101, and a floating diffusion (charge storage unit) 103 that temporarily stores charge output from the photoelectric conversion unit 101 via the transfer transistor 102. Similarly to the comparative example, the pixel 10 also includes a reset transistor 201, an amplification transistor 202, and a selection transistor 203. Furthermore, in the present embodiment, as shown in FIG. 3 , the pixel 10 also includes a conversion efficiency switching transistor (additional transistor) 301 electrically connected to the floating diffusion 103, and an additional capacitance unit (first additional capacitance unit) 303 electrically connected to the conversion efficiency switching transistor 301.

[0040] In detail, in this embodiment, one of the source and drain of the conversion efficiency switching transistor 301 is electrically connected to the floating diffusion 103, and the other of the source and drain of the conversion efficiency switching transistor 301 is electrically connected to the additional capacitance section 303. In this embodiment, by turning on the conversion efficiency switching transistor 301, the additional capacitance section 303 is electrically connected to the floating diffusion 103, and the conversion efficiency can be switched.

[0041] In this embodiment, the equivalent circuit of the pixel 10 is not limited to that shown in Fig. 3. This embodiment is applicable even when a part of the equivalent circuit in Fig. 3 is changed, and can also be applied to, for example, the equivalent circuit in Fig. 14, which is the equivalent circuit of the second embodiment of the present disclosure described later.

[0042] <2.3 Detailed Configuration> Next, a detailed configuration of the pixel 10 according to this embodiment will be described with reference to FIGS. 4A to 4C. FIG. 4A is a plan view showing an example of the planar configuration of the pixel 10 according to this embodiment. Specifically, in this embodiment, the pixel 10 has a two-tiered pixel structure and is composed of a first layer 401 and a second layer 402 stacked on the first layer 401. In FIG. 4A, the plan view of the first layer 401 as viewed from above is shown on the left, and the plan view of the second layer 402 as viewed from above is shown on the right. FIG. 4B is a cross-sectional view showing an example of the cross-sectional configuration of the pixel 10 according to this embodiment, illustrating the two-tiered pixel structure of the pixel 10. Furthermore, FIG. 4C is a cross-sectional view of the semiconductor substrate 200 taken along line A-A' shown in FIG. 4A.

[0043] In this embodiment, as shown on the left side of FIG. 4A , a photoelectric conversion unit 411, a transfer transistor 102 having a transfer gate 412, a floating diffusion (charge storage unit) (FD) 413, and an additional capacitance unit (first additional capacitance unit) 433 are provided on the semiconductor substrate 200 of the first layer 401. Specifically, as shown in FIG. 4A , four photoelectric conversion units 411 are provided on the semiconductor substrate 200 so as to surround one floating diffusion 413. In this specification, the four photoelectric conversion units 411 provided so as to surround one floating diffusion 413 are referred to as a pixel unit, and the pixel array unit 12 of the imaging device (photodetector) 30 is provided with a plurality of pixel units arranged in a matrix along the row and column directions. The four photoelectric conversion units 411 in one pixel unit are electrically connected to one floating diffusion 413 and share the floating diffusion 413. In this embodiment, the number of photoelectric conversion units 411 in a pixel unit is not limited to four, and for example, the pixel unit may have two photoelectric conversion units 411 arranged on either side of one floating diffusion 413.

[0044] In this embodiment, the total of eight (2 × 4) photoelectric conversion sections 411 included in the two pixel units share a reset transistor (RST) 421, an amplification transistor (AMP) 422, a selection transistor (SEL) 423, a conversion efficiency switching transistor (FDG) 431, and an additional capacitance section 433.

[0045] Furthermore, transfer gates (TG) 412 of four transfer transistors 102 are also provided on each photoelectric conversion unit 411 so as to surround one floating diffusion 413. As described above, the transfer transistor 102 transfers the charge generated in the photoelectric conversion unit 411 to the floating diffusion 413. The transfer gates 412 can be formed from polysilicon (poly-Si) or a metal material. In this specification, the region on the top surface of the semiconductor substrate 200 in which such a plurality of pixel units are provided is referred to as a region (first region) 401a.

[0046] 4A , an additional capacitance portion 433 is provided in a region (second region) 401b on the top surface of the semiconductor substrate 200, which is located adjacent to the region 401a. In detail, the additional capacitance portion 433 (specifically, an electrode (first electrode) 433a of the additional capacitance portion 433) is provided so as to extend along two adjacent pixel units.

[0047] Furthermore, the semiconductor substrate 200 may be provided with an isolation portion 440 to separate the regions 401a and 401b. The isolation portion 440 may be, for example, a diffusion region formed by diffusing impurities of a first conductivity type (e.g., p-type) in the semiconductor substrate 200. Alternatively, the isolation portion 440 may be a trench (Shallow Trench Isolation; STI) that partially penetrates the semiconductor substrate 200 along the film thickness direction, or a trench (Full Trench Isolation; FTI) that completely penetrates the semiconductor substrate 200. In this embodiment, such a trench may be filled with, for example, silicon oxide (SiO ２ The insulating film (insulating layer) may be filled with a conductive film such as polycrystalline silicon (Poly-Si), or a metal film such as tungsten (W).

[0048] In this embodiment, as shown on the right side of FIG. 4A, a reset transistor 421, an amplifier transistor 422, a selection transistor 423, and a conversion efficiency switching transistor 431 are provided on the semiconductor substrate 250 of the second layer 402.

[0049] 4B , the pixel 10 has a two-tiered pixel structure made up of a first layer 401 and a second layer 402. More specifically, the first layer 401 and the second layer 402 are stacked, and in this stack, the semiconductor substrate 200 of the first layer 401 and the semiconductor substrate 250 of the second layer 402 are located at the bottom in the figure. In other words, in this embodiment, the pixel transistor provided in the first layer 401 and the pixel transistor provided in the second layer 402 face each other with the semiconductor substrate 250 sandwiched between them.

[0050] The semiconductor substrate 200 is made of, for example, a silicon substrate. For example, a photoelectric conversion section 411 having impurities of a second conductivity type (for example, n-type) is provided in the semiconductor substrate 200. Also, a floating diffusion 413 containing impurities of the same second conductivity type as the photoelectric conversion section 411 at a higher concentration than the photoelectric conversion section 411 is provided in the semiconductor substrate 200.

[0051] 4A and 4B, in this embodiment, the pixel transistors are electrically connected by wiring 444. The pixel transistors provided in the second layer 402 are electrically connected to the pixel transistors, floating diffusion 413, and additional capacitance portion 433 provided in the first layer 401 by vias 442. The vias 442 can be formed from polysilicon or a metal film.

[0052] 4C , the additional capacitance section 433 is formed from a diffusion region 206 containing impurities of a first conductivity type (e.g., p-type) in the semiconductor substrate 200, and an electrode (first electrode) 433a provided on the diffusion region 206 via an insulating film 210. The diffusion region 206 may be a well region of the first conductivity type (e.g., p-type) provided in the semiconductor substrate 200. That is, the additional capacitance section 433 is formed from a MOS (Metal Oxide Semiconductor) capacitor. In this embodiment, the electrode 433a is electrically connected to the conversion efficiency switching transistor 431 via a via 442. The electrode 433a can be formed from polysilicon or a metal film.

[0053] Furthermore, the configuration of the additional capacitance section 433 is not limited to the configuration shown in Fig. 4C. Therefore, a modified example of the additional capacitance section 433 will be described with reference to Fig. 5. Fig. 5 is a cross-sectional view showing an example of a modified example of the additional capacitance section 433, and corresponds to the cross-sectional view of the semiconductor substrate 200 taken along line A-A' shown in Fig. 4A.

[0054] 5 , the additional capacitance section 433 is not limited to being a MOS capacitor, but may be a MIM (Metal Insulator Metal) capacitor. Specifically, the additional capacitance section 433 has an electrode 433a provided on an insulating layer 204 provided in the semiconductor substrate 200, a dielectric layer 434 provided on the electrode 433a, and an electrode 435 provided on the dielectric layer 434. The electrode 435 is electrically connected to the conversion efficiency switching transistor 431 through a via 442. A fixed potential is applied to the electrode 433a through the via 442. That is, in this embodiment, the substrate on which the additional capacitance section 433 is provided is not particularly limited.

[0055] As described above, in this embodiment, the two-stage pixel structure is used to provide the reset transistor 421, the amplification transistor 202, the selection transistor 203, and the conversion efficiency switching transistor 301 in the second layer 402 stacked on the first layer 401. In this manner, according to this embodiment, the additional capacitance section 433 can be disposed in an empty space in the first layer 401, and therefore the capacitance value of the additional capacitance section 433 can be increased without increasing the area of ​​the first layer 401.

[0056] It should be noted that the configuration of the pixel 10 according to this embodiment is not limited to the examples shown in FIGS. 4A to 4C.

[0057] <2.4 Modifications> Next, modifications of the pixel 10 in this embodiment will be described.

[0058] (Variation 1) First, the planar configuration of a pixel 10 according to Variation 1 of this embodiment will be described with reference to Figures 6A and 6B. Figure 6A is a plan view showing an example of the planar configuration of a pixel 10 according to Variation 1, and in detail, the plan view of the first layer 401 as seen from above is shown on the left, and the plan view of the second layer 402 as seen from above is shown on the right. Also, Figure 6B is a cross-sectional view of the semiconductor substrate 200 taken along line B-B' shown in Figure 6A. Note that the cross-section of the semiconductor substrate 200 taken along line D-D' shown in Figure 6A is the same as the cross-section shown in Figure 4C.

[0059] In this first modification, as shown on the left side of FIG. 6A , a photoelectric conversion unit 411, a transfer transistor 102 having a transfer gate 412, and a floating diffusion 413 are provided in a region 401a of the first layer 401. Furthermore, in this first modification, an additional capacitance unit 433, a reset transistor 421, and a conversion efficiency switching transistor 431 are provided in a region 401b of the first layer 401. Specifically, the additional capacitance unit 433 (specifically, an electrode 433a of the additional capacitance unit 433) is provided so as to extend along one pixel unit. Furthermore, the reset transistor 421 and the conversion efficiency switching transistor 431 are provided so as to be adjacent to another pixel unit. In this first modification, by providing the conversion efficiency switching transistor 431 and the reset transistor 421 in the first layer 401, it is possible to shorten the routing of wiring electrically connected to these pixel transistors.

[0060] 6A, the second layer 402 is provided with an amplifying transistor 202 and a selecting transistor 203. In the present modification 1, by providing two pixel transistors in the second layer 402, the area of ​​the amplifying transistor 202 can be increased.

[0061] 6B , the conversion efficiency switching transistor 431 and the reset transistor 421 are formed by a diffusion region 206a containing impurities of a second conductivity type (e.g., n-type) in the semiconductor substrate 200 and an electrode (gate electrode) 431a provided on the diffusion region 206a via an insulating film 210. The source / drain of the conversion efficiency switching transistor 431 and the reset transistor 421 can be electrically connected to other elements by vias 442. Furthermore, although not shown, the additional capacitance section 433 provided in the region 401b is preferably separated from the conversion efficiency switching transistor 431 and the reset transistor 421 by an isolation section 440. As described above, the isolation section 440 may be, for example, a diffusion region formed by diffusing impurities of a first conductivity type (e.g., p-type) in the semiconductor substrate 200. Alternatively, the isolation section 440 may be an STI or FTI.

[0062] (Modification 2) Next, the configuration of the pixel 10 according to Modification 2 will be described with reference to Figures 7A and 7B. Figure 7A is a plan view showing an example of the planar configuration of the pixel 10 according to Modification 2, and in detail, the plan view of the first layer 401 as viewed from above is shown on the left, and the plan view of the second layer 402 as viewed from above is shown on the right. Also, Figure 7B is a cross-sectional view of the semiconductor substrate 200 taken along line L-L' shown in Figure 7A. Note that the configuration of the pixel 10 according to Modification 2 is the same as that of Modification 1 described above, except for the additional capacitance 433, and therefore, description of the elements other than the additional capacitance 433 will be omitted here.

[0063] 7B , in the second modification, the additional capacitance portion 433 includes, as in the present embodiment, a diffusion region 206 containing impurities of a first conductivity type (e.g., p-type) in the semiconductor substrate 200, and an electrode (first electrode) 433a provided on the diffusion region 206 via an insulating film 210. Furthermore, in the second modification, the additional capacitance portion 433 includes a dielectric layer 434 provided on the electrode 433a and an electrode (second electrode) 435 provided on the dielectric layer 434. The electrode 435 is electrically connected to the conversion efficiency switching transistor 431 via a via 442. That is, in the second modification, the additional capacitance portion 433 is configured by stacking a MOS capacitor (first load capacitance portion) and an MIM capacitor (second additional capacitance portion). According to the second modification, this configuration allows the capacitance value of the additional capacitance portion 433 to be increased without increasing the area of ​​the additional capacitance portion 433. Furthermore, in this modification, by forming the dielectric layer 434 from a high dielectric constant film such as hafnium oxide, it is possible to obtain the additional capacitance section 433 having a large capacitance value.

[0064] (Variation 3) Next, the planar configuration of the pixel 10 according to Variation 3 of the present embodiment will be described with reference to Fig. 8. Fig. 8 is a plan view showing an example of the planar configuration of the pixel 10 according to Variation 3, and in detail, the planar view of the first layer 401 as seen from above is shown on the left side, and the planar view of the second layer 402 as seen from above is shown on the right side.

[0065] In the present modification 3, a region 401a of the first layer 401 is provided with a photoelectric conversion unit 411, a transfer transistor 102 having a transfer gate 412, and a floating diffusion 413. Furthermore, in the present modification 3, an additional capacitance unit 433 and a reset transistor 421 are provided in a region 401b of the first layer 401. Specifically, the additional capacitance unit 433 (specifically, the electrode 433a of the additional capacitance unit 433) extends along one pixel unit and further extends to a part of another pixel unit adjacent to that pixel unit. Furthermore, the reset transistor 421 is provided adjacent to the other pixel unit. That is, in the present modification 3, unlike the above-described modification 1, the conversion efficiency switching transistor 431 is provided in the second layer 402. Therefore, in the present modification 3, the amplification transistor 202, the selection transistor 203, and the conversion efficiency switching transistor 431 are provided in the second layer 402. In this modification 3, by moving the conversion efficiency switching transistor 431 to the second layer 402, the area of ​​the additional capacitance section 433 can be made larger than in modification 1, and therefore the capacitance value can be made larger.

[0066] (Modification 4) Next, the planar configuration of a pixel 10 according to Modification 4 of the present embodiment will be described with reference to Fig. 9. Fig. 9 is a plan view showing an example of the planar configuration of a pixel 10 according to Modification 4, and in detail, the planar view of the first layer 401 as seen from above is shown on the left side, and the planar view of the second layer 402 as seen from above is shown on the right side.

[0067] In this fourth variant, a total of four (2 x 2) photoelectric conversion sections 411 included in one pixel unit share a reset transistor 421, an amplification transistor 422, a selection transistor 423, a conversion efficiency switching transistor 431, and an additional capacitance section 433.

[0068] In this fourth modification, a photoelectric conversion unit 411, a transfer transistor 102 having a transfer gate 412, and a floating diffusion 413 are provided in a region 401a of the first layer 401. Furthermore, in this fourth modification, an additional capacitance unit 433, a reset transistor 421, and a conversion efficiency switching transistor 431 are provided in a region 401b of the first layer 401. In detail, the additional capacitance unit 433 (more specifically, an electrode 433a of the additional capacitance unit 433) is provided adjacent to one pixel unit.

[0069] Furthermore, in the fourth modification, the second layer 402 is provided with an amplifying transistor (AMP) 202 and a selecting transistor (SEL) 203 .

[0070] (Variation 5) Next, the planar configuration of a pixel 10 according to Variation 5 of the present embodiment will be described with reference to Fig. 10. Fig. 10 is a plan view showing an example of the planar configuration of a pixel 10 according to Variation 5, and in detail, the planar view of the first layer 401 as seen from above is shown on the left, and the planar view of the second layer 402 as seen from above is shown on the right. The configuration of the pixel 10 according to Variation 5 is the same as that of Variation 1 described above, except for the additional capacitance portion 433, and therefore, description of the elements other than the additional capacitance portion 433 will be omitted here.

[0071] 10 , in the fifth modification, the additional capacitance portion 433 may be provided on a well region 208 having a second conductivity type (e.g., n-type) in the semiconductor substrate 200. In this case, a via 442 a is provided in the well region 208 to apply a reference potential (e.g., GND).

[0072] (Variation 6) Next, a variation of the isolation portion 440 will be described as Variation 6 of the present embodiment with reference to Figures 11A and 11B. Figure 11A is a cross-sectional view showing an example of Variation 6 of the isolation portion 440, and more specifically, the upper part shows a cross section of the semiconductor substrate 200 cut along line CC' shown in Figure 6A, and the lower part shows a cross section of the semiconductor substrate 200 cut along line DD' shown in Figure 6A. Figure 11B is a plan view showing an example of Variation 6 of the isolation portion 440, and more specifically, corresponds to the plan view of Figure 4A and shows only the isolation portion 440, which is a main part.

[0073] The left side of FIG. 11A shows a case where a well region 240 having a first conductivity type (e.g., p-type) is provided in the semiconductor substrate 200 as the isolation portion 440. The center of FIG. 11A shows a case where an STI 244a is provided as the isolation portion 440. In this case, it is preferable that a diffusion region 242 formed by diffusing impurities of the first conductivity type (e.g., p-type) is provided around the STI 244a. The right side of FIG. 11A shows a case where an FTI 244b is provided as the isolation portion 440. In this case, it is also preferable that a diffusion region 242 formed by diffusing impurities of the first conductivity type (e.g., p-type) is provided around the FTI 244b.

[0074] Furthermore, when an FTI 244b is provided as the separation unit 440, the planar configuration of the FTI 244b can be configured as shown in FIG. 11B . The left side of FIG. 11B shows an example of the planar configuration of the FTI 244b in the case where eight (2 × 4) photoelectric conversion units 411 share the reset transistor 421, the amplification transistor 422, the selection transistor 423, the conversion efficiency switching transistor 431, and the additional capacitance unit 433. The right side of FIG. 11B shows an example of the planar configuration of the FTI 244b in the case where four (2 × 2) photoelectric conversion units 411 share the reset transistor 421, the amplification transistor 422, the selection transistor 423, the conversion efficiency switching transistor 431, and the additional capacitance unit 433. Compared to the example shown in FIG. 11A , the example shown in FIG. 11B does not provide a separation unit 440 that completely surrounds the region 401b, thereby making it possible to increase the area of ​​the additional capacitance unit 433.

[0075] (Variation 7) Next, a variation of the amplifier transistor 422 will be described as Variation 7 of the present embodiment with reference to Fig. 12. Fig. 12 is a cross-sectional view showing an example of Variation 7 of the amplifier transistor 422, and corresponds to the drawing of Fig. 4B.

[0076] 12 , the amplification transistor 422 provided in the semiconductor substrate 250 of the second layer 402 may be a Fin Field Effect Transistor (FET). A Fin FET has a gate electrode with multiple fins embedded in the semiconductor substrate 250. In this way, by employing a Fin FET structure for the amplification transistor 422 in the present modification 7, random noise contained in pixel signals can be further suppressed.

[0077] (Variation 8) Next, a variation of the two-tier pixel structure will be described as Variation 8 of the present embodiment with reference to Fig. 13. Fig. 13 is a cross-sectional view showing an example of a pixel 10 according to Variation 8 of the present embodiment, and corresponds to the drawing of Fig. 4B.

[0078] In this eighth modification, as shown in FIG. 13 , the semiconductor substrate 200 of the first layer 401 and the semiconductor substrate 250 of the second layer 402 are located outside the stack of layers of the two-tier pixel structure. In other words, in this eighth modification, the pixel transistors provided in the first layer 401 and the pixel transistors provided in the second layer 402 are arranged to face each other. In this case, by bonding a bonding electrode 452 provided on the surface of the first layer 401 to a bonding electrode 452 provided on the surface of the second layer 402, the first layer 401 and the second layer 402 can be physically bonded and electrically connected. The bonding electrode 452 is preferably formed of a highly conductive metal such as copper (Cu).

[0079] 2.5 Manufacturing Method Next, an example of a method for manufacturing the pixel 10 according to this embodiment will be described with reference to Fig. 14. Fig. 14 is an explanatory diagram showing the method for manufacturing the pixel 10 according to this embodiment, and more specifically, corresponds to a cross section of the semiconductor substrate 200 taken along line E-E' shown in Fig. 4A.

[0080] First, as shown in the upper left of FIG. 14, silicon oxide (SiO ２ A protective film 290 made of silicon nitride (SiN) or silicon nitride (SiN) is formed, and a well region having n-type conductivity that becomes a photoelectric conversion portion 411 is formed in the semiconductor substrate 200 .

[0081] 14, a well region 240 having p-type conductivity that will become the isolation portion 440 is formed in the semiconductor substrate 200. Then, as shown in the upper right side of FIG. 14, a diffusion region 230 having n-type conductivity that will become the channel of the transfer transistor 102 is formed in the semiconductor substrate 200.

[0082] Next, as shown in the lower left side of Fig. 14 , p-type impurities are also implanted into the surface side of the semiconductor substrate 200 above the well region 240 to form a diffusion region 206. Then, as shown in the lower center of Fig. 14 , the protective film 290 is peeled off, and an insulating film 210 made of silicon oxide to serve as a gate oxide film is formed on the surface of the semiconductor substrate 200. Furthermore, as shown in the lower right side of Fig. 14 , a transfer gate 412 and an electrode 433a made of polysilicon are formed on the insulating film 210.

[0083] 14 shows an example of a method for manufacturing the pixel 10 according to this embodiment, and the method for manufacturing the pixel 10 according to this embodiment is not limited to the example shown in FIG.

[0084] <<3. Second Embodiment>> <3.1 Overview> In the second embodiment of the present disclosure created by the present inventors, as described above, a two-tier pixel structure is used to increase the capacitance value of the additional capacitance portion 433. In the first embodiment, in the two-tier pixel structure, pixel transistors are distributed across two layers 401 and 402, and the additional capacitance portion 433 is disposed in the vacant space in the first layer 401, thereby increasing the capacitance value of the additional capacitance portion 433. However, providing a large-area additional capacitance portion 433 in the first layer 401 increases the area of ​​the first layer 401, which may increase the size of the imaging device 30 and the manufacturing costs. On the other hand, providing a large-area additional capacitance portion 433 without increasing the area of ​​the first layer 401 results in a reduction in the size of the floating diffusion 413. In such a case, even if a function for switching the conversion efficiency is provided, when shooting in a bright place, the charge generated in the photoelectric conversion unit 101 will not be received by the floating diffusion 103 and the additional capacitance unit 433. Also, when shooting in a dark place, the charge generated in the photoelectric conversion unit 101 will not be received by the floating diffusion 103.

[0085] Therefore, the inventors have come up with the creation of a second embodiment of the present disclosure, in which an additional capacitance section 433 having a large capacitance value can be obtained without increasing the area of ​​the first layer 401 by forming an additional capacitance section 433 that extends in the film thickness direction of the semiconductor substrate 200 using a trench structure.

[0086] More specifically, in the second embodiment of the present disclosure, an additional capacitance section (first additional capacitance section) 433 is provided in the first layer 401 of the two-tier pixel structure. The additional capacitance section 433 has a diffusion region containing impurities of a first conductivity type (e.g., p-type) formed around the FTI 244b that penetrates the semiconductor substrate 200 of the first layer 401, and a diffusion region containing impurities of a second conductivity type (e.g., n-type) formed around the diffusion region. A capacitor is then generated where these two diffusion regions are adjacent to each other, and in this embodiment, this capacitor is used as the additional capacitance section 433.

[0087] In this embodiment, the additional capacitance portion 433 is provided by utilizing the trench structure of the semiconductor substrate 200, that is, the additional capacitance portion 433 is provided so as to extend in the depth direction of the semiconductor substrate 200, and therefore it is possible to obtain the additional capacitance portion 433 having a large capacitance value without increasing the area of ​​the first layer 401. Details of the second embodiment of the present disclosure will be described below in order.

[0088] <3.2 Equivalent Circuit> First, an equivalent circuit of the pixel 10 according to the second embodiment will be described with reference to Fig. 15. Fig. 15 is an equivalent circuit diagram of the pixel 10 according to this embodiment.

[0089] 15 , in the present embodiment, a pixel 10, like the comparative example, includes a photoelectric conversion unit 101, a transfer transistor 102 electrically connected to the photoelectric conversion unit 101, and a floating diffusion (charge storage unit) 103 that temporarily stores charge output from the photoelectric conversion unit 101 via the transfer transistor 102. Similarly to the comparative example, the pixel 10 also includes a reset transistor 201, an amplification transistor 202, and a selection transistor 203. Furthermore, in the present embodiment, the pixel 10 also includes a conversion efficiency switching transistor (additional transistor) 301 and an additional capacitance unit (first additional capacitance unit) 303. Unlike the first embodiment described above, in the present embodiment, one of the source and drain of the conversion efficiency switching transistor 301 is electrically connected to a node between the floating diffusion 103 and the reset transistor 201, and the additional capacitance unit 303 is electrically connected to the other of the source and drain of the conversion efficiency switching transistor 301.

[0090] <3.3 Detailed Configuration> Next, a detailed configuration of the pixel 10 according to this embodiment will be described with reference to FIGS. 16A to 16D. FIG. 16A is a plan view showing an example of the planar configuration of the pixel 10 according to this embodiment. Specifically, in this embodiment, the pixel 10 also has a two-tiered pixel structure and is composed of a first layer 401 and a second layer 402 stacked on the first layer 401. Therefore, FIG. 16A shows a plan view of the first layer 401 as viewed from above. FIG. 16B is a cross-sectional view showing an example of the cross-sectional configuration of the pixel 10 according to this embodiment, illustrating the two-tiered pixel structure of the pixel 10. Furthermore, FIG. 16C is a cross-sectional view of the semiconductor substrate 200 taken along line F-F' shown in FIG. 16A, and FIG. 16D is a cross-sectional view of the semiconductor substrate 200 taken along line G-G' shown in FIG. 16A.

[0091] Furthermore, in this embodiment, the total of eight (2 x 4) photoelectric conversion sections 411 included in the two pixel units will be described as sharing a reset transistor (RST) 421, an amplification transistor (AMP) 422, a selection transistor (SEL) 423, a conversion efficiency switching transistor (FDG) 431, and an additional capacitance section (first load capacitance section) 433.

[0092] In this embodiment, as shown in FIG. 16A , a region (first region) 401 a of a first layer 401 of a semiconductor substrate 200 is provided with a photoelectric conversion unit 411, a transfer transistor 102 having a transfer gate 412, and a floating diffusion (charge accumulation unit) 413. Specifically, as shown in FIG. 16A , the semiconductor substrate 200 is provided with four photoelectric conversion units 411 surrounding one floating diffusion 413. As described above, the four photoelectric conversion units 411 surrounding one floating diffusion 413 are referred to as a pixel unit. The pixel array unit 12 of the imaging device (photodetector) 30 is provided with a plurality of pixel units arranged in a matrix along the row and column directions. Furthermore, the four photoelectric conversion units 411 in one pixel unit are electrically connected to one floating diffusion 413 and share the floating diffusion 413. In this embodiment, the number of photoelectric conversion units 411 in a pixel unit is not limited to four, and for example, the pixel unit may have two photoelectric conversion units 411 arranged on either side of one floating diffusion 413.

[0093] In addition, a reset transistor 421, a conversion efficiency switching transistor 431, and an additional capacitance section 433 are provided in a region (second region) 401b of the semiconductor substrate 200 located adjacent to the region 401a.

[0094] Furthermore, the semiconductor substrate 200 is provided with an FTI (second trench) 244b that penetrates the entire semiconductor substrate 200 in the film thickness direction so as to separate the regions 401a and 401b. In this embodiment, the FTI 244b may be provided so as to surround each pixel unit, or may be provided so as to surround the periphery of each photoelectric conversion section 411. In this embodiment, the FTI 244b that separates the regions 401a and 401b is not limited to being an FTI that penetrates the semiconductor substrate 200, and may be an STI that penetrates a portion of the semiconductor substrate 200.

[0095] Furthermore, in this embodiment, for example, silicon oxide (SiO ２ The insulating film (insulating layer) may be filled with a conductive film such as polycrystalline silicon (Poly-Si), or a metal film such as tungsten (W).

[0096] 16B , an amplification transistor 422 and a selection transistor 423 (not shown) are provided in the second layer 402. In this embodiment, as shown in FIG. 16B , the pixel transistors provided in the second layer 402 are electrically connected to each other by a wiring 444. The pixel transistors provided in the second layer 402 are also electrically connected to the reset transistor 421 (not shown), the floating diffusion 413, and the like provided in the first layer 401 by vias 442.

[0097] 16C , the semiconductor substrate 200 of the first layer 401 has an FTI (first trench) 244b penetrating the semiconductor substrate 200 in the film thickness direction. Furthermore, a diffusion region (first diffusion region) 242 containing impurities of a first conductivity type (e.g., p-type) is formed around the FTI 244b, and a diffusion region (second diffusion region) 280 containing impurities of a second conductivity type (e.g., n-type) is formed around the diffusion region 242. In this case, the diffusion regions 242 and 280 can be formed by injecting impurities into the trench (groove) of the FTI 244b, or by forming a layer containing impurities in the trench and annealing the layer to diffuse the impurities from inside the trench to outside the trench. A capacitor is formed where the two diffusion regions 242 and 280 are adjacent to each other, and in this embodiment, this capacitor is used as the additional capacitance section 433.

[0098] In this embodiment, the FTI 244b that forms the additional capacitance portion 433 is not limited to being an FTI that penetrates the semiconductor substrate 200, and may be an STI that penetrates a portion of the semiconductor substrate 200. However, when attempting to obtain an additional capacitance portion 433 with a larger capacitance value, it is preferable to increase the area where the two diffusion regions 242, 280 are in contact, and therefore it is preferable that the trenches used to form these regions also extend long. Therefore, in this embodiment, it is preferable that the FTI 244b that forms the additional capacitance portion 433 is an FTI that penetrates the semiconductor substrate 200.

[0099] Furthermore, in this embodiment, the FTI 244b forming the additional capacitance portion 433 may extend not only in the film thickness direction of the semiconductor substrate 200 but also in the surface direction of the semiconductor substrate 200. By doing so, the contact area between the two diffusion regions 242, 280 provided around the FTI 244b can be increased, and as a result, an additional capacitance portion 433 with a large capacitance value can be obtained.

[0100] Furthermore, in this embodiment, a conductive film such as polycrystalline silicon or a metal film such as tungsten may be buried in the trench of the FTI 244b (or STI) that forms the additional capacitance portion 433. Through such a conductive film or the like in the trench, the additional capacitance portion 433 is electrically connected to an electrode provided on the upper surface of the additional capacitance portion 433. The electrode is formed of, for example, polysilicon or the like.

[0101] As described above, in this embodiment, the additional capacitance 433 is provided by utilizing the trench structure (FTI 244b) of the semiconductor substrate 200. That is, the additional capacitance 433 is provided so as to extend in the depth direction of the semiconductor substrate 200. This makes it possible to obtain the additional capacitance 433 having a large capacitance value without increasing the area of ​​the first layer 401. Furthermore, according to this embodiment, the additional capacitance 433 is formed using the diffusion regions 242 and 280. This makes it possible to easily form the additional capacitance 433 without significantly changing the conventional manufacturing process. Furthermore, in this embodiment, the FTI (second trench) 244b is provided, which penetrates the entire semiconductor substrate 200 in the film thickness direction so as to separate the regions 401a and 401b. This prevents impurities from diffusing into the photoelectric conversion region 411 from the diffusion region for forming the additional capacitance 433. Furthermore, by providing the FTI 244 b that separates the regions 401 a and 401 b , it is possible to inject an amount of impurity suitable for the additional capacitance section 433 into the diffusion regions 242 and 280 without worrying about the influence on the photoelectric conversion section 411 .

[0102] It should be noted that the configuration of the pixel 10 according to this embodiment is not limited to the examples shown in FIGS. 16A to 16D.

[0103] <3.4 Modifications> Next, modifications of the pixel 10 in this embodiment will be described.

[0104] 17A and 17B, a configuration of a pixel 10 according to Modification 1 of the present embodiment will be described. Fig. 17A is a plan view showing an example of the planar configuration of the pixel 10 according to Modification 1, and Fig. 17B is a cross-sectional view of a semiconductor substrate 200 taken along line HH' shown in Fig. 17A.

[0105] In this first modification, in order to further increase the size of the additional capacitance 433, vias (through vias) 442 provided on the FTIs 244b that form the additional capacitance 433 are used. In detail, as shown in FIG. 17B , in this first modification, the vias 442 that electrically connect the first layer 401 and the second layer 402 are formed from a metal film or the like and face each other with the insulating layer 260 in between, so that a capacitor can be formed between the vias 442. Therefore, in this first modification, by combining the additional capacitance (first load capacitance) using the FTIs 244b and the additional capacitance (second load capacitance) using the vias 442, it is possible to obtain an additional capacitance 433 with a large capacitance value.

[0106] 17, the vias 442 are shown as having a columnar shape, but in this embodiment, the shape is not limited to this and may be flat. By doing so, the area where the vias 442 face each other can be increased, and therefore, an additional capacitance section 433 with a large capacitance value can be obtained. Furthermore, instead of forming the insulating layer 260 from silicon oxide, hafnium oxide (HfO ２ ) can provide the additional capacitance portion 433 with a large capacitance value.

[0107] (Variation 2) First, the planar configuration of a pixel 10 according to Variation 2 of the present embodiment will be described with reference to Fig. 18A to Fig. 18C. Fig. 18A is a plan view showing an example of the planar configuration of a pixel 10 according to Variation 2, Fig. 18B is a cross-sectional view of a semiconductor substrate 200 taken along line J-J' shown in Fig. 18A, and Fig. 18C is a cross-sectional view of a semiconductor substrate 200 taken along line K-K' shown in Fig. 18A.

[0108] In this second modification, the reset transistor 421 is moved to the second layer 402, and the additional capacitance section 433 is expanded into the space created. In detail, as shown in FIG. 18C , a plurality of FTIs 244 b are arranged side by side at the expanded position, and a diffusion region (first diffusion region) 242 containing an impurity having a first conductivity type (e.g., p-type) is formed around each FTI 244 b, and a diffusion region (second diffusion region) 280 containing an impurity having a second conductivity type (e.g., n-type) is further formed around the diffusion region 242. In this manner, in this second modification, the additional capacitance section 433 can be expanded into the space created by moving the reset transistor 421 to the second layer 402, thereby obtaining an additional capacitance section 433 with a large capacitance value. 18B , by forming two diffusion regions 242, 280 around a plurality of FTIs 244b arranged laterally in the semiconductor substrate 200, capacitances arranged laterally in the semiconductor substrate 200 are generated, thereby making it possible to obtain an additional capacitance section 433 having a large capacitance value overall. Also, as shown in FIGS. 18A and 18B , by extending the electrode onto the extended additional capacitance section 433, the extended additional capacitance section 433 can also be electrically connected to the conversion efficiency switching transistor 431.

[0109] In this second modification, the FTI 244b forming the extended additional capacitance portion 433 is not limited to being an FTI that penetrates the semiconductor substrate 200, but may be an STI that penetrates a portion of the semiconductor substrate 200. However, when attempting to obtain an additional capacitance portion 433 with a larger capacitance value, it is preferable to increase the area where the two diffusion regions 242, 280 are in contact, and therefore it is preferable that the trenches used to form these regions also extend long. Therefore, in this embodiment, it is preferable that the FTI 244b forming the extended additional capacitance portion 433 is an FTI that penetrates the semiconductor substrate 200.

[0110] Also in the second modification, the FTI 244b forming the expanded additional capacitance 433 may extend not only in the film thickness direction of the semiconductor substrate 200 but also in the planar direction of the semiconductor substrate 200. Furthermore, the FTI 244b may have a zigzag shape or a rectangular wave shape. In this way, the contact area between the two diffusion regions 242, 280 provided around the FTI 244b can be increased, resulting in an additional capacitance 433 with a large capacitance value.

[0111] <<4. Summary>> As described above, in the embodiment of the present disclosure, the two-stage pixel structure is used to make it possible to reduce the size of the imaging device 30 and increase the capacitance value of the additional capacitance section.

[0112] In the above-described embodiment, the pixel 10 has been described as having a two-tier pixel structure consisting of two layers, but these layers may further include a substrate having a logic circuit mounted thereon, a substrate having a memory mounted thereon, a substrate having a circuit with an AI (Artificial Intelligence) function mounted thereon, etc. Furthermore, any of the layers of the pixel 10 may be provided with an element that detects not only visible light but also light of other wavelengths.

[0113] In the above-described embodiment of the present disclosure, the photoelectric conversion unit (photodiode) 101 is described in which the first conductivity type is p-type, the second conductivity type is n-type, and electrons are used as signal charges, but the embodiment of the present disclosure is not limited to such an example. For example, the present embodiment can also be applied to a photoelectric conversion unit 101 in which the first conductivity type is n-type, the second conductivity type is p-type, and holes are used as signal charges.

[0114] Furthermore, the imaging device 30 according to the embodiment of the present disclosure is not limited to an imaging device that detects the distribution of incident light amounts of visible light and captures an image. For example, the present embodiment may be applied to an imaging device that captures an image of the distribution of incident amounts of infrared rays, X-rays, particles, etc., a distance measuring device that measures distances by light reflection, or other semiconductor devices.

[0115] Furthermore, in this embodiment, it is possible to manufacture the semiconductor device by using the method, apparatus, and conditions that are used in the manufacture of a general semiconductor device, i.e., in this embodiment, it is possible to use the existing semiconductor device manufacturing process.

[0116] Examples of the above-mentioned method include a PVD (Physical Vapor Deposition) method, a CVD (Chemical Vapor Deposition) method, and an ALD (Atomic Layer Deposition) method. Examples of PVD methods include vacuum deposition, EB (electron beam) deposition, various sputtering methods (magnetron sputtering, RF (radio frequency)-DC (direct current) combined bias sputtering, ECR (electron cyclotron resonance) sputtering, facing target sputtering, high frequency sputtering, etc.), ion plating, laser ablation, molecular beam epitaxy (MBE), and laser transfer. Examples of CVD methods include plasma CVD, thermal CVD, metal organic (MO) CVD, and photo CVD. Other methods include electroplating, electroless plating, spin coating, dipping, casting, microcontact printing, drop casting, various printing methods such as screen printing, inkjet printing, offset printing, gravure printing, and flexographic printing, stamping, spraying, and various coating methods such as air doctor coater, blade coater, rod coater, knife coater, squeeze coater, reverse roll coater, transfer roll coater, gravure coater, kiss coater, cast coater, spray coater, slit orifice coater, and calendar coater. Furthermore, patterning methods include chemical etching such as shadow mask, laser transfer, and photolithography, and physical etching using ultraviolet light or laser. Additionally, planarization techniques include CMP (Chemical Mechanical Polishing), laser planarization, and reflow.

[0117] <<5. Application Examples>> <5.1 Application Examples to Smartphones> The technology according to the present disclosure may also be applied to electronic devices such as cameras and smartphones. Therefore, a configuration example of a smartphone 900 as an electronic device to which the present technology is applied will be described with reference to Fig. 19. Fig. 19 is a block diagram showing an example of a schematic functional configuration of a smartphone 900 to which the technology according to the present disclosure (the present technology) can be applied.

[0118] 19 , the smartphone 900 includes a CPU (Central Processing Unit) 901, a ROM (Read Only Memory) 902, and a RAM (Random Access Memory) 903. The smartphone 900 also includes a storage device 904, a communication module 905, and a sensor module 907. The smartphone 900 also includes an imaging device 30, a display device 910, a speaker 911, a microphone 912, an input device 913, and a bus 914. The smartphone 900 may also include a processing circuit such as a DSP (Digital Signal Processor) instead of or in addition to the CPU 901.

[0119] The CPU 901 functions as an arithmetic processing unit and control device, and controls all or part of the operations within the smartphone 900 in accordance with various programs recorded in the ROM 902, RAM 903, storage device 904, etc. The ROM 902 stores programs and calculation parameters used by the CPU 901. The RAM 903 temporarily stores programs used in the execution of the CPU 901 and parameters that change as appropriate during the execution. The CPU 901, ROM 902, and RAM 903 are interconnected by a bus 914. The storage device 904 is a data storage device configured as an example of a storage unit of the smartphone 900. The storage device 904 is configured, for example, by a magnetic storage device such as an HDD (hard disk drive), a semiconductor storage device, an optical storage device, etc. This storage device 904 stores programs executed by the CPU 901, various data, and various data acquired from outside.

[0120] The communication module 905 is a communication interface configured with, for example, a communication device for connecting to the communication network 906. The communication module 905 may be, for example, a communication card for a wired or wireless local area network (LAN), Bluetooth (registered trademark), or wireless USB (WUSB). The communication module 905 may also be a router for optical communication, a router for asymmetric digital subscriber line (ADSL), or a modem for various communications. The communication module 905 transmits and receives signals between the Internet and other communication devices using a predetermined protocol such as TCP (Transmission Control Protocol) / IP (Internet Protocol). The communication network 906 connected to the communication module 905 is a wired or wireless network, such as the Internet, a home LAN, infrared communication, or satellite communication.

[0121] The sensor module 907 includes various sensors such as a motion sensor (e.g., an acceleration sensor, a gyro sensor, a geomagnetic sensor, etc.), a biometric information sensor (e.g., a pulse sensor, a blood pressure sensor, a fingerprint sensor, etc.), or a position sensor (e.g., a GNSS (Global Navigation Satellite System) receiver, etc.).

[0122] The imaging device 30 is provided on the surface of the smartphone 900 and can capture an image of an object located on the front or back side of the smartphone 900. Specifically, the imaging device 30 is configured to employ the technology disclosed herein (the present technology). That is, the imaging device 30 may include an imaging element (not shown) and a signal processing circuit (not shown) that performs imaging signal processing on a signal photoelectrically converted by the imaging element. Furthermore, the imaging device 30 may further include an optical system mechanism (not shown) including an imaging lens, a zoom lens, a focus lens, and the like, and a drive system mechanism (not shown) that controls the operation of the optical system mechanism. The imaging element collects incident light from an object as an optical image, and the signal processing circuit photoelectrically converts the formed optical image on a pixel-by-pixel basis, reads out the signal from each pixel as an imaging signal, and performs image processing to obtain a captured image.

[0123] The display device 910 is provided on the surface of the smartphone 900 and can be, for example, a display device such as an LCD (Liquid Crystal Display) or an organic EL (Electro Luminescence) display. The display device 910 can display an operation screen, an image captured by the imaging device 30 described above, and the like.

[0124] The speaker 911 can output, for example, telephone call audio and audio accompanying the video content displayed by the display device 910 described above to the user.

[0125] The microphone 912 can collect, for example, the user's voice during a call, voice including commands to activate functions of the smartphone 900, and voice from the surrounding environment of the smartphone 900.

[0126] The input device 913 is a device operated by a user, such as a button, a keyboard, a touch panel, or a mouse. The input device 913 includes an input control circuit that generates an input signal based on information input by the user and outputs the signal to the CPU 901. By operating the input device 913, the user can input various data to the smartphone 900 and instruct processing operations.

[0127] The above describes an example configuration of the smartphone 900. Each of the above components may be configured using general-purpose components, or may be configured using hardware specialized for the function of each component. Such a configuration may be changed as appropriate depending on the technical level at the time of implementation.

[0128] Furthermore, by applying the technology according to the present disclosure, a small imaging device (photodetector) 30 can be obtained, which can be applied to a camera attached to a part of the user's body, etc. Similarly, the technology according to the present disclosure can also be applied to a camera mounted on an HMD (Head Mounted Display) that provides a virtual reality experience by superimposing and displaying virtual items on a real spatial image.

[0129] 5.2 Application Example to Endoscopic Surgery System The technology according to the present disclosure (the present technology) may be applied to, for example, an endoscopic surgery system.

[0130] FIG. 20 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0131] 20 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0132] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0133] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0134] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected by the optical system onto the image sensor. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0135] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various types of image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0136] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0137] The light source device 11203 is composed of a light source such as an LED (Light Emitting Diode), and supplies the endoscope 11100 with irradiation light when photographing the surgical site, etc.

[0138] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0139] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0140] The light source device 11203, which supplies illumination light to the endoscope 11100 when photographing the surgical site, can be configured from a white light source, such as an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, allowing the light source device 11203 to adjust the white balance of the captured image. In this case, it is also possible to time-share images corresponding to each RGB by irradiating the object of observation with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, color images can be obtained without providing a color filter to the image sensor.

[0141] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0142] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light in a narrower band than the light irradiated during normal observation (i.e., white light) to capture high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, in what is known as narrow band imaging. Alternatively, special light observation may involve fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation may involve irradiating excitation light onto body tissues and observing the fluorescence from the tissues (autofluorescence observation), or may involve locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissues with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow band light and / or excitation light corresponding to such special light observation.

[0143] FIG. 21 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0144] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0145] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0146] The imaging unit 11402 may include one imaging element (a so-called single-chip type) or multiple imaging elements (a so-called multi-chip type). When the imaging unit 11402 is configured as a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. The 3D display allows the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is configured as a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0147] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0148] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0149] The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0150] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0151] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0152] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0153] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0154] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0155] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102 .

[0156] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0157] Furthermore, the control unit 11413 displays the captured image showing the surgical site, etc., on the display device 11202 based on the image signal subjected to image processing by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0158] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for electrical signal communication, an optical fiber for optical communication, or a composite cable of these.

[0159] In the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0160] The above describes an example of an endoscopic surgery system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the imaging unit 11402 of the camera head 11102, etc., among the above-described configurations.

[0161] Although an endoscopic surgery system has been described as an example here, the technology disclosed herein may also be applied to other systems, such as a microsurgery system.

[0162] 5.3 Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0163] FIG. 22 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0164] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 22, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0165] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0166] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0167] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0168] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0169] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0170] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0171] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0172] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0173] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 22, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0174] FIG. 23 is a diagram showing an example of the installation position of the imaging unit 12031.

[0175] In FIG. 23, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0176] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0177] 23 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0178] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0179] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0180] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0181] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0182] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to, for example, the image capturing unit 12031 and the like among the above-described components.

[0183] <<6. Supplementary Information>> Although preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, the technical scope of the present disclosure is not limited to such examples. It is clear that a person skilled in the art of the present disclosure can conceive of various modified or altered examples within the scope of the technical idea described in the claims, and it is understood that these also naturally fall within the technical scope of the present disclosure.

[0184] Furthermore, the effects described herein are merely descriptive or exemplary and are not limiting. In other words, the technology according to the present disclosure may achieve other effects that will be apparent to those skilled in the art from the description of this specification, in addition to or in place of the above-described effects.

[0185] The present technology can also be configured as follows: (1) A photodetector device including: a photoelectric conversion unit that converts light into an electric charge, a charge accumulation unit that accumulates the electric charge from the photoelectric conversion unit, an amplification transistor that converts the electric charge accumulated in the charge accumulation unit into a pixel signal, a first additional capacitance unit that adds capacitance to the charge accumulation unit, and an additional transistor that switches conversion efficiency by switching between enabling and disabling the addition of the first additional capacitance unit to the charge accumulation unit, the photodetector device being formed by laminating a first layer having the photoelectric conversion unit, the charge accumulation unit, and the first additional capacitance unit, and a second layer having the amplification transistor and laminated on the first layer. (2) The photodetector according to (1), wherein the first layer includes a semiconductor substrate, and when viewed from above the semiconductor substrate, a first region of the semiconductor substrate is provided with a plurality of pixel units arranged in a matrix along row and column directions, and a second region adjacent to the first region is provided with the first additional capacitance section, and the pixel unit has one of the charge accumulation sections and a predetermined number of the photoelectric conversion sections provided to correspond to the one charge accumulation section. (3) The photodetector according to (2), wherein the pixel unit has four of the photoelectric conversion sections provided to surround the one charge accumulation section. (4) The photodetector according to (2) or (3), further comprising a selection transistor electrically connected to the amplification transistor and selecting the amplification transistor that outputs the pixel signal, and the selection transistor is provided in the second layer. (5) The photodetector according to any one of (2) to (4), wherein the first additional capacitance section has a first electrode extending along one of the pixel units when viewed from above the semiconductor substrate. (6) The photodetector according to (5), further comprising a reset transistor electrically connected to the charge accumulation section and resetting the charge accumulated in the charge accumulation section, the reset transistor being provided in the first layer. (7) The photodetector according to (6), wherein the additional transistor is provided in the first layer.(8) The photodetector according to any one of (2) to (4), wherein the first additional capacitance has a first electrode extending along two adjacent pixel units when viewed from above the semiconductor substrate. (9) The photodetector according to (8), further comprising a reset transistor that resets the charge stored in the charge storage section, wherein the reset transistor and the additional transistor are provided in the second layer. (10) The photodetector according to any one of (5) to (9), wherein the first additional capacitance is formed from a diffusion region in which impurities are diffused in the semiconductor substrate and the first electrode provided on the diffusion region via an insulating film. (11) The photodetector according to (10), wherein the first additional capacitance is electrically connected to a second additional capacitance formed from a dielectric layer provided on the first electrode and a second electrode provided on the dielectric layer. (12) The photodetector according to any one of (2) to (4), wherein the first layer includes a first trench penetrating at least a portion of the semiconductor substrate along a film thickness direction of the semiconductor substrate, and the first additional capacitance is formed by: a first diffusion region located around the first trench and containing an impurity of a first conductivity type; and a second diffusion region located around the first region and containing an impurity of a second conductivity type that is the opposite conductivity type to the first conductivity type. (13) The photodetector according to (12), wherein the first trench penetrates the semiconductor substrate along a film thickness direction of the semiconductor substrate. (14) The photodetector according to (12) or (13), wherein the first additional capacitance is formed by the first and second diffusion regions provided in each of a plurality of first trenches provided in the semiconductor substrate. (15) The photodetector according to any one of (12) to (14) above, further comprising a reset transistor electrically connected to the charge storage section via the additional transistor and resetting the charge stored in the charge storage section, wherein the reset transistor and the additional transistor are provided in the first layer.(16) The photodetector according to (15), wherein, when viewed from above the semiconductor substrate, the reset transistor and the additional transistor are provided in the second region, and the first and second regions are separated by a second trench that penetrates at least a part of the semiconductor substrate along a film thickness direction of the semiconductor substrate. (17) The photodetector according to any one of (12) to (16), wherein the first layer further includes an insulating layer stacked on the semiconductor substrate, and the first additional capacitance portion is electrically connected to a second additional capacitance portion formed between a plurality of through vias that penetrate the insulating layer. (18) The photodetector according to any one of (1) to (17), further comprising a transfer transistor that is electrically connected to one terminal of the photoelectric conversion portion and transfers the charge to the charge accumulation portion, and the transfer transistor is provided in the first layer. (19) The photodetector according to any one of (1) to (18), wherein the first additional capacitance section is electrically connected to the charge storage section via the additional transistor. (20) The photodetector according to any one of (1) to (19), wherein the amplifying transistor is electrically connected to the charge storage section.

[0186] 10, 10a Pixel 12 Pixel array section 30 Imaging device 32 Vertical drive circuit section 34 Column signal processing circuit section 36 Horizontal drive circuit section 38 Output circuit section 42 Pixel drive wiring 44 Control circuit section 46 Horizontal signal line 48 Vertical signal line 101, 411 Photoelectric conversion section 102 Transfer transistor 103, 413 Floating diffusion 200, 250 Semiconductor substrate 201, 421 Reset transistor 202, 422 Amplification transistor 203, 423 Selection transistor 204, 260 Insulating layer 206, 206a, 230, 242, 280 Diffusion region 208, 240 Well region 210 Insulating film 244a STI 244b FTI 290 Protective film 301, 431 Conversion efficiency switching transistor 303, 433 Additional capacitance section 401, 402 Layer 401a, 401b Region 412 Transfer gate 431a, 433a, 435 Electrode 434 Dielectric layer 440 Separation section 442, 442a Via 444 Wiring 452 Junction electrode

Claims

1. A photodetection device comprising: a photoelectric conversion unit that converts light into charges; a charge storage unit that stores the charges from the photoelectric conversion unit; an amplification transistor that converts the charges stored in the charge storage unit into pixel signals; a first additional capacitance unit that adds capacitance to the charge storage unit; and an additional transistor that switches the conversion efficiency by enabling or disabling the addition of the first additional capacitance unit to the charge storage unit, wherein the photodetection device is formed from a stack of a first layer having the photoelectric conversion unit, the charge storage unit, and the first additional capacitance unit, and a second layer having the amplification transistor and laminated on the first layer.

2. The first layer includes a semiconductor substrate. When viewed from above the semiconductor substrate, a plurality of pixel units arranged in a matrix along the row direction and the column direction are provided in a first region of the semiconductor substrate, and the first additional capacitance unit is provided in a second region adjacent to the first region. The pixel unit has one of the charge storage units and a predetermined number of the photoelectric conversion units provided corresponding to the one charge storage unit. The photodetection device according to claim 1.

3. The pixel unit has four of the photoelectric conversion units provided so as to surround the one charge storage unit. The photodetection device according to claim 2.

4. The photodetection device further comprises a selection transistor that is electrically connected to the amplification transistor and selects the amplification transistor that outputs the pixel signal, and the selection transistor is provided in the second layer. The photodetection device according to claim 2.

5. The first additional capacitance unit has a first electrode that extends along one of the pixel units when viewed from above the semiconductor substrate. The photodetection device according to claim 2.

6. The photodetection device further comprises a reset transistor that is electrically connected to the charge storage unit and resets the charges stored in the charge storage unit, and the reset transistor is provided in the first layer. The photodetection device according to claim 5.

7. The additional transistor is provided in the first layer. The photodetection device according to claim 6.

8. The first additional capacitance unit has a first electrode that extends along two adjacent pixel units when viewed from above the semiconductor substrate. The photodetection device according to claim 2.

9. The photodetection device according to claim 8, further comprising a reset transistor configured to reset the charge stored in the charge storage unit, wherein the reset transistor and the additional transistor are provided in the second layer.

10. The photodetection device according to claim 5, wherein the first additional capacitance unit is formed of a diffusion region in which impurities are diffused in the semiconductor substrate and a first electrode provided on the diffusion region via an insulating film.

11. The photodetection device according to claim 10, wherein the first additional capacitance unit is electrically connected to a second additional capacitance unit formed of a dielectric layer provided on the first electrode and a second electrode provided on the dielectric layer.

12. The photodetection device according to claim 2, wherein the first layer includes a first trench that penetrates at least a part of the semiconductor substrate along the thickness direction of the semiconductor substrate, and the first additional capacitance unit is located around the first trench and includes a first diffusion region containing impurities having a first conductivity type, and a second diffusion region located around the first region and containing impurities having a second conductivity type opposite to the first conductivity type.

13. The photodetection device according to claim 12, wherein the first trench penetrates the semiconductor substrate along the thickness direction of the semiconductor substrate.

14. The photodetection device according to claim 12, wherein the first additional capacitance unit is formed by the first and second diffusion regions provided in each of the plurality of first trenches provided in the semiconductor substrate.

15. The photodetection device according to claim 12, further comprising a reset transistor that is electrically connected to the charge storage unit via the additional transistor and configured to reset the charge stored in the charge storage unit, wherein the reset transistor and the additional transistor are provided in the first layer.

16. The photodetection device according to claim 15, wherein when viewed from above the semiconductor substrate, the reset transistor and the additional transistor are provided in the second region, and the first and second regions are separated by a second trench that penetrates at least a part of the semiconductor substrate along the thickness direction of the semiconductor substrate.

17. The first layer further includes an insulating layer laminated on the semiconductor substrate, and the first additional capacitance portion is electrically connected to a second additional capacitance portion formed between a plurality of through vias penetrating the insulating layer. The photodetection device according to claim 12.

18. The photodetection device according to claim 1 further includes a transfer transistor that is electrically connected to one terminal of the photoelectric conversion portion and transfers the charge to the charge storage portion, and the transfer transistor is provided in the first layer.

19. The photodetection device according to claim 1, wherein the first additional capacitance portion is electrically connected to the charge storage portion via the additional transistor.

20. The photodetection device according to claim 1, wherein the amplification transistor is electrically connected to the charge storage portion.

Images