Circuit board and semiconductor package comprising same

Abstract

In an embodiment of the present invention, disclosed is a circuit board comprising: a first insulating layer; a second insulating layer disposed on the first insulating layer; a first via land disposed between the first insulating layer and the second insulating layer; a first via electrode disposed between the first via land and the lower surface of the first insulating layer; a second via electrode disposed between the first via land and the upper surface of the second insulating layer; and a third via electrode disposed between the lower surface of the first insulating layer and the upper surface of the second insulating layer, wherein the vertical length of the third via electrode is greater than the sum of the vertical length of the first via electrode and the vertical length of the second via electrode.

Description

Circuit boards and semiconductor packages including the same

[0001] Embodiments according to the present invention relate to circuit boards and semiconductor packages.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to attach a greater number of packages to a limited-size substrate. However, because typical packages are based on mounting a single semiconductor chip, achieving the desired performance is limited.

[0003] A typical circuit board or package substrate consists of a processor package, which houses the processor chip, and a memory package, which houses the memory chips, all connected together. These package substrates integrate the processor and memory chips into a single package, reducing the chip footprint and enabling high-speed signal transmission through short paths. Due to these advantages, these package substrates are widely used in mobile devices and other devices.

[0004] Meanwhile, the recent advancements in electronic devices, such as mobile devices, and the adoption of High Bandwidth Memory (HBM) have led to larger package sizes. Furthermore, as the number of functions required for application processors increases, there is a growing demand for separate processor chips for each function, along with circuit boards capable of mounting these processor chips. Even when the application processor is split into two processor chips, the number of terminals (input / output) provided on each processor chip is increasing.

[0005] In addition, due to recent trends such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed, the number of terminals on processor chips is gradually increasing due to the increase in power and signal quantity. Accordingly, the area, thickness, and circuit pattern density of circuit boards are also increasing. When the area and thickness of circuit boards increase, it becomes difficult to miniaturize products, and there are problems such as reliability issues such as warpage of circuit boards, and product price increases. Therefore, increasing the density of circuit patterns is more advantageous in terms of product price, reliability issues such as warpage, and product miniaturization than increasing the area and thickness of circuit boards. Therefore, miniaturization of circuit patterns and through-holes is required.

[0006] In particular, as circuit boards become increasingly thinner, structures with improved reliability are being proposed.

[0007] An embodiment of the present invention provides a circuit board and a semiconductor package including the same that suppresses the occurrence of voids or gaps at the interface of the insulating layers by controlling the structure of a via hole penetrating a multi-layer insulating layer.

[0008] Additionally, the embodiment can provide a circuit board and a semiconductor package including the same with improved integration, increased input / output count, and reduced signal loss through an embedded capacitor structure.

[0009] In addition, the embodiment can provide a circuit board with improved structural reliability through protrusions, etc., and a semiconductor package including the same.

[0010] The problem to be solved in the embodiment is not limited to this, and it can be said that the purpose or effect that can be understood from the solution or implementation form of the problem described below is also included.

[0011] A circuit board according to an embodiment of the present invention includes a first insulating layer; a second insulating layer disposed on the first insulating layer; a first via land disposed between the first insulating layer and the second insulating layer; a first via electrode disposed between the first via land and a lower surface of the first insulating layer; a second via electrode disposed between the first via land and an upper surface of the second insulating layer; and a third via electrode disposed between the lower surface of the first insulating layer and an upper surface of the second insulating layer, wherein a vertical length of the third via electrode is greater than a sum of a vertical length of the first via electrode and a vertical length of the second via electrode.

[0012] The third via electrode may overlap the first via electrode and the second via electrode in a horizontal direction.

[0013] The second insulating layer includes a protrusion penetrating at least a portion of the first insulating layer from the upper surface toward the lower surface of the first insulating layer, and the third via electrode can be disposed within the protrusion.

[0014] The width of the first via electrode may gradually increase from the upper surface of the first insulating layer toward the lower surface of the first insulating layer, and the width of the second via electrode may gradually decrease from the upper surface of the second insulating layer toward the lower surface of the second insulating layer.

[0015] The width of the third via electrode may gradually decrease from the upper surface of the second insulating layer toward the lower surface of the first insulating layer.

[0016] The first via electrode includes a first width having the smallest width on the upper surface of the first insulating layer, the second via electrode includes a second width having the smallest width on the lower surface of the second insulating layer, and the third via electrode includes a third width having the smallest width in an area adjacent to the lower surface of the first insulating layer, and the third width may be smaller than the first width.

[0017] It may include a capacitor structure including the first via land, the dielectric layer, and the second via land sequentially stacked on the first insulating layer.

[0018] The second via electrode may be disposed on the capacitor structure.

[0019] The above capacitor structure may include a first capacitor structure and a second capacitor structure that are spaced apart.

[0020] The third via electrode may be disposed between the first capacitor structure and the second capacitor structure.

[0021] The third via electrode can penetrate the capacitor structure.

[0022] The second via electrode may overlap the capacitor structure in the vertical direction.

[0023] The above capacitor structure may be at least partially embedded in the first insulating layer.

[0024] The above protrusion can overlap horizontally with the third via electrode.

[0025] The above protrusion may be placed below the second via electrode.

[0026] The difference between the height of the third via electrode and the height of the second via electrode may be greater than the thickness of the second insulating layer.

[0027] The angle of the third via electrode may be different from the angle of the inner wall of the protrusion.

[0028] A third insulating layer disposed on the first insulating layer; wherein the second insulating layer can cover the third insulating layer.

[0029] The third via electrode and the second via electrode can penetrate the third insulating layer.

[0030] The protrusion may include a first protrusion adjacent to the third via electrode; and a second protrusion adjacent to the second via electrode.

[0031] The above first protrusion can protrude toward the third insulating layer and the first insulating layer.

[0032] The second protrusion may protrude toward the third insulating layer.

[0033] The above protrusion can be in contact with the boundary surface of the first insulating layer and the third insulating layer.

[0034] An embodiment of the present invention implements a circuit board and a semiconductor package including the same, which suppresses the occurrence of voids or gaps at the interface of the insulating layers by controlling the structure of a via hole penetrating a multi-layer insulating layer.

[0035] In addition, the embodiment can implement a circuit board and a semiconductor package including the same with improved integration, increased input / output count, and reduced signal loss through an embedded capacitor structure.

[0036] In addition, the embodiment can implement a circuit board with improved structural reliability through protrusions, etc., and a semiconductor package including the same.

[0037] The various advantageous and beneficial effects of the present invention are not limited to the above-described contents, and will be more easily understood in the course of explaining specific embodiments of the present invention.

[0038] Figure 1 is a cross-sectional view of a circuit board according to a first embodiment of the present invention.

[0039] Figure 2 is an enlarged view of part K1 in Figure 1,

[0040] Figure 3 is an enlarged view of part K2 in Figure 1,

[0041] Figure 4 is an enlarged view of part K3 in Figure 1,

[0042] Fig. 5 is a modified example of Fig. 4,

[0043] Figures 6a to 6p are drawings explaining a method for manufacturing a circuit board according to the first embodiment.

[0044] Fig. 7 is a cross-sectional view of a circuit board according to a second embodiment of the present invention.

[0045] FIG. 8 is a perspective view showing the relationship between the third via electrode and the capacitor structure in a circuit board according to the second embodiment of the present invention.

[0046] Fig. 9 is a cross-sectional view of a circuit board according to a third embodiment of the present invention.

[0047] Figure 10 is an enlarged view of K4 of Figure 9,

[0048] Figure 11 is an enlarged view of K5 of Figure 9,

[0049] Figure 12 is an enlarged view of K6 of Figure 9,

[0050] Figures 13a to 13q are drawings explaining a method for manufacturing a circuit board according to a third embodiment.

[0051] Fig. 14 is a schematic diagram of a circuit board according to an embodiment and a package board to which the circuit board is applied.

[0052] The present invention can be modified in various ways and has various embodiments, and specific embodiments are illustrated and described in the drawings. However, this is not to be construed as a specific embodiment of the present invention.

[0053] It is not intended to be limited to the embodiments, and should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention.

[0054] Terms that include ordinal numbers, such as "second," "first," etc., may be used to describe various components, but the components are not limited by the terms. The terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a second component may be referred to as "first component," and similarly, a first component may also be referred to as "second component." The term "and / or" includes a combination of multiple related items described herein or any of multiple related items described herein.

[0055] When a component is referred to as being "connected" or "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but that there may be other components intervening. Conversely, when a component is referred to as being "directly connected" or "connected" to another component, it should be understood that there are no other components intervening.

[0056] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0057] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0058] Hereinafter, embodiments will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or corresponding components are given the same reference numbers, and redundant descriptions thereof will be omitted.

[0059] Before describing the embodiments, an electronic device to which the circuit board and semiconductor package of the embodiments are applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. The semiconductor package may further include a circuit board, a plurality of semiconductor elements arranged on the circuit board, and a connecting member electrically connecting the plurality of semiconductor elements.

[0060] The circuit board may include a plurality of laminated insulating layers, circuit patterns arranged within each of the plurality of laminated insulating layers, and via electrodes for connecting the circuit patterns arranged within each of the insulating layers.

[0061] The semiconductor device may be mounted on a circuit board, and may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions or more active and / or passive devices are integrated into a single chip. For example, the semiconductor device may be a logic chip, a memory chip, etc. The logic chip may be a central processor (CPU), a graphics processor (GPU), etc. For example, the logic chip may be an application processor (AP) chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), a field programmable gate array (FPGA), etc., or a chip set including a specific combination of those listed so far. In addition, the semiconductor device may be a memory device such as a high bandwidth memory (HBM).

[0062] A connecting member is a component that functions to electrically connect a plurality of semiconductor elements, and can be placed between the semiconductor elements and the circuit board. For example, the connecting member can be embedded in the circuit board, or can be placed on the circuit board. When embedded in the circuit board, it can have the advantage of reducing the thickness of the semiconductor package. The connecting member can be formed of silicon, but is not limited thereto, and can be formed of an organic material, and since it functions to electrically interconnect a plurality of semiconductor elements, it can be referred to as a bridge.

[0063] Additionally, the connecting member may be placed on a circuit board. When placed on a circuit board, the connecting member may be covered with a molding member, and the circuit board, semiconductor element, and connecting member may be electrically interconnected through a Through Mold Via (TMV) penetrating the molding member. Additionally, a redistribution layer may be placed between the molding member and the semiconductor element.

[0064] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0065] Additionally, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the present invention is not limited thereto, and it is to be understood that the electronic device may be any other electronic device that processes data.

[0066] Hereinafter, a circuit board according to an embodiment of the present invention may include a core layer, a first build-up layer disposed on one surface of the core layer, and a second build-up layer disposed on the other surface of the core layer. In addition, the first build-up layer and the second build-up layer may each include a plurality of laminated insulating layers. In addition, the circuit board may not include a core layer, and may be composed of the first build-up layer and / or the second build-up layer. That is, the circuit board may be composed of insulating layers of the first build-up layer, the core layer, and the second build-up layer (or the first build-up layer and / or the second build-up layer). In addition, the first build-up layer and the second build-up layer may be distinguished by a structure in which the expansion directions of via holes within the layers are opposite to each other. For example, the width or area of ​​the via hole may increase (increase) toward the top of the first build-up layer. In addition, the width or area of ​​the via hole may decrease (increase) toward the top of the second build-up layer. In addition, each build-up layer may correspond to an insulating layer other than the core layer. A detailed explanation of this will be provided later.

[0067] FIG. 1 is a cross-sectional view of a circuit board according to a first embodiment of the present invention, FIG. 2 is an enlarged view of a portion K1 in FIG. 1, FIG. 3 is an enlarged view of a portion K2 in FIG. 1, FIG. 4 is an enlarged view of a portion K3 in FIG. 1, and FIG. 5 is a modified example of FIG. 4.

[0068] Referring to FIG. 1, a circuit board (100) according to the first embodiment may include an insulating layer (110), an electrode portion (120), and a capacitor structure (CAS, see FIG. 4). Furthermore, the circuit board (100) may include a protective layer disposed on the electrode portion (120), or a core layer, which is an insulating layer disposed within the insulating layer (110).

[0069] The insulating layer (110) may be composed of multiple layers. The insulating layer (110) may include a first insulating layer (111), a second insulating layer (112), a first lower insulating layer (114), and a second lower insulating layer (115).

[0070] The second lower insulating layer (115), the first lower insulating layer (114), the first insulating layer (111), and the second insulating layer (112) can be sequentially positioned along the lamination direction or the vertical direction (X-axis direction). In other words, the second lower insulating layer (115), the first lower insulating layer (114), the first insulating layer (111), and the second insulating layer (112) can be sequentially laminated.

[0071] The insulating layer (110) may include a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide. In addition, the insulating layer (110) may further include a reinforcing material in the resin. The reinforcing material may be, for example, a fabric reinforcing material, an inorganic filler, etc. The fabric reinforcing material may be glass fiber, and the glass fiber may be impregnated into the resin to form a prepreg (PPG).

[0072] For example, the insulating layer (110) may be formed of any insulating resin, such as a thermosetting and / or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto, can be used, and a material such as prepreg (PPG) containing glass fiber can be used. As the photocurable resin, any insulating resin, such as PID (Photo Imageable Dielectric) resin, can be used. The above-described arbitrary insulating resin may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and may include an inorganic filler such as silica. When the insulating resin is used as a core, it may include a reinforcing material formed of glass fiber or aramid fiber. For example, the insulating layer (110) may use ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., as an example, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. may be used. For example, the insulating layer (110) may include a plurality of layers composed of ABF.

[0073] Each insulating layer may be made of the same or different material. For example, the second insulating layer may be made of the same or different material from the other insulating layers.

[0074] Additionally, a protective layer may be further disposed on the uppermost or lowermost portion of the insulating layer (110). The protective layer (not shown) may have the function of protecting the pad from external moisture or contaminants, and may be formed of, for example, a solder resist to prevent a short circuit problem when bonding between a semiconductor element and / or a main board and a circuit board. Specifically, the semiconductor element and / or the main board, etc., have a plurality of terminals to be connected to the circuit board. In addition, the plurality of terminals may be arranged at a high density. When bonding the plurality of terminals and the pads of the circuit board, solder may be used, for example. When using solder, a solder short circuit problem may occur between terminals having a high density, and thus, a solder resist having poor wettability with the solder may be disposed to solve this short circuit problem. In addition, the protective layer (not shown) may be formed of a material having insulating properties for electrical connection. Accordingly, the protective layer (not shown) may be called an 'insulating layer' and may be a component of the above-described insulating layer (120). The protective layer (not shown) may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. In addition, the third insulating layer (not shown) may include any one of a photo solder resist layer, a cover-lay, and a polymer material.

[0075] And the insulating layer or protective layer (not shown) located in the outer laminated area of ​​the circuit board may have an opening. Through the opening, it may be electrically connected to other semiconductor elements, the circuit board, etc.

[0076] The electrode portion (120) may include a circuit pattern (or circuit pattern layer), a pad, and a via electrode. The wiring may correspond to an 'electrode pattern', a 'pattern', a 'line', etc.

[0077] In an embodiment, the electrode portion (120) may include a wiring electrode and a via electrode. The embryonic electrode may include a wiring (or circuit pattern, pattern) and a pad arranged in an insulating layer. The via electrode may be located within a through hole or a via (Vertical Interconnect Access) hole formed in the insulating layer. Through the via electrode, an electrical connection may be implemented within the insulating layer or above or below the insulating layer.

[0078] The electrode portion (120) may include a first electrode portion (121), a second electrode portion (122), a third electrode portion (123), a fourth electrode portion (124), and a fifth electrode portion (125). Each electrode portion may include a wiring portion and a via electrode.

[0079] The first electrode portion (121) may be located in the first insulating layer (111). The second electrode portion (122) may be located in the second insulating layer (112). The third electrode portion (123) may be located in the first insulating layer (111) and the second insulating layer (112). In addition, the fourth electrode portion (124) may be located in the first lower insulating layer (114). The fifth electrode portion (125) may be located in the second lower insulating layer (115). A detailed description thereof will be provided later.

[0080] Furthermore, the first electrode portion (121) may include a first via electrode (121a) and a first wiring portion (121b). In addition, the second electrode portion (122) may include a second via electrode (122a) and a second wiring portion (122b). The third electrode portion (123) may include a third via electrode (123a) and a third wiring portion (123b). In addition, the fourth electrode portion (124) may include a fourth via electrode (124a) and a fourth wiring portion (124b). And the fifth electrode portion (125) may include a fifth via electrode (125a) and a fifth wiring portion (125b).

[0081] In addition, the outer pad of the electrode portion (120) can be bonded to a semiconductor element, substrate, board, etc. using solder, wire, conductive adhesive, etc., and can be arranged with a width larger than the width of the circuit pattern to solve problems such as securing yield. However, the present invention is not limited thereto, and can have the same width as the width of the circuit pattern depending on the technical limitations of the bonding process.

[0082] And the pads arranged on the inside have the function of connecting the via electrode and the circuit pattern. When the via electrode is arranged with a wider width than the circuit pattern, a pad with a wider width than the circuit pattern is provided for positional alignment during the manufacturing process of the via electrode to be arranged on each circuit pattern. Therefore, each via electrode may have an upper surface that is located on the same plane as the lower surface of the upper pad that is in direct contact with the via electrode, and a lower surface that is located on the same plane as the upper surface of the lower pad that is in direct contact with the lower surface of the via electrode. Here, the lower surface of the upper pad and the upper surface of the lower pad do not necessarily mean a flat surface, and it should be understood that even concave or convex surfaces that may appear depending on various processes may be present.

[0083] Additionally, semiconductor devices may be mounted within or on the circuit board. The semiconductor devices may be logic chips, memory chips, etc. The logic chips may be central processing units (CPUs), graphics processors (GPUs), etc. For example, the logic chips may be APs including at least one of a central processing unit (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), etc., or a chip set including a specific combination of the above. And the memory chips may be stacked memories such as HBM. In addition, the memory chips may include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, etc.

[0084] The capacitor structure (CAS) may be located on the first insulating layer (111). Alternatively, the capacitor structure (CAS) may be located between the first insulating layer (111) and the second insulating layer (112). Additionally, the capacitor structure (CAS) may be covered by the second insulating layer (112).

[0085] A capacitor structure (CAS) according to an embodiment may include a first via land (VL1), a dielectric layer (DL), and a second via land (VL2). In the capacitor structure (CAS), the first via land (VL1), the dielectric layer (DL), and the second via land (VL2) may be sequentially stacked or positioned along a vertical direction (X-axis direction). The first and second via lands (VL1, VL2) may be directly connected to a via electrode. Through the first and second via lands (VL1, Vl2), a function for securing positional alignment of the via electrode and a function of a circuit electrically connected to the via electrode may be implemented.

[0086] Referring further to FIG. 2, in the circuit board (100) according to the embodiment, the second insulating layer (112) may be disposed on the first insulating layer (111). Furthermore, the first via land (VL1) may be positioned between the first insulating layer (111) and the second insulating layer (112).

[0087] As an example, the first via electrode (121a), the second via electrode (122a), and the third via electrode (123a) may have different lengths in the vertical direction and may also have different positions at which they are arranged.

[0088] The first via electrode (121a) may be placed between the lower surface (BS1) of the first insulating layer (111) and the first via land (VL1). The first via electrode (121a) may penetrate at least a portion of the first insulating layer (111).

[0089] The second via electrode (122a) may be arranged between the first via land (VL1) and the upper surface (US2) of the second insulating layer (112). In addition, the second via electrode (122a) may be positioned between the upper surface (US1) of the first insulating layer (111) (or the lower surface, BS2, of the second insulating layer (112)) and the upper surface (US2) of the second insulating layer (112). The second via electrode (122a) may penetrate at least a portion of the second insulating layer (112).

[0090] The third via electrode (123a) may be arranged between the lower surface (BS1) of the first insulating layer (111) and the upper surface (US2) of the second insulating layer (112). The third via electrode (123a) may penetrate at least a portion of the first insulating layer (111) and the second insulating layer (112). The second insulating layer (112) may penetrate at least a portion of the first insulating layer (111). In this specification, the via electrode may be positioned within a via hole formed in each insulating layer, etc. This corresponds to the via electrode penetrating each insulating layer, etc. In this specification, a description will be made based on this.

[0091] Accordingly, the second insulating layer (112) is placed in a via hole formed in the first insulating layer (111), and the third via electrode (123a) can penetrate the second insulating layer (112) that penetrates the first insulating layer (111). Accordingly, the via hole of the second insulating layer (112) can be positioned within the via hole of the first insulating layer (111), and the third via electrode (123a) can be positioned within the via hole of the second insulating layer (112).

[0092] In an embodiment, the vertical length (T3) of the third via electrode (123a) may be greater than the sum of the vertical length (T1) of the first via electrode (121a) and the vertical length (T2) of the second via electrode (122a).

[0093] By this configuration, a crevasse occurring at the interface of the insulating layers can be easily removed according to the third via electrode (123a) that penetrates both the first insulating layer and the second insulating layer.

[0094] Furthermore, the third via electrode (123b) according to the embodiment may overlap the first via electrode (121a) and the second via electrode (122b) in the horizontal direction (Y-axis direction). In addition, the third via electrode (123b) may also overlap the capacitor structure in the horizontal direction.

[0095] In addition, the width (W1) of the first via electrode (121a) may gradually increase from the upper surface (US1) of the first insulating layer (111) toward the lower surface (BS1) of the first insulating layer (111). For example, the width (or diameter, etc.) of the first via electrode (121a) may increase in the direction opposite to the vertical direction.

[0096] In addition, the minimum width (W1b) of the first via electrode (121a) may be smaller than the maximum width (W1a) of the first via electrode (121a). In an embodiment, the first width (W1b), which is the minimum width of the first via electrode (121a), may correspond to the smallest width on the upper surface (US1) of the first insulating layer (111). Alternatively, the first width (W1b), which is the minimum width of the first via electrode (121a), may correspond to the width in the region closest to the upper surface (US1) of the first insulating layer (111). And the maximum width (W1a) of the first via electrode (121a) may correspond to the width on the lower surface (BS1) of the first insulating layer (111). Alternatively, the maximum width of the first via electrode (121a) may correspond to the width in the area closest to the lower surface (BS1) of the first insulating layer (111).

[0097] Additionally, the width (W2) of the second via electrode (122a) may gradually decrease from the upper surface (US2) of the second insulating layer (112) toward the lower surface (BS2) of the second insulating layer (112). Alternatively, the width (W2) of the second via electrode (122a) may gradually increase in the vertical direction.

[0098] The minimum width (W2a) of the second via electrode (122a) may be smaller than the maximum width (W2b) of the second via electrode (122a). In an embodiment, the second width (W2a), which is the minimum width of the second via electrode (122a), may correspond to the smallest width on the lower surface (BS2) of the second insulating layer (112) (or the upper surface of the first insulating layer). Alternatively, the second width (W2a), which is the minimum width of the second via electrode (122a), may correspond to the width in the region closest to the upper surface (US1) of the first insulating layer (111) (or the lower surface (BS2) of the second insulating layer). In addition, the maximum width (W2b) of the second via electrode (122a) may correspond to the width on the upper surface (US2) of the second insulating layer (112). Alternatively, the maximum width of the second via electrode (122a) may correspond to the width in the area closest to the upper surface (US2) of the second insulating layer (112).

[0099] In addition, the width (W3) of the third via electrode (123a) may gradually decrease from the upper surface (US2) of the second insulating layer (112) toward the lower surface (BS2) of the second insulating layer (112) (or from the upper surface (or lower surface) of the second insulating layer to the upper surface (or lower surface) of the first insulating layer). Alternatively, the width (W3) of the third via electrode (123a) may gradually increase in the vertical direction.

[0100] The minimum width (W3a) of the third via electrode (123a) may be smaller than the maximum width (W3b) of the third via electrode (123a). In an embodiment, the third width (W3a), which is the minimum width of the third via electrode (123a), may correspond to the smallest width on the lower surface (BS2) of the second insulating layer (112) (or the upper surface of the first insulating layer). Alternatively, the third width (W3a), which is the minimum width of the third via electrode (123a), may correspond to the width in the region closest to the upper surface (US1) of the first insulating layer (111) (or the lower surface (BS2) of the second insulating layer). In addition, the maximum width (W3b) of the third via electrode (123a) may correspond to the width on the upper surface (US2) of the second insulating layer (112). Alternatively, the maximum width of the third via electrode (123a) may correspond to the width in the area closest to the upper surface (US2) of the second insulating layer (112).

[0101] The first width (W1b), which is the minimum width of the first via electrode (121a), may be greater than the third width (W3a), which is the minimum width of the third via electrode (123a). That is, the third width (W3a) may be smaller than the first width (W1b).

[0102] Referring further to FIG. 3, the second insulating layer (112) according to the embodiment may penetrate the first insulating layer (111). In addition, the second insulating layer (112) may include a protrusion (PR) penetrating at least a portion of the first insulating layer (111) from the upper surface (US1) toward the lower surface (BS1) of the first insulating layer (111).

[0103] By virtue of these protrusions (PR), the second insulating layer (112) can have a width (length in the horizontal direction) that changes in the direction opposite to the vertical direction within the via of the first insulating layer (111) rather than on the upper surface (US1) of the first insulating layer (111).

[0104] That is, even if a via hole is located, the boundary surface between the second insulating layer (112) and the first insulating layer (111) may be vertical rather than gently inclined depending on the via hole.

[0105] With this configuration, the boundary between the electrode portion and the insulating layer is separated by the protrusion (PR), thereby suppressing the occurrence of voids or gaps. Furthermore, the supporting capacity of the capacitor structure on the upper surface due to the protrusion can be improved. In other words, the circuit board according to the embodiment can improve structural and electrical reliability.

[0106] And the third via electrode (123a) may be placed within the protrusion (PR). For example, the third via electrode (123a) may be partially surrounded by the protrusion (PR).

[0107] Additionally, in the circuit board (100) according to the embodiment, the longest via electrode in the vertical direction within the first insulating layer (111) and the second insulating layer (112) may overlap with the protrusion (PR) in the horizontal direction. In the embodiment, the third via electrode (123a) may overlap with the protrusion (PR) in the horizontal direction (Y-axis direction).

[0108] In addition, the protrusion (PR) may be arranged below the second via electrode (122a). For example, the second via electrode (122a) may be positioned adjacent to the third via electrode (123a). At this time, the protrusion (PR) may overlap with the second via electrode (122a) in a vertical direction. For example, the protrusion (PR) may at least partially overlap with the second via electrode (122a) in a vertical direction. By this configuration, a supporting force for the second via electrode (122a) may be secured.

[0109] The difference between the vertical length (or height) of the third via electrode (123a) and the vertical length (or height) of the second via electrode (122a) may be greater than the thickness (vertical length) of the second insulating layer (112).

[0110] In addition, the angle (θ1) of the third via electrode (123a) may be different from the angle (θ2) of the inner wall of the protrusion (PR). For example, the angle (θ1) of the third via electrode (123a) may be an angle formed between the outer surface and the bottom surface of the third via electrode (123a). Alternatively, the angle (θ1) of the third via electrode (123a) may correspond to an angle formed between the lower surface (BS1) of the first insulating layer (111). In addition, the angle (θ2) of the inner wall of the protrusion (PR) may correspond to an angle formed between the inner wall of the protrusion (PR) and the lower surface (BS1) of the first insulating layer (111). Accordingly, the occurrence of a gap that occurs when the first insulating layer (111) partially penetrates the second insulating layer (112) (e.g., a protrusion) and the second insulating layer (112) is formed on top can be suppressed. Accordingly, the deterioration of the electrical characteristics of the third via electrode (123a) can also be prevented.

[0111] Additionally, the capacitor structure (CAS) may be positioned on the first insulating layer (111). Additionally, the capacitor structure (CAS) may be positioned between the first insulating layer (111) and the second insulating layer (112).

[0112] A capacitor structure (CAS) may include a first via land (VL1), a dielectric layer (DL), and a second via land (VL2). The first via land (VL1), the dielectric layer (DL), and the second via land (VL2) may be sequentially stacked in a vertical direction.

[0113] A dielectric layer (DL) can be interposed between the first via land (VL1) and the second via land (VL2) to form a storage capacity or capacitance. In other words, the capacitor structure (CAS) can function as a 'capacitor'.

[0114] These capacitor structures or capacitors need to be further reduced in size to accommodate substrates and semiconductor devices that require increased integration.

[0115] As a method for improving the storage capacity of such a capacitor, increasing the effective area of ​​the first and second via lands (electrodes), reducing the thickness of the dielectric film, using a high-k material as the dielectric film, etc. can be considered. In particular, when the high-k material is used as the dielectric film, the leakage current that frequently occurs between the first via land, which is the lower electrode, and the second via land, which is the upper electrode, can be sufficiently reduced while maintaining a thin equivalent oxide thickness. In an embodiment, a high-k material can be used as the dielectric film. For example, the high-k material can include, for example, tantalum oxide, aluminum oxide, zirconium oxide, hafnium oxide, titanium oxide, etc.

[0116] In addition, the circuit board according to the embodiment can solve problems such as reduced circuit board integration and input / output count due to the volume of the capacitor when mounting a high-capacity capacitor. In other words, the capacitor structure according to the embodiment can increase the circuit board integration and input / output count while providing improved storage capacity.

[0117] The second via electrode (122a) may be electrically connected to the capacitor structure (CAS). In an embodiment, the second via electrode (122a) may be disposed on the second via land (VL2). That is, the second via electrode (122a) may be disposed on the capacitor structure (CAS). Accordingly, the second via electrode (122a) may overlap the capacitor structure (CAS) in a vertical direction (X-axis direction).

[0118] In addition, the first via electrode (121a) may be electrically connected to the capacitor structure (CAS). In an embodiment, the first via electrode (121a) may be disposed below the first via land (VL1). That is, the first via electrode (121a) may be disposed below the capacitor structure (CAS). Accordingly, the first via electrode (121a) may overlap with the capacitor structure (CAS) in a vertical direction (X-axis direction). In addition, the first via electrode (121a) may also at least partially overlap with the second via electrode (122a) in the vertical direction.

[0119] Additionally, there may be at least one capacitor structure (CAS) on the circuit board (100). In an embodiment, the capacitor structure (CAS) may be multiple, including a first capacitor structure (CAS1) and a second capacitor structure (CAS2). The first capacitor structure (CAS1) and the second capacitor structure (CAS2) may be spaced apart from each other.

[0120] The third via electrode (123a) may be positioned between the first capacitor structure (CAS1) and the second capacitor structure (CAS2). Accordingly, a portion of the third via electrode (123a) may overlap the first capacitor structure (CAS1) and the second capacitor structure (CAS2) in the horizontal direction (Y-axis direction).

[0121] In addition, the capacitor structure (CAS) according to the embodiment may be at least partially embedded in the first insulating layer (111). A portion of the first via electrode (121a) may be in contact with the second insulating layer (112). Alternatively, a portion of the first via electrode (121a) may horizontally overlap with the second insulating layer (112). More specifically, the upper surface (US1) of the first insulating layer (111) (or the lower surface, BS2, of the second insulating layer) may be positioned to be misaligned with the upper surface or lower surface of the first via land (VL1). For example, the upper surface (US1) of the first insulating layer (111) may be positioned lower than the upper surface of the first via land (VL1).

[0122] Furthermore, the first capacitor structure (CAS1) and the second capacitor structure (CAS2) may overlap each other in the horizontal direction. In addition, the first via land (VL1) of the first capacitor (CAS1) and the first via land (VL1) of the second capacitor structure (CAS2) may overlap each other at least partially in the horizontal direction. For example, the upper surface of the first via land (VL1) of the first capacitor (CAS1) and the upper surface of the first via land (VL1) of the second capacitor structure (CAS2) may form the same plane. In addition, the upper surface of the first via land (VL1) of the first capacitor (CAS1) and the upper surface of the first via land (VL1) of the second capacitor structure (CAS2) may be misaligned with each other. For example, the upper surface of the first via land (VL1) in the first capacitor (CAS1) and the upper surface of the first via land (VL1) in the second capacitor structure (CAS2) may have a vertical separation distance.

[0123] Referring further to FIG. 5, in a circuit board according to a modified example, the first capacitor structure (CAS1) and the second capacitor structure (CAS2) of the capacitor structure (CAS) may be embedded in the upper surface (US1) of the first insulating layer (111). Furthermore, the upper surface of the first via land (VL1) of at least one of the first capacitor structure (CAS1) and the second capacitor structure (CAS2) and the upper surface (US1) of the first insulating layer (111) may be misaligned.

[0124] For example, in the first capacitor (CAS1), the upper surface of the first via land (VL1) and the upper surface (US1) of the first insulating layer (111) may be misaligned. In addition, in the second capacitor structure (CAS2), the upper surface of the first via land (VL1) and the upper surface (US1) of the first insulating layer (111) may be misaligned.

[0125] FIGS. 6A to 6P are drawings explaining a method for manufacturing a circuit board according to the first embodiment.

[0126] Referring to FIG. 6a, in an embodiment, a basic material for manufacturing a circuit board or a semiconductor package including the same can be prepared using an ETS method.

[0127] For example, in an embodiment, a carrier board may be prepared. The carrier board may include a carrier insulating layer (310) and a carrier metal layer (320) disposed on at least one surface of the carrier insulating layer (310).

[0128] Furthermore, a second electrode layer (EL2), a dielectric layer (DL'), and a first electrode layer (EL1) for a capacitor structure may be sequentially laminated on a carrier board. The electrode layer (EL1) may correspond to the first via land described above. And the second electrode layer (EL2) may correspond to the second via land described above. In addition, the dielectric layer (DL') may correspond to the dielectric layer described above.

[0129] And the carrier metal layer (320) can be placed on only one of the upper and lower surfaces of the carrier insulating layer (310), or alternatively, can be placed on both surfaces.

[0130] For example, the carrier metal layer (320) may be disposed on both sides of the carrier insulating layer (310). In addition, when the carrier metal layer (320) is disposed on both sides of the carrier insulating layer (310), a process of manufacturing two semiconductor packages simultaneously on both sides of the carrier board may be performed. In this case, two semiconductor packages may be manufactured at one time.

[0131] This carrier metal layer (320) can be formed by electroless plating on the carrier insulating layer (310). Alternatively, the carrier insulating layer (310) and the carrier metal layer (320) can be CCL (Copper Clad Laminate).

[0132] Referring further to FIG. 6b, patterning can be performed on the first electrode layer (EL1) on the outer side. For example, the first electrode layer (EL1) can be etched using various methods. Accordingly, the first electrode layer (EL1) can have a shape corresponding to the first via land (VL1) described above. In other words, the first electrode layer (EL1) can be etched to control the position of the capacitor structure.

[0133] Referring further to FIG. 6c, a first insulating layer (111) may be laminated. The first insulating layer (111) may cover the first via land (VL1). Furthermore, the first insulating layer (111) may be positioned on top of the dielectric layer (DL').

[0134] Referring to FIG. 6d, a first electrode portion (121) can be formed on a first insulating layer (111). The first electrode portion (121) can be formed by sequentially forming a mask such as a dry film, forming a mask pattern, etching a portion of the first insulating layer (forming a via hole, etc.), and forming an electrode.

[0135] And a first lower insulating layer (114) can be formed on the first insulating layer (111) and the first electrode portion (121). The first lower insulating layer (114) can be positioned on the first insulating layer (111) and the first electrode portion (121).

[0136] And, on the first lower insulating layer (114), mask formation such as a dry film, mask pattern formation, partial etching of the first insulating layer (formation of a via hole, etc.), and electrode formation can be sequentially performed. Accordingly, a fourth electrode portion (124) can be formed on the first lower insulating layer (114).

[0137] Referring to FIG. 6e, in the embodiment, a process for removing the carrier board may be performed. For example, a process for removing the carrier insulation layer (310) from the carrier board may be performed. For example, in the embodiment, a process for separating the carrier insulation layer (310) from the carrier metal layer (320) may be performed.

[0138] Referring to FIG. 6F, a mask (330') may be formed on the second electrode layer (EL2). For example, the mask (330') may be a dry film. Then, exposure and development, etc. may be performed on the mask (330') to form an open area. In other words, patterning may be performed on the dry film. The mask (330') may be positioned at a position corresponding to the first via land. Furthermore, a curing process of the mask may be performed after the formation of the open area by exposure, etc. This mask formation may be applied to other mask formations in the same manner.

[0139] Referring to FIG. 6g, etching may be performed on an open area. In other words, etching may be performed on a portion of the second electrode layer (EL2). As a portion of the second electrode layer (EL2) is removed, a second via land (VL2), which is a remaining layer of the second electrode layer (EL2), may be formed corresponding to the first via land (VL1).

[0140] Referring to FIG. 6h, etching of the dielectric layer (DL') may be performed. In other words, etching may be performed on a portion of the dielectric layer (DL'). As a portion of the dielectric layer (DL') is removed, the remaining dielectric layer (DL) may be positioned between the first via land (VL1) and the second via land (VL2). As a result, the capacitor structure may be positioned on the first insulating layer (111).

[0141] Furthermore, the mask (330') can be removed. The mask (330') can be removed by various etching methods.

[0142] Referring to FIG. 6i, a first via (V1) can be formed by etching or etching the first insulating layer (111). The first via (V1) can be spaced apart from the capacitor structure.

[0143] Referring to FIG. 6j, a second insulating layer (112) can be formed on the first insulating layer (111). The second insulating layer (112) can also be formed on the first via (V1). Furthermore, the second insulating layer (112) can be in contact with the capacitor structure and cover the capacitor structure.

[0144] Furthermore, a second lower insulating layer (115) can be formed under the first lower insulating layer (114).

[0145] Referring to FIG. 6k, etching, etching, and drilling may be performed on the second insulating layer (112). For example, a second via (V2) and a third via (V3) may be formed in the second insulating layer (112). The second via (V2) and the third via (V3) may have different lengths in the vertical direction. For example, the second via (V2) may be located on the capacitor structure or on the first electrode portion. The third via (V3) may penetrate the first via (V1). That is, the third via (V3) may be formed at a position corresponding to the first via (V1).

[0146] Furthermore, etching, etching, and drilling may be performed on the second lower insulating layer (115). Alternatively, etching, etc. may be performed on the second lower insulating layer (115) previously.

[0147] Referring to FIG. 6l, a plating layer (340) for plating can be formed on the second insulating layer (112). For example, a plating layer (340) for chemical plating can be formed. However, various processes other than this plating process can be applied.

[0148] The plating layer (340) can also be formed in the same manner under the second lower insulating layer (115).

[0149] Referring to FIG. 6m, a mask (330'') may be formed on the second insulating layer (112) and the plating layer (340). For example, the mask (330'') may be a dry film. Then, exposure and development, etc. may be performed on the mask (330'') to form an open area. In other words, patterning may be performed on the dry film. The mask (330'') may be positioned in an area other than the second via (V2) and the third via (V3).

[0150] Furthermore, a mask curing process can be performed after the formation of an open area by exposure, etc. This mask formation can be applied to other mask formations in the same manner.

[0151] The formation and patterning of this mask (330'') can be equally applied to the lower portion of the second lower insulating layer (115).

[0152] Referring to FIG. 6n, a second electrode portion (122) and a third electrode portion (123) can be formed. For example, plating can be performed on the second via (V2) and the third via (V3) through an electroplating process. Accordingly, the second electrode portion (122) can be formed on the second via (V2), and the third electrode portion (123) can be formed on the third via (V3).

[0153] In addition, the same can be applied to the lower part of the second lower insulating layer (115) through electroplating. Thus, the fifth electrode portion (125) can be formed.

[0154] Referring to FIG. 6o, the mask (330'') can be removed. The mask (330'') can be removed by various etching methods. For example, the mask (330'') on the second insulating layer (112) and the mask (330'') under the second lower insulating layer (115) can be removed.

[0155] Referring to FIG. 6p, etching (e.g., flash etching) may be performed on the plating layer (340). That is, the plating layer (340) may be removed by etching. For example, the plating layer (340) at a location corresponding to the mask (330'') may be removed.

[0156] The plating layer (340) on the upper side of the second insulating layer (112) and the plating layer (340) on the lower side of the second lower insulating layer (115) can be removed.

[0157] By this configuration, the second electrode portion (122) and the third electrode portion (123) can be electrically separated. Furthermore, electrical separation between a plurality of second electrode portions (122) can be achieved. In addition, electrical separation between a plurality of third electrode portions (123) can be achieved.

[0158] Likewise, electrical separation between multiple fifth electrode sections (125) can be achieved.

[0159] FIG. 7 is a cross-sectional view of a circuit board according to a second embodiment of the present invention, and FIG. 8 is a perspective view showing the relationship between a third via electrode and a capacitor structure in a circuit board according to the second embodiment of the present invention.

[0160] Referring to FIGS. 7 and 8, a circuit board (100A) according to the second embodiment may include an insulating layer (110), an electrode portion (120), and a capacitor structure (CAS). Furthermore, the circuit board (100A) may include a protective layer disposed on the electrode portion (120), or a core layer, which is an insulating layer disposed within the insulating layer (110). Furthermore, the configuration described in the embodiments of the present invention may be applied in the same manner, except for the contents described below.

[0161] In the circuit board (100A) according to the present embodiment, the third via electrode (123a) can penetrate the capacitor structure (CAS). That is, the third via electrode (123a) can be surrounded by the capacitor structure (CAS).

[0162] The protrusion (PR) may be vertically overlapped by the capacitor structure (CAS). For example, the protrusion (PR) may be partially vertically overlapped by the capacitor structure (CAS).

[0163] Furthermore, the second via electrode (122a) may be horizontally misaligned with the protrusion (PR). In addition, the second via electrode (122a) may not horizontally overlap with the protrusion (PR).

[0164] And the separation distance between the third via electrode (123a) and the capacitor structure (CAS) through which the third via electrode penetrates may be the same. For example, the separation distance between the outer surface of the third via electrode (123a) and the adjacent capacitor structure (CAS) may be maintained the same along the shape or edge of the third via electrode (123a).

[0165] Furthermore, the second insulating layer (112) may be positioned on the inside of the capacitor structure (CAS). For example, the second insulating layer (112) may penetrate the capacitor structure (CAS). Accordingly, electrical insulation between the third via electrode (123a) and the capacitor structure (CAS) may be maintained. By this configuration, a circuit board with improved integration may be provided by forming the third via electrode penetrating the first and second insulating layers, which are double layers, and at the same time forming the capacitor structure (CAS).

[0166] Additionally, the protrusion (PR) may be positioned below the second via electrode (122a). For example, the protrusion (PR) may be positioned below the second via electrode (122a) along the second insulating layer (112). By this configuration, the support for the second via electrode (122a) may be improved.

[0167] Furthermore, the second via electrode (122a) and the first via electrode (121a) may be in contact with the second via land and the first via land of the capacitor structure (CAS), respectively. In this case, the area where the second via electrode (122a) is in contact with the second via land may not overlap at least partially in the vertical direction with the area where the first via electrode (121a) is in contact with the first via land. Accordingly, the electrical connection in the circuit board according to the embodiment can be easily designed and changed.

[0168] FIG. 9 is a cross-sectional view of a circuit board according to a third embodiment of the present invention, FIG. 10 is an enlarged view of K4 of FIG. 9, FIG. 11 is an enlarged view of K5 of FIG. 9, and FIG. 12 is an enlarged view of K6 of FIG. 9.

[0169] Referring to FIGS. 9 and 10, a circuit board (100B) according to a third embodiment may include an insulating layer (110), an electrode portion (120), and a capacitor structure (CAS). Furthermore, the circuit board (100B) may include a protective layer disposed on the electrode portion (120), or a core layer, which is an insulating layer disposed within the insulating layer (110). Furthermore, the configuration described in the embodiments of the present invention may be applied in the same manner, except for the contents described below.

[0170] The insulating layer (110) may include a first insulating layer (111) and a second insulating layer (112) as described above. In addition, in the present embodiment, the insulating layer (110) may include a third insulating layer (113).

[0171] The third insulating layer (113) may be disposed on the first insulating layer (111). In addition, the third insulating layer (113) may be positioned between the first insulating layer (111) and the second insulating layer (112). Accordingly, the second insulating layer (112) may cover the third insulating layer (113). In other words, in the above-described embodiments, the second insulating layer may correspond to the first insulating layer and the third insulating layer in the present embodiment.

[0172] In this embodiment, the third insulating layer (113) may be in contact with the capacitor structure (CAS). At this time, the third insulating layer (113) may form an interface with the first insulating layer (111). For example, the upper surface of the first insulating layer (111) may correspond to the lower surface of the third insulating layer (113). And the upper surface of the third insulating layer (113) may correspond to the lower surface of the second insulating layer (112).

[0173] Additionally, as described above, the third insulating layer (113) is disposed on the first insulating layer (111), and the first via land (VL1) may be located between the first insulating layer (111) and the third insulating layer (113).

[0174] In addition, as described above, the first via electrode (121a), the second via electrode (122a), and the third via electrode (123a) may have different lengths in the vertical direction and may also have different positions at which they are arranged.

[0175] The first via electrode (121a) may be placed between the lower surface (BS1) of the first insulating layer (111) and the first via land (VL1). The first via electrode (121a) may penetrate at least a portion of the first insulating layer (111).

[0176] The second via electrode (122a) may be disposed between the first via land (VL1) and the upper surface of the third insulating layer (113) (or the upper surface (US2) of the second insulating layer). In addition, the second via electrode (122a) may be positioned between the upper surface (US1) of the first insulating layer (111) (or the lower surface, BS2, of the third insulating layer (113)) and the upper surface (US2) of the second insulating layer (112). The second via electrode (122a) may penetrate at least a portion of the third insulating layer (113) and the second insulating layer (112). In this case, the second insulating layer (112) may penetrate the third insulating layer (113). Accordingly, the third insulating layer (113) may be positioned on the inner surface of the via hole or via of the third insulating layer (113). Additionally, the inner surface of the via hole or via of the third insulating layer (113) can be in contact with the third insulating layer (113).

[0177] The third via electrode (123a) may be arranged between the lower surface (BS1) of the first insulating layer (111) and the upper surface (US2) of the second insulating layer (112). The third via electrode (123a) may penetrate at least a portion of the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113). The third insulating layer (113) may penetrate at least a portion of the first insulating layer (111) and the third insulating layer (113).

[0178] Accordingly, the second insulating layer (112) is arranged in the via hole formed in the first insulating layer (111) and the third insulating layer (113), and the third via electrode (123a) can penetrate the second insulating layer (112) that penetrates the first insulating layer (111). Accordingly, the via hole of the second insulating layer (112) can be located in the via hole of the first insulating layer (111), and the second insulating layer (112) can be located in the via hole of the third insulating layer (113). In addition, the third via electrode (123a) can be located in the via hole of the second insulating layer (112).

[0179] Furthermore, the second via electrode (122a) can penetrate the third insulating layer (113) and the second insulating layer (112). Adjacent to the second via electrode (122a), the second insulating layer (112) can be positioned within a via hole of the third insulating layer (113). And the second via electrode (122a) can be positioned within a via hole of the second insulating layer (112).

[0180] In an embodiment, the vertical length of the third via electrode (123a) may be greater than the sum of the vertical length of the first via electrode (121a) and the vertical length of the second via electrode (122a). By this configuration, a crevasse occurring at the interface of the insulating layers can be easily removed according to the third via electrode (123a) penetrating through all of the first to third insulating layers.

[0181] Referring further to FIGS. 11 and 12, the circuit board (100B) according to the embodiment may include a protrusion (PR). In particular, in the present embodiment, there may be a plurality of protrusions (PR). For example, the protrusions (PR) may include a first protrusion (PR1) and a second protrusion (PR2). In addition, the second insulating layer (112) may include the protrusions (PR). That is, the second insulating layer (112) may include a first protrusion (PR1) and a second protrusion (PR2). The outer surface of the protrusion (PR) may correspond to the interface between the second insulating layer (112) and another insulating layer. That is, the protrusion (PR) according to the embodiment may be in contact with the boundary surface of the insulating layer.

[0182] In the protrusion (PR), the first protrusion (PR1) may be positioned adjacent to the third via electrode (123a). For example, the first protrusion (PR1) may be positioned along the edge of the third via electrode (123a). Alternatively, the first protrusion (PR1) may surround the third via electrode (123a) with the third via electrode (123a) as the center.

[0183] The second protrusion (PR2) may be positioned adjacent to the second via electrode (122a). For example, the second protrusion (PR2) may be positioned along the edge of the second via electrode (122a). Alternatively, the second protrusion (PR2) may surround the second via electrode (122a) with the second via electrode (122a) as the center.

[0184] The first protrusion (PR1) may protrude toward the third insulating layer (113) and the first insulating layer (111). For example, the first protrusion (PR1) may protrude toward at least one of the first insulating layer (111) and the third insulating layer (113) adjacent to the outside of the third via electrode (123a). The first protrusion (PR1) may protrude toward the first insulating layer (111). The first protrusion (PR1) may protrude toward the third insulating layer (113). Accordingly, the first protrusion (PR1) may contact the boundary between the first insulating layer (11) and the third insulating layer (113). For example, the first protrusion (PR1) may not partially overlap with the third wiring portion (123b) in the vertical direction. By this configuration, electrical or structural reliability degradation due to a gap occurring at the boundary surface (e.g., the upper surface of the first insulating layer) between the first insulating layer (111) and the third insulating layer (113) can be prevented.

[0185] The second protrusion (PR2) may protrude toward the third insulating layer (113). The second protrusion (PR2) may protrude toward the adjacent third insulating layer (113) from the outside of the second via electrode (122a). For example, the second protrusion (PR2) may not overlap with the second wiring portion in the vertical direction. With this configuration, a crevasse occurring at the interface of the insulating layers can be easily removed.

[0186] Furthermore, the first protrusion (PR1) and the second protrusion (PR2) can increase the distance between the boundary surface of the insulating layer and the adjacent via electrode. As a result, the circuit board according to the embodiment, as described above, can provide improved structural and electrical reliability.

[0187] And by the protrusion (PR), the width (length in the horizontal direction) within the via of the first insulating layer (111) can change in the direction opposite to the vertical direction.

[0188] And the third via electrode (123a) and the second via electrode (122a) may be arranged within the protrusion (PR). For example, the third via electrode (123a) and the second via electrode (122a) may be partially surrounded by the protrusion (PR).

[0189] Additionally, in the circuit board (100) according to the embodiment, the longest via electrode in the vertical direction within the first insulating layer (111) and the third insulating layer (113) may overlap with the protrusion (PR) in the horizontal direction. In the embodiment, the third via electrode (123a) may overlap with the protrusion (PR) in the horizontal direction (Y-axis direction).

[0190] Additionally, the distance between the third via electrode (123a) and the first protrusion (PR1) may be smaller than the distance between the second protrusion (PR2) and the third via electrode (123a). For example, the third via electrode (123a) may be positioned closer to the first protrusion (PR1) than to the second protrusion (PR2).

[0191] In addition, a portion of the first protrusion (PR1) may be positioned below the second via electrode (122a). For example, the second via electrode (122a) may be positioned adjacent to the third via electrode (123a). At this time, the first protrusion (PR1) may overlap with the second via electrode (122a) in a vertical direction. For example, the first protrusion (PR1) may overlap with the second via electrode (122a) at least in a vertical direction. By this configuration, a supporting force for the second via electrode (122a) may be secured.

[0192] The difference between the vertical length (or height) of the third via electrode (123a) and the vertical length (or height) of the second via electrode (122a) may be greater than the thickness (vertical length) of the second insulating layer (112).

[0193] Additionally, the angle of the third via electrode (123a) may be different from the angle of the inner walls of the first and second protrusions (PR1, PR2). Furthermore, the angle of the second insulating layer (112) may be different from the angle of the inner walls of the first and second protrusions.

[0194] For example, the angle of the third via electrode (123a) may be the angle formed by the outer surface and the bottom surface of the third via electrode (123a). In addition, the angle of the second insulating layer (112) may correspond to the angle formed by the lower surface of the first insulating layer (111) and the via of the second insulating layer. In addition, the angle of the inner wall of the protrusion (PR) may correspond to the angle formed by the inner wall of the protrusion (PR) and the lower surface (BS1) of the first insulating layer (111). Accordingly, the occurrence of a gap that occurs when the third insulating layer (113) is formed on the first insulating layer (111) due to a portion of the first insulating layer (111) penetrating through the third insulating layer (113) (e.g., the protrusion) can be suppressed. Accordingly, the deterioration of the electrical characteristics of the third via electrode (123a) can also be prevented.

[0195] The capacitor structure (CAS) may be located at least partially above the interface between the first insulating layer (111) and the third insulating layer (113). Additionally, the capacitor structure (CAS) may be embedded within the first insulating layer (111).

[0196] The upper surface of the first via land (VL1) of the capacitor structure (CAS) may be flush with the boundary surface of the first insulating layer (111) and the third insulating layer (113), or may be misaligned with the boundary surface of the first insulating layer (111) and the third insulating layer (113). For example, the boundary surface of the first insulating layer (111) and the third insulating layer (113) may be located below the upper surface of the first via land (VL1). Accordingly, at least a portion of the first via land (VL1) may overlap with the third insulating layer (113) in the horizontal direction. In addition, at least a portion of the first via land (VL1) may overlap with the first insulating layer (111) in the horizontal direction.

[0197] FIGS. 13a to 13q are drawings explaining a method for manufacturing a circuit board according to a third embodiment.

[0198] In the embodiment, as described above, a basic material for manufacturing a circuit board or a semiconductor package including the same can be prepared using the ETS (Embedded Trace Substrate) method.

[0199] Referring to FIG. 13A, in an embodiment, a carrier board may be prepared. The carrier board may include a carrier insulating layer (310) and a carrier metal layer (320) disposed on at least one surface of the carrier insulating layer (310).

[0200] Furthermore, a second electrode layer (EL2), a dielectric layer (DL'), and a first electrode layer (EL1) for a capacitor structure may be sequentially laminated on a carrier board. The electrode layer (EL1) may correspond to the first via land described above. And the second electrode layer (EL2) may correspond to the second via land described above. In addition, the dielectric layer (DL') may correspond to the dielectric layer described above.

[0201] And the carrier metal layer (320) can be placed on only one of the upper and lower surfaces of the carrier insulating layer (310), or alternatively, can be placed on both surfaces.

[0202] For example, the carrier metal layer (320) may be disposed on both sides of the carrier insulating layer (310). In addition, when the carrier metal layer (320) is disposed on both sides of the carrier insulating layer (310), a process of manufacturing two semiconductor packages simultaneously on both sides of the carrier board may be performed. In this case, two semiconductor packages may be manufactured at one time.

[0203] This carrier metal layer (320) can be formed by electroless plating on the carrier insulating layer (310). Alternatively, the carrier insulating layer (310) and the carrier metal layer (320) can be CCL (Copper Clad Laminate).

[0204] Referring further to FIG. 13b, patterning can be performed on the first electrode layer (EL1) on the outer side. For example, the first electrode layer (EL1) can be etched using various methods. Accordingly, the first electrode layer (EL1) can have a shape corresponding to the first via land (VL1) described above. In other words, the first electrode layer (EL1) can be etched to control the position of the capacitor structure.

[0205] Referring further to FIG. 13c, a first insulating layer (111) may be laminated. The first insulating layer (111) may cover the first via land (VL1). Furthermore, the first insulating layer (111) may be positioned on top of the dielectric layer (DL').

[0206] Referring to FIG. 13d, a first electrode portion (121) can be formed on a first insulating layer (111). The first electrode portion (121) can be formed by sequentially forming a mask such as a dry film, forming a mask pattern, etching a portion of the first insulating layer (forming a via hole, etc.), and forming an electrode.

[0207] And a first lower insulating layer (114) can be formed on the first insulating layer (111) and the first electrode portion (121). The first lower insulating layer (114) can be positioned on the first insulating layer (111) and the first electrode portion (121).

[0208] And, on the first lower insulating layer (114), mask formation such as a dry film, mask pattern formation, partial etching of the first insulating layer (formation of a via hole, etc.), and electrode formation can be sequentially performed. Accordingly, a fourth electrode portion (124) can be formed on the first lower insulating layer (114).

[0209] Referring to FIG. 13e, in the embodiment, a process for removing a carrier board may be performed. For example, a process for removing a carrier insulating layer (310) from the carrier board may be performed. For example, in the embodiment, a process for separating the carrier insulating layer (310) from the carrier metal layer (320) may be performed.

[0210] Referring to FIG. 13F, a mask (330') may be formed on the second electrode layer (EL2). For example, the mask (330') may be a dry film. Then, exposure and development, etc. may be performed on the mask (330') to form an open area. In other words, patterning may be performed on the dry film. The mask (330') may be positioned at a position corresponding to the first via land. Furthermore, a curing process of the mask may be performed after the formation of the open area by exposure, etc. This mask formation may be applied to other mask formations in the same manner.

[0211] Referring to FIG. 13g, etching may be performed on an open area. In other words, etching may be performed on a portion of the second electrode layer (EL2). As a portion of the second electrode layer (EL2) is removed, a second via land (VL2), which is a remaining layer of the second electrode layer (EL2), may be formed corresponding to the first via land (VL1).

[0212] Referring to FIG. 13h, etching of the dielectric layer (DL') may be performed. In other words, etching may be performed on a portion of the dielectric layer (DL'). As a portion of the dielectric layer (DL') is removed, the remaining dielectric layer (DL) may be positioned between the first via land (VL1) and the second via land (VL2). As a result, the capacitor structure may be positioned on the first insulating layer (111).

[0213] Furthermore, the mask (330') can be removed. The mask (330') can be removed by various etching methods.

[0214] Referring to FIG. 13i, a third insulating layer (113) may be formed on the first insulating layer (111). The third insulating layer (113) may cover the capacitor structure. Furthermore, a second lower insulating layer (115) may be formed under the first lower insulating layer (114). The second lower insulating layer (115) may be formed during, before, or after the formation of the second insulating layer (112).

[0215] Referring to FIG. 13j, a first via (V1) can be formed by etching or etching in the first insulating layer (111) and the third insulating layer (113). The first via (V1) can be spaced apart from the capacitor structure. The first via (V1) may be plural, and may at least partially penetrate both the first insulating layer (111) and the third insulating layer (113), or may penetrate only the third insulating layer (113). For example, a first via that penetrates both the first insulating layer (111) and the third insulating layer (113) may have a longer vertical length than a first via that penetrates only the third insulating layer (113).

[0216] Additionally, etching, etching, and drilling may be performed on the second lower insulating layer (115). Alternatively, etching, etc. may be performed on the second lower insulating layer (115) previously.

[0217] Referring to FIG. 13k, a second insulating layer (112) may be formed on the first insulating layer (111) and the third insulating layer (113). The second insulating layer (112) may also be formed on the first via (V1). Furthermore, the second insulating layer (112) may be in contact with a partially exposed capacitor structure. Accordingly, the second insulating layer (112) may partially cover the capacitor structure.

[0218] Referring to FIG. 13l, etching, etching, and drilling may be performed on the second insulating layer (112). For example, a second via (V2) and a third via (V3) may be formed in the second insulating layer (112). The second via (V2) and the third via (V3) may have different lengths in the vertical direction. For example, the second via (V2) may be located on the capacitor structure or on the first electrode portion. The third via (V3) may penetrate the first via (V1). That is, the third via (V3) may be formed at a position corresponding to the first via (V1).

[0219] Referring to FIG. 13m, a plating layer (340) for plating can be formed on the second insulating layer (112). For example, a plating layer (340) for chemical plating can be formed. However, various processes other than this plating process can be applied. The plating layer (340) can also be formed in the same manner on the lower part of the second lower insulating layer (115).

[0220] Referring to FIG. 13n, a mask (330'') may be formed on the second insulating layer (112) and the plating layer (340). For example, the mask (330'') may be a dry film. Then, exposure and development, etc. may be performed on the mask (330'') to form an open area. In other words, patterning may be performed on the dry film. The mask (330'') may be positioned in an area other than the second via (V2) and the third via (V3).

[0221] Furthermore, a mask curing process can be performed after the formation of an open area by exposure, etc. This mask formation can be applied to other mask formations in the same manner.

[0222] The formation and patterning of this mask (330'') can be equally applied to the lower portion of the second lower insulating layer (115).

[0223] Referring to FIG. 13o, a second electrode portion (122) and a third electrode portion (123) can be formed. For example, plating can be performed on the second via (V2) and the third via (V3) through an electroplating process. Accordingly, the second electrode portion (122) can be formed on the second via (V2), and the third electrode portion (123) can be formed on the third via (V3).

[0224] In addition, the same can be applied to the lower part of the second lower insulating layer (115) through electroplating. Thus, the fifth electrode portion (125) can be formed.

[0225] Referring to FIG. 13p, the mask (330'') can be removed. The mask (330'') can be removed by various etching methods. For example, the mask (330'') on the second insulating layer (112) and the mask (330'') under the second lower insulating layer (115) can be removed.

[0226] Referring to FIG. 13q, etching (e.g., flash etching) may be performed on the plating layer (340). That is, the plating layer (340) may be removed by etching. For example, the plating layer (340) at a position corresponding to the mask (330'') may be removed.

[0227] The plating layer (340) on the upper side of the third insulating layer (113) and the plating layer (340) on the lower side of the second lower insulating layer (115) can be removed.

[0228] By this configuration, the second electrode portion (122) and the third electrode portion (123) can be electrically separated. Furthermore, electrical separation can be achieved between a plurality of second electrode portions (122). In addition, electrical separation can be achieved between a plurality of third electrode portions (123). Similarly, electrical separation can be achieved between a plurality of fifth electrode portions (125).

[0229] Fig. 14 is a schematic diagram of a circuit board according to an embodiment and a package board to which the circuit board is applied.

[0230] Referring to FIG. 14, the circuit board described above may be positioned in a portion of a semiconductor package or may correspond to a single substrate. Alternatively, the structure of the circuit board according to the above-described embodiment may be positioned within the semiconductor package. Furthermore, although the package substrate is illustrated as having a core layer, the core layer may be positioned on a side. In this way, the circuit board according to the various embodiments described above may be positioned on a single substrate or a single area of ​​the semiconductor package. In particular, the circuit board according to the embodiment may be applied to a substrate having a built-in bridge.

[0231] The semiconductor package of the embodiment may include a circuit board (100) and a first semiconductor element (DI1), a second semiconductor element (DI2), and a bridge (BR).

[0232] The first semiconductor element (DI1) and the second semiconductor element (DI2) may be different types of semiconductor elements as described above. In addition, the bridge (BR) may be embedded in the circuit board (100). In addition, the circuit board (100) may be various circuit boards described above. Accordingly, the capacitor structure (CAS) described above may be present in the semiconductor package. This capacitor structure (CAS) may be electrically connected to another substrate, etc., through the first and second semiconductor elements on the upper side or the solder member (SB2) on the lower side.

[0233] Additionally, the package substrate may include solder members (SB1, 2) for connection between the first and second semiconductor elements and the electrodes on the upper or lower portion of the circuit board (100). The solder member (SB1) may also be positioned between the bridge (BR) and the first and second semiconductor elements. Additionally, the solder member (SB2) may be positioned between the package substrate and the lower element or substrate.

[0234] Additionally, in the package substrate according to the embodiment, the via electrode in the core layer of the circuit board (100) may overlap with the bridge (BR) in the vertical direction. Furthermore, the bridge (BR) and the via electrode in the core layer may be electrically connected. Additionally, the capacitor structure (CAS) may also be electrically connected to the via electrode in the core layer or may overlap with it in the vertical direction.

[0235] Additionally, the bridge (BR) may be an organic or inorganic bridge. For example, the bridge (BR) may be an organic bridge, in which case the via electrode of the core layer may be advantageous for power transmission.

[0236] Furthermore, the circuit board according to the embodiment can be divided into a package board and an interposer according to its function. The package board functions to mount semiconductor devices and / or interposers. As the area of ​​the circuit board increases due to the increase in data, or as the number of laminated insulating layers increases, the yield of the circuit board may be significantly reduced. Therefore, in order to improve the yield of a circuit board with a high number of laminated layers, the yield of the circuit board can be improved by separating it into an interposer and a package board. In addition, as the density of terminals of semiconductor devices increases, it may be difficult to implement pads of the package board having an area corresponding to the terminals of the semiconductor devices. Therefore, the pad size of the package board and the fine pattern size of the terminals of the semiconductor devices can act as a buffer.

[0237] The package substrate and interposer described above can be classified into core substrates and coreless substrates, depending on the composition of the insulating layer. In the case of a core substrate, the insulating layer may include a core layer, and the core layer may refer to a layer among the laminated insulating layers that includes a reinforcing member. The reinforcing member may refer to glass fiber. The core layer may have the function of preventing warpage of the circuit board during the process by being arranged thicker than other insulating layers. However, the core layer may cause problems such as voltage drop and signal loss, or may be difficult to thin. Therefore, depending on the application, the insulating layer of the circuit board may use a coreless substrate that does not include a core layer.

[0238] In various semiconductor packages, circuit boards according to the various embodiments described above may be located in some areas or correspond to one substrate.

[0239] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0240] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0241] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as being included within the scope of the embodiments.

[0242] Although the above description focuses on examples, these are merely examples and are not intended to limit the examples. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present examples. For example, each component specifically shown in the examples can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. First insulation layer; A second insulating layer disposed on the first insulating layer; A first via land disposed between the first insulating layer and the second insulating layer; A first via electrode disposed between the first via land and the lower surface of the first insulating layer; A second via electrode disposed between the first via land and the upper surface of the second insulating layer; and Including a third via electrode arranged between the lower surface of the first insulating layer and the upper surface of the second insulating layer, A circuit board wherein the vertical length of the third via electrode is greater than the sum of the vertical length of the first via electrode and the vertical length of the second via electrode.

2. In paragraph 1, A circuit board in which the third via electrode is horizontally overlapped with the first via electrode and the second via electrode.

3. In paragraph 1, The second insulating layer includes a protrusion penetrating at least a portion of the first insulating layer from the upper surface of the first insulating layer toward the lower surface; The third via electrode is a circuit board arranged within the protrusion.

4. In paragraph 1, The width of the first via electrode gradually increases from the upper surface of the first insulating layer toward the lower surface of the first insulating layer. A circuit board in which the width of the second via electrode gradually decreases from the upper surface of the second insulating layer toward the lower surface of the second insulating layer.

5. In paragraph 1, A circuit board in which the width of the third via electrode gradually decreases from the upper surface of the second insulating layer toward the lower surface of the first insulating layer.

6. In paragraph 1, The above first via electrode includes a first width having the smallest width on the upper surface of the first insulating layer, The second via electrode includes a second width having the smallest width on the lower surface of the second insulating layer, The third via electrode includes a third width having the smallest width in an area adjacent to the lower surface of the first insulating layer, A circuit board having the third width smaller than the first width.

7. In paragraph 1, A circuit board comprising a capacitor structure including a first via land, a dielectric layer, and a second via land sequentially laminated on the first insulating layer.

8. In paragraph 7, A circuit board in which the second via electrode is disposed on the capacitor structure.

9. In paragraph 7, The above capacitor structure is a circuit board including a first capacitor structure and a second capacitor structure that are spaced apart.

10. In paragraph 9, A circuit board wherein the third via electrode is positioned between the first capacitor structure and the second capacitor structure.

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