Circuit board and semiconductor package comprising same

Abstract

Disclosed in one embodiment of the present invention is a circuit board comprising first and second build-up layers on one surface and the other surface of a core layer, respectively, the core layer including: a first insulating layer; second and third insulating layers on one surface and the other surface of the first insulating layer, respectively; and a via electrode integrally penetrating the first to third insulating layers, wherein an inclination angle between one surface of the first insulating layer and the outer surface of a first part of the via electrode arranged in the first insulating layer is greater than an inclination angle between the outer surface of a second part of the via electrode arranged in the second insulating layer and one surface of the first insulating layer.

Description

Circuit boards and semiconductor packages including the same

[0001] Embodiments according to the present invention relate to circuit boards and semiconductor packages.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to mount more semiconductor chips on a limited-size substrate. However, because typical packages are based on mounting a single semiconductor chip, achieving desired performance is limited.

[0003] A typical circuit board or package substrate consists of a processor package, which houses the processor chip, and a memory package, which houses the memory chips, all connected together. These package substrates integrate the processor and memory chips into a single package, reducing the chip footprint and enabling high-speed signal transmission through short paths. Due to these advantages, these package substrates are widely used in mobile devices and other devices.

[0004] Meanwhile, with the recent advancements in electronic devices such as mobile devices, servers, and PCs, and the adoption of HBM (High Bandwidth Memory), the area of ​​semiconductor chips has increased, and multiple semiconductor chips have been attached to a single package substrate to shorten the electrical connection distance between semiconductor chips, which has led to an increase in the size of the package. In addition, as the functions required for application processors increase, there is a need for separate chips for each function, and a circuit substrate on which these processor chips can be mounted. At this time, even when the application processor is separated into two processor chips for each function, the number of terminals (input / output) provided on each processor chip is increasing.

[0005] In addition, due to recent reasons such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed, the number of terminals on processor chips is gradually increasing as the number of power and signals increases. Accordingly, the area, thickness, and circuit pattern density of circuit boards are also increasing. When the area and thickness of circuit boards increase, it becomes difficult to miniaturize products, and there are problems such as reliability problems such as warpage of the circuit board, and increase in product price. Therefore, there is a recent trend to prevent problems such as warpage of the circuit board by forming a thick core layer of the circuit board. However, using a thick core layer may cause difficulties in forming via electrodes on the core layer, such as yield, density of the spacing between via electrodes, and productivity.

[0006] Furthermore, increasing the density of circuit patterns is more advantageous than increasing the area and thickness of the circuit board in terms of product price, reliability (e.g., warpage), and miniaturization. Therefore, miniaturization of circuit patterns and through-hole electrodes is required.

[0007] In particular, as circuit boards become increasingly thinner, deformations such as warping and twisting that occur during circuit board manufacturing are increasing. Accordingly, various technologies are being developed to prevent this.

[0008] An embodiment of the present invention provides a circuit board and a semiconductor package including the same, which secure structural reliability (e.g., mitigation of warpage phenomenon) through a core layer with increased thickness.

[0009] In addition, the embodiment can provide a circuit board and a semiconductor package including the same, which facilitates fine pattern formation and has improved integration by controlling the angle of inclination between the via electrodes of the build-up layer and the core layer.

[0010] In addition, the embodiment can provide a circuit board and a semiconductor package including the same with improved reliability by forming a non-conductive layer on the outer surface of a via electrode to suppress migration.

[0011] In addition, the embodiment can provide a circuit board and a semiconductor package including the same, which can easily change the spacing between via holes or the target by controlling the size of the via holes of the build-up layer through a preventive member.

[0012] The problem to be solved in the embodiment is not limited to this, and it can be said that the purpose or effect that can be understood from the solution or implementation form of the problem described below is also included.

[0013] A circuit board according to an embodiment of the present invention comprises: a core layer including one surface and an opposite surface; a first build-up layer disposed on one surface of the core layer; a second build-up layer disposed on the opposite surface of the core layer; wherein the core layer comprises: a first insulating layer including one surface and an opposite surface; a second insulating layer disposed on one surface of the first insulating layer; a third insulating layer disposed on the opposite surface of the first insulating layer; And a via electrode integrally penetrating the first insulating layer, the second insulating layer, and the third insulating layer, wherein the via electrode includes a first portion disposed within the first insulating layer, a second portion disposed within the second insulating layer, and a third portion disposed within the third insulating layer, wherein the first portion includes a first inclination angle, and the second portion and the third portion each include a second inclination angle, wherein the first inclination angle is an inclination angle formed between one surface of the first insulating layer and an outer surface of the first portion, and the second inclination angle is an inclination angle formed between an outer surface of the second portion and one surface of the first insulating layer, and wherein the first inclination angle is greater than the second inclination angle.

[0014] The first portion may include a first sub-portion having a first inclination angle from one surface of the first insulating layer toward the other surface and a width that gradually decreases, and a first-second portion having a first inclination angle from the other surface of the first insulating layer toward the one surface and a width that gradually decreases.

[0015] The above first part may be symmetrical about the center.

[0016] The first central axis of the first part may be the same as the second central axis of the second part.

[0017] The thickness of the first portion may be greater than the thickness of the first build-up layer or the second build-up layer.

[0018] It may include a first non-conductive layer disposed on the outer surface of the first section.

[0019] It may include a second non-conductive layer disposed on the outer surface of the second portion.

[0020] The upper surface of the first part is in contact with the lower surface of the second part, and the width of the upper surface of the first part may be greater than the width of the lower surface of the second part.

[0021] It may include a third build-up layer disposed on the first build-up layer.

[0022] It may include a first electrode part disposed on the first build-up layer; a second electrode part disposed on the second build-up layer; and a third electrode part disposed on the third build-up layer.

[0023] The second central axis of the second part may be the same as the third central axis of the third part.

[0024] The third inclination angle of the first via electrode of the first electrode portion may be different from the first inclination angle.

[0025] The first slope angle may be greater than the third slope angle.

[0026] The fourth inclination angle of the third via electrode of the third electrode portion may be the same as the third inclination angle.

[0027] The second and third sections may have widths that increase in a direction away from the first section.

[0028] The second insulating layer may have the same thickness as the third insulating layer.

[0029] The maximum width of the first section may be smaller than the maximum width of the second section.

[0030] It may include a third non-conductive layer arranged on the outer surface of the first via electrode of the first electrode portion.

[0031] The above via electrodes are multiple, and the spacing between adjacent via electrodes among the multiple via electrodes may be smaller than the maximum radius of the via electrodes.

[0032] An embodiment of the present invention implements a circuit board and a semiconductor package including the same, which secure structural reliability (e.g., mitigation of warpage phenomenon) through a core layer with increased thickness.

[0033] In addition, the embodiment can implement a circuit board and a semiconductor package including the same, which facilitates fine pattern formation and has improved integration by controlling the angle of inclination between the via electrodes of the build-up layer and the core layer.

[0034] In addition, the embodiment can implement a circuit board and a semiconductor package including the same with improved reliability by forming a non-conductive layer on the outer surface of a via electrode to suppress migration.

[0035] In addition, the embodiment can implement a circuit board and a semiconductor package including the same, which can easily change the spacing between via holes or the target by controlling the size of the via holes of the build-up layer through the preventive member.

[0036] The various advantageous and beneficial effects of the present invention are not limited to the above-described contents, and will be more easily understood in the course of explaining specific embodiments of the present invention.

[0037] Figure 1 is a cross-sectional view of a circuit board according to a first embodiment of the present invention.

[0038] Figure 2a is an enlarged view of K1 in Figure 1,

[0039] Figure 2b is an enlarged view of a portion of Figure 2a,

[0040] Fig. 3 is a modified example of Fig. 2a,

[0041] Figure 4 is an enlarged view of K2 in Figure 1,

[0042] Fig. 5 is a modified example of Fig. 4,

[0043] Figure 6 is an enlarged view of K3 in Figure 1,

[0044] Figures 7 to 10 are drawings explaining a method for manufacturing a circuit board according to the first embodiment of the present invention.

[0045] Fig. 11 is a cross-sectional view of a circuit board according to a second embodiment of the present invention.

[0046] Figure 12 is an enlarged view of K4 in Figure 11,

[0047] Fig. 13 is a cross-sectional view of a circuit board according to a third embodiment of the present invention.

[0048] Figure 14 is an enlarged view of K5 of Figure 13,

[0049] Fig. 15 is a plan view of the electrode portion arranged on the build-up layer in Fig. 13.

[0050] Fig. 16 is a drawing showing a circuit board according to an embodiment and a semiconductor package using the same.

[0051] Fig. 17 is a cross-sectional view showing a semiconductor package according to the first embodiment.

[0052] Fig. 18 is a cross-sectional view showing a semiconductor package according to the second embodiment.

[0053] Fig. 19 is a cross-sectional view showing a semiconductor package according to the third embodiment.

[0054] The present invention can be modified in various ways and has various embodiments, and specific embodiments are illustrated and described in the drawings. However, this is not to be construed as a specific embodiment of the present invention.

[0055] It is not intended to be limited to the embodiments, and should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention.

[0056] Terms that include ordinal numbers, such as "second," "first," etc., may be used to describe various components, but the components are not limited by the terms. The terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a second component may be referred to as "first component," and similarly, a first component may also be referred to as "second component." The term "and / or" includes a combination of multiple related items described herein or any of multiple related items described herein.

[0057] When a component is referred to as being "connected" or "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but that there may be other components intervening. Conversely, when a component is referred to as being "directly connected" or "connected" to another component, it should be understood that there are no other components intervening.

[0058] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0059] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning they have in the context of this specification, and general terms explicitly defined in this application should be interpreted in the sense defined herein.

[0060] Hereinafter, embodiments will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or corresponding components are given the same reference numbers, and redundant descriptions thereof will be omitted.

[0061] Before describing the embodiments, an electronic device to which the circuit board and semiconductor package of the embodiments are applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. The semiconductor package may contain various semiconductor elements.

[0062] The semiconductor device may include active components and / or passive components. The active components may be semiconductor devices in the form of integrated circuits (ICs) in which hundreds to millions of components are integrated into a single chip. The semiconductor device may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an application processor (AP) chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chip set including a specific combination of the above-mentioned components.

[0063] The memory chip may be a stacked memory such as HBM. Additionally, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

[0064] Additionally, when multiple semiconductor devices are mounted on a package substrate, a connecting member may be placed to electrically connect them. The connecting member may be embedded in the package substrate, but is not limited thereto, and may be placed on the package substrate.

[0065] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0066] Additionally, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the present invention is not limited thereto, and it is to be understood that the electronic device may be any other electronic device that processes data.

[0067] In the circuit board according to the embodiment of the present invention, the insulating layer may be composed of a plurality of insulating layers. The insulating layer may include a core layer (a glass layer described below) and an insulating layer. In addition, such a circuit board may be divided into an outer laminated region and an inner laminated region, and the inner laminated region may correspond to the core layer.

[0068] FIG. 1 is a cross-sectional view of a circuit board according to a first embodiment of the present invention, FIG. 2a is an enlarged view of K1 in FIG. 1, FIG. 2b is an enlarged view of a portion of FIG. 2a, FIG. 3 is a modified example of FIG. 2a, FIG. 4 is an enlarged view of K2 in FIG. 1, FIG. 5 is a modified example of FIG. 4, and FIG. 6 is an enlarged view of K3 in FIG. 1.

[0069] Referring to FIGS. 1 and 2a, a circuit board (100) according to the first embodiment may include an insulating layer (110), an electrode portion (121, 122, VE), and a protective layer (not shown).

[0070] As an example, the insulating layer (110) may be formed of multiple layers in the circuit board (100). The insulating layer (110) may include a core layer (CL) and a build-up layer (114, 115).

[0071] The core layer (CL) functions to prevent warpage of the package substrate, may include a reinforcing member such as glass fiber, and may be positioned at the center of the insulating layer (110). For example, a build-up layer (114, 115) may be positioned on the outside of the core layer (CL).

[0072] In addition, the core layer (CL) may include one side (US) and the other side (BS). In the vertical direction (X-axis direction), the one side (US) of the core layer (CL) may correspond to the 'upper side'. And the other side (BS) of the core layer (CL2) may correspond to the 'lower side'. In addition, in the present specification, the one side may correspond to the 'upper side', and the other side may correspond to the 'lower side' or the 'lower side'.

[0073] Recently, as the number of layers and area of ​​semiconductor packages increase, the thickness of the core layer (CL) is trending towards increasing to prevent warpage of the semiconductor package. In addition, when processing a via hole in a thick core layer, there is a problem of reduced productivity because a mechanical drill must be used. To improve this, the present invention can improve productivity and reduce costs by providing the core layer (CL) with multiple layers. For example, as illustrated in FIG. 1, the core layer (CL) may include a first insulating layer (111), a second insulating layer (112), and a third insulating layer (113). In addition, a bonding layer may be additionally arranged between the first insulating layer (111) and the second insulating layer (112), and between the first insulating layer (111) and the third insulating layer (113) to secure bonding strength between each insulating layer. In a first use example, the core layer / adhesive layer / core layer may be bonded to each other on the inside of a circuit board. Accordingly, as described above, the bonding layer, which is an adhesive layer, may be positioned between the first insulating layer (111) and the second insulating layer (112), and between the first insulating layer (111) and the third insulating layer (113). As a second use example, the circuit board may be formed of a core layer / PPG on the inner side. For example, the first insulating layer (111) may be a core layer, and the second insulating layer (112) and the third insulating layer (113) may be PPG.

[0074] The first insulating layer (111) may be arranged between the second insulating layer (112) and the third insulating layer (113). Alternatively, the third insulating layer (113), the first insulating layer (111), and the second insulating layer (112) may be sequentially arranged or laminated along the vertical direction (X-axis direction). Accordingly, the circuit board may have a core layer composed of multiple layers, thereby facilitating the processing of via holes, thereby providing the effect of reducing manufacturing costs.

[0075] As an example, the first insulating layer (111) may include one side (US1) and the other side (BS1). And the second insulating layer (112) may be disposed on the one side (US1) of the first insulating layer (111). Alternatively, the second insulating layer (112) may be positioned on the one side (US1) of the first insulating layer (111). And the second insulating layer (112) may be in contact with the one side (US1) of the first insulating layer (111).

[0076] And the third insulating layer (113) can be arranged on the other surface (BS1) of the first insulating layer (111). The third insulating layer (113) can be positioned below the other surface (BS1) of the first insulating layer (111). And the third insulating layer (113) can be in contact with the other surface (BS1) of the first insulating layer (111).

[0077] In addition, one side (US) of the core layer (CL) may correspond to one side of the second insulating layer (112). And the other side (BS) of the core layer (CL) may correspond to the other side of the third insulating layer (113). In addition, the other side of the second insulating layer (112) may correspond to one side (US1) of the first insulating layer (111). And one side of the third insulating layer (113) may correspond to the other side (BS1) of the first insulating layer (111).

[0078] The build-up layer (114, 115) may include at least one layer. For example, the build-up layer may include a plurality of build-up layers. The build-up layer may include a first build-up layer (114) and a second build-up layer (115). In addition, the first build-up layer (114) and the second build-up layer (115) each include an insulating layer and a circuit layer. The circuit layer functions to electrically connect between the package substrate and the semiconductor element and may be provided in a plurality of layers. Therefore, in order to secure an insulating function between the plurality of circuit layers, an insulating layer is provided between each of the plurality of circuit layers.

[0079] The first build-up layer (114) may be disposed on one surface (US) of the core layer (CL). And the second build-up layer (115) may be disposed on the other surface (BS) of the core layer (CL). For example, the first build-up layer (114) may be positioned above the one surface (US) of the core layer (CL), and the second build-up layer (115) may be positioned below the other surface (BS) of the core layer (CL). In addition, the core layer (CL) may be positioned between the first build-up layer (114) and the second build-up layer (115).

[0080] The insulating layer (110) may include a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide. In addition, the insulating layer (110) may further include a reinforcing material in the resin. The reinforcing material may be, for example, a fabric reinforcing material, an inorganic filler, etc. The fabric reinforcing material may be glass fiber, and the glass fiber may be impregnated into the resin to form a prepreg (PPG). In addition, the core layer (CL) may include, for example, CCL, etc.

[0081] For example, the insulating layer (110) may be formed of any insulating resin, such as a thermosetting and / or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto, can be used, and a material such as prepreg (PPG) containing glass fiber can be used. As the photocurable resin, any insulating resin, such as PID (Photo Imageable Dielectric) resin, can be used. The above-described arbitrary insulating resin may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and may include an inorganic filler such as silica. When the insulating resin is used as a core, it may include a reinforcing material formed of glass fiber or aramid fiber. For example, the insulating layer (110) may use ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., as an example, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. may be used. For example, the insulating layer (110) may include a plurality of layers composed of ABF.

[0082] In particular, the insulating layer (110) in the build-up layer (114, 115) can be formed as a build-up film such as ABF, PPG, PID, etc., considering the insulating function, dielectric constant, and the possibility of securing a fine pattern of the circuit layer.

[0083] The electrode portions (121, 122, VE) may include a via electrode (VE), a first electrode portion (121), and a second electrode portion (122). The first and second electrode portions (121, 122) function as a circuit connected to a semiconductor element, and the via (Vertical Interconnect Access, VIA) electrode (VE) functions to electrically connect the first and second electrode portions (121, 122) along the vertical direction. In Fig. 1, the first and second build-up layers (114, 115) are briefly illustrated for the purpose of explaining the present invention, but the present invention is not limited thereto, and the first and second build-up layers (114, 115) may each be provided as a plurality of layers. Accordingly, the via electrode (VE) may be provided not only in the core layer (CL), but also in the first and second build-up layers (114, 115).

[0084] First, the via electrode (VE) can penetrate the core layer (CL). For example, the via electrode (VE) can penetrate the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113) of the core layer (CL). The via electrode (VE) can integrally penetrate the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113) of the core layer (CL). According to the present invention, as the core layer becomes thicker, the second insulating layer (112) and the third insulating layer (113) are arranged on one surface and the other surface of the first insulating layer (111), thereby making the core layer thicker. That is, when using a thick core layer (CL), productivity and yield may be reduced because a mechanical drill is used to form a via electrode (VE), whereas according to the present invention, a laser drill is used to form a via electrode (VE) on a first insulating layer (111) that is relatively thin compared to the entire core layer (CL), and then second and third insulating layers (112, 113) are laminated to continuously form a via electrode (VE), thereby improving productivity and yield.

[0085] And the via electrode (VE) may be composed of a plurality of parts (parts, portions, or sections). The via electrode (VE) may include a first part (P1), a second part (P2), and a third part (P3).

[0086] The first portion (P1) may correspond to an area of ​​a via electrode disposed within the first insulating layer (111). That is, the first portion (P1) may be a via electrode located in a via hole of the first insulating layer (111).

[0087] And the second portion (P2) may correspond to the area of ​​the via electrode disposed within the second insulating layer (112). That is, the second portion (P2) may be a via electrode located in a via hole of the second insulating layer (112).

[0088] The third portion (P3) may correspond to the area of ​​the via electrode disposed within the third insulating layer (113). That is, the third portion (P3) may be a via electrode located in a via hole of the third insulating layer (113).

[0089] And since the first part (P1) processes a via hole using a laser drill in the first insulating layer (111), it may include a first sub-part (or 1-1 part) (P11) and a second sub-part (or 1-2 part) (P12).

[0090] The first sub-section (P11) may have a first-first width (W11) that becomes smaller from one side (US1) of the first insulating layer (111) toward the other side (BS1). In an embodiment, the width may correspond to a length in a direction perpendicular to the vertical direction (X-axis direction) (e.g., a horizontal direction (Y-axis direction)) or an area or diameter in a vertical plane. The first-first width (W11) may gradually become smaller toward the center of the core layer (CL). Alternatively, the first-first width (W11) may gradually become smaller from one side (US1) of the first insulating layer (111) toward the other side (BS1). For example, the first-first width closest to the one side (US1) of the first insulating layer (111) may be larger than the first-first width closest to the other side (BS1) of the first insulating layer (111).

[0091] And the second sub-section (P12) may have a first-second width (W12) that may become smaller from the other side (BS1) of the first insulating layer (111) toward the one side (US1). The first-second width (W12) may gradually become smaller toward the center of the core layer (CL). Alternatively, the first-second width (W12) may gradually become larger from the one side (US1) of the first insulating layer (111) toward the other side (BS1). For example, the first-second width that is closest to the one side (US1) of the first insulating layer (111) may be larger than the first-second width that is closest to the other side (BS1) of the first insulating layer (111).

[0092] In addition, the first portion (P1) may have a first inclination angle (θ). The first sub-portion (P11) may have a first inclination angle (θ) from one side (US1) of the first insulating layer (111) toward the other side (BS1). The second sub-portion (P12) may have a first inclination angle (θ) from the other side (BS1) of the first insulating layer (111) toward the one side (US1). In an embodiment, the first inclination angle (θ) may be an angle formed between one side (US1) of the first insulating layer (111) and the outer side (SF1) of the first portion (P1). In an embodiment, the inclination angle may be a value less than or equal to 180 degrees or 90 degrees. In addition, the inclination angle is an angle formed between a plane perpendicular to the vertical direction based on the center of the core layer (CL) and the outer side of each portion. In this case, the inclination angle may be a clockwise and counterclockwise angle based on a plane perpendicular to the vertical direction based on the center of the core layer (CL). It is an angle formed by one of them. Furthermore, the inclination angle is the degree of separation (angle) between a straight line on a plane perpendicular to the vertical direction based on the center of the core layer (CL) and a straight line on the outer surface of each part.

[0093] The second portion (P2) and the third portion (P3) may include a second inclination angle (θθ). In addition, the third portion (P3) may include a second inclination angle (θ). The second inclination angle (θ) and the second inclination angle (θ) have different drawing symbols but are the same. That is, the second inclination angle (θ) and the second inclination angle (θ) may have the same size.

[0094] The second inclination angle (θθ) is the inclination angle formed by the outer surface (SF2) of the second portion (P2) and one surface (US1) of the first insulating layer (111), or the inclination angle formed by the outer surface (SF3) of the third portion (P3) and the other surface (BS1) of the first insulating layer (111).

[0095] By forming a gap between the core layer (CL) and the build-up layer of the circuit board (100) according to the embodiment, space for heat dissipation and grounding can be easily secured.

[0096] A protective layer (not shown) may be located on top and / or bottom of the insulating layer (110). For example, the protective layer (not shown) may be located on the top and / or bottom of the insulating layer (110).

[0097] A protective layer (not shown) can have the function of protecting the electrode part from external moisture or contaminants, and to prevent a short circuit problem due to a bridge between solders when soldering between a semiconductor element and / or a main board and a circuit board, the protective layer (not shown) may be provided with a solder resist, for example. Specifically, a semiconductor element and / or a main board, etc. have a plurality of terminals for connecting a circuit board. In addition, the plurality of terminals may be arranged at a high density. When a plurality of terminals and pads of a circuit board are joined, solder may be used, for example. When solder is used, a solder short circuit problem may occur between terminals having a high density, and thus, a solder resist that does not have good wettability with the solder may be arranged to solve this short circuit problem. In addition, the protective layer (not shown) may be formed of a material having insulating properties for electrical connection. The protective layer (not shown) may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. Additionally, the third insulating layer (not shown) may include any one of a photo solder resist layer, a cover-lay, and a polymer material.

[0098] And the insulating layer or protective layer (not shown) located in the outer laminated area of ​​the circuit board may have an opening. Through the opening, it may be electrically connected to other semiconductor elements, the circuit board, etc.

[0099] For the electrical connection described above, the conductive member may be located on the upper or lower side of the circuit board (100).

[0100] In an embodiment, a wiring or electrode portion may be arranged for electrical connection between a main board or other components (or semiconductor components (not shown), dies). The electrode portion may include a circuit pattern (or circuit pattern layer), pads, or via electrodes. The wiring may correspond to an 'electrode pattern', a 'pattern', a 'line', or the like.

[0101] In the electrode portion, the circuit pattern can be designed in various forms for transmitting signals and / or power to the semiconductor elements, and can be respectively arranged within a plurality of laminated insulating layers (110).

[0102] In the electrode section, the via electrode is arranged to penetrate at least a portion of each insulating layer for vertical connection between circuit patterns arranged on each vertically stacked insulating layer. That is, the insulating layer may include a via hole for arrangement of the via electrode. In addition, the via electrode may have a wider width than the circuit pattern for impedance optimization or heat dissipation, but is not limited thereto and may be freely designed. As described above, the via electrode may be provided in the first and second build-up layers (114, 115) and the core layer (CL).

[0103] In the electrode section, pads may be arranged on each insulating layer. The pads may be arranged to electrically connect between a circuit pattern and a via electrode. For example, when the width of the via electrode is greater than the width of the circuit pattern, the pad may have a wider width than the circuit pattern for alignment of the via electrode, and may have a circular shape for convenience of the process. In addition, the pads may be electrically connected to a semiconductor element and / or a main board or substrate, etc.

[0104] In particular, pads arranged on the uppermost and / or lowermost insulating layers along the stacking direction of the pads can be bonded to semiconductor elements, substrates, boards, etc. using solder, wires, conductive adhesives, etc., and may be arranged with a width greater than the width of the circuit pattern to solve problems such as securing yield. However, the present invention is not limited thereto, and may have the same width as the width of the circuit pattern depending on the technical limitations of the bonding process.

[0105] And the pad arranged between the uppermost and lowermost insulating layers along the stacking direction functions to connect the via electrode and the circuit pattern. When the via electrode is arranged with a wider width than the circuit pattern, a pad having a wider width than the circuit pattern is provided for alignment during the manufacturing process of the via electrode to be arranged on each circuit pattern. Therefore, each via electrode may have an upper surface that is located on the same plane as the lower surface of the upper pad that is in direct contact with the via electrode, and a lower surface that is located on the same plane as the upper surface of the lower pad that is in direct contact with the lower surface of the via electrode. Here, the lower surface of the upper pad and the upper surface of the lower pad do not necessarily mean a flat surface, and it should be understood that even a concave surface or a convex surface that may appear depending on various processes may be present.

[0106] A semiconductor device (not shown) or bridge may be mounted on or inside the circuit board (100). The semiconductor device (not shown) may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an AP including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chip set including a specific combination of those listed so far. And the memory chip may be a stacked memory such as HBM. In addition, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, or the like.

[0107] Furthermore, a wiring pattern (DL1, DL2) may be present as an electrode in the build-up layer (114, 115). The wiring pattern (DL1, DL2) may be provided with a smaller pitch than the pads of the first and second electrode portions.

[0108] In an embodiment, the first inclination angle (θ) in the circuit board (100) may be different from the second inclination angle (θθ3). For example, the first inclination angle (θ) may be greater than the second inclination angle (θθ3). Accordingly, in the first to third insulating layers having a thick thickness, the width of the via electrode may also increase depending on the inclination angle. Accordingly, it may not be easy to adjust the spacing or pitch between circuit patterns such as pads on the upper surface. At this time, by having different inclination angle structures for the via electrodes penetrating the first and second insulating layers (or the third insulating layer), the pitch between the pads (or electrode portions) on the upper surface can be easily adjusted even in the thick core layer. Furthermore, since the plating thickness of the via electrode can be controlled in a wide range, the voltage drop issue occurring in the thick core layer (CL) can also be resolved.

[0109] And the thickness (T1) of the first insulating layer (111) may be greater than the thickness (T2) of the second insulating layer (112) or the thickness (T3) of the third insulating layer (113). In addition, the thickness of the first portion (P1) may be greater than the thickness of the second portion (P2) or the third portion (P3). The thickness may be a length in the vertical direction.

[0110] In addition, the thickness (T1) of the first insulating layer (111) may be greater than the thickness of the first build-up layer (114) or the second build-up layer (115). Furthermore, the thickness of the core layer (CL) may be greater than the thickness of the build-up layers (114, 115). By this configuration, the thickness of the core layer in the circuit board increases, and the warpage phenomenon due to a large area and a high number of layers can be suppressed.

[0111] In addition, the thickness of the first insulating layer (111), the second insulating layer (112), or the third insulating layer (113) may be greater than the thickness of the build-up layer (114, 115). As a result, as described above, heat dissipation and reliability may be improved through the thick core layer, and a high-speed signal layer may be implemented as the fine pitch between the electrode portions of the build-up layer becomes easier.

[0112] As an example, the thickness (T2) of the second insulating layer (112) and the thickness (T3) of the third insulating layer (113) may be the same. In addition, the second insulating layer (112) and the third insulating layer (113) may be positioned symmetrically with respect to the center line (CA) of the core layer (CL). In addition, the first portion (P1) may be positioned symmetrically with respect to the center line (CA) of the core layer (CL). For example, the first sub-portion (P11) and the second sub-portion (P12) may also be positioned symmetrically with respect to the center line (CA) of the core layer (CL). By this configuration, the structural reliability of the circuit board may be improved.

[0113] Furthermore, the first central axis (AX1) of the first portion (P1) may be identical to the second central axis (AX2) of the second portion (P2). In an embodiment, the first central axis (AX1) may be parallel to the vertical direction (X-axis direction). And the first central axis (AX1) may correspond to a line connecting the centers of the first portion (P1) to a plane perpendicular to the vertical direction.

[0114] The first central axis (AX1) and the second central axis (AX2) are parallel to the vertical direction and can be vertically overlapped with each other. Accordingly, the structure of the via electrode can be symmetrical with respect to the central axis rather than being concentrated on one side. Therefore, the reliability of the via electrode and the circuit board can be secured.

[0115] Referring further to Fig. 2b, the areas of the upper surface of the first portion (P1) and the lower surface of the second portion (P2) may be the same or different. In addition, the width of the upper surface of the first portion (P1) and the width of the lower surface of the second portion (P2) may be the same or different.

[0116] Referring to (a) of FIG. 2B, the upper surface of the first portion (P1) may be smaller than the area of ​​the lower surface of the second portion (P2). In addition, the width (Wb) of the upper surface of the first portion (P1) may be larger than the width (Wa) of the lower surface of the second portion (P2). Accordingly, the edge of the lower surface of the second portion (P2) may be located inside the edge of the upper surface of the first portion (P1).

[0117] Referring to (b) of FIG. 2B, the upper surface of the first portion (P1) may be smaller than the area of ​​the lower surface of the second portion (P2). In addition, the width (Wd) of the upper surface of the first portion (P1) may be smaller than the width (Wc) of the lower surface of the second portion (P2). Accordingly, the edge of the lower surface of the second portion (P2) may be located outside the edge of the upper surface of the first portion (P1).

[0118] Referring to (c) of FIG. 2b, the upper surface of the first portion (P1) may have the same area as the lower surface of the second portion (P2). In addition, the width of the upper surface of the first portion (P1) may be the same as the width of the lower surface of the second portion (P2). Furthermore, the edge of the lower surface of the second portion (P2) may be the same as the edge of the upper surface of the first portion (P1).

[0119] Furthermore, the width (W11) of one side or the upper surface of the first portion (P1) may be greater than or equal to the width (W2) of the lower surface of the second portion (P2). For example, the width (W11) of one side or the upper surface of the first portion (P1) may be greater than the width (W2) of the lower surface of the second portion (P2). This allows the pitch between the uppermost electrode portions to be reduced while reducing the width of some areas.

[0120] Additionally, the width (W12) of the top or bottom surface of the first portion (P1) may be greater than or equal to the width (W3) of the top surface of the third portion (P3). For example, the width (W12) of the top or bottom surface of the first portion (P1) may be greater than the width (W3) of the top surface of the third portion (P3).

[0121] In addition, the second portion (P2) and the third portion (P3) may increase in width in a direction away from the first portion (P1). For example, the width (W2) of the second portion (P2) may increase from the other side (BS) of the core layer (CL) toward the one side (US). And the width (W3) of the third portion (P3) may increase from the one side (US) of the core layer (CL) toward the other side (BS). That is, the width (W2) of the second portion (P2) may increase in the vertical direction, and the width (W3) of the third portion (P3) may increase in the opposite direction to the vertical direction. Accordingly, the width may be maximum on one side of the second portion (P2), and minimum on the other side. Conversely, the width may be minimum on one side of the third portion (P3), and maximum on the other side. Accordingly, alignment of the second part (P2) and the third part (P3) arranged on one side and the other side of the first part (P1) can be secured, and more advantageous effects can be achieved in terms of heat dissipation and voltage drop prevention characteristics.

[0122] And the maximum width of the first part (P1) may be smaller than the maximum width of the second part (P2) or the third part (P3). Accordingly, the maximum width of the first part (P1) may be smaller than the maximum width of the second part (P2). And the maximum width of the first part (P1) may be smaller than the maximum width of the third part (P3). By this configuration, the issue of voltage drop according to the thickness of the via electrode can be resolved.

[0123] Additionally, the second central axis (AX2) of the second portion (P2) may be identical to the third central axis (AX3) of the third portion (P3). That is, the via electrode (VE) provides structural stability, thereby improving heat dissipation characteristics.

[0124] Furthermore, the first electrode portion (121) may be placed on the first build-up layer (114), and the second electrode portion (122) may be placed on the second build-up layer (115).

[0125] The first electrode portion (121) may include a first via electrode (121a) and a first pad (121b). The second electrode portion (122) may include a second via electrode (122a) and a second pad (122b). For example, the pad of the electrode portion disposed on the build-up layer may be formed using a modified semi-additive process (mSAP) process.

[0126] Referring further to FIG. 3, a first non-conductive layer (NC1) may be further disposed on an outer surface of the first portion (P1). The first non-conductive layer (NC1) may be formed of a non-conductive material. For example, the first non-conductive layer (NC1) may include a resin or the like. This description may be equally applied to the non-conductive layer below. For example, the first non-conductive layer (NC1) may include a first-first non-conductive layer (NC11) and a first-second non-conductive layer (NC12). The first-first non-conductive layer (NC11) may be disposed on an outer surface of the first sub-portion (P11). The first-second non-conductive layer (NC12) may be disposed on an outer surface of the second sub-portion (P12). For example, the first non-conductive layer (NC1) may be disposed along the outer surface of the first portion (P1). In addition, the first non-conductive layer (NC1) may be positioned on at least a portion of the outer surface of the first portion (P1). When the core layer (CL) includes a reinforcing member such as glass fiber, ion migration may occur between the conductive material constituting the via electrodes (VE) along the reinforcing member to the via electrodes (VE) that are closest to each other. However, with this configuration, migration between the via electrodes (VE) that are closest to each other can be suppressed. Therefore, the electrical reliability of the circuit board (100) according to the embodiment can be improved.

[0127] The first non-conductive layer (NC1) is arranged along the outer surface of the first portion (P1), for example, the first non-conductive layer (NC1) can surround the outer surface of the first portion (P1).

[0128] In addition, the circuit board (100) may include a second non-conductive layer (NC2, NC3) disposed on the outer surface of the second portion (P2) or the third portion (P3). The second non-conductive layer (NC2) disposed on the outer surface of the second portion (P2) may suppress migration of a conductive material that occurs when voltage is applied to the second portion (P2). In addition, the third non-conductive layer (NC3) may suppress migration of a conductive material that occurs when voltage is applied to the third portion (P3).

[0129] The second non-conductive layer (NC2, NC3) may be arranged along the outer surface of the second portion (P2) or the third portion (P3). The second non-conductive layer (NC2, NC3) may be arranged to surround the second portion (P2) or the third portion (P3).

[0130] In addition, the first non-conductive layer (NC1) may form an inclined angle with respect to one surface of the insulating layer, such as the first portion (P1). The second non-conductive layer (NC2, NC3) may form an inclined angle with respect to one surface of the insulating layer (110), such as the second portion (P2) or the third portion (P3). The inclined angle of the first non-conductive layer (NC1) may be smaller than the inclined angle of the second non-conductive layer (NC2, NC3). Accordingly, the second non-conductive layer (NC2, NC3) may be positioned outside the first non-conductive layer (NC1) with respect to the central axis of the via electrode (VE). For example, the width (or maximum width) between the second non-conductive layer (NC2, NC3) and the central axis of the via electrode (VE) may be larger than the width (or maximum width) between the first non-conductive layer (NC1) and the central axis of the via electrode (VE).

[0131] Referring further to FIG. 4, the third inclination angle (θ) of the first via electrode (121a) of the first electrode portion (121) may be different from the first inclination angle (θ). The third inclination angle (θ) may be an angle formed by one surface of the second insulating layer (112) and the outer surface of the first via electrode (121a).

[0132] For example, the third inclination angle (θ) may be greater than the first inclination angle (θ). By this configuration, the alignment of the first electrode portion (121) with respect to the via electrode (VE) is easy, and the spacing between the first pad of the first electrode portion and the pad of the adjacent electrode portion can be easily adjusted. In other words, the pitch between adjacent first electrode portions can be easily adjusted, so that the formation of a fine pattern can be more easily achieved. That is, the integration degree of the circuit board (100) can be improved.

[0133] Additionally, the third inclination angle (θ) may be smaller than the first inclination angle (θ). With this configuration, electrical connection between the first electrode portion and the first via electrode can be easily achieved.

[0134] Additionally, the width (W4) of the first via electrode (121a) in the first electrode portion (121) may increase along the vertical direction. Conversely, the width of the first via electrode (122b) in the second electrode portion (122) may decrease along the vertical direction.

[0135] And the fourth central axis (AX4) of the first electrode portion (121) or the second electrode portion (122) may be the same as the via electrode (VE). For example, the fourth central axis (AX4) of the first electrode portion (121) or the second electrode portion (122) may overlap the central axis of the via electrode in the vertical direction.

[0136] Referring further to FIG. 5, in a circuit board according to an embodiment, a third non-conductive layer (NC4) may be arranged on the outer surface of the first via electrode (121) (or the second via electrode) in the first electrode portion (121) (or the second electrode portion (122). The third non-conductive layer (NC4) may suppress migration of a conductive material according to voltage application in the first and second electrode portions. As a result, the electrical reliability of the circuit board (100) may be improved.

[0137] The third non-conductive layer (NC4) may be arranged along the outer surface of the first and second electrode portions. The third non-conductive layer (NC4) may be arranged to surround the first and second electrode portions (e.g., the first and second via electrodes).

[0138] Referring to FIG. 6, a circuit board (100) may have a plurality of via electrodes (VE). The plurality of via electrodes (VE) may be positioned adjacent to each other. In an embodiment, a spacing (sp) between adjacent via electrodes (VE) may be smaller than a maximum radius (DI) of the via electrodes (VE). For example, the spacing (sp) between adjacent via electrodes may be 30 um or less, and the maximum radius (DI) of the via electrodes (VE) may be 80 um or less. By this configuration, the thickness of the via electrodes may be secured while at the same time making the spacing between the electrodes fine. For example, the pitch between the via electrodes of the core (the sum of the spacing (sp) and the maximum radius (DI) of the via electrodes) may be implemented to be 130 um or less.

[0139] FIGS. 7 to 10 are drawings explaining a method for manufacturing a circuit board according to a first embodiment of the present invention.

[0140] A method for manufacturing a circuit board according to an embodiment may include providing a first insulating layer (111) (step), forming a via hole and a via electrode (first portion) through one surface and the other surface of the first insulating layer (111) (step), forming a second insulating layer and a third insulating layer on both surfaces of the first insulating layer (step), forming a via hole and a via electrode (second and third portions) in the second insulating layer and the third insulating layer (step), and forming a build-up layer and forming first and second electrode portions (step).

[0141] Referring to Fig. 7, a first insulating layer can be provided. The first insulating layer can include, for example, a copper clad laminate as a core layer. In addition, a via hole can be formed on one side and the other side of the first insulating layer (111). That is, a via hole can be formed on both sides of the first insulating layer (111). The via hole can be formed in various ways. For example, a via hole can be formed on both sides of the first insulating layer using a laser.

[0142] And, via filling can be performed in the via hole of the first insulating layer (111). That is, a via electrode (VE) (first part) can be formed in the first insulating layer (111).

[0143] Referring to Fig. 8, a second insulating layer (112) and a third insulating layer (113) may be disposed on both sides of a first insulating layer (111) to form a core layer (CL). For example, the second insulating layer (112) and the third insulating layer (113) may be laminated on one side and the other side of the first insulating layer (111), respectively, and the first insulating layer may be bonded to the second insulating layer (or the second insulating layer) through a press. In addition, as described above, they may be bonded to each other in a structure of core layer / adhesive layer / core layer on the inner side of the circuit board. Accordingly, as described above, a bonding layer, which is an adhesive layer, may be positioned between the first insulating layer (111) and the second insulating layer (112), and between the first insulating layer (111) and the third insulating layer (113).

[0144] In addition, the core layer may be composed of a first insulating layer (111), a second insulating layer (112), and a third insulating layer (113) as described above. In addition, as an additional example, the first insulating layer (111) may be a core layer, and the second insulating layer (112) and the third insulating layer (113) may have a structure in which at least one build-up layer is laminated. In this case, the above-described contents may be equally applied. However, the following description will be based on the contents of FIGS. 1 and 2.

[0145] Referring to Fig. 9, via holes can be formed in the second insulating layer (112) and the third insulating layer (113). The via holes can be formed in various ways. For example, the via holes in the second and third insulating layers can be formed using a laser.

[0146] And via filling can be performed on the via holes of the second insulating layer (112) and the third insulating layer (113). That is, the second portion (P2) and the third portion (P3) of the via electrode (VE) can be formed.

[0147] Referring to Fig. 10, a build-up layer can be formed on one side and the other side of the core layer, and first and second electrode portions can be formed. Specifically, a first build-up layer (114) can be formed on one side of the core layer, and a second build-up layer (115) can be formed on the other side of the core layer.

[0148] In addition, via holes can be formed in various ways in the first build-up layer (114) and the second build-up layer (115) and via-fill can be performed. Accordingly, alignment between the vias of the core layer and the vias of the build-up layer can be easily achieved, and via-fill with a high aspect ratio can be applied. In addition, the first and second electrode parts can be formed by performing full etching except for the pads of the first electrode part or the second electrode part. Accordingly, the first electrode part (121) and the second electrode part (122) can be formed in the first build-up layer (114) and the second build-up layer (115), respectively. Furthermore, wiring patterns (DL1, DL2) can also be formed in the build-up layers (114, 115).

[0149] Fig. 11 is a cross-sectional view of a circuit board according to a second embodiment of the present invention, and Fig. 12 is an enlarged view of K4 in Fig. 11.

[0150] Referring to FIGS. 11 and 12, a circuit board (100A) according to the second embodiment may include an insulating layer (110), an electrode portion (121, 122, VE), and a protective layer (not shown). The configuration described in the embodiments of the present invention may be applied equally, except for the contents described below.

[0151] In the circuit board (100A) according to the present embodiment, the build-up layer of the insulating layer (110) may be formed of a plurality of layers. As an example, the insulating layer (110) may include a third build-up layer (116) disposed on a first build-up layer (114). In addition, the insulating layer (110) may include a fourth build-up layer (117) disposed on a second build-up layer (115). The third build-up layer (116) may be disposed on top of the first build-up layer (114), and the fourth build-up layer (117) may be disposed on bottom of the second build-up layer (115).

[0152] Furthermore, the electrode part may include a third electrode part (123) and a fourth electrode part (124).

[0153] As an example, the insulating layer (110) may be formed of multiple layers in the circuit board (100). The insulating layer (110) may include a core layer (CL) and build-up layers (114, 115). The third electrode portion (123) may include a third via electrode (123a) and a third pad (123b). The fourth electrode portion (124) may include a fourth via electrode (124a) and a fourth pad (124b).

[0154] The third electrode portion (123) may include a fifth central axis (AX5). The fifth central axis (AX5) may overlap with the fourth central axis (AX4).

[0155] Furthermore, the outer surface of the third via electrode (123a) in the third electrode portion (123) may form a fourth inclination angle (θ) with the other surface or bottom surface of the third build-up layer (116). The fourth inclination angle (θ) may be equal to the third inclination angle (θ). In addition, that is, the fourth inclination angle of the third via electrode of the third electrode portion may be equal to the third inclination angle.

[0156] Accordingly, the fourth inclination angle (θ) may be different from the first inclination angle (θ). For example, the fourth inclination angle (θ) may be greater than the first inclination angle (θ). By this configuration, alignment of the third electrode portion with respect to the via electrode (VE) or the first electrode portion can be easily performed. Furthermore, since pitch adjustment between adjacent third electrode portions can be easily performed, formation of a fine pattern can be more easily performed. In other words, the integration degree of the circuit board can be improved.

[0157] In addition, the fourth inclination angle (θ) may be smaller than the first inclination angle (θ). Since the thickness of the build-up layer is smaller than that of the core layer, the inclination angles (third and fourth inclination angles) for the via holes of each build-up layer may be formed gently. As a result, the electrical connection, i.e., reliability, may be improved.

[0158] Fig. 13 is a cross-sectional view of a circuit board according to a third embodiment of the present invention, Fig. 14 is an enlarged view of K5 of Fig. 13, and Fig. 15 is a plan view of an electrode portion arranged on a build-up layer in Fig. 13.

[0159] Referring to FIGS. 13 to 15, a circuit board (100B) according to the third embodiment may include an insulating layer (110), an electrode portion (121, 122, VE), and a protective layer (not shown). The configuration described in the embodiments of the present invention may be applied equally, except for the contents described below.

[0160] In the circuit board (100B) according to the present embodiment, the build-up layer may be multiple as described above. That is, as in the embodiment described above, the build-up layer of the insulating layer (110) may be formed of multiple layers. As an example, the insulating layer (110) may include a third build-up layer (116) disposed on the first build-up layer (114). In addition, the insulating layer (110) may include a fourth build-up layer (117) disposed on the second build-up layer (115). The third build-up layer (116) may be disposed on the first build-up layer (114), and the fourth build-up layer (117) may be disposed on the second build-up layer (115).

[0161] Furthermore, the electrode part may include a third electrode part (123) and a fourth electrode part (124).

[0162] As an example, the insulating layer (110) may be formed of multiple layers in the circuit board (100). The insulating layer (110) may include a core layer (CL) and build-up layers (114, 115). The third electrode portion (123) may include a third via electrode (123a) and a third pad (123b). The fourth electrode portion (124) may include a fourth via electrode (124a) and a fourth pad (124b).

[0163] Furthermore, when a build-up layer, such as PGG, is formed on the core layer (CL), the diameter of the via hole may increase due to the thickness of the build-up layer. In other words, expansion of the via hole may occur due to the thin thickness of the build-up layer.

[0164] The circuit board (100A) according to the present embodiment may include a prevention member (R1, R2) placed on the lower part of the pad among the electrode portions of the build-up layer or on the upper surface of the build-up layer.

[0165] The protective members (R1, R2) may be arranged on the upper surface of each build-up layer. In addition, the protective members (R1, R2) may be arranged to have a predetermined radius based on the central axis of the via hole or via electrode of the electrode portion. For example, the protective members (R1, R2) may have a ring shape.

[0166] The preventive members (R1, R2) may be stoppers or preventive elements that form a build-up layer (e.g., 114, 115, 116, 117) and prevent expansion of a via when forming a via hole in the build-up layer. The lower surface of the preventive members (R1, R2) may be flush with the upper surface of the build-up layer. Therefore, the diameter of the preventive members (R1, R2) may be larger than the maximum diameter of the via hole of the build-up layer or the via electrode of the electrode portion. As a result, as described above, expansion of the via hole can be suppressed, and control of a fine line width, etc. can be easily achieved.

[0167] The protective members (R1, R2) may be formed of a conductive material, such as a metal. For example, the protective members (R1, R2) may be formed of copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), etc.

[0168] Furthermore, the protective members (R1, R2) may be partially covered by pads among the electrode portions of the build-up layer. In addition, the thickness of the protective members (R1, R2) may be smaller than the thickness of the pads of the electrode portions.

[0169] In various semiconductor packages, a circuit board according to the various embodiments described above may be located in a certain area or may correspond to a single substrate. For example, a circuit board according to an embodiment may be a semiconductor package, such as an FC-BGA (Flip Chip Ball Grid Array) as described above.

[0170] In addition, circuit boards can be divided into package substrates and interposers according to their function. The package substrate functions to mount semiconductor devices and / or interposers. As data increases, the circuit board area increases or the number of laminated insulating layers increases, which can significantly reduce the yield of the circuit board. Therefore, in order to improve the yield of circuit boards with a high number of laminated layers, the yield of the circuit board can be improved by separating them into an interposer and a package substrate. In addition, as the terminal density of semiconductor devices increases, it may be difficult to implement pads on the package substrate with an area corresponding to the terminals of the semiconductor devices. Therefore, the pad size of the package substrate and the fine pattern size of the terminals of the semiconductor devices can act as a buffer.

[0171] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor elements from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor elements. In addition, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, so that the entire product and the circuit board to which the invention is applied can achieve functional integration or technical interoperability with each other. FIG. 16 is a drawing showing a circuit board according to an embodiment and a semiconductor package to which the same is applied.

[0172] Referring to FIG. 16, the circuit board described above may be located in a portion of a semiconductor package or may correspond to a single substrate. For example, the circuit board according to the various embodiments described above may be located on a single substrate of the semiconductor package. In particular, the circuit board according to the embodiments may be applied to a substrate having a built-in bridge.

[0173] The semiconductor package of the embodiment may include a circuit board (100) and a first semiconductor element (DI1), a second semiconductor element (DI2), and a bridge (BR).

[0174] The first semiconductor element (DI1) and the second semiconductor element (DI2) may be different types of semiconductor elements as described above. In addition, the bridge (BR) may be embedded in the circuit board (100). In addition, the circuit board (100) may be any of the various circuit boards described above.

[0175] Additionally, the package substrate may include a solder member (SB) for connection between the first and second semiconductor elements and the electrode (EP) on the upper portion of the circuit board (100). The solder member (SB) may also be placed between the bridge (BR) and the first and second semiconductor elements.

[0176] As an example, a via electrode in a core layer of a circuit board (100) may overlap a bridge (BR) in a vertical direction. Furthermore, the bridge (BR) and the via electrode in the core layer may be electrically connected. Furthermore, the bridge (BR) may overlap at least a portion of the first and second semiconductor elements (DI1, DI2) in a vertical direction.

[0177] Additionally, as described above, a plurality of build-up layers (BL), which are insulating layers, may be arranged on top and / or bottom of the core layer.

[0178] Additionally, the bridge (BR) may be an organic or inorganic bridge. For example, the bridge (BR) may be an organic bridge, in which case the via electrode of the core layer may be advantageous for power transmission.

[0179] Fig. 17 is a cross-sectional view showing a semiconductor package according to the first embodiment, Fig. 18 is a cross-sectional view showing a semiconductor package according to the second embodiment, and Fig. 19 is a cross-sectional view showing a semiconductor package according to the third embodiment.

[0180] In the various semiconductor packages described below, the circuit board described above may be located in a certain area or may correspond to one substrate. For example, the circuit boards according to the first, second, and third embodiments described above may be located on one substrate of the semiconductor package. In particular, the circuit boards according to the first to third embodiments may be applied to a FC-BGA (Flip Chip Ball Grid Array) substrate. For example, the circuit boards according to the various embodiments may be applied to the first substrate (1100) in each semiconductor package.

[0181] Referring to FIG. 17, the semiconductor package of the first embodiment may include a first substrate (1100), a second substrate (1200), and a semiconductor element (1300).

[0182] The first substrate (1100) may mean or include a 'package substrate' or a 'circuit substrate'. For example, the first substrate (1100) may provide a space to which at least one external substrate is coupled. The external substrate may mean a second substrate (1200) coupled on the first substrate (1100). In addition, the external substrate may mean a main board included in an electronic device coupled to a lower portion of the first substrate (1100).

[0183] Additionally, although not shown in the drawing, the first substrate (1100) can provide a space in which at least one semiconductor element is mounted.

[0184] The first substrate (1100) may include at least one insulating layer and an electrode portion disposed on at least one insulating layer.

[0185] A second substrate (1200) may be placed on the first substrate (1100).

[0186] The second substrate (1200) may be an interposer. For example, the second substrate (1200) may provide a space in which at least one semiconductor element is mounted. The second substrate (1200) may be connected to at least one semiconductor element (1300). For example, the second substrate (1200) may provide a space in which a first semiconductor element (1310) and a second semiconductor element (1320) are mounted. The second substrate (1200) may electrically connect the first semiconductor element (1310) and the second semiconductor element (1320), and electrically connect the first and second semiconductor elements (1310, 1320) and the first substrate (1100). That is, the second substrate (1200) may perform a horizontal connection function between a plurality of semiconductor elements and a vertical connection function between the semiconductor element and the package substrate.

[0187] In Fig. 17, two semiconductor elements (1310, 1320) are illustrated as being arranged on a second substrate (1200), but this is not limited thereto. For example, one semiconductor element may be arranged on the second substrate (1200), or alternatively, three or more semiconductor elements may be arranged.

[0188] A second substrate (1200) may be placed between at least one semiconductor element (1300) and the first substrate (1100).

[0189] In one embodiment, the second substrate (1200) may be an active interposer that functions as a semiconductor device. When the second substrate (1200) functions as a semiconductor device, the semiconductor package of the embodiment may have a vertically stacked structure on the first substrate (1100) and may function as a plurality of logic chips. Having the function of a logic chip may mean having the functions of an active device and a passive device. Unlike passive devices, the characteristics of current and voltage may not be linear in the case of an active device, and the active interposer may have the function of an active device. In addition, the active interposer may perform the function of a corresponding logic chip while performing a signal transmission function between the second logic chip disposed thereon and the first substrate (1100).

[0190] In another embodiment, the second substrate (1200) may be a passive interposer. For example, the second substrate (1200) may function as a signal relay between the semiconductor device (1300) and the first substrate (1100), and may have passive device functions such as a resistor, a capacitor, and an inductor. For example, the number of terminals in the semiconductor device (1300) is gradually increasing due to reasons such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed. That is, the number of terminals provided in the semiconductor device (1300) is increasing, and as a result, the width of the terminals or the spacing between the plurality of terminals is decreasing. At this time, the first substrate (1100) may be connected to the main board of the electronic device. Accordingly, in order for the electrodes provided on the first substrate (1100) to have a width and spacing for connection with the semiconductor element (1300) and the main board, respectively, there is a problem that the thickness of the first substrate (1100) increases or the layer structure of the first substrate (1100) becomes complicated. Therefore, in the first embodiment, a second substrate (1200) can be placed on the first substrate (1100) and the semiconductor element (1300). In addition, the second substrate (1200) can include electrodes having a micro width and spacing corresponding to the terminals of the semiconductor element (1300).

[0191] In addition, the second substrate (1200) can be used as the package substrate disclosed in the present invention. That is, the package substrate of the present invention can be applied to at least one of the first substrate (1100) and / or the second substrate (1200). As described above, as the number of stacked package substrates increases and the area increases, the yield of the package substrate may decrease. Therefore, when the package substrate is manufactured by dividing it into the first substrate (1100) and the second substrate (1200) and then mounting them, the yield of the package substrate can be improved. In this case, the package substrate described above can be used as the first substrate (1100) and / or the second substrate (1200).

[0192] The semiconductor device (1300) may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an AP including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chip set including a specific combination of the above-mentioned. And the memory chip may be a stacked memory such as HBM. In addition, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

[0193] Meanwhile, the semiconductor package of the first embodiment may include a connecting portion.

[0194] For example, a semiconductor package may include a first connection portion (1410) disposed between a first substrate (1100) and a second substrate (1200). The first connection portion (1410) may electrically connect the second substrate (1200) to the first substrate (1100) while bonding them thereto.

[0195] For example, the semiconductor package may include a second connection portion (1420) disposed between a second substrate (1200) and a semiconductor element (1300). The second connection portion (1420) may electrically connect the semiconductor element (1300) while bonding them to the second substrate (1200).

[0196] The semiconductor package may include a third connector (1430) disposed on the lower surface of the first substrate (1100). The third connector (1430) may electrically connect the first substrate (1100) to the main board while connecting them therebetween.

[0197] At this time, the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) can electrically connect the plurality of components using at least one bonding method among wire bonding, solder bonding, and direct metal-to-metal bonding. That is, since the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) have the function of electrically connecting the plurality of components, when direct metal-to-metal bonding is used, the semiconductor package can be understood as a part that is electrically connected rather than solder or wire.

[0198] The wire bonding method may refer to electrically connecting a plurality of components using a conductor such as gold (Au). In addition, the solder bonding method may electrically connect a plurality of components using a material including at least one of Sn, Ag, and Cu. In addition, the direct metal-to-metal bonding method may refer to directly bonding a plurality of components by applying heat and pressure between the plurality of components to recrystallize them without the use of solder, wires, conductive adhesives, etc. In addition, the direct metal bonding method may refer to a bonding method using a second connection portion (1420). In this case, the second connection portion (1420) may refer to a metal layer formed between the plurality of components by recrystallization.

[0199] Specifically, the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) can be bonded to each other by a thermal compression bonding method. The thermal compression bonding method may refer to a method of directly bonding the plurality of components by applying heat and pressure to the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430).

[0200] At this time, in at least one of the first substrate (1100) and the second substrate (1200), the electrodes on which the first connection portion (1410), the second connection portion (1420) and the third connection portion (1430) are arranged may be provided with a protrusion that protrudes outward away from the insulating layer of the corresponding substrate. The protrusion may protrude outward from the first substrate (1100) or the second substrate (1200).

[0201] The protrusion may be referred to as a bump. The protrusion may also be referred to as a post. The protrusion may also be referred to as a pillar. Preferably, the protrusion may refer to an electrode on which a second connection portion (1420) for coupling with a semiconductor element (1300) is arranged among the electrodes of the second substrate (1200). That is, as the pitch of the terminals of the semiconductor element (1300) becomes finer, a short circuit may occur between the plurality of second connection portions (1420) that are respectively connected to the plurality of terminals of the semiconductor element (1300) by a conductive adhesive such as solder. Therefore, in the embodiment, thermal compression bonding may be performed to reduce the volume of the second connection portion (1420). Accordingly, the embodiment may include a protrusion in the electrode of the second substrate (1200) on which the second connecting portion (1420) is arranged to secure alignment (positional alignment), diffusion, and diffusion-preventing properties that prevent intermetallic compounds (IMCs) formed between the conductive adhesive such as solder and the protrusion from diffusing into the interposer and / or the substrate.

[0202] Additionally, looking further into FIG. 18, the semiconductor package of the second embodiment may further include a connecting member (1210).

[0203] The connecting member (1210) may be referred to as a bridge substrate. The connecting member (1210) may function to electrically connect a plurality of semiconductor devices horizontally to each other. For example, if the area required for the semiconductor device is too large, there may be a problem of reduced yield of the semiconductor device. Therefore, the semiconductor devices may be functionally divided and mounted, and the connecting member (1210) may be used to electrically connect them. Alternatively, by connecting the semiconductor devices, the signal transmission path can be significantly reduced compared to the existing individual package level, thereby improving the speed and performance of the semiconductor device.

[0204] In an embodiment, the connecting member (1210) may be an organic bridge. For example, the connecting member (1210) may include an organic material. For example, the connecting member (1210) may include an organic substrate instead of a silicon substrate. The connecting member (1210) may be embedded within the second substrate (1200).

[0205] To this end, the second substrate (1200) may include a cavity, and a connecting member (1210) may be embedded in the second substrate (1200). The connecting member (1210) may horizontally connect a plurality of semiconductor elements disposed on the second substrate (1200).

[0206] Referring to FIG. 19, the semiconductor package of the third embodiment may include a second substrate (1200) and a semiconductor element (1300). At this time, the semiconductor package of the third embodiment may have a structure in which the first substrate (1100) is omitted compared to the semiconductor package of the first embodiment.

[0207] That is, the second substrate (1200) of the second embodiment can function as a package substrate while also functioning as an interposer.

[0208] The first connection portion (1410) arranged on the lower surface of the second substrate (1200) can couple the second substrate (1200) to the main board of the electronic device. When the circuit board having the characteristics of the above-described invention is used in a transportation device such as a vehicle, the problem of distortion of a signal transmitted to the transportation device can be solved, or the semiconductor chip controlling the transportation device can be safely protected from the outside, and the problem of leakage current or electrical short circuit between terminals or electrical open of the terminal supplying to the semiconductor chip can be solved, thereby further improving the stability of the transportation device. Therefore, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0209] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as being included within the scope of the embodiments.

[0210] Although the above description focuses on examples, these are merely examples and are not intended to limit the examples. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present examples. For example, each component specifically shown in the examples can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. Core layer including one side and the other side; A first build-up layer disposed on one surface of the core layer; and A second build-up layer is disposed on the other side of the core layer, The above core layer is, A first insulating layer including one side and the other side; A second insulating layer disposed on one surface of the first insulating layer; A third insulating layer disposed on the other surface of the first insulating layer; and Including a via electrode integrally penetrating the first insulating layer, the second insulating layer, and the third insulating layer, The above via electrode includes a first portion disposed within the first insulating layer, a second portion disposed within the second insulating layer, and a third portion disposed within the third insulating layer, The first part above includes a first inclination angle, The second part and the third part each include a second inclination angle, The above first inclination angle is the inclination angle formed by one side of the first insulating layer and the outer side of the first portion, The above second inclination angle is the inclination angle formed by the outer surface of the second portion and one surface of the first insulating layer, A circuit board wherein the first inclination angle is greater than the second inclination angle.

2. In paragraph 1, A circuit board including a first sub-section having a first inclination angle from one surface of the first insulating layer toward the other surface and a width that gradually decreases, and a first-2 section having a first inclination angle from the other surface of the first insulating layer toward the one surface and a width that gradually decreases.

3. In paragraph 1, The above first part is a circuit board symmetrical with respect to the center.

4. In paragraph 1, The first central axis of the first part and the second central axis of the second part are the same circuit board.

5. In paragraph 1, A circuit board wherein the thickness of the first portion is greater than the thickness of the first build-up layer or the second build-up layer.

6. In paragraph 1, A circuit board comprising a first non-conductive layer disposed on an outer surface of the first portion.

7. In paragraph 1, A circuit board comprising a second non-conductive layer disposed on an outer surface of the second portion.

8. In paragraph 1, The upper surface of the above first part is in contact with the lower surface of the above second part, A circuit board wherein the width of the upper surface of the first portion is greater than the width of the lower surface of the second portion.

9. In paragraph 1, A circuit board comprising a third build-up layer disposed on the first build-up layer.

10. In paragraph 9, A first electrode part arranged on the first build-up layer; A second electrode part arranged on the second build-up layer; and A circuit board including a third electrode portion arranged on the third build-up layer.

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