Display panel

Abstract

This display panel comprises: a transistor; a first conductive layer including a first connection pattern connected to the transistor; a first inorganic layer covering the first conductive layer; a first organic layer disposed on the first inorganic layer; a second conductive layer disposed on the first organic layer and including a second connection pattern connected to the first connection pattern; a second inorganic layer covering the second conductive layer; a second organic layer disposed on the second inorganic layer; a light-emitting element disposed on the second organic layer and connected to the second connection pattern; a contact hole passing through the second inorganic layer and exposing at least a portion of the second conductive layer; and an opening that is spaced apart on a plane from the contact hole and passes through the second inorganic layer to expose at least a portion of the first organic layer.

Description

Display panel

[0001] The present invention relates to a display panel, and more particularly, to a display panel with improved process reliability.

[0002] Multimedia electronic devices such as televisions, mobile phones, tablet computers, navigation devices, and game consoles may include a display panel for displaying images. The display panel may include a plurality of pixels, each of which may include a light-emitting element that generates light and a driving element connected to the light-emitting element.

[0003] Among light-emitting elements, display panels featuring organic light-emitting elements (OLEDs) offer advantages such as wide viewing angles, fast response times, and low power consumption, attracting attention as next-generation electronic devices. However, as electronic devices become larger in size, the voltage stability across the area deteriorates, leading to uneven brightness.

[0004] Accordingly, the present invention aims to provide a display panel with improved process reliability. Furthermore, the present invention aims to provide a high-resolution display panel.

[0005] A display panel according to the present invention comprises a substrate including a display area and a peripheral area adjacent to the display area, a transistor disposed in the display area, a first conductive layer including a first connection pattern disposed on the transistor and connected to the transistor, a first inorganic layer covering the first conductive layer, a first organic layer disposed on the first inorganic layer, a second conductive layer disposed on the first organic layer and including a second connection pattern penetrating through the first inorganic layer and the first organic layer and connected to the first connection pattern, a second inorganic layer covering the second conductive layer, a second organic layer disposed on the second inorganic layer, a light emitting element disposed on the second organic layer and connected to the second connection pattern, a contact hole penetrating the second inorganic layer and exposing at least a portion of the second conductive layer, and an opening spaced in plane from the contact hole and penetrating the second inorganic layer and exposing at least a portion of the first organic layer.

[0006] The second connection pattern can be connected to the first connection pattern through the contact hole.

[0007] The second organic layer can be in contact with the first organic layer through the opening.

[0008] The above openings may be provided in multiple numbers and arranged spaced apart from each other.

[0009] Any one of the above plurality of openings may have different shapes on a plane.

[0010] The above opening may be non-overlapping on a plane with the second connection pattern.

[0011] The second conductive layer further includes a plurality of conductive patterns spaced apart from the second connecting pattern on a plane, and the opening may not overlap with the conductive patterns on a plane.

[0012] Within the above display area, the area on the plane of the opening relative to the area on the plane of the second weapon layer may be 30% or less.

[0013] The first conductive layer may further include a pad electrically connected to the transistor and disposed in the peripheral region, and a first pad opening exposing the pad may be defined in the first inorganic layer.

[0014] The second inorganic layer may be non-overlapping on a plane with the first pad opening.

[0015] A second pad opening overlapping the first pad opening may be defined in the second weapon layer.

[0016] The first pad opening and the second pad opening can be aligned in cross section.

[0017] Each of the first connection pattern and the pad includes a first sub-layer, a second sub-layer disposed on the first sub-layer, and a third sub-layer disposed on the second sub-layer and including a material different from the second sub-layer, and a thickness of the third sub-layer of the first connection pattern may be different from a thickness of the third sub-layer of the pad.

[0018] A display panel according to the present invention comprises: a substrate including a display area including a plurality of light-emitting areas and a peripheral area adjacent to the display area; a transistor disposed in each of the light-emitting areas; a first conductive layer including a plurality of first conductive patterns disposed on the transistor and spaced apart from each other; a first inorganic layer covering the first conductive layer; a first organic layer disposed on the first inorganic layer; a second conductive layer including a plurality of second conductive patterns disposed on the first organic layer and spaced apart from each other; and a second inorganic layer covering the second conductive layer.

[0019] A second organic layer disposed on the second inorganic layer, and a light emitting element disposed in each of the light emitting areas, and disposed on the second organic layer, and connected to the transistor through a first connection pattern among the first conductive patterns and a second connection pattern among the second conductive patterns, wherein the second inorganic layer includes an opening spaced apart from the second conductive patterns in a plane, and the second organic layer can contact the first organic layer through the opening.

[0020] The light-emitting element is connected to the second connection pattern through a contact hole penetrating the second organic layer and the second inorganic layer, and the opening can be spaced apart from the contact hole in a plane.

[0021] The above opening may have a larger area than the above contact hole.

[0022] The above aperture can be defined for each of the above light-emitting areas.

[0023] The above openings may be provided in multiple numbers and arranged spaced apart from each other within each of the above light-emitting regions.

[0024] The first conductive layer may further include a pad disposed in the peripheral region, and a first pad opening exposing the pad may be defined in the first inorganic layer.

[0025] A second pad opening overlapping the first pad opening may be defined in the second weapon layer.

[0026] According to the present invention, a display panel with improved process reliability can be provided.

[0027] Figure 1 is a perspective view of an electronic device of one embodiment.

[0028] Figure 2 is an exploded perspective view of an electronic device of one embodiment.

[0029] Figure 3 is a cross-sectional view of a display module according to one embodiment.

[0030] FIG. 4A is a plan view of a display panel according to one embodiment.

[0031] Figure 4b is an equivalent circuit diagram of a pixel according to one embodiment.

[0032] Figure 4c is a cross-sectional view illustrating a portion of the display panel.

[0033] FIG. 5a is a plan view according to the stacking order of conductive patterns included in a unit pixel according to one embodiment of the present invention.

[0034] FIG. 5b is a cross-sectional view of a portion of a display panel according to one embodiment of the present invention.

[0035] FIGS. 6A to 6M are plan views dividing the stacking order of conductive patterns included in a unit pixel according to one embodiment of the present invention into layers.

[0036] FIG. 7a is a cross-sectional view illustrating a portion of a display panel according to a comparative embodiment of the present invention.

[0037] FIG. 7b is a cross-sectional view illustrating a portion of a display panel according to one embodiment of the present invention.

[0038] FIGS. 8A to 8C are cross-sectional views of a display panel according to one embodiment of the present invention.

[0039] FIGS. 9A to 9D are plan views illustrating a portion of a display panel according to one embodiment of the present invention.

[0040] FIGS. 10A to 10F are plan views illustrating a portion of a display panel according to one embodiment of the present invention.

[0041] FIGS. 11A to 11F are plan views illustrating a portion of a display panel according to one embodiment of the present invention.

[0042] In this specification, when it is said that a component (or region, layer, portion, etc.) is “on,” “connected to,” or “coupled to” another component, it means that it can be directly disposed / connected / coupled to the other component, or a third component may be disposed between them.

[0043] Identical drawing numbers indicate identical components. Furthermore, in the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the purpose of effectively illustrating the technical content.

[0044] “And / or” includes any combination of one or more of the associated constructs that can be defined.

[0045] While terms such as "first" and "second" may be used to describe various components, these components should not be limited by these terms. These terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a "second component," and similarly, a second component may also be referred to as a "first component." Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0046] Additionally, terms such as "below," "lower," "above," and "upper" are used to describe the relationships between components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. Furthermore, terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant technical context, and may be explicitly defined herein, unless interpreted in an idealized or overly formal sense.

[0048] Terms such as "include" or "have" should be understood to specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but not to exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0049] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0050] FIG. 1 is a perspective view of an electronic device according to one embodiment. FIG. 2 is an exploded perspective view of an electronic device according to one embodiment, and FIG. 3 is a cross-sectional view of a display module according to one embodiment.

[0051] An electronic device (DD) may be a device that is activated by an electrical signal and displays an image. The electronic device (DD) may include various embodiments, and for example, the electronic device (DD) may include large devices such as televisions and outdoor billboards, as well as small and medium-sized devices such as monitors, mobile phones, tablet computers, navigation systems, and game consoles. The embodiments of the electronic device (DD) are merely exemplary and are not limited to any one of them, unless they depart from the scope of the present invention.

[0052] Meanwhile, in FIG. 1 and the drawings below, the first direction axis (DR1) to the third direction axis (DR3) are illustrated, and the directions indicated by the first to third direction axes (DR1, DR2, DR3) described in this specification are relative concepts and can be converted into other directions. In addition, the directions indicated by the first to third direction axes (DR1, DR2, DR3) can be described as the first to third directions, and the same drawing symbols can be used.

[0053] In the present specification, the thickness direction of the electronic device (DD) may be a direction parallel to the third direction axis (DR3), which is a normal direction to a plane defined by the first direction axis (DR1) and the second direction axis (DR2). In the present specification, the front (or upper surface) and the back (or lower surface) of the members constituting the electronic device (DD) may be defined based on the third direction axis (DR3).

[0054] An electronic device (DD) can display an image (IM) in a third direction (DR3) through a display surface (IS) that is parallel to a plane defined by a first direction (DR1) and a second direction (DR2). The third direction (DR3) can be parallel to a normal direction of the display surface (IS). The display surface (IS) on which the image (IM) is displayed can correspond to the front surface of the electronic device (DD). The image (IM) can include a still image as well as a dynamic image. Fig. 1 illustrates icon images as an example of an image (IM).

[0055] In this specification, "on a plane" may be defined as a state viewed from a third direction (DR3). In this specification, "on a cross-section" may be defined as a state viewed from a first direction (DR1) or a second direction (DR2). Meanwhile, the directions indicated by the first to third directions (DR1, DR2, DR3) are relative concepts and may be converted into other directions.

[0056] In Fig. 1, an electronic device (DD) having a flat display surface (IS) is exemplarily illustrated. However, the shape of the display surface (IS) of the electronic device (DD) is not limited thereto, and may be curved or three-dimensional.

[0057] The electronic device (DD) may be flexible. "Flexible" refers to the ability to bend, and may encompass a range of structures, from completely foldable to structures that can bend at the nanometer level. For example, the flexible electronic device (DD) may include a curved display device or a foldable display device. However, the electronic device (DD) is not limited thereto, and may be rigid.

[0058] The display surface (IS) of the electronic device (DD) may include a display area (D-DA) and a peripheral area (D-NDA). The display area (D-DA) may display an image (IM). A user may view the image (IM) through the display area (D-DA). In the embodiments illustrated in FIG. 1 and elsewhere, the display area (D-DA) is illustrated as having a rectangular shape, but this is merely an example, and the display area (D-DA) may have various shapes.

[0059] The peripheral area (D-NDA) may be a non-display area that does not display an image (IM). The peripheral area (D-NDA) may have a predetermined color and correspond to a portion that blocks light. The peripheral area (D-NDA) may be adjacent to the display area (D-DA). For example, the peripheral area (D-NDA) may be arranged on at least one side of the display area (D-DA), and the peripheral area (D-NDA) may surround the display area (D-DA). However, this is merely an example, and the peripheral area (D-NDA) may be adjacent to only one side of the display area (D-DA), or may be arranged on a side other than the front of the display device (DD), and the present invention is not limited thereto, and the peripheral area (D-NDA) may be omitted.

[0060] Meanwhile, the electronic device (DD) of one embodiment can detect external input applied from the outside. The external input may take various forms, such as pressure, temperature, and light provided from the outside. The external input may include not only input that contacts the electronic device (DD) (e.g., contact by a user's hand or pen), but also input that is applied in proximity to the display device (DD) (e.g., hovering).

[0061] Referring to FIGS. 2 and 3, the electronic device (DD) includes a window (WM), a display module (DM), and a housing (HAU), and the display module (DM) may include a display panel (DP) and a light control member (LCM). The window (WM) and the housing (HAU) may be combined to define the appearance of the electronic device (DD) and provide an internal space that can accommodate components of the electronic device (DD), such as the display module (DM).

[0062] A window (WM) may be placed on a display module (DM). The window (WM) may protect the display module (DM) from external impact. The front surface of the window (WM) may correspond to the display surface (IS) of the display device (DD) described above. The front surface of the window (WM) may include a transparent area (TA) and a bezel area (BA).

[0063] The transparent area (TA) of the window (WM) may be an optically transparent area. The window (WM) may transmit an image provided by the display module (DM) through the transparent area (TA), and the user may view the image. The transparent area (TA) may correspond to the display area (D-DA) of the electronic device (DD).

[0064] A display module (DM) can display an image according to an electrical signal. The display module (DM) can include a display area (DA) and a non-display area (NDA) adjacent to the display area (DA).

[0065] The display area (DA) may be a portion corresponding to the display area (D-DA, FIG. 1) of the electronic device (DD). The display area (DA) may be an area activated according to an electrical signal. The display area (DA) may be an area that emits an image provided by the display module (DM). The display area (DA) of the display module (DM) may correspond to the above-described transparent area (TA). Meanwhile, in the present specification, "areas / portions correspond to each other" means "overlapping each other" and is not limited to having the same area and / or the same shape. The image displayed in the display area (DA) can be viewed from the outside through the transparent area (TA).

[0066] The non-display area (NDA) may be adjacent to the display area (DA). For example, the non-display area (NDA) may surround the display area (DA). However, the present invention is not limited thereto, and the non-display area (NDA) may be defined in various shapes. The non-display area (NDA) may be a portion corresponding to a peripheral area (D-NDA, FIG. 1) of the electronic device (DD). The non-display area (NDA) may be an area where a driving circuit or driving wire for driving the display area (DA), various signal lines for providing electrical signals, and pads are arranged. The non-display area (NDA) of the display module (DM) may correspond to the bezel area (BA) described above. Components of the display module (DM) arranged in the non-display area (NDA) may be prevented from being viewed from the outside by the bezel area (BA).

[0067] The display panel (DP) according to one embodiment may be an emissive display panel, and is not particularly limited thereto. For example, the display panel (DP) may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material, and the light-emitting layer of the inorganic light-emitting display panel may include an inorganic light-emitting material. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots and quantum rods, etc. Hereinafter, the display panel (DP) is described as an organic light-emitting display panel.

[0068] A display panel (DP) may include a base substrate (BS), a circuit layer (DP-CL), a display element layer (DP-OL), and an encapsulation layer (TFE). Each layer of the display panel (DP) will be described in more detail below.

[0069] A light control member (LCM) can be placed on a display panel (DP). After the light control member (LCM) is provided on the display panel (DP), it can be bonded to the display panel (DP) through a bonding process using a sealing member (SML).

[0070] However, the present invention is not limited thereto, and the light control member (LCM) may be directly disposed on the display panel (DP). In the present specification, the term "directly disposed" may be used to refer to a state in which a separate adhesive layer or adhesive member is not disposed and the light control member (LCM) is formed through a continuous process. For example, the expression "the light control member (LCM) is directly disposed on the display panel (DP)" may refer to a state in which the light control member (LCM) is formed through a continuous process on a base surface provided by the display panel (DP) after the display panel (DP) is formed.

[0071] A sealing member (SML) is arranged in a non-display area (NDA), which is an outer portion of a display module (DM), to prevent foreign substances, oxygen, moisture, etc. from entering the display module (DM) from the outside. The sealing member (SML) may be formed from a sealant containing a curable resin.

[0072] In addition, the display module (DM) according to one embodiment may further include a filling layer (FML) disposed between the display panel (DP) and the light control member (LCM). The filling layer (FML) may fill a space between the display panel (DP) and the light control member (LCM). The filling layer (FML) may function as a buffer between the display panel (DP) and the light control member (LCM). In one embodiment, the filling layer (FML) may have a shock absorption function, etc., and may increase the strength of the display module (DM). The filling layer (FML) may be formed from a filling resin including a polymer resin. For example, the filling layer (FML) may be formed from a filling layer resin including an acrylic resin, an epoxy resin, or the like. Meanwhile, in one embodiment, the filling layer (FML) and the sealing member (SML) may be omitted, the light control member (LCM) may be directly disposed on the display panel (DP), and the base layer (BL) may be omitted from the light control member (LCM).

[0073] A light control member (LCM) may include light control patterns capable of converting optical properties of source light provided from a display panel (DP). The light control member (LCM) may selectively convert a wavelength or color of the source light, or transmit the source light. The light control member (LCM) may control color purity or color reproducibility of light emitted from an electronic device (DD), and may prevent reflection of external light incident from the outside of the electronic device (DD). For example, in one embodiment, the light control member (LCM) may include quantum dots that convert a wavelength of source light provided from the display panel (DP). In addition, in one embodiment, the light control member (LCM) may include a light control layer (CCL) including quantum dots, and a color filter (CFL) disposed on the light control layer (CCL). The light control layer (CCL) and the color filter (CFL) may be disposed on a base layer (BL) of the light control member (LCM).

[0074] A housing (HAU) is positioned below a display module (DM) to accommodate the display module (DM). The housing (HAU) absorbs external impact and protects the display module (DM) by preventing foreign substances / moisture from penetrating into the display module (DM). In one embodiment, the housing (HAU) may be provided in a form in which a plurality of storage members are combined.

[0075] Meanwhile, the display module (DM) may further include an input detection unit. The input detection unit may obtain coordinate information of an external input applied from outside the display device (DD). The input detection unit may be disposed between the display panel (DP) and the light control member (LCM). For example, the input detection unit may be directly disposed on the display panel (DP) through a continuous process, or, not limited thereto, may be manufactured separately and attached to the display panel (DP) through an adhesive layer.

[0076]

[0077] FIG. 4A is a plan view of a display panel according to one embodiment. FIG. 4B is an equivalent circuit diagram of a pixel according to one embodiment. FIG. 4C is a cross-sectional view illustrating a portion of the display panel.

[0078] Referring to FIG. 4a, the display panel (DP) has pixels (PX) arranged in the display area (DA). 11 ~PX nm ) and pixels (PX 11 ~PX nm ) may include signal lines (SL1 to SLn, DL1 to DLm) electrically connected to the display panel (DP). The display panel (DP) may include a driving circuit (GDC) and pads (PD) arranged in a non-display area (NDA).

[0079] Pixels (PX) 11 ~PX nm ) may each include a pixel driving circuit comprising a light-emitting element to be described later, a plurality of transistors (e.g., a switching transistor, a driving transistor, etc.) connected to the light-emitting element, and a capacitor. Pixels (PX 11 ~PX nm ) can each emit light in response to an electrical signal applied to the pixel. Figure 3a shows pixels (PX) arranged in a matrix form. 11 ~PX nm ) is shown as an example, but pixels (PX) 11 ~PX nm ) is not limited to this array form.

[0080] Signal lines (SL1 to SLn, DL1 to DLm) may include scan lines (SL1 to SLn) and data lines (DL1 to DLm). Pixels (PX 11 ~PX nm ) can be connected to a corresponding scan line among the scan lines (SL1 to SLn) and a corresponding data line among the data lines (DL1 to DLm). Pixels (PX 11 ~PX nm) Depending on the configuration of the pixel driving circuit, more types of signal lines can be provided in the display panel (DP).

[0081] The driver circuit (GDC) may include a gate driver circuit. The gate driver circuit may generate gate signals and sequentially output the gate signals to the scan lines (SL1 to SLn). The gate driver circuit may be configured to generate pixels (PX 11 ~PX nm ) can output another control signal to the pixel driving circuit.

[0082] A driving circuit (GDC) and pixels (PX) according to one embodiment 11 ~PX nm ) may include a plurality of thin film transistors (TFTs) formed through a low temperature polycrystalline silicon (LTPS) process, a low temperature polycrystalline oxide (LTPO) process, or an oxide semiconductor process.

[0083] The pads (PD) may be arranged along one direction on the non-display area (NDA). The pads (PD) may be portions connected to a circuit board. The pads (PD) may be respectively connected to corresponding signal lines among the signal lines (SL1 to SLn, DL1 to DLm) and may be electrically connected to corresponding pixels through the signal lines. The pads (PD) may have an integral shape with the signal lines (SL1 to SLn, DL1 to DLm). However, the present invention is not limited thereto, and the pads (PD) may be arranged on a different layer from the signal lines (SL1 to SLn, DL1 to DLm) and may be connected through contact holes.

[0084] Figure 4b shows a pixel (PX) connected to the ith scan line (SLi), the ith sensing line (SSLi), the jth data line (DLj), and the jth reference line (RLj). ij ) is illustrated as an example. Referring to Fig. 4b, the pixel (PXij ) may include a pixel circuit (PC) and a light-emitting element (OLED) connected to the pixel circuit (PC).

[0085] The pixel circuit (PC) may include a plurality of transistors (T1, T2, T3) and a capacitor (Cst). The plurality of transistors (T1, T2, T3) may include a first transistor (T1, or driving transistor), a second transistor (T2, or switching transistor), and a third transistor (T3, sensing transistor). Each of the first to third transistors (T1, T2, T3) may be a thin film transistor.

[0086] The first to third transistors (T1, T2, T3) may be NMOS transistors, but are not limited thereto, and may be PMOS transistors. Each of the first to third transistors (T1, T2, T3) may include a source (S1, S2, S3), a drain (D1, D2, D3), and a gate (G1, G2, G3).

[0087] The light-emitting element (OLED) may be an organic light-emitting element including a first electrode (AE, see FIG. 5b) and a second electrode (CE, see FIG. 5b). Meanwhile, the first electrode (AE) may be referred to as an anode or a pixel electrode, and the second electrode may be referred to as a cathode or a common electrode. The first electrode (AE, see FIG. 5b) of the light-emitting element (OLED) may receive a first voltage (ELVDD) through a driving transistor (T1), and the second electrode (CE, see FIG. 5b) of the light-emitting element (OLED) may receive a second voltage (ELVSS). The light-emitting element (OLED) may emit light by receiving the first voltage (ELVDD) and the second voltage (ELVSS).

[0088] The driving transistor (T1) may include a drain (D1) receiving a first voltage (ELVDD), a source (S1) connected to a first electrode (AE, FIG. 5b) of the light-emitting element (OLED), and a gate (G1) connected to a capacitor (Cst). The driving transistor (T1) may control a driving current flowing from the first voltage (ELVDD) to the light-emitting element (OLED) in response to a voltage value stored in the capacitor (Cst).

[0089] The switch transistor (T2) may include a drain (D2) connected to the j-th data line (DLj), a source (S2) connected to a capacitor (Cst) and a gate (G1) of the driving transistor (T1), and a gate (G2) receiving the i-th write scan signal (SCi). The j-th data line (DLj) may receive a data voltage (Vd) and a data voltage for sensing. The switch transistor (T2) may transfer the data voltage (Vd) input from the j-th data line (DLj) to the driving transistor (T1) according to a switching voltage input from the i-th write scan signal (SCi).

[0090] The sensing transistor (T3) may include a source (S3) connected to the jth reference line (RLj), a drain (D3) connected to the first electrode (AE, FIG. 5b) of the light-emitting element (OLED), and a gate (G3) receiving the ith sampling scan signal (SSi). The jth reference line (RLj) may receive a reference voltage (Vr).

[0091] A capacitor (Cst) may be connected to a gate (G1) of a driving transistor (T1) and a first electrode (AE, FIG. 5b) of a light-emitting element (OLED). The capacitor (Cst) may include a first capacitor electrode connected to the gate (G1) of the driving transistor (T1) and a second capacitor electrode connected to the first electrode (AE, FIG. 5b) of the light-emitting element (OLED). The capacitor (Cst) may store a voltage corresponding to a difference between a voltage received from a switching transistor (T2) and a first voltage (ELVDD).

[0092] Meanwhile, the pixel (PX) shown in Fig. 4b ij ) is the equivalent circuit of one pixel (PX ij ) is shown as an example for pixels (PX) 11 ~PX nm ) is not limited to that shown in Fig. 4b. In another embodiment of the present invention, the pixel (PX ij ) can be implemented in various forms to emit light from the light-emitting element (OLED).

[0093] Figure 4c shows the pixels (PX) shown in Figure 4a. 11 ~PX nm ) is simply illustrated in cross-section corresponding to light-emitting areas corresponding to three pixels. One light-emitting area may be an area where light generated by one light-emitting element included in one pixel is displayed. Meanwhile, as an example, in FIG. 4c, a circuit element layer (DP-CL), a display element layer (DP-OL), a thin film encapsulation layer (TFE), and a filler (FL) are illustrated together with a color filter layer (CFL) and a light conversion layer (LCL). In addition, as an example, in FIG. 4c, the circuit element layer (DP-CL), the display element layer (DP-OL), and the thin film encapsulation layer (TFE) are illustrated as a single layer.

[0094] Referring to FIG. 4C, the display area (DA) may include a first light-emitting area (PA1), a second light-emitting area (PA2), a third light-emitting area (PA3), and a non-light-emitting area (NPA) disposed around each of the first to third light-emitting areas (PA1, PA2, PA3). The first to third light-emitting areas (PA1, PA2, PA3) may generate first light of the same color. For example, the first light may be blue light. However, this is merely an example, and the first to third light-emitting areas (PA1, PA2, PA3) may be areas that emit light of two or more colors, and are not limited to any one embodiment.

[0095] The color filter layer (CFL) may include a first color filter (CF1), a second color filter (CF2), a third color filter (CF3), a low-refractive-index layer (LRL), and a first insulating layer (IL1). By way of example, one each of the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) is illustrated, but in practice, each of the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) may be provided in multiples.

[0096] The light conversion layer (LCL) may include a first quantum dot layer (QDL1), a second quantum dot layer (QDL2), a light transmitting layer (LTL), a bank layer (BK), and a second insulating layer (IL2). By way of example, one each of the first quantum dot layer (QDL1), the second quantum dot layer (QDL2), and the light transmitting layer (LTL) is illustrated, but in practice, each of the first quantum dot layer (QDL1), the second quantum dot layer (QDL2), and the light transmitting layer (LTL) may be provided in multiples.

[0097] A first color filter (CF1), a second color filter (CF2), and a third color filter (CF3) may be disposed under a second substrate (SUB2). When viewed from a plan view, the first color filter (CF1) may overlap the first light-emitting area (PA1), the second color filter (CF2) may overlap the second light-emitting area (PA2), and the third color filter (CF3) may overlap the third light-emitting area (PA3). The first color filter (CF1) may include a red color filter. The second color filter (CF2) may include a green color filter. The third color filter (CF3) may include a blue color filter.

[0098] A low-refractive-index layer (LRL) may be disposed under the second substrate (SUB2) to cover the first to third color filters (CF1, CF2, CF3). The low-refractive-index layer (LRL) may have a lower refractive index than the first quantum dot layer (QDL1), the second quantum dot layer (QDL2), and the light-transmitting layer (LTL). The low-refractive-index layer (LRL) may include an organic layer and a plurality of scattering particles disposed within the organic layer to scatter light. A first insulating layer (IL1) may be disposed under the low-refractive-index layer (LRL). The first insulating layer (IL1) may include an inorganic layer.

[0099] The bank layer (BK) may be disposed under the first insulating layer (IL1). When viewed in a plan view, the bank layer (BK) may overlap the non-emissive area (NPA). Openings (QOP) may be defined in the bank layer (BK) that overlap the first to third emissive areas (PA1, PA2, PA3). The width of each of the openings (QOP) may be greater than the width of the pixel opening described above. The bank layer (BK) may have a black color.

[0100] First and second quantum dot layers (QDL1, QDL2) and a light transmitting layer (LTL) may be arranged in the openings (QOP). Accordingly, the first and second quantum dot layers (QDL1, QDL2) and the light transmitting layer (LTL) may overlap the first to third light emitting areas (PA1, PA2, PA3) when viewed in a plan view. The first quantum dot layer (QDL1) may overlap the first light emitting area (PA1), the second quantum dot layer (QDL2) may overlap the second light emitting area (PA2), and the light transmitting layer (LTL) may overlap the third light emitting area (PA3).

[0101] A second insulating layer (IL2) may be disposed below the bank layer (BK), the first and second quantum dot layers (QDL1, QDL2), and the light transmitting layer (LTL). The second insulating layer (IL2) may include an inorganic layer.

[0102] The first light (L1) generated in the first to third light-emitting areas (PA1, PA2, PA3) can be provided to the first and second quantum dot layers (QDL1, QDL2) and the light-transmitting layer (LTL). The first light (L1) generated in the first light-emitting area (PA1) can be provided to the first quantum dot layer (QDL1), and the first light (L1) generated in the second light-emitting area (PA2) can be provided to the second quantum dot layer (QDL2). The first light (L1) generated in the third light-emitting area (PA3) can be provided to the light-transmitting layer (LTL).

[0103] The first quantum dot layer (QDL1) can convert the first light (L1) into the second light (L2). The second quantum dot layer (QDL2) can convert the first light (L1) into the third light (L3). For example, the second light (L2) can be red light, and the third light (L3) can be green light. The first quantum dot layer (QDL1) can include first quantum dots, and the second quantum dot layer (QDL2) can include second quantum dots. The light-transmitting layer (LTL) can include light-scattering particles.

[0104] The first quantum dots can convert the first light (L1) having a blue wavelength into the second light (L2) having a red wavelength. The second quantum dots can convert the first light (L1) having a blue wavelength into the third light (L3) having a green wavelength. The first and second quantum dots can scatter the second and third lights (L2, L3).

[0105] The light transmitting layer (LTL) can transmit the first light (L1) without performing a light conversion operation. The first light (L1) can be scattered by light scattering particles of the light transmitting layer (LTL) and emitted. The light scattering particles may be included in the first and second quantum dot layers (QDL1, QDL2).

[0106] The first quantum dot layer (QDL1) can emit the second light (L2), the second quantum dot layer (QDL2) can emit the third light (L3), and the light-transmitting layer (LTL) can emit the first light (L1). Accordingly, an image can be displayed by the second light (L2), the third light (L3), and the first light (L1) that display red, green, and blue colors.

[0107] The first to third lights (L1, L2, L3) emitted from the light conversion layer (LCL) can be provided to the user by transmitting through the low-refractive-index layer (LRL), the first, second, and third color filters (CF1, CF2, CF3), and the second substrate (SUB2). The first to third lights (L1, L2, L3) can be further scattered by scattering particles arranged in the low-refractive-index layer (LRL) after being refracted in the low-refractive-index layer (LRL) and then emitted.

[0108] A portion of the first light (L1) may not be converted by the first quantum dots and may pass through the first quantum dot layer (QDL1) to be provided to the first color filter (CF1). In other words, there may be first light (L1) that does not come into contact with the first quantum dots and is not converted into second light (L2). The first color filter (CF1) may block light of other colors. The first light (L1) that is not converted by the first quantum dot layer (QDL1) may be blocked by the first color filter (CF1) having a red color filter and may not be emitted upward.

[0109] A portion of the first light (L1) may not be converted by the second quantum dots and may pass through the second quantum dot layer (QDL2) to be provided to the second color filter (CF2). In other words, there may be first light (L1) that does not come into contact with the second quantum dots and is not converted into third light (L3). The second color filter (CF2) may block light of other colors. The first light (L1) that is not converted by the second quantum dot layer (QDL2) may be blocked by the second color filter (CF2) having a green color filter and may not be emitted upward.

[0110] External light may be provided toward the display panel (DP) from above the display device (DD). The external light may be white light. The white light may include red light, green light, and blue light. If the first to third color filters (CF1, CF2, and CF3) are not used, the external light may be reflected from metal layers (e.g., wiring) within the display panel (DP) and then provided as is to the user from outside. In this case, the external light may be perceived by the user, like light reflected from a mirror.

[0111] The first to third color filters (CF1, CF2, CF3) can prevent reflection of external light. The first to third color filters (CF1, CF2, CF3) can filter external light into red, green, and blue.

[0112] Specifically, green light and blue light of external light provided to the first color filter (CF1) can be blocked by the first color filter (CF1) including a red color filter. Accordingly, the external light provided to the first color filter (CF1) can be filtered into red light, which is the same as the light emitted from the first quantum dot layer (QDL1), by the first color filter (CF1).

[0113] The red and blue light of the external light provided to the second color filter (CF2) can be blocked by the second color filter (CF2), which is a green color filter. Accordingly, the external light provided to the second color filter (CF2) can be filtered by the second color filter (CF2) into the same green light as the light emitted from the second quantum dot layer (QDL2).

[0114] The red and green light of the external light provided to the third color filter (CF3) can be blocked by the third color filter (CF3), which is a blue color filter. Accordingly, the external light provided to the third color filter (CF3) can be filtered by the third color filter (CF3) into the same blue light as the light emitted from the light transmitting layer (LTL). Accordingly, the external light can be blocked by the first to third color filters (CF1, CF2, CF3), thereby reducing the reflection of the external light.

[0115] A bank layer (BK) having a black color can block unnecessary light in a non-luminous area (NPA). For example, the bank layer (BK) can prevent color mixing between the first light (L1), the second light (L2), and the third light (L3) in the non-luminous area (NPA).

[0116]

[0117] FIG. 5A is a plan view illustrating a stacking order of conductive patterns included in a unit pixel according to an embodiment of the present invention. FIG. 5B is a cross-sectional view of a portion of a display panel according to an embodiment of the present invention. FIG. 5B illustrates a portion corresponding to one of the light-emitting areas (PXA) illustrated in FIG. 5A and a non-light-emitting area (NPXA) adjacent thereto. Hereinafter, the present invention will be described with reference to FIGS. 5A and 5B. Meanwhile, the same reference numerals are given to the same components as those described in FIGS. 1 to 4C, and redundant descriptions are omitted.

[0118] FIG. 5A illustrates the arrangement relationship of three pixels included in one unit pixel (PXU) and components included in a driving element. FIG. 5A illustrates a first power line (ED), a second power line (EL), a scan line (SCL), a sensing line (SSL), and data lines (DL1, DL2, and DL3) among signal lines connected to each of the pixels. The pixels are each connected to the first power line (ED), the second power line (EL), the scan line (SCL), and the sensing line (SSL). In addition, the pixels may be connected to corresponding data lines (DL1, DL2, and DL3). The first power line (ED) may provide a first voltage (ELVDD), and the second power line (EL) may provide a second voltage (ELVSS, see FIG. 4B) lower than the first voltage (ELVDD). Meanwhile, this is an example, and the number or arrangement of pixels included in a unit pixel (PXU), and the number or arrangement of signal lines may be varied and are not limited to any one embodiment.

[0119] Each of the pixels according to the present invention may include first to third transistors (T1, T2, T3), a capacitor (Cst), and a light-emitting element (OLED, see FIG. 4b). FIG. 5a illustrates first electrodes (AE1, AE2, AE3) of the light-emitting elements (OLED) included in each of the pixels (PX1, PX2, PX3). An equivalent circuit diagram regarding the first to third transistors (T1, T2, T3) and the capacitor (Cst) included in one of the pixels may correspond to that described in FIG. 4b.

[0120] Referring to FIG. 5b, the display panel (DP) may include a base substrate (BS), a circuit layer (DP-CL), a display element layer (DP-OL), and an encapsulation layer (TFE) that are sequentially laminated. The display panel (DP) may include insulating layers, semiconductor patterns, conductive patterns, signal lines, and the like. In the manufacturing step of the display panel (DP), an insulating layer, a semiconductor layer, and a conductive layer may be formed on the base substrate (BS) by coating, deposition, or the like. Thereafter, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by photolithography. Through this process, a semiconductor pattern, a conductive pattern, a signal line, and the like included in the circuit layer (DP-CL) may be formed. The semiconductor pattern of the circuit layer (DP-CL) may be arranged in a predetermined pattern across the pixels.

[0121] The base substrate (BS) may include a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, or an organic / inorganic composite material substrate. The base substrate (BS) may have a single-layer or multi-layer structure. For example, a multi-layer base substrate (BS) may include synthetic resin layers and at least one inorganic layer disposed between the synthetic resin layers.

[0122] The synthetic resin layer of the base substrate (BS) may include at least one of an acrylate resin, a methacrylate resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin, a perylene resin, and a polyimide resin. However, the material of the synthetic resin layer of the base substrate (BS) is not limited to the above examples.

[0123] A circuit layer (DP-CL) may be disposed on a base substrate (BS). The circuit layer (DP-CL) may include a plurality of transistors constituting a pixel circuit (PC, FIG. 4B), at least one capacitor, and a plurality of insulating layers. In a display panel (DP) according to an embodiment, the circuit layer (DP-CL) may include lower conductive patterns (LPT1, LPT2, LPT3), a transistor (TR), a second conductive layer (MSL2), a third conductive layer (MSL3), a second source conductive pattern (CPT1, CPT2), and insulating layers (10, 20, 30, 40, 50, 60, 70). The insulating layers (10, 20, 30, 40, 50, 60, 70) may include first to seventh insulating layers (10, 20, 30, 40, 50, 60, 70) that are sequentially disposed. However, this is an example and it is obvious that the circuit layer (DP-CL) may further include additional insulating layers between, below, or above the insulating layers (10, 20, 30, 40, 50, 60, 70).

[0124] Each of the insulating layers (10, 20, 30, 40, 50, 60, 70) may include an inorganic layer or an organic layer, and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide, but is not limited to the above materials. The organic layer may include a phenol-based polymer, an acrylic polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorinated polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, and a polymer comprising a combination thereof, but is not limited to the above materials.

[0125] Meanwhile, in Fig. 5b, only one transistor (TR) electrically connected to the light-emitting element (OLED) is shown, but as shown in Fig. 3b, one pixel (PX) ij ) may include a plurality of transistors for driving a light emitting device (OLED).

[0126] The lower conductive patterns (LPT1, LPT2, LPT3) may be arranged between the base substrate (BS) and the first insulating layer (10). In the present embodiment, each of the lower conductive patterns (LPT1, LPT2, LPT3) may have a laminated structure. Each of the lower conductive patterns (LPT1, LPT2, LPT3) may include a first layer (Ma1) and a second layer (Ma2) laminated in the thickness direction. In one embodiment, the thickness of the second layer (Ma2) and the thickness of the first layer (Ma1) may be different from each other. For example, in one embodiment, the thickness of the second layer (Ma2) may be thicker than the thickness of the first layer (Ma1). However, the embodiment is not limited thereto.

[0127] Each of the first layer (Ma1) and the second layer (Ma2) may be formed of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). For example, the first layer (Ma1) may include titanium (Ti), and the second layer (Ma2) may include copper (Cu). However, the embodiment is not limited thereto.

[0128] The lower conductive patterns (LPT1, LPT2, LPT3) may correspond to a first conductive layer (MSL1, see FIG. 6a) described below. The lower conductive patterns (LPT1, LPT2, LPT3) may include a first lower conductive pattern (LPT1), a second lower conductive pattern (LPT2), and a third lower conductive pattern (LPT3) at least partially spaced apart from each other. A first insulating layer (10) may be disposed on a base substrate (BS) to cover the lower conductive patterns (LPT1, LPT2, LPT3). The spaced apart between the lower conductive patterns (LPT1, LPT2, LPT3) may be filled by the first insulating layer (10).

[0129] Alternatively, at least two of the first to third lower conductive patterns (LPT1, LPT2, LPT3) may be conductive patterns having an integral shape that are connected to each other. In this case, the lower conductive patterns that are connected to each other may receive the same electrical signal.

[0130] The first lower conductive pattern (LPT1) may be arranged to overlap (e.g., overlap in a third direction) the transistor (TR). The first lower conductive pattern (LPT1) may block light from entering the semiconductor pattern of the transistor (TR) or may be electrically coupled to the transistor (TR) to control the driving characteristics of the transistor (TR). However, this is merely an example, and the first lower conductive pattern (LPT1) may not overlap the semiconductor pattern (SP) of the transistor (TR) on a plane.

[0131] For example, the first lower conductive pattern (LPT1) may be any one of the light-shielding patterns (BML1, BML2, BML3, see FIG. 6a) described below. Alternatively, the first lower conductive pattern (LPT1) may correspond to or be electrically connected to the power pattern (EBR, see FIG. 6a) described below. The first lower conductive pattern (LPT1) may have various configurations and connection relationships if it is included in the first conductive layer (MSL1, see FIG. 6a), and is not limited to any one embodiment.

[0132] The second lower conductive pattern (LPT2) may be configured to form a capacitor with the upper conductive pattern (UPT). For example, the second lower conductive pattern (LPT2) may have an integral shape with the first lower conductive pattern (LPT1). Alternatively, the second lower conductive pattern (LPT2) may be a physically separate pattern that receives the same electrical signal as the first lower conductive pattern (LPT1), or may be a conductive pattern that receives a different signal, for example, any one of the signal lines (IL, EBR, DL1, DL2, DL3, E-1, see FIG. 6a) described below, and is not limited to any one embodiment.

[0133] The third lower conductive pattern (LPT3) may be any one of the initial line (IL), the power pattern (EBR), the plurality of light-shielding patterns (BML1, BML2, BML3), the first to third data lines (DL1, DL2, DL3), and the first line (E-1). That is, the third lower conductive pattern (LPT3) may be a pattern connected to at least one of the first and second lower conductive patterns (LPT1, LPT2), or may be a separate pattern. In the present embodiment, the third lower conductive pattern (LPT3) may be any one of the signal lines transmitting the second voltage (ELVSS, see FIG. 4B), or may be a conductive pattern connected thereto. For example, the third lower conductive pattern (LPT3) may be the first line (E-1). The first to third lower conductive patterns (LPT1, LPT2, LPT3) may have various configurations as long as they are conductive patterns arranged between the base substrate (BS) and the first insulating layer (10), and are not limited to any one embodiment.

[0134] The first insulating layer (10) may be a buffer layer that improves the bonding strength between the base substrate (BS) and the semiconductor pattern of the circuit layer (DP-CL). The first insulating layer (10) may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide, but is not limited to the above materials.

[0135] A transistor (TR) is disposed on a first insulating layer (10). The transistor (TR) may include a gate electrode (GT) and a semiconductor pattern (SP). The transistor (TR) may be any one of the first to third transistors (T1, T2, T3) illustrated in FIG. 5A. The semiconductor pattern (SP) may include polysilicon. However, the present invention is not limited thereto, and the semiconductor pattern (SP) may include amorphous silicon or a metal oxide.

[0136] In the present embodiment, the source, channel, and drain of the transistor (TR) may be formed from a semiconductor pattern (SP). The semiconductor pattern (SP) of the transistor (TR) may be divided into a plurality of regions (R1, CR, R2) depending on the degree of conductivity. For example, the electrical properties of the semiconductor pattern (SP) may vary depending on whether it is doped or whether the metal oxide is reduced. Regions (R1, R2) having relatively high conductivity among the semiconductor pattern (SP) may serve as electrodes or signal lines, and each of the regions (R1, R2) may correspond to a source or a drain of the transistor (TR). Hereinafter, in the present embodiment, the first region (R1) may be referred to as a source of the transistor (TR), and the second region (R2) may be referred to as a drain of the transistor (TR).

[0137] A region of the semiconductor pattern (SP) that is non-doped, relatively lightly doped, or non-reduced may have relatively low conductivity, and may correspond to a channel (CR) of the transistor (TR). However, this is merely an example, and only the channel (CR) of the transistor (TR) may be formed on the semiconductor pattern (SP), and the source (R1) and the drain (R2) may be formed as separate conductive patterns, such as a gate electrode (GT), and connected to the semiconductor pattern (SP). The transistor (TR) according to one embodiment of the present invention may be formed in various structures and is not limited to any one embodiment.

[0138] A second insulating layer (20) is disposed on the first insulating layer (10). The second insulating layer (20) can cover at least a portion of the semiconductor pattern (SP) of the circuit layer (DP-CL). The second insulating layer (20) can be an inorganic layer. In the present embodiment, a portion (20T) of the second insulating layer (20) can be a gate insulating film (20T) covering the channel (CR). Another portion (20C) can be a capacitor insulating film (20C) disposed on the first insulating layer (10) spaced apart from the semiconductor pattern (SP) and overlapping with the second lower conductive pattern (LPT2). The gate insulating film (20T) and the capacitor insulating film (20C) can be separate patterns that are spaced apart from each other on a plane, or can be insulating patterns that are connected to each other and have an integral shape. Meanwhile, this is an example, and the second insulating layer (20) may be provided in a shape that covers the entire semiconductor pattern of the circuit layer (DP-CL) by being placed on the first insulating layer (10), and is not limited to any one embodiment.

[0139] A gate electrode (GT) and an upper conductive pattern (UPT) may be arranged on the second insulating layer (20). The gate electrode (GT) and the upper conductive pattern (UPT) may form a second conductive layer (MSL2, see FIG. 6e) described later. In the present embodiment, the gate electrode (GT) and the upper conductive pattern (UPT) are illustrated as being spaced apart from each other on a plane. The gate electrode (GT) and the upper conductive pattern (UPT) may be separate conductive patterns spaced apart from each other on a plane, or may be conductive patterns that are connected to each other and have an integral shape, and are not limited to any one embodiment.

[0140] Specifically, the gate electrode (GT) is disposed on the gate insulating film (20T). The gate electrode (GT) overlaps the channel (CR) of the transistor (TR) and can function as the gate of the transistor (TR). Meanwhile, the gate electrode (GT) can function as a mask in the process of doping the semiconductor pattern (SP).

[0141] An upper conductive pattern (UPT) is disposed on a capacitor insulating film (20C). The upper conductive pattern (UPT) overlaps a second lower conductive pattern (LPT2) in a plane to form a capacitor. The capacitor insulating film (20C) can serve as a dielectric of the capacitor together with the first insulating layer (10). The capacitor formed by the second lower conductive pattern (LPT2) and the upper conductive pattern (UPT) may correspond to the capacitor (Cst) illustrated in FIG. 4B or may constitute a part of the capacitor (Cst).

[0142] The gate electrode (GT) and the upper conductive pattern (UPT) may be formed by being simultaneously patterned with the same material. The gate electrode (GT) and the upper conductive pattern (UPT) may each have a structure in which multiple layers are laminated. For example, the gate electrode (GT) and the upper conductive pattern (UPT) may each include a first layer (Mb1) and a second layer (Mb2) that are sequentially laminated. However, the embodiment is not limited thereto, and the gate electrode (GT) and the upper conductive pattern (UPT) may each be formed as a single layer or may be formed by laminating three or more layers.

[0143] The gate electrode (GT) and the upper conductive pattern (UPT) may each be formed of a metal material. The gate electrode (GT) and the upper conductive pattern (UPT) may each be formed of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and indium tin oxide (ITO). For example, the first layer (Mb1) may include titanium (Ti), and the second layer (Mb2) may include copper (Cu). However, the embodiment is not limited thereto.

[0144] A third insulating layer (30) may be disposed on the gate electrode (GT) and the upper conductive pattern (UPT). The third insulating layer (30) may include an organic layer. The third insulating layer (30) may provide a flat upper surface. However, the embodiment is not limited thereto.

[0145] A plurality of first conductive patterns (CPT1a, CPT1b, CPT1c, CPT1d) may be arranged on the third insulating layer (30). The first conductive patterns (CPT1a, CPT1b, CPT1c, CPT1d) may correspond to the third conductive layer (MSL3, see FIG. 6g) described below.

[0146] In the present embodiment, the first conductive patterns (CPT1a, CPT1b, CPT1c, CPT1d) may be formed by being simultaneously patterned with the same material. The first conductive patterns (CPT1a, CPT1b, CPT1c, CPT1d) may each have a structure in which a plurality of layers are stacked. For example, the first conductive patterns (CPT1a, CPT1b, CPT1c, CPT1d) may each include a first sub-layer (Mc1), a second sub-layer (Mc2), and a third sub-layer (Mc3) that are sequentially stacked. However, the embodiment is not limited thereto, and the first conductive patterns (CPT1a, CPT1b, CPT1c, CPT1d) may each be a single layer, a stack of two layers, or a stack of four or more layers.

[0147] The first conductive patterns (CPT1a, CPT1b, CPT1c, CPT1d) may include a first connection electrode (CPT1a), a second connection electrode (CPT1b), a first pattern (CPT1c), and a third connection electrode (CPT1d). The first connection electrode (CPT1a) may be connected to the first lower conductive pattern (LPT1) through a first contact hole (CH1) penetrating the third insulating layer (30) and the first insulating layer (10). In addition, the first connection electrode (CPT1a) may be connected to the source (R1) through a second contact hole (CH2) defined in the third insulating layer (30). In the present embodiment, the first connection electrode (CPT1a) may be connected to a power line that supplies power to the light-emitting element (OLED). A first voltage (ELVDD, see FIG. 4b) may be provided to the transistor (TR) through the power line. However, this is merely an example, and the first connection electrode (CPT1a) may be selectively connected to only one of the first lower conductive pattern (LPT1) and the source (R1). In this case, the first lower conductive pattern (LPT1) may receive a different voltage from the source (R1).

[0148] The second connection electrode (CPT1b) can be connected to the drain (R2) of the transistor (TR) through a third contact hole (CH3) penetrating the third insulating layer (30). The drain (R2) of the transistor (TR) can be electrically connected to other transistors constituting the pixel circuit or signal lines connected to the pixel circuit through the second connection electrode (CPT1b).

[0149] The first pattern (CPT1c) may be arranged at a position overlapping the upper conductive pattern (UPT) on a plane. The first pattern (CPT1c) may form a capacitor with the upper conductive pattern (UPT) and the third insulating layer (30) interposed therebetween. At this time, the second lower conductive pattern (LPT2), the upper conductive pattern (UPT), and the first pattern (CPT1c) may form a single capacitor connected in series, which may correspond to the capacitor (Cst) illustrated in FIG. 4b. However, this is merely an example, and the first pattern (CPT1c) may be arranged at a position that does not overlap the upper conductive pattern (UPT), or may not form a capacitor with the upper conductive pattern (UPT), and is not limited to any one embodiment.

[0150] The third connection electrode (CPT1d) may be connected to the third lower conductive pattern (LPT3) through a fourth contact hole (CH4) penetrating the first insulating layer (10) and the third insulating layer (30). The third connection electrode (CPT1d) may be a signal line transmitting the second power voltage (ELVSS, see FIG. 4b) or a conductive pattern connected thereto.

[0151] A fourth insulating layer (40) may be disposed on the third insulating layer (30). The fourth insulating layer (40) may be an inorganic layer. For example, the fourth insulating layer (40, hereinafter referred to as the first inorganic layer) may include silicon oxide. However, the embodiment is not limited thereto. The first inorganic layer (40) is disposed on the third insulating layer (30) to cover the first conductive patterns (CPT1a, CPT1b, CPT1c, CPT1d). The spaces between the first conductive patterns (CPT1a, CPT1b, CPT1c, CPT1d) may be covered by the first inorganic layer (40).

[0152] A fifth insulating layer (50) is disposed on the first inorganic layer (40). The fifth insulating layer (50) may be an organic layer. The fifth insulating layer (50, hereinafter referred to as the first organic layer) covers the upper surface of the curved first inorganic layer (40) and provides a flat surface thereon.

[0153] A plurality of second conductive patterns (CPT2a, CPT2b, CPT2c) may be arranged on the first organic layer (50). The second conductive patterns (CPT2a, CPT2b, CPT2c) may correspond to a fourth conductive layer (MSL4, see FIG. 6j) described later. In the present embodiment, the second conductive patterns (CPT2a, CPT2b, CPT2c) may be formed by being simultaneously patterned with the same material. The second conductive patterns (CPT2a, CPT2b, CPT2c) may each have a structure in which a plurality of layers are stacked. For example, the second conductive patterns (CPT2a, CPT2b, CPT2c) may each include a first sub-layer (Md1), a second sub-layer (Md2), and a third sub-layer (Md3) that are sequentially stacked. However, the embodiment is not limited thereto, and the second challenge patterns (CPT2a, CPT2b, CPT2c) may each include two or fewer layers, or four or more layers may be laminated.

[0154] The second conductive patterns (CPT2a, CPT2b, CPT2c) may include, but are not limited to, a fourth connection electrode (CPT2a), a second pattern (CPT2b), and a fifth connection electrode (CPT2c). The fourth connection electrode (CPT2a), the second pattern (CPT2b), and the fifth connection electrode (CPT2c) are arranged spaced apart from each other on the first organic layer (50).

[0155] The fourth connection electrode (CPT2a) is connected to the first connection electrode (CPT1a) through the fifth contact hole (CH5) penetrating the first inorganic layer (40) and the first organic layer (50). The fourth connection electrode (CPT2a) may correspond to the node connecting the light-emitting element (OLED) illustrated in FIG. 4b and the source (S1) of the first transistor (T1).

[0156] The second pattern (CPT2b) may be spaced apart from and electrically insulated from the fourth connection electrode (CPT2a) and the fifth connection electrode (CPT2c) in a plane. For example, the second pattern (CPT2b) may be data lines (DL1, DL2, DL3), a sensing line (SSL), or a scan line (SCL). Alternatively, the second pattern (CPT2b) may be a conductive pattern connected to any one of the fourth connection electrode (CPT2a) and the fifth connection electrode (CPT2c), and is not limited to any one embodiment.

[0157] The fifth connecting electrode (CPT2c) is connected to the third connecting electrode (CPT1d) through the sixth contact hole (CH6) penetrating the first inorganic layer (40) and the first organic layer (50). The fifth connecting electrode (CPT2c) may be a power line transmitting a second power voltage (ELVSS, see FIG. 4b) or a conductive pattern connected thereto.

[0158] A sixth insulating layer (60, hereinafter referred to as a second inorganic layer) is disposed on the first organic layer (50). The second inorganic layer (60) may include an inorganic material. For example, the second inorganic layer (60) may include silicon oxide. However, the embodiment is not limited thereto. The second inorganic layer (60) covers the second conductive patterns (CPT2a, CPT2b, CPT2c). Specifically, the second inorganic layer (60) may cover all conductive patterns constituting the second conductive patterns (CPT2a, CPT2b, CPT2c), i.e., the fourth connection electrode (CPT2a), the second pattern (CPT2b), and the fifth connection electrode (CPT2c) in FIG. 5b.

[0159] A seventh insulating layer (70, hereinafter referred to as the second organic layer) is disposed on the second inorganic layer (60). The second organic layer (70) includes an organic material. The second organic layer (70) covers the upper surface of the curved second inorganic layer (60) and provides a flat surface thereon.

[0160] According to the present invention, by additionally forming second conductive patterns (CPT2a, CPT2b, CPT2c) in addition to first conductive patterns (CPT1a, CPT1b, CPT1c, CPT1d), connections between pixel circuit configurations including a transistor (TR), a capacitor (Cst), and a light-emitting element (OLED) can be made not only through the first conductive patterns (CPT1a, CPT1b, CPT1c, CPT1d) but also through the second conductive patterns (CPT2a, CPT2b, CPT2c). Accordingly, the area occupied by circuit configurations for driving one light-emitting element (OLED) can be reduced, so that a display panel (DP) with a high resolution can be easily formed.

[0161] At least one opening (HH) may be defined in the second inorganic layer (60) according to the present embodiment. The opening (HH) may be defined at a position spaced apart from each of the conductive patterns constituting the second conductive patterns (CPT2a, CPT2b, CPT2c) on a planar surface. That is, the opening (HH) does not overlap with the third connecting pattern (CNE3) and the second conductive pattern (CPT2) on a planar surface. The opening (HH) penetrates the second inorganic layer (60) to expose the upper surface of the first organic layer (50). Specifically, the opening (HH) penetrates a portion of the second inorganic layer (60) that covers the spaced space between the second conductive patterns (CPT2a, CPT2b, CPT2c), and the second organic layer (70) and the first organic layer (50) may be in contact with each other through the opening (HH).

[0162] The opening (HH) can be a path for air or gas present in the first organic layer (50) to move to the second organic layer (70). The air or gas transferred from the first organic layer (50) to the second organic layer (70) can be discharged to the outside together with the air or gas present in the second organic layer (70). According to the present invention, by forming the opening (HH) in the second inorganic layer (60), even if the inorganic layer (60) is formed on the first organic layer (50), air or gas does not remain in the first organic layer (50) and can move to the second organic layer (70) through the opening (HH). Accordingly, the occurrence of defects such as lifting or peeling of the second inorganic layer (60) due to air or gas can be prevented. Therefore, the process reliability can be improved.

[0163] A display element layer (DP-OL) including a light-emitting element (OLED) and a pixel defining layer (PDL) may be disposed on a circuit layer (DP-CL). In addition, the display element layer (DP-OL) may include an encapsulation layer (TFE) disposed on the light-emitting element (OLED).

[0164] A light-emitting element (OLED) and a pixel defining layer (PDL) may be disposed on a second organic layer (70). The light-emitting element (OLED) may include a first electrode (AE), a hole transport region (HCL), an emission layer (EML), an electron transport region (ECL), and a second electrode (CE) that are sequentially stacked. Meanwhile, in the light-emitting element (OLED), the hole transport region (HCL) and the electron transport region (ECL) may be omitted or provided in a multiple layer structure, and are not limited to any one embodiment.

[0165] A pixel aperture (PX-OP) may be defined in a pixel defining layer (PDL) corresponding to a light-emitting area (PXA). A portion of a first electrode (AE) of a light-emitting element (OLED) may be exposed in the pixel aperture (PX-OP). Meanwhile, the light-emitting area (PXA) may correspond to the exposed portion of the first electrode (AE).

[0166] The pixel defining layer (PDL) may include an organic material. For example, the pixel defining layer (PDL) may include a polyacrylate-based resin or a polyimide-based resin, but the material of the pixel defining layer (PDL) is not limited to the above examples. Meanwhile, the pixel defining layer (PDL) may also be formed of an inorganic material. For example, the pixel defining layer (PDL) may include silicon nitride (SiN). x ), silicon oxide (SiO x ), silicon nitride (SiO x N y ) may be included, but the material of the pixel defining layer (PDL) is not limited to the above examples.

[0167] The pixel defining layer (PDL) may include a light absorbing material or may have a predetermined color. For example, the pixel defining layer (PDL) may include a base resin and a black pigment and / or black dye mixed into the base resin.

[0168] The first electrode (AE) may be formed of a metal material, a metal alloy, or a conductive compound. The first electrode (AE) may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The first electrode (AE) may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca (a laminated structure of LiF and Ca), LiF / Al (a laminated structure of LiF and Al), Mo, Ti, W, or a compound or mixture thereof (for example, a mixture of Ag and Mg). Alternatively, the first electrode (AE) may have a multi-layer structure including a reflective film or a semi-transmissive film formed of the above materials and a transparent conductive film formed of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), or the like. For example, the first electrode (AE) may include a first layer (Ma1), a second layer (Ma2), and a third layer (CL3) that are sequentially laminated. Specifically, the first electrode (AE) may have a three-layer structure in which the first layer (Ma1) includes ITO, the second layer (Ma2) includes Ag, and the third layer includes ITO, but the embodiment is not limited thereto.

[0169] The first electrode (AE) can be connected to the fourth connection electrode (CPT2a) through the seventh contact hole (CH7) penetrating the second inorganic layer (60) and the second organic layer (70). Accordingly, the first electrode (AE) can be electrically connected to the source (S1) of the transistor (TR).

[0170] A hole transport region (HCL) is provided on the first electrode (AE). The hole transport region (HCL) may have a multilayer structure including a single layer made of a single material, a single layer made of multiple different materials, or multiple layers made of multiple different materials.

[0171] The hole transport region (HCL) may include at least one of a hole injection layer, a hole transport layer, and an electron blocking layer. Additionally, the hole transport region (HCL) may include a plurality of stacked hole transport layers.

[0172] An emission layer (EML) may be disposed on the hole transport layer (HCL). The emission layer (EML) may have a multilayer structure including a single layer made of a single material, a single layer made of multiple different materials, or multiple layers made of multiple different materials. In one embodiment, the emission layer (EML) may emit blue light as source light. However, the embodiment is not limited thereto, and the display element layer (DP-OL) may include light-emitting elements (OLED) including emission layers (EML) that emit light in different wavelength ranges.

[0173] The electron transport region (ECL) may be disposed on the emission layer (EML). The electron transport region (ECL) may have a multilayer structure including a single layer made of a single material, a single layer made of multiple different materials, or multiple layers made of multiple different materials. The electron transport region (ECL) may include at least one of a hole blocking layer, an electron transport layer, and an electron injection layer, but the embodiment is not limited thereto.

[0174] The hole transport region (HCL), the emission layer (EML), and the electron transport region (ECL) can be formed using various methods, such as vacuum deposition, spin coating, casting, Langmuir-Blodgett (LB) method, inkjet printing, laser printing, and laser induced thermal imaging (LITI).

[0175] Meanwhile, the hole transport region (HCL), the emission layer (EML), and the electron transport region (ECL) may be provided as a common layer so as to overlap the entire plurality of emission regions (PXA) and non-emission regions (NPXA). However, the embodiment is not limited thereto, and the emission layer (EML) may be provided by being patterned so as to correspond only to the emission region (PXA) and a portion of the non-emission region (NPXA) adjacent to the emission region (PXA).

[0176] The second electrode (CE) is provided on the electron transport region (ECL). The second electrode (CE) may be a common electrode. That is, in the light-emitting device (OLED) of one embodiment, the second electrode (CE) may be provided as a common layer so as to overlap the entirety of the plurality of light-emitting regions (PXA) and the non-light-emitting region (NPXA).

[0177] The second electrode (CE) may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca (a laminated structure of LiF and Ca), LiF / Al (a laminated structure of LiF and Al), Mo, Ti, Yb, W, or a compound or mixture thereof (for example, AgMg, AgYb, or MgYb). Alternatively, the second electrode (CE) may have a multi-layer structure including a reflective film or a semi-transmissive film formed of the above-described material and a transparent conductive film formed of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), or the like. For example, the second electrode (CE) may include the above-described metal materials, a combination of two or more metal materials selected from the above-described metal materials, or oxides of the above-described metal materials.

[0178] The second electrode (CE) can be connected to the auxiliary electrode (AXE) through an auxiliary opening (AX-OP) defined in a pixel defining layer (PDL). The auxiliary electrode (AXE) can be disposed on the same layer as the first electrode (AE). The auxiliary electrode (AXE) and the first electrode (AE) can correspond to a pixel electrode layer (AEL, see FIG. 6m) described later. The auxiliary electrode (AXE) can be disposed on the second organic layer (70) and connected to the fifth connection electrode (CPT2c) through an eighth contact hole (CH8) formed by penetrating the second inorganic layer (60) and the second organic layer (70). Accordingly, the second electrode (CE) can be electrically connected to a signal line transmitting the second power voltage (ELVSS).

[0179] The encapsulation layer (TFE) may cover the light-emitting element (OLED). The encapsulation layer (TFE) may seal the display element layer (DP-OL). The encapsulation layer (TFE) may be a thin film encapsulation layer. The encapsulation layer (TFE) may be a single layer or a plurality of laminated layers. The encapsulation layer (TFE) includes at least one insulating layer. The encapsulation layer (TFE) according to one embodiment may include at least one inorganic film (hereinafter, referred to as an encapsulation inorganic film). In addition, the encapsulation layer (TFE) according to one embodiment may include at least one organic film (hereinafter, referred to as an encapsulation organic film) and at least one encapsulation inorganic film.

[0180] The encapsulating inorganic film protects the display element layer (DP-OL) from moisture / oxygen, and the encapsulating organic film protects the display element layer (DP-OL) from foreign substances such as dust particles. The encapsulating inorganic film may include, but is not particularly limited to, silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, or aluminum oxide. The encapsulating organic film may include, but is not particularly limited to, an acrylic compound, an epoxy compound, or the like. The encapsulating organic film may include, but is not particularly limited to, a photopolymerizable organic material.

[0181]

[0182] FIGS. 6A to 6M are plan views dividing the stacking order of conductive patterns included in a unit pixel according to an embodiment of the present invention into layers. FIGS. 6A to 6M illustrate the configurations illustrated in FIG. 5B by dividing them into layers based on the area illustrated in FIG. 5A. Hereinafter, the present invention will be described with reference to FIGS. 6A to 6M. An equivalent circuit diagram for the first to third transistors (T1, T2, T3) and the capacitor (Cst) included in one pixel among the pixels may correspond to that described in FIG. 4B.

[0183] Referring to FIG. 6a, the first conductive layer (MSL1) according to the present invention may include an initial line (IL), a power pattern (EBR), a plurality of light-shielding patterns (BML1, BML2, BML3), first to third data lines (DL1, DL2, DL3), and a first line (E-1) among the second power lines (EL). As described above, the first conductive layer (MSL1) may correspond to the lower conductive patterns (LPT1, LPT2, LPT3) illustrated in FIG. 5b.

[0184] Each of the initial line (IL) and the power pattern (EBR) extends along the second direction (DR2), and the initial line (IL) and the power pattern (EBR) may be spaced apart in the first direction (DR1). The first to third data lines (DL1, DL2, DL3) may be spaced apart in the first direction (DR1), and each of the first to third data lines (DL1, DL2, DL3) may extend along the second direction (DR2). Although FIGS. 6A to 6M illustrate the second data line (DL2), the first data line (DL1), and the third data line (DL3) being sequentially arranged along the first direction (DR1), the present invention is not limited thereto, and the arrangement order of the first to third data lines (DL1, DL2, DL3) may be changed and is not limited to any one embodiment. In addition, in the present embodiment, the first to third data lines (DL1, DL2, DL3) are illustrated as being included in the first conductive layer (MSL1), but this is not limited to the first to third data lines (DL1, DL2, DL3) and the first to third data lines (DL1, DL2, DL3) may be arranged in a layer other than the first conductive layer (MSL1), and are not limited to any one embodiment.

[0185] The first line (E-1) arranged at the lowest layer among the second power lines (EL) may extend in the second direction (DR2). Accordingly, the first line (E-1) may extend in the same direction as the first to third data lines (DL1, DL2, DL3) and the initial line (IL). The first line (E-1) may correspond to the third lower conductive pattern (LPT3, see FIG. 5b) described above. That is, the first line (E-1) may be connected to an additional line (E-12) of the third conductive layer (MSL3) described later, and may provide a second power voltage (ELVSS) to the light-emitting element (OLED).

[0186] The shading patterns (BML1, BML2, BML3) are arranged between the second data line (DL2) and the power pattern (EBR), and can be spaced apart from each other along the second direction (DR2). The first lower conductive pattern (LPT1, see FIG. 5b) described above can correspond to any one of the shading patterns (BML1, BML2, BML3). That is, the shading patterns (BML1, BML2, BML3) can be individually provided so that a portion thereof overlaps with a semiconductor layer of a first transistor (T1) among the corresponding pixels. According to one embodiment, each of the shading patterns (BML1, BML2, BML3) is connected to a source (S1) of an overlapping transistor (e.g., the first transistor (T1)), and receives a signal applied to the source (S1), thereby forming a sync structure under the semiconductor pattern.

[0187] Meanwhile, the second lower conductive pattern (LPT2, see FIG. 5b) described above may correspond to another part of the shading patterns (BML1, BML2, BML3). That is, a part of each of the shading patterns (BML1, BML2, BML3) may correspond to the first lower conductive pattern (LPT1) overlapping the transistor (e.g., the first transistor (T1)), and another part of each of the shading patterns (BML1, BML2, BML3) may correspond to the second lower conductive pattern (LPT2) forming the capacitor (Cst). Accordingly, the first lower conductive pattern (LPT1) and the second lower conductive pattern (LPT2) may have an integral shape. However, this is merely an example, and the second lower conductive pattern (LPT2) may have a configuration other than that of the shading patterns (BML1, BML2, BML3), and is not limited to any one embodiment.

[0188] Referring to Fig. 6b, the first conductive layer (MSL1) may be covered by the first insulating layer (10). Fig. 6b illustrates contact holes formed in the first insulating layer (10). The first insulating layer (10) is disposed on a base layer (BS, see Fig. 5b) and covers the first conductive layer (MSL1). A plurality of contact holes may be defined in the first insulating layer (10) that penetrate the first insulating layer (10) and expose a portion of the first conductive layer (MSL1).

[0189] The first initial contact holes (CNT-R1) may expose a portion of the initial line (IL). The first-first additional contact holes (CNT-A1) and the first-second additional contact holes (CNT-Q1) may expose a portion of the first line (E-1). Either of the first-first additional contact holes (CNT-A1) and the first-second additional contact holes (CNT-Q1) may correspond to a portion of the fourth contact hole (CH4, see FIG. 5b) described above. The first-first power contact holes (CNT-P1), the first-second power contact holes (CNT-V1), and the first line contact hole (CNT-E1) may expose a portion of the power pattern (EBR).

[0190] The first data contact holes (CNT-D1) can expose a portion of the corresponding data line among the first to third data lines (DL1, DL2, DL3).

[0191] The first shading contact holes (CNT-B1) may expose a portion of a corresponding shading pattern among the shading patterns (BML1, BML2, BML3). Each of the first shading contact holes (CNT-B1) may correspond to a portion of the first contact hole (CH1, see FIG. 5b) described above. Meanwhile, this is merely an example, and the number and positions of the contact holes formed in the first insulating layer (10) may vary and are not limited to any one embodiment.

[0192] Referring to FIG. 6c, a semiconductor pattern layer (SML) according to the present invention may be disposed on a first insulating layer (10). The semiconductor pattern layer (SML) may include first to third semiconductor patterns (SP1, SP2, SP3) that are disposed spaced apart from each other on a plane.

[0193] The first semiconductor pattern (SP1) may include a source (S1), a drain (D1), and a channel region (A1, hereinafter referred to as a channel). A channel (A1) may be arranged between the source (S1) and the drain (D1). The first semiconductor pattern (SP1) may be provided in multiple numbers and may be arranged to overlap each of the light-shielding patterns (BML1, BML2, BML3).

[0194] Similarly, the second semiconductor pattern (SP2) may include a source (S2), a drain (D2), and a channel (A2). The channel (A2) may be arranged between the source (S2) and the drain (D2). The second semiconductor pattern (SP2) may be provided in multiple numbers and spaced apart from each other along the second direction (DR2). Each second semiconductor pattern (SP2) may be arranged between a corresponding light-shielding pattern and data lines (DL1, DL2, DL3).

[0195] In addition, the third semiconductor pattern (SP3) may include a source (S3), a drain (D3), and a channel (A3). The channel (A3) may be arranged between the source (S3) and the drain (D3). The third semiconductor pattern (SP3) may be provided in multiple numbers and may be arranged between the initial line (IL) and the power pattern (EBR) while being spaced apart from each other along the second direction (DR2).

[0196] The regions included in each of the semiconductor patterns (SP1, SP2, SP3) may be divided into a source, drain, and channel after performing a reduction process using the gate described below as a mask.

[0197] Each of the semiconductor patterns (SP1, SP2, SP3) may be formed as an oxide semiconductor pattern. For example, the oxide semiconductor may include either IGZO (Indium Gallium Zinc Oxide) or ITZO (Indium Tin Zinc Oxide). However, the present invention is not limited thereto, and the semiconductor patterns may be formed of amorphous silicon or polycrystalline silicon, and are not limited to any one embodiment.

[0198] Referring to FIG. 6d, a second insulating layer (20) is formed on a semiconductor pattern layer (SML). The second insulating layer (20) is disposed on the first insulating layer (10) and covers at least a portion of the semiconductor pattern layer (SML). The second insulating layer (20) may include a plurality of insulating patterns (21, 22, 23, 24, 25) that are disposed spaced apart from each other on a plane. In the present embodiment, the second insulating layer (20) may include first to fifth insulating patterns (21, 22, 23, 24, 25).

[0199] The first to third insulating patterns (21, 22, 23) may be patterns that overlap the first to third shading patterns (BML1, BML2, BML3), respectively. Each of the first to third insulating patterns (21, 22, 23) may have a shape that overlaps the channel (A1) of the first semiconductor pattern (SP1) and exposes the source (S1) and the drain (D1). Specifically, the first insulating pattern (21) may overlap the first shading pattern (BML1) and the first semiconductor pattern (SP1). A portion of the first insulating pattern (21) that overlaps the channel (A1) of the first semiconductor pattern (SP1) corresponds to a gate insulating film (20T, see FIG. 5b), and a portion that overlaps the first shading pattern (BML1) other than the channel (A1) corresponds to a capacitor insulating film (20C, see FIG. 5b) and may function as a dielectric film of the capacitor. In the present embodiment, the gate insulating film (20T) and the capacitor insulating film (20C) are connected to each other and are illustrated as a first insulating pattern (21) having an integral shape, but this is not limited thereto, and the gate insulating film (20T) and the capacitor insulating film (20C) may be provided as separate patterns and are not limited to any one embodiment. Similarly, the second insulating pattern (22) may overlap the second light-shielding pattern (BML2) and the channel (A1) of the first semiconductor pattern (SP1) overlapping therewith. The third insulating pattern (23) may overlap the third light-shielding pattern (BML3) and the channel (A1) of the first semiconductor pattern (SP1) overlapping therewith.

[0200] The fourth insulating pattern (24) may be a pattern overlapping with the second semiconductor pattern (SP2). In the present embodiment, the fourth insulating pattern (24) may have an integral line shape overlapping with all of the plurality of second semiconductor patterns (SP2). The channels (A2) of the second semiconductor patterns (SP2) may overlap with one fourth insulating pattern (24).

[0201] The fifth insulating pattern (25) may be a pattern overlapping with the third semiconductor pattern (SP3). In the present embodiment, the fifth insulating pattern (25) may have an integral line shape overlapping with all of the plurality of third semiconductor patterns (SP3). The channels (A3) of the third semiconductor patterns (SP3) may overlap with one fifth insulating pattern (25).

[0202] A plurality of contact holes may be defined in the second insulating layer (20) to penetrate the second insulating layer (20) and expose a portion of the second conductive layer (MSL2). For example, a first gate contact hole (CNT-T1) may be formed in each of the first to third insulating patterns (21, 22, 23). The first gate contact hole (CNT-T1) may overlap with a protrusion protruding from a drain (D2) included in the second transistor (T2).

[0203] Meanwhile, this is merely an example, and the first to fifth insulating patterns (21, 22, 23, 24, 25) may be connected to each other. At this time, the second insulating layer (20) may be formed as a single layer, and the first gate contact hole (CNT-T1) may be formed in the second insulating layer (20). Alternatively, some of the first to fifth insulating patterns (21, 22, 23, 24, 25) may be connected to each other and some may have separate shapes, and the present invention is not limited to any one embodiment.

[0204] Meanwhile, a predetermined contact hole may be formed in the first to third insulating patterns (21, 22, 23). For example, the first gate contact hole (CNT-T1) may be formed in an area overlapping the second semiconductor patterns (SP2) among the first to third insulating patterns (21, 22, 23). The portions overlapping the first to third insulating patterns (21, 22, 23) may be portions of the drains (D2) of each of the second semiconductor patterns (SP2) that protrude toward the first to third light-shielding patterns (BML1, BML2, BML3). Therefore, the first gate contact hole (CNT-T1) exposes a portion of the drains (D2) of each of the second semiconductor patterns (SP2).

[0205] Referring to FIG. 6e, the second conductive layer (MSL2) can be disposed on the second insulating layer (20). Meanwhile, according to the present invention, after forming contact holes in the second insulating layer (20), the conductive layer formed on the second insulating layer (20) is patterned to form conductive patterns of the second conductive layer (MSL2). Thereafter, using the conductive patterns as a mask, the second insulating layer (20) illustrated in FIG. 6d can be patterned to include first to fifth insulating patterns (21, 22, 23, 24, 25). That is, the first to fifth insulating patterns (21, 22, 23, 24, 25) may be formed after the formation of the second conductive layer (MSL2). However, this is an example, and the second conductive layer (MSL2) may be formed after the first to fifth insulating patterns (21, 22, 23, 24, 25) are formed, and is not limited to any one embodiment.

[0206] Accordingly, in the present invention, the shape of the second insulating layer (20) on a plane may correspond to the shape of the conductive patterns included in the second conductive layer (MSL2), excluding the contact holes formed in the second insulating layer (20). In the present invention, the meaning of 'shape and correspondence' does not mean having the same area on a plane, and may include an error in the process. Meanwhile, this is illustrated as an example, and patterning of the second insulating layer (20) may be omitted after forming the third conductive layer (MSL3), and in this case, the second insulating layer (20) may be provided in a form that covers both the semiconductor pattern (SP) and the first insulating layer (10).

[0207] Referring again to FIG. 6e, the second conductive layer (MSL2) may include a sensing pattern (SS-P), a scan pattern (SC-P), and first to third gate conductive patterns (GML1, GML2, GML3).

[0208] The sensing pattern (SS-P) may extend along the second direction (DR2) and overlap with a plurality of third semiconductor patterns (SP3). The sensing pattern (SS-P) may overlap with the channel (A3) of each of the third semiconductor patterns (SP3) and may not overlap with the drain (D3) and the source (S3). The sensing pattern (SS-P) may form a gate of each of the third transistors (T3) illustrated in FIG. 5A and may correspond to the gate (GT) illustrated in FIG. 5B.

[0209] The scan pattern (SC-P) may extend along the second direction (DR2) and overlap with a plurality of second semiconductor patterns (SP2). The scan pattern (SC-P) may overlap with the channel (A2) of each of the second semiconductor patterns (SP2) and may not overlap with the drain (D2) and the source (S2). The scan pattern (SC-P) may form the gate of each of the second transistors (T2) illustrated in FIG. 5A.

[0210] The first to third gate conductive patterns (GML1, GML2, GML3) may be arranged to overlap the first to third light-shielding patterns (BML1, BML2, BML3), respectively. The first to third gate conductive patterns (GML1, GML2, GML3) may form capacitors with the first to third light-shielding patterns (BML1, BML2, BML3), respectively. Each of the first to third gate conductive patterns (GML1, GML2, GML3) may correspond to the upper conductive pattern (UPT) illustrated in FIG. 5b and may form one electrode of the capacitor (Cst) illustrated in FIG. 4b.

[0211] Meanwhile, some of the first to third gate conductive patterns (GML1, GML2, GML3) may overlap with the first semiconductor patterns (SP1). Each of the first to third gate conductive patterns (GML1, GML2, GML3) may overlap with the channel (A1) of each of the first semiconductor patterns (SP1) and may not overlap with the drain (D1) and the source (S1). A portion of the first to third gate conductive patterns (GML1, GML2, GML3) overlapping with the channel (A1) may form a gate of the first transistor (T1). This may correspond to the gate electrode (GT) illustrated in FIG. 5B. Meanwhile, other portions of the first to third gate conductive patterns (GML1, GML2, GML3) may overlap with the source (S2) of each of the second semiconductor patterns (SP2). The first to third gate conductive patterns (GML1, GML2, GML3) can each be connected to the second semiconductor pattern (SP2) through the first gate contact hole (CNT-T1).

[0212] According to the present invention, a reduction process of semiconductor patterns included in each of the first to third transistors (T1, T2, T3) can be performed using the second conductive layer (MSL2) as a mask. Accordingly, the source and drain of each of the semiconductor patterns (SP1, SP2, SP3) can be exposed from the sensing pattern (SS-P), the scan pattern (SC-P), and the first to third gate conductive patterns (GML1, GML2, GML3) to have greater conductivity compared to the channel. Meanwhile, the second insulating layer (20) can be patterned after the formation of the second conductive layer (MSL2) to be formed into a plurality of insulating patterns (21, 22, 23, 24, 25). That is, the insulating patterns (21, 22, 23, 24, 25) may be formed by patterning using the sensing pattern (SS-P), the scan pattern (SC-P), and the first to third gate conductive patterns (GML1, GML2, GML3) as masks. Meanwhile, this is illustrated as an example, and as described above, the second insulating layer (20) may be provided as an integrated layer in which the insulating patterns (21, 22, 23, 24, 25) are all connected without a patterning process, and is not limited to any one embodiment.

[0213] Referring to Fig. 6f, a third insulating layer (30) may be formed on the second conductive layer (MSL2). The third insulating layer (30) covers the second conductive layer (MSL2). Fig. 6f illustrates contact holes formed in the third insulating layer (30). A plurality of contact holes may be defined in the third insulating layer (30) that penetrate the third insulating layer (30) and expose a portion of the third conductive layer (MSL3).

[0214] The second initial contact holes (CNT-R2) may overlap with the first initial contact holes (CNT-R1) of the first insulating layer (10). The second initial contact holes (CNT-R2) and the first initial contact holes (CNT-R1) may expose a portion of the initial line (IL).

[0215] The second line contact hole (CNT-E2) may overlap with the first line contact hole (CNT-E1) of the first insulating layer (10). The first line contact hole (CNT-E1) and the second line contact hole (CNT-E2) may expose a portion of the power pattern (EBR).

[0216] The second-first power contact holes (CNT-P2) can overlap with the first-first power contact holes (CNT-P1). The second-first power contact holes (CNT-P2) and the first-first power contact holes (CNT-P1) can expose the power pattern (EBR). The second-second power contact holes (CNT-V2) can overlap with the first-second power contact holes (CNT-V1). The second-second power contact holes (CNT-V2) and the first-second power contact holes (CNT-V1) can expose a portion of the power pattern (EBR).

[0217] The second shading contact hole (CNT-B2) may overlap with the first shading contact hole (CNT-B1). The second shading contact hole (CNT-B2) may expose corresponding shading patterns (BML1, BML2, BML3). A contact hole defined by connecting the second shading contact hole (CNT-B2) and the first shading contact hole (CNT-B1) may correspond to the first contact hole (CH1, see FIG. 5b).

[0218] The second-first additional contact holes (CNT-A2) and the second-second additional contact holes (CNT-Q2) overlap with the first line (E-1). The second-first additional contact holes (CNT-A2) may overlap with the first-first additional contact holes (CNT-A1) of the first insulating layer (10), respectively. The second-second additional contact holes (CNT-Q2) may overlap with the first-second additional contact holes (CNT-Q1) of the first insulating layer (10), respectively. The contact holes defined by connecting the 2-1 additional contact holes (CNT-A2) and the 1-1 additional contact holes (CNT-A1) or the contact holes defined by connecting the 2-2 additional contact holes (CNT-Q2) and the 1-2 additional contact holes (CNT-Q1) may correspond to the 4th contact hole (CH4, see FIG. 5b).

[0219] The second-first semiconductor contact holes (CNT-21) may expose a portion of the source (S1) and the drain (D1) included in the first transistor (T1). A contact hole defined by overlapping with the source (S1) included in the first transistor (T1) among the second-first semiconductor contact holes (CNT-21) may correspond to a second contact hole (CH2, see FIG. 5b). A contact hole defined by overlapping with the drain (D1) included in the first transistor (T1) among the second-first semiconductor contact holes (CNT-21) may correspond to a third contact hole (CH3, see FIG. 5b).

[0220] The second-second semiconductor contact holes (CNT-22) may expose a portion of the source (S2) and the drain (D2) included in the second transistor (T2). The second-third semiconductor contact holes (CNT-23) may expose a portion of the source (S3) and the drain (D3) included in the third transistor (T3). The second gate contact hole (CNT-T2) may expose a portion of each of the gate conductive patterns (GML1, GML2, GML3).

[0221] The scan contact hole (CNT-C) can expose a portion of the scan pattern (SC-P). The sensing contact hole (CNT-S) can expose a portion of the sensing pattern (SS-P).

[0222] The second data contact holes (CNT-D2) may overlap with the first data contact holes (CNT-D1). The second data contact holes (CNT-D2) may expose a portion of a corresponding data line among the first to third data lines (DL1, DL2, DL3). Meanwhile, this is merely an example, and the number and positions of the contact holes formed in the third insulating layer (30) may vary and are not limited to any one embodiment.

[0223] Referring to FIG. 6g, a third conductive layer (MSL3) may be disposed on a third insulating layer (30). The third conductive layer (MSL3) may include a scan line (SCL), a sensing line (SSL), a first power line (ED), a first sub-pattern (CP1), a second sub-pattern (CP2), a sub-initial line (IL-S), a first additional power pattern (ED-S1), first to third source conductive patterns (SML1, SML2, SML3), and a second line (E-2) among the second power lines (EL). That is, each of the first conductive patterns described above (CPT1a, CPT1b, CPT1c, CPT1d, see FIG. 5b) may correspond to any one of the scan line (SCL), the sensing line (SSL), the first power line (ED), the first sub-pattern (CP1), the second sub-pattern (CP2), the sub-initial line (RL-S), the first additional power pattern (ED-S1), the first to third source conductive patterns (SML1, SML2, SML3), and the second line (E-2).

[0224] The second line (E-2) may overlap the first line (E-1) and extend in the second direction (DR2). The second line (E-2) may be arranged in the second-first additional contact holes (CNT-A2) and connected to the first line (E-1). The second line (E-2) may be connected to the first line (E-1) through the first-second additional contact holes (CNT-Q1) and the second-second additional contact holes (CNT-Q2). Among the second power lines (EL), the second line (E-2) may correspond to the third connection electrode (CPT1d, see FIG. 5b).

[0225] Each of the scan line (SCL), the sensing line (SSL), and the first power line (ED) extends in a first direction (DR1), and the scan line (SCL), the sensing line (SSL), and the first power line (ED) may be spaced apart in a second direction (DR2). The scan line (SCL) may be connected to the scan pattern (SC-P) through the scan contact hole (CNT-C). For convenience of explanation, FIG. 6g illustrates that the scan line (SCL) arranged at the top is connected to the scan pattern (SC-P) through the scan contact hole (CNT-C), and the overlapping of the scan line (SCL) arranged at the bottom with the scan pattern (SC-P) is omitted. However, the connection relationship between the scan line (SCL) arranged at the bottom and the scan pattern (SC-P) may be the same as the connection relationship between the scan line (SCL) and the scan pattern (SC-P) at the top.

[0226] The sensing line (SSL) can be connected to the sensing pattern (SS-P) through the sensing contact hole (CNT-S).

[0227] The first power line (ED) can intersect the power pattern (EBR) in a plane. The first power line (ED) can be connected to the power pattern (EBR) through the second line contact hole (CNT-E2) and the first line contact hole (CNT-E1).

[0228] The first additional power pattern (ED-S1) may be individually provided to each pixel. A portion of the first additional power pattern (ED-S1) that overlaps with the power pattern (EBR) may be arranged in the second-first power contact holes (CNT-P2) and connected to the power pattern (EBR). The first additional power pattern (ED-S1) may correspond to the second connection electrode (CPT1b) described above.

[0229] In addition, a portion of the first additional power pattern (ED-S1) that overlaps with the first semiconductor pattern (S1) may be placed in a contact hole that overlaps with the drain (D1) of the first transistor (T1) among the second-first semiconductor contact holes (CNT-21) and may be connected to the first transistor (T1).

[0230] The first to third source conductive patterns (SML1, SML2, SML3) are arranged spaced apart from each other along the second direction (DR2). The first to third source conductive patterns (SML1, SML2, SML3) may be arranged to overlap the first to third light-shielding patterns (BML1, BML2, BML3), respectively.

[0231] A portion of each of the first to third source conductive patterns (SML1, SML2, SML3) may be arranged in a first shading contact hole (CNT-B1) and a second shading contact hole (CNT-B2) and connected to a corresponding shading pattern. Another portion of each of the first to third source conductive patterns (SML1, SML2, SML3) may be arranged in a contact hole overlapping with a source (S1) of a first transistor (T1) among the second-first semiconductor contact holes (CNT-21) and connected to the first transistor (T1). Accordingly, each of the first to third source conductive patterns (SML1, SML2, SML3) may correspond to the first connection electrode (CPT1a, see FIG. 5b) described above, and the contact hole overlapping with the source (S1) of the first transistor (T1) among the second-first semiconductor contact holes (CNT-21) may correspond to the second contact hole (CH2, see FIG. 5b).

[0232] Another portion of each of the first to third source conductive patterns (SML1, SML2, SML3) may extend to the drain (D3) of the third transistor (T3). Each of the first to third source conductive patterns (SML1, SML2, SML3) may be arranged in a contact hole overlapping the drain (D3) among the second to third semiconductor contact holes (CNT-23) to connect the first transistor (T1) and the third transistor (T3).

[0233] In addition, the first to third source conductive patterns (SML1, SML2, SML3) may be arranged to overlap the first to third gate conductive patterns (GML1, GML2, GML3, see FIG. 6e), respectively. Another portion of each of the first to third source conductive patterns (SML1, SML2, SML3) may correspond to the first pattern (CPT1c, see FIG. 5b) described above. That is, the first pattern (CPT1c, see FIG. 5b) may have an integral shape connected to the second connection electrode (CPT1b). However, this is merely an example, and the first pattern (CPT1c) may be a conductive pattern other than the first to third source conductive patterns (SML1, SML2, SML3) and is not limited to any one embodiment.

[0234] The first sub-pattern (CP1) can connect a corresponding data line among the data lines (DL1, DL2, DL3) and the second transistor (T2). One end of the first sub-pattern (CP1) may overlap with the drain (D2) of the second transistor (T2) and may be arranged in a contact hole that overlaps with the drain (D2) of the second transistor (T2) among the 2-2 semiconductor contact holes (CNT-22). The other end of the first sub-pattern (CP1) may extend to the corresponding data line and may be arranged in the first data contact hole (CNT-D1) and the second data contact hole (CNT-D2) to be connected to the corresponding data line. Therefore, the second transistor (T2) and the data line may be connected through the first sub-pattern (CP1).

[0235] One end of the second sub-pattern (CP2) may overlap with the source (S2) of the second transistor (T2) and may be arranged in a contact hole that overlaps with the source (S2) of the second transistor (T2) among the second-second semiconductor contact holes (CNT-22). The other end of the second sub-pattern (CP2) may overlap with each of the gate conductive patterns (GML1, GML2, GML3) and may be arranged in the second gate contact hole (CNT-T2). Therefore, the second transistor (T2) and the first transistor (T1) may be connected through the second sub-pattern (CP2).

[0236] The sub-initial line (RL-S) can overlap with the initial line (IL). The sub-initial line (RL-S) can be connected to the initial line (IL) through the first and second initial contact holes (CNT-R1, CNT-R2).

[0237] In the present embodiment, the conductive patterns included in the third conductive layer (MSL3) may be provided in multiple layers. For example, the third conductive layer (MSL3) may be provided as a two-layer metal layer laminated with titanium (Ti) / copper (Cu), or as a three-layer metal layer laminated with titanium (Ti) / aluminum (Al) / titanium (Ti).

[0238] Referring to FIG. 6h, a first inorganic layer (40) may be formed on a third conductive layer (MSL3). FIG. 6h illustrates contact holes formed in the first inorganic layer (40). The first inorganic layer (40) is disposed on the first insulating layer (30) and covers the third conductive layer (MSL3). A plurality of contact holes may be defined in the first inorganic layer (40) that penetrate the first inorganic layer (40) and expose a portion of the fourth conductive layer (MSL4).

[0239] The first via contact hole (EL-H1) may expose a portion of the second line (E-2). The first via contact hole (EL-H1) may correspond to a portion of the sixth contact hole (CH6, see FIG. 5b) described above. The first anode contact hole (EL-S1) may expose a portion of each of the source conductive patterns (SML1, SML2, SML3). The first anode contact hole (EL-S1) may correspond to a portion of the fifth contact hole (CH5, see FIG. 5b) described above.

[0240] The third-first power contact holes (CNT-P3) are arranged to overlap with the first additional power patterns (ED-S1). The third-first power contact holes (CNT-P3) may expose a portion of the corresponding first additional power pattern (ED-S1).

[0241] Referring to Fig. 6i, a first organic layer (50) is formed on a first inorganic layer (40). Fig. 6i illustrates contact holes formed in the first organic layer (50). A plurality of contact holes may be defined in the first organic layer (50) that penetrate the first organic layer (50) and overlap with the contact holes defined in the first inorganic layer (40).

[0242] The second via contact hole (EL-H2) may overlap with the first via contact hole (EL-H1). The area of ​​the second via contact hole (EL-H2) may be larger than the area of ​​the first via contact hole (EL-H1). The first via contact hole (EL-H1) and the second via contact hole (EL-H2) may expose a portion of the second line (E-2) of the first power line (ED). That is, the first via contact hole (EL-H1) and the second via contact hole (EL-H2) may be connected to each other to form a sixth contact hole (CH6, see FIG. 5b).

[0243] The second anode contact hole (EL-S2) may overlap with the first anode contact hole (EL-S1). The first anode contact hole (EL-S1) and the second anode contact hole (EL-S2) may expose a portion of each of the source conductive patterns (SML1, SML2, SML3). The second anode contact hole (EL-S2) may be connected to the first anode contact hole (EL-S1) to form the fifth contact hole (CH5, see FIG. 5b) described above.

[0244] The 4-1 power contact holes (CNT-P4) can overlap with the 3-1 power contact holes (CNT-P3). The 4-1 power contact holes (CNT-P4) can be connected to the 3-1 power contact holes (CNT-P3) to expose the corresponding first additional power patterns (ED-S1).

[0245] Meanwhile, according to one embodiment of the present invention, the first inorganic layer (40) may be omitted. Accordingly, the first inorganic layer (40) and the first organic layer (50) are provided as one insulating layer, and the contact holes defined in the first inorganic layer (40) and the contact holes defined in the first organic layer (50) described above may be defined in one insulating layer, and are not limited to any one embodiment.

[0246] Referring to FIG. 6j, a fourth conductive layer (MSL4) may be formed on the first organic layer (50). The fourth conductive layer (MSL4) may include first to third additional conductive patterns (MP1, MP2, MP3), second additional power patterns (ED-S2), and a third line (E-3).

[0247] The first to third additional challenge patterns (MP1, MP2, MP3) are arranged spaced apart from each other along the second direction (DR2). The first to third additional challenge patterns (MP1, MP2, MP3) may be arranged to overlap the first to third source challenge patterns (SML1, SML2, SML3), respectively.

[0248] Each of the first to third additional conductive patterns (MP1, MP2, MP3) can overlap with the second anode contact hole (EL-S2). Each of the first to third additional conductive patterns (MP1, MP2, MP3) is connected to a corresponding source conductive pattern among the first to third source conductive patterns (SML1, SML2, SML3) through the second anode contact hole (EL-S2) and the first anode contact hole (EL-S1). Therefore, each of the first to third additional conductive patterns (MP1, MP2, MP3) can correspond to the fourth connection electrode (CPT2a) described above.

[0249] The second additional power patterns (ED-S2) are arranged spaced apart from each other along the second direction (DR2). The second additional power patterns (ED-S2) may be arranged to overlap the first additional power patterns (ED-S1), respectively. Each of the second additional power patterns (ED-S2) may be connected to each of the first additional power patterns (ED-S1) through the 4-1 power contact holes (CNT-P4) and the 3-1 power contact holes (CNT-P3).

[0250] The third line (E-3) may have a bar shape having a length extending along the second direction (DR2), but is not limited thereto. The third line (E-3) may be arranged to overlap the second line (E-2). The third line (E-3) may be connected to the second line (E-2) through the second via contact hole (EL-H2) and the first via contact hole (EL-H1). Therefore, the third line (E-3) may correspond to the fifth connection electrode (CPT2c) described above.

[0251] Referring to FIG. 6k, a second inorganic layer (60) is formed on the first organic layer (50). The second inorganic layer (60) can cover the fourth conductive layer (MSL4). Specifically, the second inorganic layer (60) can cover each of the plurality of conductive patterns (MP1, MP2, MP3, E-3, ED-S) constituting the fourth conductive layer (MSL4). FIG. 6k illustrates contact holes (EL-S3, EL-H3) and openings (HH) formed in the second inorganic layer (60).

[0252] The contact holes (EL-S3, EL-H3) penetrate the second inorganic layer (60) and expose the fourth conductive layer (MSL4). Specifically, the third anode contact hole (EL-S3) may overlap with a corresponding conductive pattern among the first to third additional conductive patterns (MP1, MP2, MP3). The third anode contact hole (EL-S3) exposes a portion of a corresponding conductive pattern among the first to third additional conductive patterns (MP1, MP2, MP3). The third anode contact hole (EL-S3) may correspond to a portion of the seventh contact hole (CH7, see FIG. 5b) described above. The third via contact hole (EL-H3) may overlap with the third line (E-3). The third via contact hole (EL-H3) exposes a portion of the third line (E-3). The third via contact hole (EL-H3) may correspond to a part of the eighth contact hole (CH8, see FIG. 5b) described above.

[0253] The openings (HH) penetrate the second inorganic layer (60) and expose the first organic layer (50). The openings (HH) are defined spaced apart from the contact holes (EL-S3, EL-H3) on a plane. In addition, the openings (HH) may be defined in an area that does not overlap on a plane with a plurality of conductive patterns (MP1, MP2, MP3, E-3, ED-S) constituting the fourth conductive layer (MSL4). In the present embodiment, the openings (HH) may include a first opening (HH1) and a second opening (HH2).

[0254] The first opening (HH1) may be provided in multiple numbers and arranged in an area between additional conductive patterns (MP1, MP2, MP3) of the fourth conductive layer (MSL4) and the third line (E-3). The second opening (HH2) may be provided in multiple numbers and arranged in an area between the second additional power patterns (ED-S2) and another third line (E-3). The first opening (HH1) is illustrated as having a smaller area than the second opening (HH2). However, this is illustrated as an example, and the first opening (HH1) may have an area equal to or larger than that of the second opening (HH2). In addition, the number of the first opening (HH1) or the second opening (HH2) may be variously changed.

[0255] In the present invention, by forming an opening (HH) including a first opening (HH1) and a second opening (HH2) in the second inorganic layer (60), gas or moisture that may be generated from the organic layer (50) can smoothly escape. Accordingly, lifting or peeling of the second inorganic layer (60) can be prevented, and the display panel process reliability can be improved. As the area occupied by the opening (HH) in the second inorganic layer (60) increases, gas discharge from the organic layer (50) can be easily achieved. However, as the area occupied by the opening (HH) in the second inorganic layer (60) increases, restrictions are placed on the arrangement of conductive patterns or elements constituting the pixel driving circuit, which may affect the pixel design. According to the present invention, the ratio occupied by the opening (HH) in the layer in which the opening (HH) is formed can be designed to be 30% or less based on the display area (DA). Specifically, within the display area (DA), the area of ​​the entire opening (HH) on the plane relative to the area of ​​the second inorganic layer (60) on the plane may be 30% or less. Accordingly, the reliability of the display panel is improved, while a high-resolution display panel can be stably designed.

[0256] Meanwhile, the opening (HH) may have a single shape or various shapes on a planar surface, such as a circular shape, an oval shape, an irregular shape, etc., as long as it penetrates the second inorganic layer (60) to expose the first organic layer (50) and can non-overlap with the conductive patterns constituting the fourth conductive layer (MSL4) on a plane, and is not limited to any one embodiment. In addition, the opening (HH) may be defined at various positions as long as it can non-overlap with the conductive patterns constituting the fourth conductive layer (MSL4) on a plane, and is not limited to any one embodiment.

[0257] Referring to FIG. 6l, a second organic layer (70) is disposed on a second inorganic layer (60). The second organic layer (70) can cover the second inorganic layer (60). FIG. 6l illustrates contact holes formed in the second organic layer (70).

[0258] Specifically, the first to third connection contact holes (70-OP1, 70-OP2, 70-OP3) can be defined to overlap the first to third additional conductive patterns (MP1, MP2, MP3). In addition, each of the first to third connection contact holes (70-OP1, 70-OP2, 70-OP3) can overlap the third anode contact hole (EL-S3). The first to third connection contact holes (70-OP1, 70-OP2, 70-OP3) are connected to the third anode contact hole (EL-S3) to expose the first to third additional conductive patterns (MP1, MP2, MP3), respectively. Each of the first to third connection contact holes (70-OP1, 70-OP2, 70-OP3) can be connected to the third anode contact hole (EL-S3) to form the seventh contact hole (CH7, see FIG. 5b) described above.

[0259] The fourth connection contact hole (70-OP4) may be defined to overlap with the third line (E-3). In addition, the fourth connection contact hole (70-OP4) may overlap with the third via contact hole (EL-H3). The fourth connection contact hole (70-OP4) is connected to the third via contact hole (EL-H3) to expose the third line (E-3). The fourth connection contact hole (70-OP4) may be connected to the third via contact hole (EL-H3) to form the above-described eighth contact hole (CH8, see FIG. 5b).

[0260] Meanwhile, the second organic layer (70) may overlap with the openings (HH) on a plane. The second organic layer (70) may be in contact with the first organic layer (50) exposed through the openings (HH). That is, the contact holes (EL-S3, EL-H3) penetrating the first inorganic layer (60) may be exposed by the contact holes (70-OP1, 70-OP2, 70-OP3, 70-OP4) penetrating the second organic layer (70), and the openings (HH) penetrating the first inorganic layer (60) may be filled by the second organic layer (70).

[0261] Referring to Fig. 6m, a pixel electrode layer (AEL) may be formed on the second organic layer (70). Fig. 6m illustrates first electrodes (AE1, AE2, AE3) and auxiliary electrodes (AXE) included in each light-emitting element (OLED) of pixels. The first electrodes (AE1, AE2, AE3) and auxiliary electrodes (AXE) may be spaced apart from each other and disposed on the second organic layer (70).

[0262] The first electrodes (AE1, AE2, AE3) may be arranged to overlap the first to third connection contact holes (70-OP1, 70-OP2, 70-OP3). The first electrodes (AE1, AE2, AE3) may be connected to the first to third additional conductive patterns (MP1, MP2, MP3) exposed through the first to third connection contact holes (70-OP1, 70-OP2, 70-OP3) and the corresponding third anode contact hole (EL-S3), respectively.

[0263] The areas of the first electrodes (AE1, AE2, AE3) included in each of the pixels providing different light may be different from each other. For example, the area of ​​the first electrode (AE2) included in the pixel providing the second color light may be smaller than the area of ​​the first electrode (AE1) included in the pixel providing the first color light, and may be larger than the area of ​​the first electrode (AE3) included in the pixel providing the third color light. However, the present invention is not limited thereto, and the areas of the first electrodes (AE1, AE2, AE3) may be the same as each other, or may have a different size from the above-described ones. The color of the light provided according to the areas of the first electrodes (AE1, AE2, AE3) may vary depending on the quality of the pixel, and is not limited to any one embodiment.

[0264] The auxiliary electrode (AXE) may overlap with the fourth connection contact hole (70-OP4). The auxiliary electrode (AXE) may be connected to the third line (E-3) through the fourth connection contact hole (70-OP4) and the third via contact hole (EL-H3). Accordingly, the auxiliary electrode (AXE) may be connected to the second power line (EL, see FIG. 4b) through the third line (E-3) to receive the second voltage (ELVSS).

[0265] Meanwhile, in one embodiment of the present invention, the pixel electrode layer (AEL) may further include an additional conductive pattern spaced apart from the first electrodes (AE1, AE2, AE3) and the auxiliary electrode (AXE). Alternatively, in the pixel electrode layer (AEL), the auxiliary electrode (AXE) may be omitted. The display panel according to one embodiment of the present invention may include a pixel electrode layer (AEL) having various structures, and is not limited to any one embodiment.

[0266]

[0267] Fig. 7a is a cross-sectional view illustrating a portion of a display panel according to a comparative embodiment of the present invention. Fig. 7b is a cross-sectional view illustrating a portion of a display panel according to an embodiment of the present invention. Fig. 7b illustrates a first organic layer (50) and a second inorganic layer (60), and Fig. 7a illustrates a laminated structure (50, 60-C) of a comparative embodiment in an area corresponding to Fig. 7b. Hereinafter, the present invention will be described with reference to Figs. 7a and 7b. Meanwhile, the same reference numerals are given to the same components as those described in Figs. 1 to 6m, and redundant descriptions are omitted.

[0268] Referring to FIGS. 7A and 7B, the comparative example may include an organic layer (50) and an inorganic layer (60-C) disposed on the organic layer (50). The organic layer (50) may correspond to the first organic layer (50) of the present invention. The inorganic layer (60-C) may correspond to the second inorganic layer (60) of the present invention, but may have a structure in which an opening (HH) is not formed.

[0269] Referring to Fig. 7a, in a comparative example, when forming an organic layer (50), moisture or gas (GS1, GS2, hereinafter referred to as gas) may be generated within the organic layer (50). Gases (GS1, GS2) may be continuously generated during the process. Some of the gases (GS1, GS2) existing within the organic layer (50) may escape to the outside of the organic layer (50). At this time, the inorganic layer (60-C) covering the organic layer (50) may be lifted or cracked due to the gases (GS1, GS2). The relatively brittle inorganic layer (60-C) may be damaged due to this.

[0270] Referring to FIG. 7b, in one embodiment of the present invention, a predetermined opening (HH) may be formed in the second inorganic layer (60). The opening (HH) may penetrate the second inorganic layer (60) to expose the upper surface of the first organic layer (50). Gases (GS1, GS2) existing in the first organic layer (50) may escape to the outside of the first organic layer (50) through the opening (HH). Accordingly, the gases (GS1, GS2) may smoothly escape from the first organic layer (50) without lifting or damaging the second inorganic layer (60). Although not shown, the gas (GS1, GS2) that escapes through the opening (HH) may be transferred to the second organic layer (70, see FIG. 5b) that contacts the first organic layer (50) through the opening (HH) and may remain within the second organic layer (70) or escape to the outside through the second organic layer (70).

[0271] According to the present invention, by forming a predetermined opening (HH) in the inorganic layer (60) covering the upper surface of the organic layer (50), an outflow path for gases or moisture that may be generated from the organic layer (50) can be provided. Accordingly, gases present in the organic layer (50) can smoothly escape, thereby improving the reliability of the display panel process.

[0272]

[0273] FIGS. 8A to 8C are cross-sectional views of a display panel according to an embodiment of the present invention. FIGS. 8A to 8C illustrate a light-emitting area (PXA) and a non-light-emitting area (NPXA). Hereinafter, the present invention will be described with reference to FIGS. 8A to 8C. Hereinafter, the same reference numerals will be given to the same components as those described in FIGS. 1 to 7B, and duplicate descriptions will be omitted.

[0274] Referring to FIGS. 8A to 8C, the display panel may include pads (PDP, PDP-A, PDP-B) arranged in a non-emitting area (NPXA). The pads (PDP, PDP-A, PDP-B) may be portions electrically connected to an external circuit board.

[0275] Referring to FIG. 8a, the pad (PDP) may be formed simultaneously with the second conductive patterns (CPT2a, CPT2b). That is, the pad (PDP) may have the same layer structure as the second conductive patterns (CPT2a, CPT2b). In the present embodiment, the pad (PDP) may have a laminated structure including a first sub-layer (Md1), a second sub-layer (Md2), and a third sub-layer (Md3). According to the present invention, since the pad (PDP) is formed simultaneously with the second conductive patterns (CPT2a, CPT2b), a separate process for forming the pad (PDP) may not be added, thereby reducing the process cost and simplifying the process.

[0276] The pad (PDP) may be disposed on the first inorganic layer (40). Meanwhile, the first organic layer (50) may be disposed within the light-emitting area (PXA) and may not extend to the non-light-emitting area (NPXA). The second inorganic layer (60) may be formed to overlap both the light-emitting area (PXA) and the non-light-emitting area (NPXA). Accordingly, the pad (PDP) may be disposed between the first inorganic layer (40) and the second inorganic layer (50) in the non-light-emitting area (NPXA).

[0277] A pad opening (HH-P) exposing at least a portion of the pad (PDP) may be defined in the second inorganic layer (50). The pad (PDP) is exposed to the outside through the pad opening (HH-P) and can be easily electrically connected to an external circuit board. When the external circuit board and the display panel are connected, a lead of the external circuit board may be placed in the pad opening (HH-P) or a conductive connecting member may be filled.

[0278] According to the present invention, the pad opening (HH-P) can be formed simultaneously with the opening (HH) of the second inorganic layer (50). By forming the pad opening (HH-P) and the opening (HH) simultaneously through a single process, an additional process for forming the opening (HH) becomes unnecessary. Accordingly, a passage through which gas generated from the first organic layer (50) can be removed can be easily formed without a separate additional process, thereby simplifying the process, reducing process costs, and improving process reliability.

[0279] Alternatively, as illustrated in FIG. 8b, the pad (PDP-A) may be formed simultaneously with the first conductive patterns (CPT1a, CPT1b, CPT1c). That is, the pad (PDP-A) may have the same layer structure as the first conductive patterns (CPT1a, CPT1b, CPT1c). That is, in the present embodiment, the pad (PDP-A) may have a laminated structure including a first sub-layer (Mc1), a second sub-layer (Mc2), and a third sub-layer (Mc3). According to the present invention, since the pad (PDP-A) is formed simultaneously with the first conductive patterns (CPT1a, CPT1b, CPT1c), a separate process for forming the pad (PDP-A) may not be added, thereby reducing the process cost and simplifying the process.

[0280] The pad (PDP-A) may be disposed on the third insulating layer (30). Meanwhile, the first organic layer (50) and the second organic layer (70) may not extend to the non-emissive region (NPXA). The first inorganic layer (40) and the second inorganic layer (60) may be formed to overlap both the emissive region (PXA) and the non-emissive region (NPXA). Accordingly, the pad (PDP-A) may be disposed between the third insulating layer (30) and the first inorganic layer (40) in the non-emissive region (NPXA).

[0281] A pad opening (PD-OP) exposing at least a portion of the pad (PDP-A) is formed through the first inorganic layer (40) and exposes the upper surface of the pad (PDP-A). The second inorganic layer (60) exposes at least a portion of the pad (PDP-A) and may not extend to the pad opening (PD-OP). That is, the second inorganic layer (60) may not overlap the pad opening (PD-OP) in a plane.

[0282] According to the present invention, since the pad (PDP-A) is formed simultaneously with the first conductive patterns (CPT1a, CPT1b, CPT1c), an electrical inspection of the panel (DP) can be performed when the first conductive patterns (CPT1a, CPT1b, CPT1c) are formed. In addition, repair of the display panel (DP) can be performed before the second conductive patterns (CPT2a, CPT2b) are formed, so that repair of elements covered by the second conductive patterns (CPT2a, CPT2b) formed thereafter can be easily performed.

[0283] Alternatively, as illustrated in FIG. 8c, the pad opening (PD-OP) may be defined by penetrating the first inorganic layer (40) and the second inorganic layer (60). That is, the pad opening (PD-OP) may be formed by connecting a first opening (H-P1) penetrating the first inorganic layer (40) and a second opening (H-P2) penetrating the second inorganic layer (60).

[0284] The first opening (H-P1) and the second opening (H-P2) can be formed continuously. According to the present invention, the pad (PDP-B) can be covered by the first inorganic layer (40) while the first inorganic layer (40) is patterned. That is, the pad (PDP-B) can be covered and protected by the first inorganic layer (40) at the stage where the fifth contact hole (CH5) is formed. Accordingly, damage to the pad (PDP-B) can be prevented while the first inorganic layer (40) is patterned.

[0285] When the opening (HH) of the second inorganic layer (60) is formed, the first opening (H-P1) may be formed simultaneously. After the first inorganic layer (40) and the second inorganic layer (60) are formed to extend to the non-emitting area (NPXA), the first inorganic layer (40) disposed underneath may also be continuously patterned to form the second opening (H-P2). That is, even after the opening (HH) of the second inorganic layer (60) is formed, the etching process may continue to form the second opening (H-P2) in the first inorganic layer (40). Accordingly, the thickness of the third sub-layer (Mc3) constituting the pad (PDP-B) may be greater than the thickness of the third sub-layer (Md3) of the second conductive patterns (CPT2a, CPT2b) disposed in the emitting area (PXA). The third sub-layer (Md3) of the second conductive patterns (CPT2a, CPT2b) arranged in the light-emitting area (PXA) may be exposed to an etching process until the first inorganic layer (40) is further etched to form the second opening (H-P2), even if it is exposed from the second inorganic layer (60). Accordingly, a portion of the third sub-layer (Md3) of the second conductive patterns (CPT2a, CPT2b) may be damaged.

[0286] According to the present invention, by forming the pad opening (PD-OP) and the opening (HH) through a single process, a passage through which gas generated from the first organic layer (50) can be removed can be easily formed without adding a separate process. In addition, even if the position of the pad (PDP-A) is changed, the pad opening (PD-OP) can be easily formed without changing or adding a process. Meanwhile, this is described as an example, and the pad opening (HH-P, PD-OP) according to an embodiment of the present invention may be formed through a separate process from the opening (HH) forming process, and is not limited to any one embodiment.

[0287]

[0288] Figures 9a to 9d are plan views illustrating portions of a display panel according to one embodiment of the present invention. For ease of explanation, some components are omitted in Figures 9a to 9d. The present invention will now be described with reference to Figures 9a to 9d.

[0289] As illustrated in FIG. 9a, the non-emissive area (NPXA) may include a connection area (PAD_O) and an inspection area (PAD_F). The connection area (PAD_O) may be an area that is relatively closer to the emissive area (PXA, see FIG. 8a), and the inspection area (PAD_F) may be an area that is relatively closer to the edge of the display panel.

[0290] The first conductive layer (MSL-L1) may include a plurality of main signal lines (SL_M) and a plurality of sub signal lines (SL_T). In the present embodiment, the first conductive layer (MSL-L1) may be a layer formed simultaneously with the lower conductive patterns (LPT1, LPT2, LPT3) of FIG. 5B and may correspond to the first conductive layer (MSL1) illustrated in FIG. 6A.

[0291] A plurality of main signal lines (SL_M) and sub signal lines (SL_T) may be arranged in the connection area (PAD_O). The main signal lines (SL_M) may be extended lines connected to pixels or gate driving circuits arranged in the display area. Each of the main signal lines (SL_M) may include a line portion (LP_M) and a pad portion (PP_M). The pad portion (PP_M) may be defined at the end of the line portion.

[0292] The pad portion (PP_M) may be a portion to which other components are connected. The width of the pad portion (PP_M) in the first direction may be relatively larger than the width of the line portion (LP_M) in the first direction. Accordingly, the contact area with other components may increase, thereby improving connection reliability. However, this is merely an example, and the pad portion (PP_M) and the line portion (LP_M) may have the same width and are not limited to any one embodiment.

[0293] The pad portion (PP_M) and the line portion (LP_M) may have an integral shape that is connected to each other. That is, the pad portion and the line portion may be simultaneously patterned and formed using a single mask. However, this is merely an example, and the pad portion (PP_M) and the line portion (LP_M) may be formed spaced apart from each other but connected to each other using separate bridge patterns, or may be formed on different layers or formed simultaneously through different processes, and the present invention is not limited to any one embodiment.

[0294] The sub-signal lines (SL_T) are arranged spaced apart from the main signal lines (SL_M) in a second direction (DR2). The sub-signal lines (SL_T) may be arranged across a connection area (PAD_O) and a test area (PAD_F). Each of the sub-signal lines (SL_T) may include a line portion (LL), a first end (E1), and a second end (E2). The line portion (LL) extends along the second direction (DR2). The first end (E1) is arranged on a side of the line portion (LL) facing the pad portion (PP_M). The first end (E1) may be arranged in the pad area (PAD_O).

[0295] The second end (E2) is positioned on the other side of the pad portion (PP_M) facing the edge of the panel. The second end (E2) may be positioned in the inspection area (PAD_F).

[0296] The first end (E1) and the second end (E2) may be portions to which other components are connected. The width of each of the first end (E1) and the second end (E2) in the first direction (DR1) may be greater than the width of the line portion (LL) in the first direction (DR1). Accordingly, the contact area with other components may increase, thereby improving connection reliability. However, this is merely an example, and the first end (E1) and the second end (E2) may have the same width as the line portion (LL) and are not limited to any one embodiment.

[0297] Meanwhile, some of the sub-signal lines (SL_T) may include a second end (E2L) having a relatively large area. The second end (E2L) having a large area may be positioned closest to the edge of the display panel among the second ends. Hereinafter, the second end (E2L) having a large area substantially corresponds to the remaining second ends (E2) except for its large area, so a redundant description thereof will be omitted.

[0298] The line portion (LL), the first end portion (E1), and the second end portion (E2, E2L) may have an integral shape that is connected to each other. That is, the line portion (LL), the first end portion (E1), and the second end portion (E2) may be simultaneously patterned and formed through one mask. However, this is merely an example, and the line portion (LL), the first end portion (E1), and the second end portion (E2) may be formed spaced apart from each other but connected to each other through separate bridge patterns, or may be formed on different layers or formed simultaneously through different processes, and are not limited to any one embodiment.

[0299] Referring to Fig. 9b, a first insulating layer (ISL1) may be formed on the first conductive layer (MSL-L). Fig. 9b illustrates a plurality of contact holes (CH_M, CH_T1, CH_T2) formed in the first insulating layer (ISL1). The first insulating layer (ISL1) may correspond to the third insulating layer (30, see Figs. 5b and 6f) described above. Accordingly, the contact holes (CH_M, CH_T1, CH_T2) may be formed simultaneously with the contact holes illustrated in Fig. 6f, but are not limited thereto.

[0300] The first main contact hole (CH_M) may be formed to overlap with the pad portion (PP_M). The first main contact hole (CH_M) exposes at least a portion of the pad portion (PP_M).

[0301] The first sub-contact hole (CH_T1) may be formed to overlap the first end portion (E1). The first sub-contact hole (CH_T1) exposes at least a portion of the first end portion (E1).

[0302] The second sub-contact hole (CH_T2) may be formed to overlap the second end portion (E2, E2L). The second sub-contact hole (CH_T2) exposes at least a portion of the second end portion (E2, E2L). Meanwhile, the second sub-contact hole (CH_T2) may be provided in multiple numbers to correspond to the second end portion (E2L) with a large area.

[0303] Referring to FIG. 9c, a second conductive layer (MSL-L2) may be formed on a first insulating layer (ISL1). The second conductive layer (MSL-L2) may be formed simultaneously with the first conductive patterns (CPT1a, CPT1b, CPT1c, CPT1d) of FIG. 5b. The second conductive layer (MSL-L2) may correspond to the third conductive layer (MSL3) illustrated in FIG. 6g. The second conductive layer (MSL-L2) may include a pad (PDP), a sub-line (TL), and a sub-pad (TP).

[0304] A plurality of pads (PDPs) may be provided and arranged spaced apart from each other along a first direction (DR1). Each pad (PDP) connects a main signal line (SL_M) and a sub signal line (SL_T) spaced apart from each other in a second direction (DR2). One side of the pad (PDP) overlaps with the pad portion (PP_M) and is connected to the pad portion (PP_M) through a first main contact hole (CH_M). The other side of the pad (PDP) overlaps with the first end (E1) and is connected to the first end (E1) through a first sub contact hole (CH_T1).

[0305] A sub-line (TL) extends along a first direction (DR1). A plurality of sub-lines (TL) may be provided and arranged spaced apart from each other along a second direction (DR2). Each sub-line (TL) may overlap each second end (E2). Each sub-line (TL) is connected to a corresponding second end (E2) through a second sub-contact hole (CH_T2).

[0306] The sub pad (TP) is arranged to overlap with the second end (E2L) having a large area. The sub pad (TP) may be provided with an area larger than the second end (E2L) having a large area. The sub pad (TP) may be connected to the sub signal line (SL_T) through a plurality of second sub contact holes overlapping the second end (E2L) having a large area.

[0307] According to the present invention, electrical connection between the sub pad (TP) and the sub line (TL) and the main signal lines (SL_M) can be established when forming the third conductive layer (MSL3). Therefore, before forming the first inorganic layer (40, see FIGS. 5b and 6h) that is performed thereafter, electrical inspection can be performed on pixels connected to the signal lines (SL_M) through the sub pad (TP) or the sub line (TL). In addition, even if a defect occurs through the electrical inspection, immediate repair can be easily performed. Therefore, according to the present invention, electrical inspection of the display panel can be easily performed during the process, so that the electrical reliability of the display panel and the process reliability can be improved.

[0308] Referring to Fig. 9d, a second insulating layer (ISL2) may be formed on the second conductive layer (MSL-L2). The second insulating layer (ISL2) may correspond to the second inorganic layer (60, see Fig. 5b) illustrated in Fig. 5b. Fig. 9d illustrates openings (OP_IM, OP_IP) defined in the second insulating layer (ISL2).

[0309] The pad opening (OP_IM) may be formed to overlap the pad (PDP). The pad opening (OP_IM) exposes at least a portion of the pad (PDP). The pad opening (OP_IM) may correspond to the pad opening (HH-P) illustrated in FIG. 8A. That is, the pad (PDP) and an external circuit board may be electrically connected through the pad opening (OP_IM).

[0310] The sub-aperture (OP_IP) may be formed to overlap with the sub-pad (TP). The sub-aperture (OP_IP) exposes at least a portion of the sub-pad (TP). The sub-aperture (OP_IP) may be an area where the sub-pad (TP) and an external inspection device are electrically connected. According to the present invention, by providing the sub-aperture (OP_IP) with a relatively large area compared to the pad opening (OP_IM), a tip portion or the like of the inspection device can be easily connected to the sub-pad (TP).

[0311] Meanwhile, the sub-aperture (OP_IP) can be formed simultaneously with the pad opening (OP_IM). In addition, the sub-aperture (OP_IP) can be formed simultaneously with the above-described opening (HH, see FIG. 5b) by forming the pad opening (OP_IM) in the second inorganic layer (60). According to the present invention, by forming the inspection pad, the connection pad, and the hole for gas discharge simultaneously, the process can be simplified and the process cost can be reduced.

[0312]

[0313] FIGS. 10A to 10F are plan views illustrating portions of a display panel according to an embodiment of the present invention. FIGS. 10A to 10F illustrate the same portions as FIGS. 9A to 9D , and some components are omitted for ease of explanation. Hereinafter, the present invention will be described with reference to FIGS. 10A to 10F .

[0314] Referring to FIG. 10A, the first conductive layer (MSL-L1A) may include main signal lines (SL_MA) and sub signal lines (SL_TA). In the present embodiment, the first conductive layer (MSL-L1A) may be a layer formed simultaneously with the lower conductive patterns (LPT1, LPT2, LPT3) of FIG. 5B and may correspond to the first conductive layer (MSL-L1A) illustrated in FIG. 6A. The main signal lines (SL_MA) may include a first signal line (SL_M1) and a second signal line (SL_M2). The first signal line (SL_M1) and the second signal line (SL_M2) may each be provided in multiple numbers and arranged alternately along the first direction (DR1).

[0315] The first signal line (SL_M1) and the second signal line (SL_M2) may have different lengths extending along the second direction (DR2). For example, the pad portion (PP_M) of the first signal line (SL_M1) may be positioned further away from the inspection area (PAD_F) than the pad portion (PP_M) of the second signal line (SL_M2).

[0316] The sub-signal lines (SL_T) may include a first sub-signal line (SL_T1) and a second sub-signal line (SL_T2). The first sub-signal line (SL_T1) and the second sub-signal line (SL_T2) may be provided in multiple numbers and arranged alternately along the first direction (DR1).

[0317] The first sub-signal line (SL_T1) and the second sub-signal line (SL_T2) may have different lengths extending along the second direction (DR2). For example, the first end (E1) of the first sub-signal line (SL_T1) may be positioned further away from the inspection area (PAD_F) than the first end (E1) of the second sub-signal line (SL_T2).

[0318] Referring to Fig. 10b, a first insulating layer (ISL1A) is formed on a first conductive layer (MSL-L1A). Fig. 10b illustrates a plurality of contact holes (CH_Ma, CH_T1a, CH_T2a) formed in the first insulating layer (ISL1A). The first insulating layer (ISL1A) may correspond to the third insulating layer (30, see Figs. 5b and 6f) described above. Accordingly, the contact holes (CH_Ma, CH_T1a, CH_T2a) may be formed simultaneously with the contact holes illustrated in Fig. 6f, but are not limited thereto.

[0319] The contact holes (CH_Ma, CH_T1a, CH_T2a) may correspond to the contact holes (CH_M, CH_T1, CH_T2) illustrated in FIG. 9B, respectively. Specifically, the first main contact hole (CH_Ma) may be formed to overlap the pad portion (PP_M). The first main contact hole (CH_Ma) exposes at least a portion of the pad portion (PP_M).

[0320] The first-first sub-contact hole (CH_T1a) may be formed to overlap with the first end portion (E1). The first-first sub-contact hole (CH_T1a) exposes at least a portion of the first end portion (E1).

[0321] The second-first sub-contact hole (CH_T2a) may be formed to overlap with the second end portion (E2, E2L). The second-first sub-contact hole (CH_T2a) exposes at least a portion of the second end portion (E2, E2L). Meanwhile, the second-first sub-contact hole (CH_T2a) may be provided in multiple numbers to correspond to the second end portion (E2L) with a large area.

[0322] Referring to FIG. 10c, a second conductive layer (MSL-L2A) may be formed on a first insulating layer (ISL1A). The second conductive layer (MSL-L2A) may be formed simultaneously with the first conductive patterns (CPT1a, CPT1b, CPT1c, CPT1d) of FIG. 5b. The second conductive layer (MSL-L2A) may correspond to the third conductive layer (MSL3) illustrated in FIG. 6g. The second conductive layer (MSL-L2A) may include a first pad (PDP1), a sub-line (TL), and a first sub-pad (TP1).

[0323] The first pads (PDP1) may be provided in multiple numbers and arranged spaced apart from each other. Each first pad (PDP1) may overlap the pad portion (PP_M) or the first end portion (E1) on a plane. Each first pad (PDP1) may be connected to the overlapping pad portion (PP_M) through the first main contact hole (CH_Ma) or may be connected to the overlapping first end portion (E1) through the first sub contact hole (CH_T1a).

[0324] A sub-line (TL) extends along a first direction (DR1). A plurality of sub-lines (TL) may be provided and arranged spaced apart from each other along a second direction (DR2). Each sub-line (TL) may overlap each second sub-contact hole (CH_T2a). Each sub-line (TL) is connected to a corresponding second end (E2) through the overlapping second sub-contact hole (CH_T2a).

[0325] The first sub-pad (TP1) is arranged to overlap with the second end (E2L) having a large area. The first sub-pad (TP1) may be provided with a larger area than the second end (E2L) having a large area. The first sub-pad (TP1) may be connected to the sub-signal line (SL_T) through a plurality of second sub-contact holes overlapping the second end (E2L) having a large area.

[0326] Referring to Fig. 10d, a second insulating layer (ISL2A) may be formed on the second conductive layer (MSL-L2A). Fig. 10d illustrates contact holes (CH_Mb, CH_T1b, CH_T2b) defined in the second insulating layer (ISL2A). The second insulating layer (ISL2A) may correspond to the first inorganic layer (40, see Fig. 5b) illustrated in Fig. 5b. Accordingly, the contact holes (CH_Mb, CH_T1b, CH_T2b) may be formed simultaneously with the contact holes illustrated in Fig. 6h, but are not limited thereto.

[0327] The second main contact hole (CH_Mb) may be formed to overlap the first pad (PDP1) and the pad portion (PP_M). The second main contact hole (CH_Mb) may be spaced apart from the first main contact hole (CH_Ma) in a plane. The first main contact hole (CH_Ma) exposes at least a portion of the first pad (PDP1).

[0328] The first-second sub-contact hole (CH_T1b) may be formed to overlap the first pad (PDP1) and the first end (E1). The first-second sub-contact hole (CH_T1b) may be spaced apart from the first-first sub-contact hole (CH_T1a) in a plane. The first-second sub-contact hole (CH_T1b) exposes at least a portion of the first pad (PDP1).

[0329] The second-second sub-contact hole (CH_T2b) may be formed to overlap the first sub-pad (TP1) and the second end portion (E2L) having a large area. The second-second sub-contact hole (CH_T2b) may be spaced apart from the second-first sub-contact hole (CH_T2a) in a plane. The second-second sub-contact hole (CH_T2b) exposes at least a portion of the first sub-pad (TP1). Meanwhile, the second-second sub-contact hole (CH_T2b) may be provided in multiple numbers corresponding to the second end portion (E2L) having a large area.

[0330] Referring to FIG. 10e, a third conductive layer (MSL-L3A) may be formed on a second insulating layer (ISL2A). The third conductive layer (MSL-L3A) may be formed simultaneously with the second conductive patterns (CPT2a, CPT2b, CPT2c) of FIG. 5b. The third conductive layer (MSL-L3A) may correspond to the fourth conductive layer (MSL4) illustrated in FIG. 6j. The third conductive layer (MSL-L3A) may include a second pad (PDP2) and a second sub-pad (TP2).

[0331] A plurality of second pads (PDP2) may be provided and arranged spaced apart from each other along the first direction (DR1). Each second pad (PDP2) connects a main signal line (SL_M) and a sub signal line (SL_T) spaced apart from each other in the second direction (DR2). One side of the second pad (PDP2) overlaps the pad portion (PP_M) and is connected to the first pad (PDP1) through a second main contact hole (CH_Mb) and is connected to the pad portion (PP_M). The other side of the second pad (PDP2) overlaps the first end (E1). The second pad (PDP2) is connected to the first pad (PDP1) through a first-second sub contact hole (CH_Tb) and is connected to the first end (E1).

[0332] The second sub-pad (TP2) is arranged to overlap the second end portion (E2L) with a large area and the first sub-pad (TP1). The second sub-pad (TP2) may be provided with a larger area than the first sub-pad (TP1). The sub-pad (TP) may be connected to the sub-signal line (SL_T) through a plurality of second sub-contact holes overlapping the second end portion (E2L) with a large area.

[0333] According to the present invention, electrical connection between the sub signal lines (SL_T) and the main signal lines (SL_M) can be made when the fourth conductive layer (MSL4) is formed. Therefore, before the OLB process of combining with the circuit board, an electrical inspection can be performed on pixels connected to the signal lines (SL_M) through the second sub pad (TP2) or the sub line (TL). In addition, even if a defect occurs through the electrical inspection, immediate repair can be easily performed. Therefore, according to the present invention, an electrical inspection of the display panel can be easily performed during the process, so that the electrical reliability of the display panel and the process reliability can be improved.

[0334] In addition, according to the present invention, since the first pads (PDP1) are added separately, the second pad (PDP2) can be connected through the first pad (PDP1) without being directly connected to the sub signal line (SL_T) or the main signal line (SL_M). Therefore, even if the area of ​​the ends (PP_M, EL1, EL2) defined in the sub signal line (SL_T) or the main signal line (SL_M) is small, by additionally forming the first pad (PDP1) that can have a larger area and making the connection with the second pad (PDP2) through the first pad (PDP1), the connection between the sub signal line (SL_T) and the main signal line (SL_M) can be easily made.

[0335] Referring to Fig. 10f, a third insulating layer (ISL3A) may be formed on a third conductive layer (MSL-L3A). Fig. 10f illustrates a plurality of openings (OP_IM, IP_IP) defined in the third insulating layer (ISL3A). The third insulating layer (ISL3A) may correspond to the second inorganic layer (60) illustrated in Fig. 5b. Accordingly, the openings (OP_IM, IP_IP) may be formed simultaneously with the contact holes and openings illustrated in Fig. 6k.

[0336] The pad opening (OP_IM) may be formed to overlap each second pad (PDP2). The pad opening (OP_IM) exposes at least a portion of the second pad (PDP2). The pad opening (OP_IM) may correspond to the pad opening (HH-P) illustrated in FIG. 8A. That is, the second pad (PDP2) and an external circuit board may be electrically connected through the pad opening (OP_IM).

[0337] The sub-opening (OP_IP) may be formed to overlap with the second sub-pad (TP2). The sub-opening (OP_IP) exposes at least a portion of the second sub-pad (TP2). The sub-opening (OP_IP) may be an area where the second sub-pad (TP2) and an external inspection device are electrically connected. According to the present invention, by providing the sub-opening (OP_IP) with a relatively large area compared to the pad opening (OP_IM), a tip portion or the like of the inspection device can be easily connected to the second sub-pad (TP2). That is, according to the present invention, electrical inspection can be possible even after the third insulating layer (ISL3A) is formed.

[0338] Meanwhile, the sub-aperture (OP_IP) can be formed simultaneously with the pad opening (OP_IM). In addition, the sub-aperture (OP_IP) can be formed simultaneously with the above-described opening (HH, see FIG. 5b) by forming the pad opening (OP_IM) in the second inorganic layer (60). According to the present invention, by forming the inspection pad, the connection pad, and the hole for gas discharge simultaneously, the process can be simplified and the process cost can be reduced.

[0339]

[0340] FIGS. 11A to 11F are plan views illustrating portions of a display panel according to an embodiment of the present invention. FIGS. 11A to 11F illustrate the same portions as FIGS. 10A to 10F, and some components are omitted for ease of explanation. Hereinafter, the present invention will be described with reference to FIGS. 11A to 11F.

[0341] Referring to FIG. 11A, the first conductive layer (MSL-L1B) may include main signal lines (SL_MA) and sub signal lines (SL_TA). In the present embodiment, the first conductive layer (MSL-L1B) may be a layer formed simultaneously with the lower conductive patterns (LPT1, LPT2, LPT3) of FIG. 5B and may correspond to the first conductive layer (MSL1) illustrated in FIG. 6A. The main signal lines (SL_MA) may include a first signal line (SL_M1) and a second signal line (SL_M2). The first signal line (SL_M1) and the second signal line (SL_M2) may each be provided in multiple numbers and arranged alternately along the first direction (DR1). The first conductive layer (MSL-L1B) may correspond to the first conductive layer (MSL-L1A) illustrated in FIG. 10A. Hereinafter, any duplicate description will be omitted.

[0342] Referring to Fig. 11b, a first insulating layer (ISL1B) is formed on a first conductive layer (MSL-L1B). Fig. 11b illustrates a plurality of contact holes (CH_Ma, CH_T1a, CH_T2a) formed in the first insulating layer (ISL1B). The first insulating layer (ISL1B) may correspond to the third insulating layer (30, see Figs. 5b and 6f) described above. Accordingly, the contact holes (CH_Ma, CH_T1a, CH_T2a) may be formed simultaneously with the contact holes illustrated in Fig. 6f, but are not limited thereto. The first insulating layer (ISL1B) may correspond to the first insulating layer (ISL1A) illustrated in Fig. 10b. Hereinafter, redundant descriptions will be omitted.

[0343] Referring to Fig. 11c, a second conductive layer (MSL-L2B) may be formed on a first insulating layer (ISL1B). The second conductive layer (MSL-L2B) may be formed simultaneously with the first conductive patterns (CPT1a, CPT1b, CPT1c, CPT1d) of Fig. 5b. The second conductive layer (MSL-L2B) may correspond to the third conductive layer (MSL3) illustrated in Fig. 6g. The second conductive layer (MSL-L2B) may include a pad (PDP_1), a sub-line (TL), and a sub-pad (TP).

[0344] A plurality of pads (PDP_1) may be provided and arranged spaced apart from each other along the first direction (DR1). Each pad (PDP) connects a main signal line (SL_M) and a sub signal line (SL_T) spaced apart from each other in the second direction (DR2). One side of the pad (PDP_1) overlaps with the pad portion (PP_M) and is connected to the pad portion (PP_M) through a first main contact hole (CH_M). The other side of the pad (PDP_1) overlaps with the first end (E1) and is connected to the first end (E1) through a first sub contact hole (CH_T1).

[0345] According to the present embodiment, the pad (PDP_1) may have a shape having different widths along the second direction (DR2). For example, the pad (PDP_1) may have a shape in which the widths of a portion overlapping the pad portion (PP_M) and connected by the main contact hole (CH_M) and a portion overlapping the first end portion (E1) and connected by the first sub contact hole (CH_T1) are relatively narrow, and the widths of a portion disposed between them and not overlapping the line portions (LP_M, LL) are relatively wide. A portion of the pad (PDP_1) having a relatively large area may correspond to a portion in which a pad opening (OP_IM, see FIG. 11f) will be formed later.

[0346] A sub-line (TL) extends along a first direction (DR1). A plurality of sub-lines (TL) may be provided and arranged spaced apart from each other along a second direction (DR2). Each sub-line (TL) may overlap each second end (E2). Each sub-line (TL) is connected to a corresponding second end (E2) through a second sub-contact hole (CH_T2).

[0347] The sub pad (TP) is arranged to overlap with the second end (E2L) having a large area. The sub pad (TP) may be provided with an area larger than the second end (E2L) having a large area. The sub pad (TP) may be connected to the sub signal line (SL_T) through a plurality of second sub contact holes overlapping the second end (E2L) having a large area.

[0348] According to the present invention, electrical connection between the sub pad (TP) and the sub line (TL) and the main signal lines (SL_M) can be established when forming the third conductive layer (MSL3). Therefore, before forming the first inorganic layer (40, see FIGS. 5b and 6h) that is performed thereafter, electrical inspection can be performed on pixels connected to the signal lines (SL_M) through the sub pad (TP) or the sub line (TL). In addition, even if a defect occurs through the electrical inspection, immediate repair can be easily performed. Therefore, according to the present invention, electrical inspection of the display panel can be easily performed during the process, so that the electrical reliability of the display panel and the process reliability can be improved.

[0349] Referring to Fig. 11d, a second insulating layer (ISL2B) may be formed on the second conductive layer (MSL-L2B). Fig. 11d illustrates an opening (OP_IP, hereinafter referred to as a sub-opening) defined in the second insulating layer (ISL2B). The second insulating layer (ISL2B) may correspond to the first inorganic layer (40, see Fig. 5b) illustrated in Fig. 5b. Accordingly, the sub-opening (OP_IP) may be formed simultaneously with the contact holes illustrated in Fig. 6h, but is not limited thereto.

[0350] According to the present invention, a sub pad (TP) can be exposed through a sub opening (OP_IP) formed when forming a first inorganic layer (40, see FIG. 5b). The display panel according to the present invention can be connected to an electrical device for inspection through the exposed sub pad (TP). Accordingly, an electrical inspection of pixels can be performed even before the next process is performed after the first inorganic layer (40) is formed. In addition, even if a defect occurs through the electrical inspection, immediate repair can be easily performed. Therefore, according to the present invention, an electrical inspection of a display panel can be easily performed at multiple stages during the process, thereby improving the electrical reliability of the display panel and improving the process reliability.

[0351] Referring to FIG. 11e, a third conductive layer (MSL-L3B) may be formed on the second insulating layer (ISL2B). The third conductive layer (MSL-L3B) may be formed simultaneously with the second conductive patterns (CPT2a, CPT2b, CPT2c) of FIG. 5b, and may correspond to the fourth conductive layer (MSL4) illustrated in FIG. 6j. In the present embodiment, the third conductive layer (MSL-L3B) formed in the non-emitting region (NPXA) may be omitted. That is, the third conductive layer (MSL-L3B) does not include a conductive pattern disposed in the non-emitting region (NPXA). Therefore, the state of the non-emitting region (NPXA) in the step of forming the third conductive layer (MSL-L3B) may be the same as the state of the non-emitting region (NPXA) in the step of forming the second insulating layer (ISL2B) illustrated in FIG. 11d.

[0352] Referring to Fig. 11f, a third insulating layer (ISL3B) may be formed after the third conductive layer (MSL-L3B) formation step. Fig. 11f illustrates an opening (OP_IM, hereinafter referred to as a pad opening) defined in the third insulating layer (ISL3B). The third insulating layer (ISL3B) may correspond to the second inorganic layer (60) illustrated in Fig. 5b. Accordingly, the pad opening (OP_IM) may be formed simultaneously with the contact holes and openings illustrated in Fig. 6k.

[0353] A pad opening (OP_IM) may be formed to overlap each pad (PDP_1). The pad opening (OP_IM) exposes at least a portion of the pad (PDP_1). The pad (PDP_1) and an external circuit board may be electrically connected through the pad opening (OP_IM).

[0354] That is, the pad opening (OP_IM) can be formed by penetrating not only the third insulating layer (ISL3B) but also the second insulating layer (ISL2B). The second insulating layer (ISL2B) and the third insulating layer (ISL3B) are simultaneously etched through the same process to form the pad opening (OP_IM). Therefore, it can correspond to the pad opening (PD-OP) illustrated in FIG. 11f, and the exposed pad (PDP_1) can correspond to the pad (PDP-A) illustrated in FIG. 11f.

[0355] According to the present invention, since the pad opening (OP_IM) is formed when the third insulating layer (ISL3B) is formed, the pad (PDP-A) may not be exposed and may be covered by the second insulating layer (ISL2B) and the third insulating layer (ISL3B) during the formation of the third conductive layer (MSL-L3B) prior to the formation of the third insulating layer (ISL3B). The second insulating layer (ISL2B) and the third insulating layer (ISL3B) may protect the pad (PDP_1) during patterning of the third conductive layer (MSL-L3B). Accordingly, exposure of the pad (PDP_1) to an etchant or the like for forming the second conductive patterns (CPT2a, CPT2b, CPT2c, see FIG. 5b) may be prevented, thereby preventing damage to the pad (PDP_1) during the process. Accordingly, process reliability may be improved.

[0356] In addition, by simultaneously patterning the third insulating layer (ISL3B) and the second insulating layer (ISL2B) when forming the pad opening (OP_IM), the process for forming the pad (PDP-A) can be simplified and the process cost can be reduced. Meanwhile, this is described as an example, and if the pixel formation process in the light-emitting area (PXA) and the pad (PDP_1) or inspection pad (TP) formation process in the non-light-emitting area (NPXA) can be performed simultaneously, various methods can be used and are not limited to any one embodiment.

[0357] While the present invention has been described above with reference to preferred embodiments, it will be understood by those skilled in the art or those with ordinary knowledge in the art that various modifications and changes can be made to the present invention without departing from the spirit and technical scope of the present invention as set forth in the claims below. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

[0358] The present invention relates to a technology for improving the process reliability of a display panel, and therefore has industrial applicability.

Claims

1. A substrate including a display area and a peripheral area adjacent to the display area; A transistor arranged in the above display area; A first conductive layer comprising a first connection pattern disposed on the transistor and connected to the transistor; A first inorganic layer covering the first challenge layer; A first organic layer disposed on the first inorganic layer; A second conductive layer disposed on the first organic layer and including a second connection pattern penetrating the first inorganic layer and the first organic layer and connected to the first connection pattern; A second inorganic layer covering the second challenge layer; A second organic layer disposed on the second inorganic layer; A light emitting element disposed on the second organic layer and connected to the second connecting pattern; A contact hole penetrating the second inorganic layer and exposing at least a portion of the second conductive layer; and A display panel including an opening spaced apart from the contact hole and in a plane and penetrating the second inorganic layer to expose at least a portion of the first organic layer.

2. In paragraph 1, A display panel in which the second connection pattern is connected to the first connection pattern through the contact hole.

3. In paragraph 1, A display panel in which the second organic layer is in contact with the first organic layer through the opening.

4. In paragraph 1, A display panel having a plurality of above openings arranged spaced apart from each other.

5. In paragraph 4, A display panel wherein one of the plurality of openings has a different shape from the other in a plane.

6. In paragraph 1, The above opening is a display panel that does not overlap on a plane with the second connecting pattern.

7. In paragraph 6, The second conductive layer further includes a plurality of conductive patterns spaced apart from the second connecting pattern on a plane, The above opening is a display panel that does not overlap on a plane with the above challenge patterns.

8. In paragraph 1, A display panel in which, within the above display area, the area of the opening on a plane is 30% or less of the area on a plane of the second weapon layer.

9. In paragraph 1, The first conductive layer further includes a pad electrically connected to the transistor and arranged in the peripheral area, A display panel in which a first pad opening exposing the pad is defined in the first weapon layer.

10. In paragraph 9, The second weapon layer is a display panel that does not overlap in a plane with the first pad opening.

11. In paragraph 9, A display panel in which a second pad opening is defined in the second weapon layer, the second pad opening overlapping the first pad opening.

12. In paragraph 11, A display panel wherein the first pad opening and the second pad opening are aligned in cross section.

13. In paragraph 9, Each of the first connection pattern and the pad includes a first sub-layer, a second sub-layer disposed on the first sub-layer, and a third sub-layer disposed on the second sub-layer and including a material different from the second sub-layer, A display panel wherein the thickness of the third sub-layer of the first connection pattern is different from the thickness of the third sub-layer of the pad.

14. A substrate comprising a display area including a plurality of light-emitting areas and a peripheral area adjacent to the display area; A transistor arranged in each of the above light-emitting regions; A first conductive layer comprising a plurality of first conductive patterns arranged on the transistor and spaced apart from each other; A first inorganic layer covering the first challenge layer; A first organic layer disposed on the first inorganic layer; A second conductive layer comprising a plurality of second conductive patterns arranged on the first organic layer and spaced apart from each other; A second inorganic layer covering the second challenge layer; a second organic layer disposed on the second inorganic layer; and A light emitting element is disposed in each of the above light emitting regions, is disposed on the second organic layer, and is connected to the transistor through a first connection pattern among the first conductive patterns and a second connection pattern among the second conductive patterns. The second weapon layer comprises an opening spaced apart from the second challenge patterns in the plane, A display panel in which the second organic layer is in contact with the first organic layer through the opening.

15. In paragraph 14, The light-emitting element is connected to the second connection pattern through a contact hole penetrating the second organic layer and the second inorganic layer, The above opening is a display panel spaced apart from the contact hole in a plane.

16. In paragraph 15, A display panel wherein the above opening has a larger area than the above contact hole.

17. In paragraph 14, The above opening is a display panel defined for each of the above light-emitting areas.

18. In paragraph 16, A display panel in which the above openings are provided in plurality and arranged spaced apart from each other within each of the above light-emitting areas.

19. In paragraph 14, The above first challenge layer further includes a pad arranged in the peripheral area, A display panel in which a first pad opening exposing the pad is defined in the first weapon layer.

20. In paragraph 19, A display panel in which a second pad opening is defined in the second weapon layer, the second pad opening overlapping the first pad opening.

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