Array substrate and liquid crystal display panel

Abstract

The present application belongs to the technical field of display. Disclosed are an array substrate and a liquid crystal display panel. The array substrate comprises: a base, thin-film transistors, a first insulating layer and an encapsulation structure. The first insulating layer in the array substrate can have a plurality of first insulating parts corresponding to a plurality of thin-film transistors, and the plurality of first insulating parts can be separately arranged, and thus the continuity of the first insulating layer can be effectively reduced. In this way, it can be ensured that the diffusion rate of moisture and oxygen from an external environment in the first insulating layer is relatively slow. Moreover, the encapsulation structure can also encapsulate the first insulating parts, so that the probability of moisture and oxygen ingress from the external environment into the first insulating parts is relatively low, thereby reducing the probability of moisture and oxygen ingress from the external environment into active layers of the thin-film transistors, and thus effectively reducing the probability that the electrical performance of the thin-film transistors is affected, and further improving the display effect of the liquid crystal display panel integrated with the array substrate.

Description

Array substrate and liquid crystal display panel Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a liquid crystal display panel. Background Art

[0002] Liquid crystal display panels have the characteristics of small size, low power consumption and no radiation, and occupy a dominant position in the current display market.

[0003] Typically, a liquid crystal display panel includes an array substrate and a color filter substrate positioned opposite each other, with a liquid crystal layer positioned therebetween. The array substrate may include multiple thin-film transistors (TFTs) and pixel electrodes electrically connected to the TFTs in a one-to-one correspondence.

[0004] However, the active layer inside the TFT in the current array substrate is easily corroded by water and oxygen in the external environment, which affects the electrical performance of the TFT and further leads to poor display effect of the liquid crystal display panel integrated with such an array substrate.

[0005] Summary of the Invention

[0006] The present invention provides an array substrate and a liquid crystal display panel. The present invention can solve the problem of poor display quality of liquid crystal display panels in the prior art. The technical solution is as follows:

[0007] In one aspect, an array substrate is provided, comprising:

[0008] substrate;

[0009] A plurality of thin film transistors located on one side of the substrate, the thin film transistors comprising: an active layer;

[0010] a first insulating layer located on a side of the active layer facing the substrate, the first insulating layer comprising: a plurality of first insulating portions corresponding to the plurality of thin film transistors, the first insulating portions being arranged in contact with the active layers in the corresponding thin film transistors, and the plurality of first insulating portions being arranged separately;

[0011] And, a packaging structure for packaging each of the first insulating parts, wherein a portion of the packaging structure is distributed between two adjacent first insulating parts.

[0012] Optionally, the packaging structure includes: a first packaging layer and a second packaging layer, the first packaging layer is located on the side of the first insulating layer facing the substrate, the second packaging layer is located on the side of the active layer away from the substrate, and a portion of the second packaging layer is distributed between two adjacent first insulating parts.

[0013] Optionally, the thin film transistor further comprises: a gate insulated from the active layer, the gate being located on a side of the active layer facing the substrate, and the first insulating layer and the first encapsulation layer being located between the gate and the active layer;

[0014] The first insulating layer has a first blocking groove between two adjacent first insulating portions, the first encapsulation layer has a second blocking groove connected to the first blocking groove, and a portion of the second encapsulation layer extends into the first blocking groove and the second blocking groove.

[0015] Optionally, the array substrate further comprises: a second insulating layer located on a side of the active layer facing away from the substrate, the second insulating layer being located on a side of the second encapsulation layer facing the substrate;

[0016] The second insulating layer includes: a plurality of second insulating portions corresponding to the plurality of thin film transistors, and a third insulating portion located between two adjacent second insulating portions;

[0017] The second insulating portion is arranged in contact with the active layer of the corresponding thin film transistor, and the third insulating portion is located in the second blocking groove.

[0018] Optionally, the orthographic projection of the first barrier groove on the substrate is located within the orthographic projection of the second barrier groove on the substrate, and the second insulating layer further includes: a connecting portion for connecting the second insulating portion and the third insulating portion, the connecting portion being attached to the side walls of the first barrier groove and the side walls of the second barrier groove, and the thickness of the connecting portion facing the third insulating portion is less than the thickness of the connecting portion facing the second insulating portion.

[0019] Optionally, the thickness of the connecting portion gradually decreases along a direction from the second insulating portion toward the third insulating portion.

[0020] Optionally, the first orthographic projection of the opening of the second barrier groove toward the substrate on the substrate is located within the second orthographic projection of the opening of the first barrier groove away from the substrate on the substrate, and the outer boundary of the first orthographic projection does not overlap with the outer boundary of the second orthographic projection; the second insulating portion and the third insulating portion are arranged separately.

[0021] Optionally, the first encapsulation layer includes: a plurality of first encapsulation parts corresponding to the plurality of first insulating parts, and a second blocking groove is provided between two adjacent first encapsulation parts;

[0022] An edge of the first insulating portion protrudes from an edge of the corresponding first packaging portion.

[0023] Optionally, the first blocking groove is annular, and the orthographic projection of the thin film transistor on the substrate is located within a region enclosed by the orthographic projection of the first blocking groove on the substrate.

[0024] Optionally, the thin film transistor further includes: a first electrode and a second electrode overlapped with the active layer, wherein the first electrode and the second electrode are both located on a side of the active layer away from the substrate;

[0025] The array substrate further includes: a first bonding electrode and a second bonding electrode, wherein the first bonding electrode is provided on the same layer and made of the same material as the gate electrode, and the second bonding electrode is provided on the same layer and made of the same material as the first electrode and the second electrode;

[0026] The first insulating layer further has a first connecting via hole, and the first encapsulation layer further has a second connecting via hole communicating with the first connecting via hole;

[0027] The second bonding electrode is bonded to the first bonding electrode through the first connection via hole and the second connection via hole in sequence.

[0028] Optionally, the thin film transistor further comprises: a gate insulated from the active layer, the gate being located on a side of the active layer facing away from the substrate, and the first insulating layer and the first encapsulation layer being located on a side of the active layer facing the substrate;

[0029] The second encapsulation layer is arranged in contact with a portion of the first encapsulation layer that is not covered by the first insulating portion.

[0030] Optionally, the array substrate further comprises: a second insulating layer located on a side of the gate facing away from the substrate, the second insulating layer being located on a side of the second encapsulation layer facing the substrate;

[0031] The second insulating layer includes: a plurality of second insulating portions corresponding to the plurality of thin film transistors;

[0032] The second insulating portion is arranged in contact with the active layer of the corresponding thin film transistor, and the plurality of second insulating portions are arranged separately.

[0033] Optionally, the first encapsulation layer includes: a plurality of first encapsulation portions corresponding to the plurality of first insulating portions, and a second encapsulation portion for connecting the plurality of first encapsulation portions, wherein the first encapsulation portions are arranged in contact with the corresponding first insulating portions, and an orthographic projection of the first insulating portion on the substrate is located within an orthographic projection of the first encapsulation portion on the substrate;

[0034] The second encapsulation layer includes: a plurality of third encapsulation portions corresponding to the plurality of second insulating portions, and a fourth encapsulation portion for connecting the plurality of third encapsulation portions, wherein the third encapsulation portions are arranged in contact with the corresponding second insulating portions, and an orthographic projection of the second insulating portion on the substrate is located within an orthographic projection of the third encapsulation portion on the substrate;

[0035] The third packaging part can cover the side surfaces of the first insulating part and the second insulating part; and the second packaging part is arranged in contact with the fourth packaging part.

[0036] Optionally, the thin film transistor also includes: a first electrode and a second electrode, the first electrode and the second electrode are both located on the side of the second insulating part away from the substrate, and the second insulating part has a third connecting via and a fourth connecting via, the first electrode is overlapped with the active layer through the third connecting via, and the second electrode is overlapped with the active layer through the fourth connecting via.

[0037] Optionally, the array substrate further includes: a plurality of pixel electrodes electrically connected to the plurality of thin film transistors in a one-to-one correspondence.

[0038] On the other hand, a liquid crystal display panel is provided, comprising: an array substrate and a color filter substrate arranged opposite to each other, and a liquid crystal layer located between the array substrate and the color filter substrate, wherein the array substrate is any of the array substrates described above.

[0039] The beneficial effects of the technical solutions provided in the embodiments of the present application include at least:

[0040] An array substrate comprises: a substrate, a thin film transistor, a first insulating layer and a packaging structure. Since the first insulating layer in the array substrate can have multiple first insulating parts corresponding to multiple thin film transistors, and the multiple first insulating parts can be separately arranged, the continuity of the first insulating layer can be effectively reduced. In this case, even if the first insulating layer is made of a silicon oxide material with a relatively loose film quality, it can be ensured that the diffusion rate of water and oxygen in the external environment in the first insulating layer is relatively slow. In addition, these first insulating parts can also be packaged by the packaging structure, and the packaging structure has good airtightness and is better insulated from water and oxygen in the external environment, so that the probability of water and oxygen in the external environment invading each first insulating part is low, thereby reducing the probability of water and oxygen in the external environment invading the active layer in the thin film transistor, effectively reducing the probability of the electrical performance of the thin film transistor being affected, and thereby improving the display effect of the liquid crystal display panel integrated with such an array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0042] FIG1 is a schematic diagram of a film layer structure of an array substrate in a display panel provided by related art;

[0043] FIG2 is a top view of an array substrate provided in an embodiment of the present application;

[0044] FIG3 is a schematic diagram of the film layer structure of the array substrate at AA′ shown in FIG2 ;

[0045] FIG4 is a schematic diagram of another film layer structure at AA′ of the array substrate shown in FIG2 ;

[0046] FIG5 is a schematic diagram of another film layer structure at the AA' position of the array substrate shown in FIG2;

[0047] FIG6 is a diagram showing the covering effect of a second insulating layer formed of a silicon oxide material according to an embodiment of the present application;

[0048] FIG7 is a diagram showing the covering effect of a second encapsulation layer formed of silicon nitride material provided in an embodiment of the present application;

[0049] FIG8 is a top view of another array substrate provided in an embodiment of the present application;

[0050] FIG9 is a partial enlarged view of a certain area of ​​the array substrate shown in FIG2 ;

[0051] FIG10 is a schematic diagram of the film structure of the gate at position BB' shown in FIG9;

[0052] FIG11 is a schematic diagram of another film layer structure at AA' of the array substrate shown in FIG2;

[0053] FIG12 is a flow chart of a method for manufacturing an array substrate provided in an embodiment of the present application;

[0054] FIG13 is a schematic diagram of a film structure of a first conductive pattern formed on a substrate provided in an embodiment of the present application;

[0055] FIG14 is a schematic diagram of a film structure forming a first encapsulation layer and a first insulating layer provided in an embodiment of the present application;

[0056] 15 is a schematic diagram of another film structure for forming a first encapsulation layer and a first insulating layer provided in an embodiment of the present application;

[0057] FIG16 is a schematic diagram of a film structure for forming an active layer and a second conductive pattern provided in an embodiment of the present application;

[0058] FIG17 is a schematic diagram of another film structure for forming an active layer and a second conductive pattern provided in an embodiment of the present application;

[0059] FIG18 is a schematic diagram of a film structure for forming a second insulating layer and a second encapsulation layer provided in an embodiment of the present application;

[0060] FIG19 is a schematic diagram of another film structure for forming a second insulating layer and a second encapsulation layer provided in an embodiment of the present application;

[0061] FIG20 is a flow chart of another method for manufacturing an array substrate provided in an embodiment of the present application;

[0062] FIG21 is a schematic diagram of a film structure for forming a light-shielding layer on a substrate provided in an embodiment of the present application;

[0063] FIG22 is a schematic diagram of another film structure for forming a first encapsulation layer and a first insulating layer provided in an embodiment of the present application;

[0064] FIG23 is a schematic diagram of a film structure for forming an active layer, a gate insulating layer, and a gate provided in an embodiment of the present application;

[0065] FIG24 is a schematic diagram of another film structure for forming a second insulating layer provided in an embodiment of the present application;

[0066] FIG25 is a schematic diagram of forming a third connecting via and a fourth connecting via according to an embodiment of the present application;

[0067] FIG26 is a schematic diagram of a film structure in which a second conductive pattern is formed on a side of a second insulating layer facing away from a substrate, provided in an embodiment of the present application;

[0068] FIG27 is a schematic diagram of another film layer structure for forming a second encapsulation layer provided in an embodiment of the present application. DETAILED DESCRIPTION

[0069] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0070] Please refer to Figure 1, which is a schematic diagram of a film structure of an array substrate in a display panel provided by related art. The array substrate 00 in the display panel may include: a substrate 01, and a thin film transistor 02 located on one side of the substrate 01.

[0071] The thin film transistor 02 may include an active layer 021. The material of the active layer 021 may include an oxide semiconductor material.

[0072] Typically, the array substrate 01 may further include: a first insulating layer 03 located on the side of the active layer 021 facing the substrate 01, and a second insulating layer 04 located on the side of the active layer 021 facing away from the substrate 01. The first insulating layer 03 may be disposed in contact with the side of the active layer 021 facing the substrate 01, and the second insulating layer 04 may be disposed in contact with the side of the active layer 021 facing away from the substrate 01. Since the active layer 021 is made of an oxide semiconductor material, the first insulating layer 03 and the second insulating layer 04 need to be made of silicon oxide material with a low hydrogen content to ensure that hydrogen ions in the first insulating layer 03 and the second insulating layer 04, which are in contact with the active layer 021, are not injected into the active layer 021, causing the active layer 021 to become conductive.

[0073] However, the first insulating layer 03 and the second insulating layer 04, made of silicon oxide, are relatively loose, resulting in a weak ability of the first insulating layer 03 and the second insulating layer 04 to isolate water and oxygen from the external environment. Consequently, water and oxygen from the external environment can easily corrode the active layer 021 of the thin-film transistor 02 through the first insulating layer 03 and the second insulating layer 04. Once the active layer 021 of the thin-film transistor 02 is corroded by water and oxygen, the electrical performance of the thin-film transistor 02 is affected, resulting in poor display quality of a liquid crystal display panel incorporating such an array substrate 00.

[0074] Please refer to Figure 2, which is a top view of an array substrate provided in an embodiment of the present application. The array substrate 000 may include a substrate 100 and a plurality of thin-film transistors 200 located on one side of the substrate 100. In the present application, the array substrate 000 may also include a plurality of pixel electrodes 800 electrically connected to the plurality of thin-film transistors 200 in a one-to-one correspondence.

[0075] To more clearly illustrate the film structure of the array substrate 000, FIG3 is a schematic diagram of the film structure of the array substrate at AA' shown in FIG2. The array substrate 000 may further include a first insulating layer 300 and an encapsulation structure 400.

[0076] The thin film transistor 200 in the array substrate 000 may be located on one side of the substrate 100, and the thin film transistor 200 may include an active layer 201. For example, the thin film transistor 200 may be an oxide thin film transistor, that is, the material of the active layer 201 in the thin film transistor 200 is an oxide semiconductor material. For example, the material of the active layer 201 is IGZO.

[0077] The first insulating layer 300 in the array substrate 000 can be located on the side of the active layer 201 in the thin film transistor 200 facing the substrate 100. The first insulating layer 300 can include: a plurality of first insulating portions 301 corresponding to the plurality of thin film transistors 200. Here, each first insulating portion 301 in the first insulating layer 300 can be arranged in contact with the active layer 201 in the corresponding thin film transistor 200, and the plurality of first insulating portions 301 in the first insulating layer 300 can be arranged separately. It should be noted that in order to prevent the active layer 201 made of oxide semiconductor material from being conductive, the first insulating layer 300 needs to be made of silicon oxide material with a low hydrogen content.

[0078] The packaging structure 400 in the array substrate 000 can be used to package each first insulating portion 301. For example, the packaging structure 400 in the array substrate 000 can be made of silicon nitride material with good airtightness, so that the film quality of the packaging structure is relatively tight.

[0079] In the present application, since the first insulating layer 300 in the array substrate 000 can have multiple first insulating portions 301 corresponding to multiple thin-film transistors 200, and the multiple first insulating portions 301 can be separately arranged, the continuity of the first insulating layer 300 can be effectively reduced. In this case, even if the first insulating layer 300 is made of a relatively loose silicon oxide material, the diffusion rate of water and oxygen in the external environment into the first insulating layer 300 can be ensured to be relatively slow. Furthermore, the first insulating portions 301 can be encapsulated by the encapsulation structure 400. The encapsulation structure 400 has good airtightness and effectively isolates water and oxygen from the external environment, thereby reducing the probability of water and oxygen from the external environment invading each first insulating portion 301. This reduces the probability of water and oxygen from the external environment invading the active layer 201 of the thin-film transistor 200, effectively reducing the probability of the electrical performance of the thin-film transistor 200 being affected, and thereby improving the display quality of the liquid crystal display panel integrated with this array substrate 000.

[0080] In summary, the array substrate provided in the embodiment of the present application includes: a substrate, a thin film transistor, a first insulating layer and a packaging structure. Since the first insulating layer in the array substrate can have multiple first insulating parts corresponding to multiple thin film transistors, and the multiple first insulating parts can be separately arranged, the continuity of the first insulating layer can be effectively reduced. In this case, even if the first insulating layer is made of a silicon oxide material with a relatively loose film quality, it can be ensured that the diffusion rate of water and oxygen in the external environment in the first insulating layer is relatively slow. In addition, these first insulating parts can also be packaged by the packaging structure, and the packaging structure has good airtightness, and its effect of isolating water and oxygen in the external environment is better, so that the probability of water and oxygen in the external environment invading each first insulating part is low, thereby reducing the probability of water and oxygen in the external environment invading the active layer in the thin film transistor, effectively reducing the probability of the electrical performance of the thin film transistor being affected, and thereby improving the display effect of the liquid crystal display panel integrated with such an array substrate.

[0081] In an embodiment of the present application, please refer to FIG4 , which is a schematic diagram of another film layer structure at the AA' position of the array substrate shown in FIG2 . The encapsulation structure 400 in the array substrate 000 may include a first encapsulation layer 401 and a second encapsulation layer 402. Here, both the first encapsulation layer 401 and the second encapsulation layer 402 may be made of silicon nitride.

[0082] The first encapsulation layer 401 in the encapsulation structure 400 may be located on the side of the first insulating layer 300 facing the substrate 100, the second encapsulation layer 402 in the encapsulation structure 400 may be located on the side of the active layer 201 facing away from the substrate 100, and a portion of the second encapsulation layer 402 may be distributed between two adjacent first insulating portions 301. The first encapsulation layer 401 and the second encapsulation layer 402 in the encapsulation structure 400 may encapsulate each first insulating portion 301, thereby reducing the probability of water and oxygen in the external environment invading the active layer 201 in the thin film transistor 200.

[0083] In the present application, the thin film transistor 200 in the array substrate 000 may further include a gate 202 insulated from the active layer 201. Here, the gate 202 in the thin film transistor 200 may be located on the side of the active layer 201 facing the substrate 100, or the gate 202 in the thin film transistor 200 may be located on the side of the active layer 201 facing away from the substrate 100. When the gate 202 in the thin film transistor 200 is located on the side of the active layer 201 facing the substrate 100, the thin film transistor 200 is a bottom-gate thin film transistor; when the gate 202 in the thin film transistor 200 is located on the side of the active layer 201 facing away from the substrate 100, the thin film transistor 200 is a top-gate thin film transistor. The structures of the first insulating layer 300 and the encapsulation structure 400 in the array substrate 000 vary for different types of thin film transistors. Therefore, the present application will use the following two optional implementations as examples for schematic illustration.

[0084] In a first optional implementation, as shown in FIG4 , when the thin film transistor 200 is a bottom-gate thin film transistor, the first insulating layer 300 and the first encapsulation layer 401 can both be located between the gate electrode 202 and the active layer 201. In this way, the gate electrode 202 of the thin film transistor 200 can be insulated from the active layer 201 of the thin film transistor 200 by the first insulating layer 300, so that there will be no short circuit between the gate electrode 202 and the active layer 201. In other words, the first insulating layer 300 and the first encapsulation layer 401 located between the gate electrode 202 and the active layer 201 can serve as the gate insulating layer of this thin film transistor 200.

[0085] 4 , the first insulating layer 300 in the array substrate 000 may have a first blocking groove U1 between two adjacent first insulating portions 301. By providing the first blocking groove U1 in the first insulating layer 300, the first insulating layer 300 may be divided into a plurality of first insulating portions 301.

[0086] The first encapsulation layer 401 in the encapsulation structure 400 may have a second barrier trench U2 connected to the first barrier trench U1. Here, by providing the second barrier trench U2 in the first encapsulation layer 401 and connected to the first barrier trench U1, the first encapsulation layer 401 may be divided into a plurality of first encapsulation portions 4011 corresponding to the plurality of first insulating portions 301. In other words, a second barrier trench U2 is provided between two adjacent first encapsulation portions 4011.

[0087] Each first packaging part 4011 can be arranged in contact with the side of the corresponding first insulating part 301 facing the substrate 100, and the first insulating part 301 can be packaged from the side of the first insulating part 301 facing the substrate 100 through the first packaging part 4011.

[0088] In the present application, a portion of the second encapsulation layer 402 in the encapsulation structure 400 can extend into the first and second barrier trenches U1 and U2. In this way, the portion of the second encapsulation layer 402 that extends into the first and second barrier trenches U2 can encapsulate the first insulating portions 301 from the side of each first insulating portion 301. Furthermore, because the second encapsulation layer 402 can be located on the side of the active layer 201 facing away from the substrate 100, the second encapsulation layer 402 can also encapsulate the first insulating portion 301 on the side of the first insulating portion 301 facing away from the substrate 100. In this way, through the coordination of the first encapsulation layer 401 and the second encapsulation layer 402 in the encapsulation structure 400, each first insulating portion 301 in the first insulating layer 300 can be encapsulated, reducing the probability of water and oxygen in the external environment corroding the active layer 201 through the first insulating portion 301.

[0089] In an embodiment of the present application, as shown in FIG4 , the array substrate 000 may further include: a second insulating layer 500 located on the side of the active layer 201 of the thin film transistor 200 facing away from the substrate 100. The second insulating layer 500 may be located on the side of the second encapsulation layer 402 of the encapsulation structure 400 facing the substrate 100. That is, the second insulating layer 500 may be located between the active layer 201 and the second encapsulation layer 402.

[0090] Here, the second insulating layer 500 in the array substrate 000 may include: a plurality of second insulating portions 501 corresponding to the plurality of thin film transistors 200, and a third insulating portion 502 located between two adjacent second insulating portions 501. Each second insulating portion 501 in the second insulating layer 500 may be disposed in contact with the active layer 201 in the corresponding thin film transistor 200, and the third insulating portion 502 in the second insulating layer 500 may be located within the second blocking trench U2. It should be noted that to prevent the active layer 201 made of an oxide semiconductor material from being conductive, the second insulating layer 500 also needs to be made of a silicon oxide material with a low hydrogen content.

[0091] In the present application, the second encapsulation layer 402 in the encapsulation structure 400 may include: a plurality of third encapsulation parts 4021 arranged corresponding to the plurality of second insulating parts 501 in the second insulating layer 500, and a fourth encapsulation part 4022 located between two adjacent third encapsulation parts 4021. It should be noted that the second encapsulation layer 402 may be a whole layer structure with continuous distribution at various positions. Therefore, the fourth encapsulation part 4022 and the third encapsulation part 4021 in the second encapsulation layer 402 are connected.

[0092] Each third encapsulation portion 4021 in the second encapsulation layer 402 can be located on a side of the corresponding second insulating portion 501 facing away from the substrate 100 and can be disposed in contact with the corresponding second insulating portion 501. In this way, the second insulating portion 501 can be encapsulated from the side of the second insulating portion 501 facing the substrate 100 through the third encapsulation portion 4021.

[0093] The fourth encapsulation portion 4022 in the second encapsulation layer 402 can extend into the first and second barrier trenches U1 and U2, and can cover the third insulating portion 502 located in the second barrier trench U2. In this way, the fourth encapsulation portion 4022 can not only encapsulate the third insulating portion 502 in the second insulating layer 500 but also encapsulate the side surfaces of the second insulating portion 501 in the second insulating layer 500.

[0094] To this end, through the cooperation of the first encapsulation layer 401 and the second encapsulation layer 402 in the encapsulation structure 400, each second insulating part 501 in the second insulating layer 500 can be encapsulated, so that the probability of water and oxygen in the external environment corroding the active layer 201 through the second insulating part 501 is low.

[0095] In the embodiment of the present application, the second insulating portion 501 and the third insulating portion 502 in the second insulating layer 500 may be connected or not connected. To this end, the embodiment of the present application uses the following two cases as examples for illustration:

[0096] In the first case, please refer to Figure 5, which is a schematic diagram of another film layer structure at the AA' position of the array substrate shown in Figure 2. The orthographic projection of the first blocking trench U1 in the first insulating layer 300 on the substrate 100 is located within the orthographic projection of the second blocking trench U2 in the first encapsulation layer 401 on the substrate 100. In this case, the second insulating portion 501 in the second insulating layer 500 can be connected to the third insulating portion 502.

[0097] For example, the second insulating layer 500 in the array substrate 000 may further include a connecting portion 503 for connecting the second insulating portion 501 and the third insulating portion 502. Here, the connecting portion 503 in the second insulating layer 500 may be attached to the sidewalls of the first blocking trench U1 and the sidewalls of the second blocking trench U2, and the second insulating portion 501 in the second insulating layer 500 may be connected to the third insulating portion 502 via the connecting portion 503.

[0098] In the embodiment of the present application, since the second insulating layer 500 is made of silicon oxide, and the viscosity of the groups formed by the silicon oxide during the film deposition process is generally high, the coverage of the film structure formed by the silicon oxide material is poor. For example, as shown in Figure 6, which is a coverage effect diagram of a second insulating layer formed of silicon oxide provided by an embodiment of the present application, in the second insulating layer 500 formed of silicon oxide, the thickness of the portion of the structure attached to the sidewall will gradually decrease from top to bottom according to the orientation of the film formation.

[0099] 5 , the thickness of the connecting portion 503 attached to the sidewalls of the first and second barrier grooves U1 and U2 on the side facing the third insulating portion 502 is smaller than the thickness of the connecting portion 503 on the side facing the second insulating portion 501 .

[0100] In this case, even though the connecting portion 503 in the second insulating layer 500 is connected to the third insulating portion 502 and the second insulating portion 501 respectively, that is, the second insulating layer 500 has a continuous, integrated structure at all locations, water and oxygen that invade the second insulating layer 500 must pass through the third insulating portion 502 and the connecting portion 503 in sequence before invading the second insulating portion 501. Therefore, when the thickness of the connecting portion 503 in the second insulating layer 500 facing the third insulating portion 502 is smaller than the thickness of the connecting portion 503 facing the second insulating portion 501, less water and oxygen can be ensured to invade the interior of the second insulating portion 501, thereby effectively reducing the probability of water and oxygen corroding the active layer 201 that is disposed in contact with the second insulating portion 501.

[0101] In addition, since the second encapsulation layer 402 is made of silicon nitride material, and during the film deposition process, the viscosity of the group formed by the silicon nitride material is generally small, the coverage of the film structure formed by the silicon nitride material is better. For example, as shown in Figure 7, Figure 7 is a coverage effect diagram of a second encapsulation layer formed by silicon nitride material provided in an embodiment of the present application. In the second encapsulation layer 402 formed by the silicon nitride material, for the partial structure attached to the side wall, the thickness of this partial structure is the same as the thickness of other areas, that is, the thickness of the second encapsulation layer 402 formed by the silicon nitride material is the same at all positions. For this reason, the thickness of the fourth insulating portion 4022 in the second encapsulation layer 402 is the same as the thickness of the third insulating portion 4011, and the fourth insulating portion 4022 can better encapsulate the connecting portion 503 in the second insulating layer 500.

[0102] In one possible implementation, the sidewall of the first barrier groove U1 in the first insulating layer 300 is flush with the sidewall of the second barrier groove U2 in the first encapsulation layer 401. In this way, for the connecting portion 503 attached to the sidewall of the first barrier groove U1 and the sidewall of the second barrier groove U2, the thickness of the connecting portion can gradually decrease along the direction from the second insulating portion 501 in the second insulating layer 500 toward the third insulating portion 502 in the second insulating layer 500.

[0103] It should be noted that, as shown in Figure 5 , when the sidewalls of the first and second barrier trenches U1 and U2 are flush, the angle between the sidewalls and the bottom surfaces of the first and second barrier trenches U1 and U2 must be less than 105 degrees and greater than or equal to 90 degrees. In other words, the angle α between the side surface of the first encapsulation portion 4011 and the surface of the first encapsulation portion 4011 facing the substrate 100 must be greater than 75 degrees and less than or equal to 90 degrees. This ensures that the thickness of the connecting portion 503 attached to the sidewalls of the first and second barrier trenches U1 and U2 facing the third insulating portion 502 is relatively small, further reducing the diffusion rate of water and oxygen that infiltrates from the third insulating portion 502 into the connecting portion 503. For example, as shown in Figure 6 , the ratio of the thickness t1 of the connecting portion 503 facing the third insulating portion 502 to the thickness t2 of the connecting portion 503 facing the second insulating portion 501 must be less than 0.4.

[0104] In the second case, as shown in Figure 4 , the opening of the second blocking trench U2 in the first encapsulation layer 401 facing the substrate 100 is located within a first orthographic projection on the substrate 100, while the opening of the first blocking trench U1 in the first insulating layer 300 facing away from the substrate 100 is located within a second orthographic projection on the substrate 100, and the outer boundaries of the first orthographic projection do not overlap with the outer boundaries of the second orthographic projection. In this case, the second insulating portion 501 in the second insulating layer 500 may not be connected to the third insulating portion 502. In other words, the second insulating portion 501 in the second insulating layer 500 and the third insulating portion 502 in the second insulating layer 500 may be provided separately.

[0105] For example, when the opening of the second blocking trench U2 in the first encapsulation layer 401 facing the substrate 100 is located on the substrate 100 in a first orthographic projection, and the opening of the first blocking trench U1 in the first insulating layer 300 facing away from the substrate 100 is located on the substrate 100 in a second orthographic projection, and the outer boundaries of the first orthographic projection do not overlap with the outer boundaries of the second orthographic projection, the edge of each first insulating portion 301 in the first insulating layer 300 will protrude beyond the edge of the corresponding first encapsulation portion 4011 in the first encapsulation layer 401. Thus, during the subsequent formation of the second insulating layer 500, the portion located inside the second blocking trench U2 is disconnected from the portion located outside the second blocking trench U2, so that the third insulating portion 502 and the second insulating portion 501 in the second insulating layer 500 are separated.

[0106] In this case, the fourth encapsulation portion 4022 in the second encapsulation layer 402 can not only be disposed in contact with the side surface of the second insulating portion 501 in the second insulating layer 500, but can also extend into the gap formed between the third insulating portion 502 in the second insulating layer 500 and the sidewall of the second blocking trench U2. In this way, through the cooperation of the first encapsulation layer 401 and the second encapsulation layer 402 in the encapsulation structure 400, the first insulating portion 301 in the first insulating layer 300 and the second insulating portion 501 in the second insulating layer 500 can be completely encapsulated to encapsulate them, preventing water and oxygen in the external environment from corroding the first insulating portion 301 and the second insulating portion 501, and thus, the active layer 201 in the thin film transistor 200.

[0107] In an embodiment of the present application, referring to FIG8 , which is a top view of another array substrate provided in an embodiment of the present application, the first barrier trench U1 can be annular, and the orthographic projection of the thin-film transistor 200 on the substrate 100 can be located within the area enclosed by the orthographic projection of the first barrier trench U1 on the substrate 100. This ensures that the probability of water and oxygen corrosion around the active layer 201 in the thin-film transistor 200 from all directions is low, further improving the electrical performance of the thin-film transistor 200.

[0108] In the present application, as shown in Figures 4, 5, and 8, the thin film transistor 200 in the array substrate 000 may further include: a first electrode 203 and a second electrode 204 overlapping the active layer 201. The first electrode 203 in the thin film transistor 200 and the second electrode 204 in the thin film transistor 200 may both be located on the side of the active layer 201 facing away from the substrate 100. Here, the first electrode 203 refers to one of the source and drain electrodes, and the second electrode 204 refers to the other of the source and drain electrodes.

[0109] Here, the first electrode 203 and the second electrode 204 in the thin film transistor 200 can be located on the side of the second insulating layer 500 facing the substrate 100. Therefore, the second insulating layer 500 and the second encapsulation layer 402 in the array substrate 000 can serve as a passivation layer for protecting the thin film transistor 200.

[0110] It should be noted that the angles between the side surfaces of the gate electrode 202, the first electrode 203, and the second electrode 204 in the thin film transistor 200 and the surface facing the substrate 100 are all required to be less than 60 degrees. In this way, even if the second insulating layer 500 is made of a silicon oxide material with poor coverage, it can be ensured that the second insulating layer 500 can completely cover the thin film transistor 200. Furthermore, with the cooperation of the second insulating layer 500 and the second encapsulation layer 402, not only can the active layer 201 in the thin film transistor 200 be prevented from being converted into a conductor, but it can also be ensured that water and oxygen in the external environment will not corrode the active layer 201.

[0111] In the present application, as shown in FIG2 and FIG8 , the array substrate 000 may further include: a plurality of parallel-arranged gate lines G and a plurality of parallel-arranged data lines D. The plurality of thin film transistors 200 in the array substrate 000 are arranged in an array, wherein the gate electrodes 202 of each thin film transistor 200 in a row of thin film transistors 200 may be electrically connected to the same gate line G, the first electrodes 203 of each thin film transistor 200 in a column of thin film transistors 200 may be electrically connected to the same gate line G, and the second electrodes 204 of each thin film transistor 200 may be electrically connected to the corresponding pixel electrode 800.

[0112] In the embodiment of the present application, please refer to Figures 9 and 10. Figure 9 is a partial enlarged view of a certain area of ​​the array substrate shown in Figure 2, and Figure 10 is a schematic diagram of the film layer structure of the gate at position BB' shown in Figure 9. The array substrate 000 may further include: a first strapping electrode 600 and a second strapping electrode 700. Here, the first strapping electrode 600 can be provided in the same layer and made of the same material as the gate 202. Therefore, the first strapping electrode 600 and the gate 202 in the thin film transistor 200 can be formed simultaneously through a single patterning process, which can effectively simplify the manufacturing difficulty of the array substrate 000 and reduce the manufacturing cost of the array substrate 000.

[0113] Similarly, the second bonding electrode 700 can be provided in the same layer and made of the same material as the first electrode 203 in the thin film transistor 200 and the second electrode 204 in the thin film transistor 200. Therefore, the second bonding electrode 700, the first electrode 203 in the thin film transistor 200, and the second electrode 204 in the thin film transistor 200 can be simultaneously formed through a single patterning process. Here, a single patterning process refers to: photoresist coating, exposure, development, etching, and photoresist stripping.

[0114] The first insulating layer 300 in the array substrate 000 may further include a first connection via V1, and the first encapsulation layer 401 may further include a second connection via V2 connected to the first connection via V1. The second bonding electrode 700 may be bonded to the first bonding electrode 600 through the first connection via V1 and the second connection via V2, respectively.

[0115] In this case, during the fabrication process of the array substrate 000, the first connection via V1 and the first blocking trench U1 can be formed simultaneously in the first insulating layer 300, and the second connection via V2 and the second blocking trench U2 can be formed simultaneously in the second insulating layer 400. Therefore, there is no need to add separate processes to form the first blocking trench U1 and the second blocking trench U2. Instead, the first blocking trench U1 can be formed simultaneously with the first via V1, and the second blocking trench U2 can be formed simultaneously with the second via V2. This effectively reduces the fabrication process requirements for the array substrate 000.

[0116] In one possible scenario, during the manufacturing process of the array substrate 000, the gate line G and the gate electrode 202 in the array substrate 000 are formed simultaneously. When the length of the gate line G is too long, the gate line G is very likely to absorb electric charge during the process. The electric charge absorbed by the gate line G is very likely to break through the insulating layer covering the gate line G after subsequent electrostatic discharge, which may cause a short circuit between the gate line G and the data line D. By reducing the length of the gate line G, the electric charge absorbed by the gate line G during the preparation process can be effectively reduced. For this reason, the gate line G is currently usually designed in a segmented manner, that is, the gate line G can include multiple sub-gate lines arranged side by side, and two adjacent sub-gate lines can be connected by jumpers arranged in different layers. In this way, it is ensured that the length of a single sub-gate line is not too long, and it is also ensured that multiple sub-gate lines can be sequentially connected to form a longer gate line G through jumpers. In this case, since the sub-gate lines are still provided on the same layer as the gate electrode 202 in the thin film transistor 200, the jumper wire located between the two sub-gate lines can be provided on the same layer as the first electrode 203 and the second electrode 204 in the thin film transistor 200. Therefore, the sub-gate lines here can serve as the first bonding electrode 600 in the above embodiment, and the jumper wire located between the two sub-gate lines can serve as the second bonding electrode 700 in the above embodiment.

[0117] In another possible scenario, the array substrate 000 may have a display area and a non-display area located outside the display area. A plurality of sub-pixels may be provided in the display area, and a gate driver circuit (English: Gate Driver on Array, abbreviated as: GOA) may be provided in the non-pixel display area. When the liquid crystal display panel needs to display a picture, the plurality of sub-pixels provided in the display area need to be controlled by the gate driver circuit. The gate driver circuit generally includes a plurality of thin film transistors, and among these thin film transistors, the gate of at least one thin film transistor needs to be electrically connected to the source or drain of other thin film transistors. Therefore, the gate of at least one thin film transistor here can serve as the first lap electrode 600 in the above embodiment, and the source or drain of other thin film transistors can serve as the second lap electrode 700 in the above embodiment.

[0118] In a second optional implementation, when the thin film transistor 200 is a top-gate thin film transistor, please refer to Figure 11, which is a schematic diagram of another film layer structure at the AA' position of the array substrate shown in Figure 2. The gate 202 in the thin film transistor 200 can be located on the side of the active layer 201 facing away from the substrate 100, and the first insulating layer 300 and the first encapsulation layer 401 can both be located on the side of the active layer 201 facing the substrate 100.

[0119] In the present application, the second encapsulation layer 402 in the array substrate 000 can be arranged in contact with the portion of the first encapsulation layer 401 that is not covered by the first insulating portion 301. Here, since the first encapsulation layer 401 is located on the side of the first insulating layer 300 facing the substrate 100, the second encapsulation layer 402 is located on the side of the first insulating layer 300 facing away from the substrate 100. Therefore, when the second encapsulation layer 402 is arranged in contact with the portion of the first encapsulation layer 401 that is not covered by the first insulating portion 301, the first encapsulation layer 401 and the second encapsulation layer 402 cooperate to completely wrap the first insulating portion 301 in the first insulating layer 300 to encapsulate the first insulating portion 301, so that water and oxygen in the external environment will not corrode the first insulating portion 301, and further, will not corrode the active layer 201 in the thin film transistor 200.

[0120] 11 , the array substrate 000 may further include a second insulating layer 500 located on the side of the gate 202 facing away from the substrate 100 . The second insulating layer 500 may be located on the side of the second encapsulation layer 402 facing the substrate 100 .

[0121] In the present application, the second insulating layer 500 in the array substrate 000 may include: a plurality of second insulating portions 501 corresponding to the plurality of thin film transistors 200. Each second insulating portion 501 in the second insulating layer 500 may be disposed in contact with the active layer 201 in the corresponding thin film transistor 200, and the plurality of second insulating portions 501 in the second insulating layer 500 may be disposed separately. It should be noted that to prevent the active layer 201 made of an oxide semiconductor material from being conductive, the second insulating layer 500 must at least include a film layer made of a silicon oxide material with a low hydrogen content.

[0122] For example, in one possible implementation, the second insulating layer 500 may be a single-layer structure made of silicon oxide. For another example, in another possible implementation, the second insulating layer 500 may include: a first sublayer 500a and a second sublayer 500b stacked in a direction away from the substrate 100. The first sublayer 500a may be a film layer made of silicon oxide, and the first sublayer 500a may be disposed in contact with the active layer 201; the second sublayer 500b may be located on the side of the first sublayer 500a facing away from the substrate 100, and the second sublayer 500b may be a film layer made of silicon nitride material with good airtightness. It should be noted that, when the second insulating layer 500 includes a first sub-layer 500a and a second sub-layer 500b that are stacked, by arranging the second sub-layer 500b on the side of the first sub-layer 500a that is away from the substrate 100, it can be ensured that during the preparation process of the array substrate 000, water and oxygen in the external environment will not invade the first sub-layer 500a, so that the probability of the active layer 201 in the thin film transistor 000 being corroded by water and oxygen during the preparation process is low.

[0123] In the embodiment of the present application, referring again to FIG. 11 , the first encapsulation layer 401 in the array substrate 000 may include: a plurality of first encapsulation portions 4011 corresponding to the plurality of first insulating portions 301, and a second encapsulation portion 4012 for connecting the plurality of first encapsulation portions 4011. For example, two adjacent first encapsulation portions 4011 in the first encapsulation layer 401 may be connected via the second encapsulation portion 4012 located therebetween. To this end, the first encapsulation layer 401 may be a continuous, integrated structure.

[0124] Each first encapsulation portion 4011 in the first encapsulation layer 401 may be disposed in contact with the side of the corresponding first insulating portion 301 facing the substrate 100, and the orthographic projection of the first insulating portion 301 on the substrate 100 may be located within the orthographic projection of the first encapsulation portion 4011 on the substrate 100. The first encapsulation portion 4011 may encapsulate the first insulating portion 301 from the side facing the substrate 100, so that water and oxygen in the external environment do not intrude into the first insulating portion 301 from the side facing the substrate 100.

[0125] In the present application, the second encapsulation layer 402 in the array substrate 000 may include: a plurality of third encapsulation portions 4021 corresponding to the plurality of second insulating portions 501, and a fourth encapsulation portion 4022 for connecting the plurality of third encapsulation portions 4021. For example, two adjacent third encapsulation portions 4021 in the second encapsulation layer 402 may be connected by the fourth encapsulation portion 4022 located therebetween. To this end, the second encapsulation layer 402 may be a continuous, single-layer structure.

[0126] Each third encapsulation portion 4021 in the second encapsulation layer 402 may be disposed in contact with the corresponding second insulating portion 501, and the orthographic projection of the second insulating portion 501 on the substrate 100 may be located within the orthographic projection of the third encapsulation portion 4021 on the substrate 100. In this way, the second insulating portion 501 can be encapsulated from the side of the second insulating portion 501 facing away from the substrate 100 by the third encapsulation portion 4021, so that water and oxygen in the external environment will not intrude into the second insulating portion 501 from the side of the second insulating portion 501 facing away from the substrate 100.

[0127] In the embodiment of the present application, the second encapsulation portion 4012 in the first encapsulation layer 401 can be arranged in contact with the fourth encapsulation portion 4022 in the second encapsulation layer 402. In this way, the third encapsulation portion 4021 in the second encapsulation layer 402 can also cover the side surfaces of the first insulating portion 301 and the second insulating portion 501, thereby encapsulating the side surfaces of the first insulating portion 301 and the second insulating portion 501, so that water and oxygen in the external environment will not intrude into the first insulating portion 301 and the second insulating portion 501 from the side surfaces.

[0128] In this case, through the cooperation of the first encapsulation layer 401 and the second encapsulation layer 402, the first insulating part 301 in the first insulating layer 300 and the second insulating part 501 in the second insulating layer 500 can be completely wrapped to encapsulate them, so that water and oxygen in the external environment will not corrode the first insulating part 301 and the second insulating part 501, and thus will not corrode the active layer 201 in the thin film transistor 200.

[0129] In the embodiment of the present application, as shown in FIG11 , the thin film transistor 200 in the array substrate 000 may further include a first electrode 203 and a second electrode 204. The first electrode 203 and the second electrode 204 may both be located on the side of the second insulating portion 501 facing away from the substrate 100. Here, the first electrode 203 refers to one of the source and drain electrodes, and the second electrode 204 refers to the other of the source and drain electrodes.

[0130] Optionally, the second insulating portion 501 may have a third connection via V3 and a fourth connection via V4, wherein the first electrode 203 may be overlapped with the active layer 201 through the third connection via V3, and the second electrode 204 may be overlapped with the active layer 201 through the fourth connection via V4.

[0131] It should be noted that if the thin film transistor 200 in the array substrate 000 is a top-gate thin film transistor, the first insulating layer 300 and the first encapsulation layer 401 in the array substrate 000 can serve as a buffer layer for the top-gate thin film transistor; the second insulating layer 402 in the array substrate 000 can serve as an interlayer dielectric layer for the top-gate thin film transistor; and the second encapsulation layer 401 in the array substrate 000 can serve as a passivation layer for protecting the top-gate thin film transistor. Furthermore, the top-gate thin film transistor may further include a gate insulating layer 205 located between the gate electrode 202 and the active layer 201, which insulates the gate electrode 202 from the active layer 201. Because the gate insulating layer 205 is disposed in contact with the side of the active layer 201 facing the substrate 100, the gate insulating layer 205 also needs to be made of a silicon oxide material with a low hydrogen content.

[0132] In addition, when the thin film transistor 200 in the array substrate 000 is a top-gate thin film transistor, the array substrate 000 may further include a light shielding layer 1000. Here, the light shielding layer 1000 may be located on the side of the active layer 201 in the thin film transistor 200 facing the substrate 100, and the active layer 201 in the thin film transistor 200 may be insulated from the light shielding layer 1000. For example, the light shielding layer 1000 may be located on the side of the first encapsulation layer 401 facing the substrate 100, that is, the first encapsulation layer 401 and the first insulating layer 300 are stacked between the light shielding layer 1000 and the active layer 201, and the first encapsulation layer 401 and the first insulating layer 300 can achieve insulation between the light shielding layer 1000 and the active layer 201.

[0133] The orthographic projection of the active layer 201 in the thin film transistor 200 on the substrate 100 can be located within the orthographic projection of the light shielding layer 1000 on the substrate 100. In this way, the light shielding layer 1002 can effectively reduce the light incident on the active layer 201, so that the electrical performance of the thin film transistor 200 is better.

[0134] For the array substrate 000 in the first and second optional implementations described above, as shown in Figures 4, 5, and 11, the array substrate 000 may further include: a plurality of pixel electrodes 800 electrically connected to the plurality of thin film transistors 200 in a one-to-one correspondence. The second electrode 204 in each thin film transistor 200 in the array substrate 000 may be electrically connected to the corresponding pixel electrode 800.

[0135] Optionally, the array substrate 000 may further include a common electrode layer 900 insulated from the plurality of pixel electrodes 800. The common electrode layer 900 in the array substrate 000 is used to apply a common voltage. The array substrate 000 can apply a pixel voltage to each pixel electrode 800 via the thin film transistor 200. In this way, a voltage difference can be formed between the pixel voltage applied to the pixel electrode 800 and the common voltage applied to the common electrode layer 900. This voltage difference can be used to control the deflection of the liquid crystal corresponding to the pixel electrode 800.

[0136] In the embodiment of the present application, the array substrate 000 may further include: a passivation layer 1100 located between the pixel electrode 800 and the common electrode layer 900 , and a planarization layer 1200 located on a side of the second encapsulation layer 402 facing away from the substrate.

[0137] The planar layer 1200 may be disposed in contact with the side of the second encapsulation layer 402 facing away from the substrate 100, and the planar layer 1200 may cover each thin film transistor 200 in the array substrate 000. Here, the planar layer 1200 may have a plurality of overlapping vias V5, through which the pixel electrode 800 may overlap the second electrode 204 of the thin film transistor 200.

[0138] The common electrode layer 900 in the array substrate 000 may be located on the side of the planar layer 1200 facing away from the substrate 100. Here, since the planar layer 1200 is highly flat, the common electrode layer 1200 disposed on the planar layer 1200 may be highly stable.

[0139] The passivation layer 1100 in the array substrate 000 can be located on the side of the common electrode layer 900 facing away from the substrate 100, and the pixel electrode 800 in the array substrate 000 can be located on the side of the passivation layer 1100 facing away from the substrate 100. Here, the passivation layer 1100 can provide insulation between the pixel electrode 800 and the common electrode layer 900. Furthermore, the passivation layer 1100 can be made of silicon nitride, a material with good airtightness, and a portion of the passivation layer 1100 can extend into the overlapping via V5 and cover the sidewalls of the overlapping via V5. In this way, the passivation layer 1100 can isolate water and oxygen that intrudes through the overlapping via V5, preventing water and oxygen from the external environment from invading the active layer 201 through the overlapping via V5, further reducing the probability of water and oxygen from the external environment invading each first insulating portion 201.

[0140] In summary, the array substrate provided in the embodiment of the present application includes: a substrate, a thin film transistor, a first insulating layer and a packaging structure. Since the first insulating layer in the array substrate can have multiple first insulating parts corresponding to multiple thin film transistors, and the multiple first insulating parts can be separately arranged, the continuity of the first insulating layer can be effectively reduced. In this case, even if the first insulating layer is made of a silicon oxide material with a relatively loose film quality, it can be ensured that the diffusion rate of water and oxygen in the external environment in the first insulating layer is relatively slow. In addition, these first insulating parts can also be packaged by the packaging structure, and the packaging structure has good airtightness, and its effect of isolating water and oxygen in the external environment is better, so that the probability of water and oxygen in the external environment invading each first insulating part is low, thereby reducing the probability of water and oxygen in the external environment invading the active layer in the thin film transistor, effectively reducing the probability of the electrical performance of the thin film transistor being affected, and thereby improving the display effect of the liquid crystal display panel integrated with such an array substrate.

[0141] The present application also provides a liquid crystal display panel. The liquid crystal display panel may include an array substrate and a color filter substrate disposed opposite each other, and a liquid crystal layer located between the array substrate and the color filter substrate. The array substrate may be the array substrate described in the above embodiment. For example, the array substrate may be the array substrate described in the above embodiment.

[0142] The present application also provides a display device, which can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. The display device may include the display panel and backlight module described in the above embodiment, wherein the backlight module may be located on the side of the array substrate facing away from the color filter substrate.

[0143] The present application also provides a method for fabricating a thin film transistor. Since the manufacturing process for an array substrate varies for different types of thin film transistors, the present application will use the following two optional implementations as examples for schematic illustration.

[0144] In a first optional implementation, when the thin film transistor is a bottom-gate thin film transistor, please refer to FIG12 , which is a flow chart of a method for manufacturing an array substrate provided in an embodiment of the present application. The method for manufacturing the array substrate can be used to manufacture the array substrate shown in FIG4 or FIG5 . The method for manufacturing the array substrate may include:

[0145] Step S101: forming a first conductive pattern on a substrate.

[0146] Optionally, the substrate may be a glass substrate, and the material of the first conductive pattern may be a metal material. For example, the material of the data line may be a metal material such as copper, titanium, molybdenum, or an alloy.

[0147] For example, please refer to Figure 13, which is a schematic diagram of a film layer structure for forming a first conductive pattern on a substrate according to an embodiment of the present application. A metal thin film can be formed on one side of the substrate 100 by any of a variety of methods, such as deposition, coating, and sputtering. Then, a single patterning process is performed on the metal thin film to form the first conductive pattern. The first conductive pattern can include the gate 202 of the thin-film transistor 200, a gate line G electrically connected to the gate 202, and a first bonding electrode 600 within the array substrate 000.

[0148] It should be noted that the single patterning process here and the single patterning process in the following embodiments all include: photoresist coating, exposure, development, etching and photoresist stripping.

[0149] Step S102 : forming a first encapsulation layer and a first insulating layer on a side of the first conductive pattern facing away from the substrate.

[0150] Optionally, the material of the first encapsulation layer may include silicon nitride, and the material of the first insulating layer may include silicon oxide. Since silicon oxide has a low hydrogen content, the first insulating layer made of silicon oxide will not directly conduct the subsequently formed active layer 201.

[0151] For example, please refer to Figures 14 and 15. Figure 14 is a schematic diagram of a film structure for forming a first encapsulation layer and a first insulating layer according to an embodiment of the present application, and Figure 15 is a schematic diagram of another film structure for forming a first encapsulation layer and a first insulating layer according to an embodiment of the present application. The first encapsulation layer 401 and the first insulating layer 300 can be sequentially formed on the side of the first conductive pattern facing away from the substrate 100 by any of a variety of methods, such as deposition, coating, and sputtering. Then, a single patterning process is performed on the first insulating layer 300 to form a first blocking trench U1 within the first insulating layer 300, and a second blocking trench U2 communicating with the first blocking trench U1 is formed within the first encapsulation layer 401.

[0152] It should be noted that, in the process of forming the first barrier groove U1 and the second barrier groove U2 through a single patterning process, by controlling the lateral etching speed when etching the first insulating layer 300, and controlling the lateral etching speed when etching the first encapsulation layer 401, the area of ​​the orthographic projection of the first barrier groove U1 on the substrate 100 can be made larger, and the area of ​​the orthographic projection of the second barrier groove U2 on the substrate 100 can also be made larger.

[0153] For example, in one case, as shown in FIG14 , the orthographic projection of the first blocking trench U1 in the first insulating layer 300 on the substrate 100 is located within the orthographic projection of the second blocking trench U2 in the first encapsulation layer 401 on the substrate 100, and the sidewalls of the first blocking trench U1 may be flush with the sidewalls of the second blocking trench U2. In another case, as shown in FIG15 , the opening of the second blocking trench U2 in the first encapsulation layer 401 facing the substrate 100 has a first orthographic projection on the substrate 100, while the opening of the first blocking trench U1 in the first insulating layer 300 facing away from the substrate 100 is located within the second orthographic projection on the substrate 100, and the outer boundaries of the first orthographic projection do not overlap with the outer boundaries of the second orthographic projection.

[0154] Step S103 : forming an active layer and a second conductive pattern on a side of the first insulating layer facing away from the substrate.

[0155] Optionally, the material of the active layer 201 may be a transparent oxide semiconductor material. For example, the material of the active layer 201 may be IGZO. The material of the second conductive pattern may be a metal material. For example, the material of the second conductive pattern may be a metal material such as copper, titanium, molybdenum, or an alloy.

[0156] For example, please refer to Figures 16 and 17. Figure 16 is a schematic diagram of a film structure for forming an active layer and a second conductive pattern, provided in an embodiment of the present application. Figure 17 is a schematic diagram of another film structure for forming an active layer and a second conductive pattern, provided in an embodiment of the present application. A semiconductor thin film can be formed on the side of the first insulating layer 300 facing away from the substrate 100 by any of a variety of methods, such as deposition, coating, or sputtering. Then, a single patterning process is performed on this semiconductor thin film to form the active layer 201 of the thin-film transistor 200. Subsequently, a metal thin film can be formed on the side of the active layer 201 facing away from the substrate 100 by any of a variety of methods, such as deposition, coating, or sputtering. Then, a single patterning process is performed on this metal thin film to form the second conductive pattern. The second conductive pattern can include the first electrode 203 and the second electrode 204 of the thin-film transistor 200, a data line D electrically connected to the first electrode 203 of the thin-film transistor 200, and a second bonding electrode 700 within the array substrate 000.

[0157] Step S104 : forming a second insulating layer and a second encapsulation layer on a side of the second conductive pattern facing away from the substrate.

[0158] Optionally, the second insulating layer may be made of silicon oxide. Since silicon oxide has a low hydrogen content, a second insulating layer made of silicon oxide will not directly convert the already formed active layer 201 into a conductor. The second encapsulation layer may be made of silicon nitride. Silicon nitride generally has a low viscosity, and therefore, a film structure formed using silicon nitride has good coverage.

[0159] For example, please refer to Figures 18 and 19. Figure 18 is a schematic diagram of a film structure for forming a second insulating layer and a second encapsulation layer according to an embodiment of the present application, and Figure 19 is a schematic diagram of another film structure for forming a second insulating layer and a second encapsulation layer according to an embodiment of the present application. The second insulating layer 500 and the second encapsulation layer 402 can be sequentially formed on the side of the second conductive pattern facing away from the substrate 100 by any of a variety of methods, such as deposition, coating, and sputtering.

[0160] In one possible scenario, as shown in Figure 18, when the orthographic projection of the first blocking groove U1 on the substrate 100 is located within the orthographic projection of the second blocking groove U2 on the substrate 100, the second insulating layer 400 formed on the side of the second conductive pattern facing away from the substrate 100 belongs to a whole layer structure continuously distributed at various positions, that is, the portion of the second insulating layer 400 located within the first blocking groove U1 and the second blocking groove U2 is connected to the portion of the second insulating layer 400 located outside the first blocking groove U1 and the second blocking groove U2.

[0161] In another possible scenario, as shown in Figure 19, when the first orthographic projection of the opening of the second barrier groove U2 toward the substrate 100 on the substrate 100 is located within the second orthographic projection of the opening of the first barrier groove U1 away from the substrate 100 on the substrate 100, and the outer boundary of the first orthographic projection does not coincide with the outer boundary of the second orthographic projection, the portion of the second insulating layer 400 located within the first barrier groove U1 and the second barrier groove U2 is disconnected from the portion of the second insulating layer 400 located outside the first barrier groove U1 and the second barrier groove U2.

[0162] It should be noted that, since the second packaging layer 400 has good coverage, the second packaging layer 402 can better package the second packaging layer 500 regardless of the structure of the second insulating layer 500 shown in FIG18 or the structure of the second insulating layer 500 shown in FIG19 .

[0163] Step S105 : forming a planarization layer, a common electrode layer, a passivation layer, and a pixel electrode in sequence on a side of the second encapsulation layer facing away from the substrate.

[0164] In the embodiment of the present application, a planar layer, a common electrode layer, a passivation layer and a pixel electrode can be sequentially formed on the side of the second encapsulation layer facing away from the substrate to obtain the array substrate shown in FIG. 4 or 5 .

[0165] In a second optional implementation, when the thin film transistor is a top-gate thin film transistor, please refer to FIG20 , which is a flow chart of another method for manufacturing an array substrate provided in an embodiment of the present application. This method for manufacturing an array substrate can be used to manufacture the array substrate shown in FIG11 . This method for manufacturing an array substrate may include:

[0166] Step S201: forming a light shielding layer on a substrate.

[0167] Optionally, the substrate may be a glass substrate, and the light shielding layer may be made of a metal material, for example, copper, titanium, molybdenum, or an alloy thereof.

[0168] For example, please refer to Figure 21, which is a schematic diagram of a film structure for forming a light-shielding layer on a substrate provided in an embodiment of the present application. A metal film can be formed on one side of the substrate 100 by any of a variety of methods such as deposition, coating, sputtering, etc., and then a patterning process is performed on the metal film to form the light-shielding layer 1000.

[0169] Step S202 : forming a first encapsulation layer and a first insulating layer on a side of the light shielding layer facing away from the substrate.

[0170] Optionally, the material of the first encapsulation layer may include silicon nitride, and the material of the first insulating layer may include silicon oxide. Since silicon oxide has a low hydrogen content, the first insulating layer made of silicon oxide will not directly conduct the subsequently formed active layer 201.

[0171] For example, please refer to Figure 22, which is a schematic diagram of another film structure for forming a first encapsulation layer and a first insulating layer according to an embodiment of the present application. The first encapsulation layer 401 and the first insulating layer 300 can be formed on the side of the light shielding layer 1000 facing away from the substrate 100 by any of a variety of methods, such as deposition, coating, and sputtering.

[0172] Step S203 : forming an active layer, a gate insulating layer and a gate on a side of the first insulating layer facing away from the substrate.

[0173] Optionally, the active layer may be made of a transparent oxide semiconductor material. For example, the active layer may be made of IGZO. The gate insulating layer may be made of silicon oxide, so that the active layer is not directly conductive. The gate may be made of a metal material. For example, the gate may be made of copper, titanium, molybdenum, or an alloy thereof.

[0174] For example, please refer to Figure 23, which is a schematic diagram of a film structure for forming an active layer, a gate insulating layer, and a gate provided in an embodiment of the present application. A semiconductor thin film can be formed on the side of the first insulating layer 300 facing away from the substrate 100 by any of a variety of methods such as deposition, coating, and sputtering. Then, a single patterning process is performed on the semiconductor thin film to form the active layer 201. Thereafter, a gate insulating layer 205 and a metal thin film can be sequentially formed on the side of the active layer 201 facing away from the substrate 100 by any of a variety of methods such as deposition, coating, and sputtering. Then, a single patterning process is performed on the metal thin film to form the gate 202. Here, the gate 202 can be insulated from the active layer 201 by the gate insulating layer 205.

[0175] In the present application, after forming the gate 202 in the array substrate 000, the gate 202 can be used as a mask to etch the gate insulating layer 205, thereby retaining the portion of the gate insulating layer 205 covered by the gate 202 and removing the remaining portion of the gate insulating layer 205. Subsequently, the active layer 201 can be made conductive using the gate 202 and the etched gate insulating layer 205 as masks. After the active layer 201 is made conductive, the portion of the active layer 201 not covered by the gate insulating layer 205 becomes a conductive portion, while the portion of the active layer 201 not covered by the gate insulating layer 205 becomes a semiconductor portion. This semiconductor portion is the channel region in the active layer 201.

[0176] Step S204 : forming a second insulating layer on a side of the gate facing away from the substrate.

[0177] Optionally, the second insulating layer may include a first sublayer and a second sublayer. The first sublayer may be made of silicon oxide, and the second sublayer may be made of silicon nitride. Since silicon oxide has a low hydrogen content, the first sublayer made of silicon oxide will not directly convert the already formed active layer into a conductor.

[0178] For example, please refer to Figure 24, which is a schematic diagram of another film layer structure for forming a second insulating layer provided in an embodiment of the present application. A first sublayer 500a and a second sublayer 500b can be sequentially formed on the side of the gate 202 facing away from the substrate 100 by any of a variety of methods, such as deposition, coating, and sputtering. The first sublayer 500a and the second sublayer 500b can constitute the second insulating layer 500, with the first sublayer 500a being closer to the substrate 100 than the second sublayer 500b.

[0179] In an embodiment of the present application, after forming the second insulating layer 500, it is necessary to perform a patterning process on the second insulating layer 500 to form a third connecting via V3 and a fourth connecting via V4. For example, please refer to Figure 25, which is a schematic diagram of forming a third connecting via and a fourth connecting via provided in an embodiment of the present application. The second insulating layer 500 can be subjected to a patterning process once to form a third via V3 and a fourth via V4 that penetrate the second insulating layer 500. The orthographic projections of the third via V3 and the fourth via V4 on the substrate 100 are both located within the orthographic projection of the active layer 201 on the substrate 100, so that the first pole 203 formed subsequently can overlap with the active layer 201 through the third via V3, and the second pole 204 formed subsequently can overlap with the active layer 204 through the fourth via V4.

[0180] It should be noted that, during the process of forming the third via hole V3 and the fourth via hole V4, the portion of the second insulating layer 500 located outside the thin film transistor 200 and the portion of the first insulating layer 300 located outside the thin film transistor 200 may also be removed, so that the second insulating layer 500 may include multiple separately arranged second insulating portions 501, and the first insulating layer 300 may include multiple separately arranged first insulating portions 301. The multiple first insulating portions 301 may be disposed in contact with the active layers 201 of the multiple thin film transistors 200, and the multiple second insulating portions 302 may be disposed in contact with the active layers 201 of the multiple thin film transistors 200.

[0181] Step S205 : forming a second conductive pattern on a side of the second insulating layer facing away from the substrate.

[0182] Optionally, the material of the second conductive pattern may be a metal material. For example, the material of the second conductive pattern may be a metal material such as copper, titanium, molybdenum, or an alloy.

[0183] For example, please refer to Figure 26, which is a schematic diagram of a film structure for forming a second conductive pattern on the side of the second insulating layer facing away from the substrate, provided in an embodiment of the present application. A metal film can be formed on the side of the second insulating layer 500 facing away from the substrate 100 by any of a variety of methods, such as deposition, coating, and sputtering. The metal film is then subjected to a single patterning process to form the second conductive pattern. The second conductive pattern may include a first electrode 203 connected to the active layer 201 via a third connecting via V3, and a second electrode 204 connected to the active layer 201 via a fourth connecting via V4.

[0184] Step S206 : forming a second encapsulation layer on a side of the second conductive pattern facing away from the substrate.

[0185] Optionally, the second encapsulation layer may be silicon nitride. The viscosity of the group formed by silicon nitride material is generally low, so the film structure formed by using silicon nitride material has good coverage.

[0186] For example, please refer to Figure 27, which is a schematic diagram of another film layer structure for forming a second encapsulation layer provided in an embodiment of the present application. The second encapsulation layer 402 can be formed on the side of the metal layer facing away from the substrate 100 by any of a variety of methods such as deposition, coating, and sputtering. Here, the second encapsulation layer 402 cooperates with the first encapsulation layer 401 to completely encapsulate the first insulating portion 301 and the second insulating portion 501.

[0187] Step S207 : forming a planarization layer, a common electrode layer, a passivation layer, and a pixel electrode in sequence on a side of the second encapsulation layer facing away from the substrate.

[0188] In an embodiment of the present application, a planarization layer, a common electrode layer, a passivation layer and a pixel electrode may be sequentially formed on the side of the second encapsulation layer facing away from the substrate, thereby obtaining the array substrate shown in FIG. 11 .

[0189] Those skilled in the art will clearly understand that for the convenience and brevity of description, the principles of the various film layer structures in the array substrate described above can refer to the corresponding contents in the aforementioned structural embodiment of the array substrate and will not be repeated here.

[0190] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it may be the only layer between the two layers or elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0191] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "plurality" refers to two or more than two, unless expressly limited otherwise.

[0192] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. An array substrate, characterized in that, include: substrate; A plurality of thin film transistors located on one side of the substrate, the thin film transistors comprising: an active layer; a first insulating layer located on a side of the active layer facing the substrate, the first insulating layer comprising: a plurality of first insulating portions corresponding to the plurality of thin film transistors, the first insulating portions being arranged in contact with the active layers in the corresponding thin film transistors, and the plurality of first insulating portions being arranged separately; And, a packaging structure for packaging each of the first insulating parts, a part of the packaging structure is distributed between two adjacent first insulating parts.

2. The array substrate according to claim 1, wherein The packaging structure includes: a first packaging layer and a second packaging layer, the first packaging layer is located on the side of the first insulating layer facing the substrate, the second packaging layer is located on the side of the active layer away from the substrate, and a part of the second packaging layer is distributed between two adjacent first insulating parts.

3. The array substrate according to claim 2, wherein The thin film transistor further comprises: a gate insulated from the active layer, the gate being located on a side of the active layer facing the substrate, and the first insulating layer and the first encapsulation layer being located between the gate and the active layer; The first insulating layer has a first blocking groove between two adjacent first insulating parts, the first encapsulation layer has a second blocking groove connected to the first blocking groove, and a portion of the second encapsulation layer extends into the first blocking groove and the second blocking groove.

4. The array substrate according to claim 3, wherein The array substrate further comprises: a second insulating layer located on a side of the active layer away from the substrate, the second insulating layer being located on a side of the second encapsulation layer facing the substrate; The second insulating layer comprises: a plurality of second insulating portions corresponding to the plurality of thin film transistors, and a third insulating portion located between two adjacent second insulating portions; The second insulating portion is arranged in contact with the active layer in the corresponding thin film transistor, and the third insulating portion is located in the second blocking groove.

5. The array substrate according to claim 4, wherein The orthographic projection of the first barrier groove on the substrate is located within the orthographic projection of the second barrier groove on the substrate, and the second insulating layer also includes: a connecting portion for connecting the second insulating portion and the third insulating portion, the connecting portion is attached to the side wall of the first barrier groove and the side wall of the second barrier groove, and the thickness of the connecting portion facing the third insulating portion is less than the thickness of the connecting portion facing the second insulating portion.

6. The array substrate according to claim 5, wherein Along a direction from the second insulating portion to the third insulating portion, a thickness of the connecting portion gradually decreases.

7. The array substrate according to claim 4, wherein A first orthographic projection of an opening of the second blocking groove facing the substrate on the substrate is located within a second orthographic projection of an opening of the first blocking groove facing away from the substrate on the substrate, and an outer boundary of the first orthographic projection does not overlap with an outer boundary of the second orthographic projection; The second insulating portion is disposed separately from the third insulating portion.

8. The array substrate according to claim 7, wherein The first encapsulation layer comprises: a plurality of first encapsulation parts corresponding to the plurality of first insulating parts, and a second blocking groove is provided between two adjacent first encapsulation parts; The edge of the first insulating portion protrudes from the edge of the corresponding first packaging portion.

9. The array substrate according to any one of claims 3 to 8, characterized in that, The first blocking groove is in a ring shape, and the orthographic projection of the thin film transistor on the substrate is located in a region enclosed by the orthographic projection of the first blocking groove on the substrate.

10. The array substrate according to any one of claims 3 to 8, characterized in that, The thin film transistor further comprises: a first electrode and a second electrode overlapped with the active layer, wherein the first electrode and the second electrode are both located on a side of the active layer away from the substrate; The array substrate further includes: a first overlapping electrode and a second overlapping electrode, wherein the first overlapping electrode is disposed in the same layer and made of the same material as the gate electrode, and the second overlapping electrode is disposed in the same layer and made of the same material as the first electrode and the second electrode; The first insulating layer further has a first connecting via hole, and the first encapsulation layer further has a second connecting via hole communicating with the first connecting via hole; The second bonding electrode is bonded to the first bonding electrode through the first connection via hole and the second connection via hole in sequence.

11. The array substrate according to claim 2, wherein, The thin film transistor further comprises: a gate insulated from the active layer, the gate being located on a side of the active layer away from the substrate, and the first insulating layer and the first encapsulation layer being located on a side of the active layer facing the substrate; The second encapsulation layer is arranged in contact with a portion of the first encapsulation layer that is not covered by the first insulating portion.

12. The array substrate according to claim 11, wherein The array substrate further comprises: a second insulating layer located on a side of the gate away from the substrate, the second insulating layer being located on a side of the second encapsulation layer facing the substrate; The second insulating layer includes: a plurality of second insulating portions corresponding to the plurality of thin film transistors; The second insulating portion is arranged in contact with the active layer in the corresponding thin film transistor, and the plurality of second insulating portions are arranged separately.

13. The array substrate according to claim 12, wherein The first encapsulation layer comprises: a plurality of first encapsulation parts corresponding to the plurality of first insulating parts one by one, and a second encapsulation part for connecting the plurality of first encapsulation parts, wherein the first encapsulation part is arranged in contact with the corresponding first insulating part, and the orthographic projection of the first insulating part on the substrate is located within the orthographic projection of the first encapsulation part on the substrate; The second encapsulation layer comprises: a plurality of third encapsulation parts corresponding to the plurality of second insulating parts, and a fourth encapsulation part for connecting the plurality of third encapsulation parts, wherein the third encapsulation parts are arranged in contact with the corresponding second insulating parts, and the orthographic projection of the second insulating part on the substrate is located within the orthographic projection of the third encapsulation part on the substrate; The third packaging part can cover the side surfaces of the first insulating part and the second insulating part; and the second packaging part is arranged in contact with the fourth packaging part.

14. The array substrate according to claim 12 or 13, wherein The thin film transistor also includes: a first electrode and a second electrode, the first electrode and the second electrode are both located on the side of the second insulating part away from the substrate, and the second insulating part has a third connecting via and a fourth connecting via, the first electrode is overlapped with the active layer through the third connecting via, and the second electrode is overlapped with the active layer through the fourth connecting via.

15. The array substrate according to any one of claims 1-8, 12-13, characterized in that The array substrate further includes: a plurality of pixel electrodes electrically connected to the plurality of thin film transistors in a one-to-one correspondence.

16. A liquid crystal display panel, characterized in that, include: An array substrate and a color filter substrate which are oppositely arranged, and a liquid crystal layer located between the array substrate and the color filter substrate, wherein the array substrate is the array substrate according to any one of claims 1 to 15.

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