Storage array and manufacturing method therefor, memory, and electronic device

Abstract

Embodiments of the present application relate to the technical field of semiconductors, and disclose a storage array and a manufacturing method therefor, a memory, and an electronic device. The storage array comprises a substrate and a memory cell chain. The memory cell chain comprises a first transistor group, a storage capacitor group, and a second transistor group. The first transistor group comprises a plurality of first transistors connected in series. The storage capacitor group is located on the side of the first transistor group distant from the substrate. The storage capacitor group comprises a plurality of storage capacitors, and first electrode plates of the plurality of storage capacitors are respectively electrically connected to first electrodes of the plurality of first transistors. The second transistor group is located on the side of the storage capacitor group distant from the substrate. The second transistor group comprises a plurality of second transistors connected in series. Second electrode plates of the plurality of storage capacitors are respectively electrically connected to second electrodes of the plurality of second transistors. The storage array is a chain-type storage architecture, the storage capacitors are 3D capacitors, and the second transistor group is provided, so that contact structures between the second electrode plates and the first transistors are omitted, facilitating reduction of the size of a memory cell.

Description

Storage array and preparation method thereof, memory, and electronic device Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a memory array and a preparation method thereof, a memory, and an electronic device. Background Art

[0002] Memory is a device that stores data. Based on its data retention characteristics, memory can be divided into volatile and non-volatile memory. Volatile dynamic random access memory (DRAM) has been widely used due to its fast data processing speed and high reliability. While memory storage density continues to increase with the advancement of integrated circuit technology, the size of DRAM has essentially reached its limit.

[0003] Ferroelectric memories primarily include ferroelectric random access memory (FeRAM or FRAM) and ferroelectric field-effect transistor (FeFET) memory. As an emerging memory type, ferroelectric memory boasts data processing speeds comparable to DRAM. Furthermore, ferroelectric memory is compatible with back-end-of-line (BEOL) processes, enabling large-capacity non-volatile storage through stacking.

[0004] At present, most ferroelectric memories have a planar device structure, which is limited by the process and is difficult to further reduce the area of ​​the storage unit and further increase the storage density, and thus it is difficult to meet the requirements of electronic devices for storage read and write speeds.

[0005] Summary of the Invention

[0006] Embodiments of the present application provide a memory array and a method for manufacturing the same, a memory, and an electronic device, for reducing the area of ​​a memory cell and improving storage density.

[0007] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0008] In a first aspect, a memory array is provided, comprising: a substrate, and at least one memory cell chain located on one side of the substrate. The memory cell chain comprises: a first transistor group, a storage capacitor group, and a second transistor group. The first transistor group is located on one side of the substrate. The first transistor group comprises a plurality of first transistors connected in series. The storage capacitor group is located on a side of the first transistor group away from the substrate. The storage capacitor group comprises a plurality of storage capacitors, each storage capacitor comprising a first electrode plate, a storage functional layer, and a second electrode plate, the storage functional layer at least surrounding the second electrode plate, and the first electrode plate at least surrounding the storage functional layer. The first electrodes of the plurality of storage capacitors are respectively electrically connected to the first electrodes of the plurality of first transistors. The second transistor group is located on a side of the storage capacitor group away from the substrate. The second transistor group comprises a plurality of second transistors connected in series. The second electrodes of the plurality of storage capacitors are respectively electrically connected to the second electrodes of the plurality of second transistors.

[0009] The storage array provided by some embodiments of the present application improves the structure of the storage cell chain, adds multiple second transistors on the side of the storage capacitor group away from the substrate, and sets the multiple second transistors in series, and adjusts the electrical connection relationship between each storage capacitor in the storage capacitor group and each first transistor in the first transistor group, so that the first plate of each storage capacitor is electrically connected to the first pole of the first transistor, and the second plate of each storage capacitor is electrically connected to the second pole of the second transistor. On the basis of using the first transistor to control the potential on the first plate of the storage capacitor, the second transistor can be used to control the potential of the second plate of the storage capacitor without the need for the first transistor to control the potential of the second plate of the storage capacitor, thereby avoiding the need to set contact contacts. In this way, on the one hand, it is possible to avoid etching to form a contact through hole with a large aspect ratio for accommodating the contact structure, which is conducive to reducing the difficulty of preparing the storage array. On the other hand, it is possible to avoid increasing the size of the first transistor and / or the second transistor due to the setting of the contact structure, which is conducive to reducing the size and area of ​​the storage unit, and facilitating the realization of a 4F in a strict sense. 2 Minimum storage unit size, improving the storage density of the storage array.

[0010] In a possible design of the first aspect, the memory cell chain includes: a plurality of first gates. The plurality of first gates are located between a substrate and a storage capacitor group, and are spaced apart along a first direction parallel to the substrate. The first gate includes a gate of a first transistor. The first gate and the substrate are disposed independently of each other, which reduces the difficulty of manufacturing the first gates and simplifies the memory array fabrication process.

[0011] In a possible design of the first aspect, the memory cell chain further includes: a first gate dielectric layer, a first channel layer, and first electrodes of multiple first transistors. The first gate dielectric layer is located between the multiple first gates and the storage capacitor group. The first gate dielectric layer serves as the gate dielectric layer for the multiple first transistors. The first channel layer is located between the first gate dielectric layer and the storage capacitor group. The orthographic projection of the first channel layer on the substrate partially overlaps with the orthographic projection of the multiple first gates on the substrate. The first channel layer serves as the channels for the multiple first transistors. The first electrodes of the multiple first transistors are located between the first channel layer and the storage capacitor group. The first electrodes of the multiple first transistors are spaced apart along a first direction. In their orthographic projection on the substrate, the first electrodes and the first gates of the first transistors are alternately arranged. The first electrodes of the multiple first transistors contact the first channel layer and respectively contact the first plates of the multiple storage capacitors. The channels of the multiple first transistors in the first transistor group are integrally structured, and the multiple first transistors can be connected in series via the first channel layer. This helps simplify the structure of the memory cell chain, the fabrication process of the memory array, and reduces the difficulty of fabricating the memory array.

[0012] In a possible design of the first aspect, the first electrode of the (i+1)th first transistor shares the second electrode of the (i)th first transistor, where i is a positive integer. This reduces the number of second electrodes of the first transistors, further simplifying the structure of the memory cell chain and the memory array fabrication process, thereby reducing the difficulty of fabricating the memory array.

[0013] In a possible design of the first aspect, a memory cell chain includes: second electrodes of multiple second transistors, a second channel layer, a second gate dielectric layer, and multiple second gates. The second electrodes of the multiple second transistors are located on a side of the storage capacitor group away from the substrate. The second electrodes of the multiple second transistors are in contact with the second plates of the multiple storage capacitors, respectively. The second channel layer is located on a side of the second electrodes of the second transistors away from the substrate. The second channel layer is in contact with the second electrodes of the multiple second transistors. The second channel layer serves as channels for the multiple second transistors. The second gate dielectric layer is located on a side of the second channel layer away from the substrate. The second gate dielectric layer serves as a gate dielectric layer for the multiple second transistors. The multiple second gates are located on a side of the second gate dielectric layer away from the substrate. The multiple second gates are spaced apart along a first direction. In an orthographic projection onto the substrate, the second electrodes and second gates of the second transistors are alternately arranged; the first direction is parallel to the substrate. The second gates include the gates of the second transistors. The channels of the multiple second transistors in the second transistor group are integrated, and the multiple second transistors can be connected in series via the second channel layer. This simplifies the structure of the memory cell chain, simplifies the fabrication process of the memory array, and reduces the difficulty of fabricating the memory array.

[0014] In a possible design of the first aspect, the second electrode of the second transistor and the second electrode plate in contact therewith are integrally structured. This avoids the need for additional fabrication of the second electrode of the second transistor, thereby simplifying the structure of the second transistor group, thereby reducing the thickness of the memory array, simplifying the memory array fabrication process, and reducing the difficulty of fabricating the memory array.

[0015] In a possible design of the first aspect, the second electrode plate protrudes from the first electrode plate in a direction perpendicular to and away from the substrate. The memory array further includes an isolation layer. The isolation layer is positioned between the first electrode plate and the second channel layer, surrounding the portion of the second electrode plate that protrudes from the first electrode plate. This isolation layer can provide electrical insulation between adjacent second electrode plates and between the first electrode plate and the second channel layer, thereby preventing crosstalk.

[0016] In a possible design of the first aspect, the second electrode of the i-th second transistor shares the first electrode of the (i+1)-th first transistor, where i is a positive integer. This reduces the number of first electrodes of the second transistors, further simplifying the structure of the memory cell chain and the memory array fabrication process, thereby reducing the difficulty of fabricating the memory array.

[0017] In a possible design of the first aspect, the storage cell chain includes a plurality of first gates and a plurality of second gates, the plurality of first gates being located between the substrate and the storage capacitor group, and the plurality of second gates being located on a side of the storage capacitor group away from the substrate. The first gate includes the gate of the first transistor, and the second gate includes the gate of the second transistor. Along a first direction, the orthographic projections of the first gate and the second gate located between two adjacent storage capacitors on the substrate at least partially overlap. The first direction is parallel to the substrate. This can make the arrangement of the first transistor group and the second transistor group more compact, reduce the area occupied by the first transistor group and the second transistor group, and thus help reduce the area occupied by the storage cell chain, further improving the storage density of the storage array.

[0018] In a possible design mode of the first aspect, the first transistor and the second transistor electrically connected to the same storage capacitor are respectively the first target transistor and the second target transistor. The material of the gate of the first target transistor is the same as the material of the gate of the second target transistor. And / or, the size of the gate of the first target transistor is the same as the size of the gate of the second target transistor. This is conducive to reducing the difference in performance of the first transistor and the second transistor electrically connected to the same storage capacitor, improving the consistency of the performance of the first transistor and the second transistor electrically connected to the same storage capacitor, and facilitating the synchronous conduction or synchronous cutoff of the first transistor and the second transistor electrically connected to the same storage capacitor.

[0019] In a possible design method of the first aspect, the storage cell chain includes a first channel layer and a second channel layer, the first channel layer is located between the substrate and the storage capacitor group, and the second channel layer is located on the side of the storage capacitor group away from the substrate. The first channel layer is a channel for a plurality of first transistors, and the second channel layer is a channel for a plurality of second transistors. The orthographic projection of the first channel layer on the substrate and the orthographic projection of the second channel layer on the substrate at least partially overlap. This can make the arrangement of the first transistor group and the second transistor group more compact, reduce the area occupied by the first transistor group and the second transistor group, and thus help reduce the area occupied by the storage cell chain, further improving the storage density of the storage array. In addition, the first channel layer and the second channel layer can be prepared and formed using the same mask plate, which helps reduce the preparation cost of the storage array.

[0020] In a possible design of the first aspect, the material of the first channel layer is the same as that of the second channel layer. And / or the size of the first channel layer is the same as that of the second channel layer. This helps reduce the performance differences between the first transistor and the second transistor electrically connected to the same storage capacitor, improves the performance consistency of the first transistor and the second transistor electrically connected to the same storage capacitor, and facilitates synchronous turning on or off of the first transistor and the second transistor electrically connected to the same storage capacitor.

[0021] In a possible design of the first aspect, the storage array includes a first gate dielectric layer and a second gate dielectric layer, the first gate dielectric layer is located between the substrate and the storage capacitor group, and the second gate dielectric layer is located on the side of the storage capacitor group away from the substrate. The first gate dielectric layer is the gate dielectric layer of the plurality of first transistors, and the second gate dielectric layer is the gate dielectric layer of the plurality of second transistors. The orthographic projection of the first gate dielectric layer on the substrate and the orthographic projection of the second gate dielectric layer on the substrate at least partially overlap. This can reduce the area occupied by the first transistor group and the second transistor group, thereby helping to reduce the area occupied by the storage cell chain and further improve the storage density of the storage array. In addition, the first gate dielectric layer and the second gate dielectric layer can be prepared and formed using the same mask plate, which helps to reduce the preparation cost of the storage array.

[0022] In a possible design of the first aspect, the material of the first gate dielectric layer is the same as the material of the second gate dielectric layer. And / or the size of the first gate dielectric layer is the same as the size of the second gate dielectric layer. This helps reduce the performance difference between the first transistor and the second transistor electrically connected to the same storage capacitor, improves the performance consistency of the first transistor and the second transistor electrically connected to the same storage capacitor, and facilitates the synchronous turning on or off of the first transistor and the second transistor electrically connected to the same storage capacitor.

[0023] In a possible design of the first aspect, the first transistor and the second transistor electrically connected to the same storage capacitor are respectively a first target transistor and a second target transistor. The gate of the first target transistor and the gate of the second target transistor are electrically connected. This allows the potentials of the gates of the first target transistor and the second target transistor to remain consistent, facilitating synchronous control of the on / off states of the first target transistor and the second target transistor.

[0024] In a possible design manner of the first aspect, the first transistor and the second transistor are both back-end process transistors.

[0025] In a possible design of the first aspect, the two first transistors located at opposite ends of the first transistor group are respectively a first input transistor and a first output transistor, and the two second transistors located at opposite ends of the second transistor group are respectively a second input transistor and a second output transistor. The first input transistor and the second input transistor are electrically connected to the same storage capacitor, and the first output transistor and the second output transistor are electrically connected to the same storage capacitor. The storage array further includes: a plate line, a word line, a selection transistor, a bit line, and a selection signal line. The plate line is electrically connected to the first electrode of the first input transistor and the first electrode of the second input transistor. The word line is electrically connected to the gates of the first transistor and the second transistor electrically connected to the same storage capacitor. The first electrode of the selection transistor is electrically connected to the second electrode of the first output transistor and the second electrode of the second output transistor. The bit line is electrically connected to the second electrode of the selection transistor. The selection signal line is electrically connected to the gate of the selection transistor. These multiple structures cooperate with each other to realize data reading and writing.

[0026] In a possible design of the first aspect, there are multiple memory cell chains. At least two memory cell chains are arranged sequentially along a first direction, and at least two memory cell chains are arranged sequentially along a second direction. Both the first direction and the second direction are parallel to the substrate and intersect. This facilitates increasing the size of the memory array and improving storage density.

[0027] In a possible design of the first aspect, at least two memory cell chains are arranged sequentially along a third direction, which is perpendicular to the substrate. This can increase the size and storage density of the memory array while improving space utilization and reducing the cost per bit of the memory cell.

[0028] In a possible design of the first aspect, the storage functional layer includes a ferroelectric material layer, a resistive material layer, or a phase change material layer. Accordingly, the storage array can be applied to a ferroelectric memory, a resistive memory, or a phase change memory.

[0029] In a possible design of the first aspect, the gate of the first transistor and the gate of the second transistor are used to receive a control signal, the first electrode of the first transistor is used to receive a plate line signal, and the second electrode of the second transistor is used to receive or output a bit line signal.

[0030] In a second aspect, a method for preparing a storage array is provided, the method comprising: providing a substrate. Forming a first transistor group on one side of the substrate; the first transistor group includes a plurality of first transistors connected in series. Forming a storage capacitor group on a side of the first transistor group away from the substrate; the storage capacitor group includes a plurality of storage capacitors, the storage capacitors including a first plate, a storage functional layer, and a second plate, the storage functional layer at least surrounding the second plate, and the first plate at least surrounding the storage functional layer; the first plates of the plurality of storage capacitors are respectively electrically connected to the first electrodes of the plurality of first transistors. Forming a second transistor group on a side of the storage capacitor group away from the substrate; the second transistor group includes a plurality of second transistors connected in series; the second plates of the plurality of storage capacitors are respectively electrically connected to the second electrodes of the plurality of second transistors.

[0031] In a possible design of the second aspect, forming a first transistor group on one side of a substrate includes forming a plurality of first gates on one side of the substrate. The plurality of first gates are spaced apart along a first direction parallel to the substrate. The first gates include gates of first transistors.

[0032] In a possible design of the second aspect, a first transistor group is formed on one side of a substrate, further comprising: forming a first gate dielectric layer and a first channel layer on a side of the multiple first gates away from the substrate; the orthographic projection of the first channel layer on the substrate partially overlaps with the orthographic projections of the multiple first gates on the substrate; the first gate dielectric layer serves as the gate dielectric layer for the multiple first transistors, and the first channel layer serves as the channels for the multiple first transistors. First electrodes of multiple first transistors are formed on a side of the first channel layer away from the substrate; the first electrodes of the multiple first transistors are spaced apart along a first direction; in their orthographic projections on the substrate, the first electrodes and the first gates of the first transistors are alternately arranged; the first electrodes of the multiple first transistors are in contact with the first channel layer and respectively with the first plates of the multiple storage capacitors.

[0033] In a possible design of the second aspect, forming a storage capacitor group on a side of the first transistor group remote from the substrate includes: forming a dielectric layer on a side of the first transistor group remote from the substrate; forming a plurality of first through-holes penetrating the dielectric layer; the plurality of first through-holes respectively exposing the first electrodes of the plurality of first transistors; forming a first electrode plate, a storage functional layer, and a second electrode plate within each of the first through-holes; the first electrode plate contacting the first electrode of the first transistor through the first through-holes.

[0034] In a possible design of the second aspect, a first electrode plate, a storage function layer, and a second electrode plate are formed within each first through hole, including: forming a first conductive film on the inner wall of each first through hole, the first conductive film also being located on the side of the dielectric layer away from the substrate. Removing the portion of the first conductive film located on the side of the dielectric layer away from the substrate, while retaining the portion of the first conductive film covering the inner wall of each first through hole, thereby obtaining the first electrode plate. Sequentially forming a storage function film and a second conductive film within each first through hole, the storage function film and the second conductive film also being located on the side of the dielectric layer away from the substrate; the portion of the storage function film located within the first through hole constitutes the storage function layer. Removing at least the portion of the second conductive film located above the storage function film, thereby obtaining the second electrode plate; the second electrode plate protrudes from the first electrode plate.

[0035] In a possible design of the second aspect, forming a first electrode plate, a storage functional layer, and a second electrode plate within each first through hole includes sequentially forming a first conductive film, a storage functional film, and a second conductive film within each first through hole, wherein the first conductive film, the storage functional film, and the second conductive film are also located on a side of the dielectric layer away from the substrate. Portions of the second conductive film, the storage functional film, and the first conductive film located on the side of the dielectric layer away from the substrate are removed, while retaining portions of the second conductive film, the storage functional film, and the first conductive film located within each first through hole, thereby obtaining the first electrode plate, the storage functional layer, and the second electrode plate.

[0036] Before forming the second transistor group on the side of the storage capacitor group facing away from the substrate, the fabrication method further includes: etching at least the dielectric layer and the first electrode plate so that the second electrode plate protrudes from the first electrode plate; and forming an isolation layer on the dielectric layer and the first electrode plate; the isolation layer surrounds the portion of the second electrode plate that protrudes from the first electrode plate.

[0037] In a possible design of the second aspect, a second transistor group is formed on a side of the storage capacitor group away from the substrate, including: forming a second channel layer on the side of the storage capacitor group away from the substrate; the second channel layer contacts the second plates of the multiple storage capacitors; the second channel layer serves as channels for the multiple second transistors. A second gate dielectric layer is formed on a side of the second channel layer away from the substrate; the second gate dielectric layer serves as the gate dielectric layer for the multiple second transistors. Multiple second gates are formed on a side of the second gate dielectric layer away from the substrate; the multiple second gates are spaced apart along a first direction; in an orthographic projection on the substrate, the second plates and the second gates are alternately arranged; the first direction is parallel to the substrate; and the second gates include the gates of the second transistors.

[0038] In a third aspect, a memory is provided, comprising: a memory array as described in any embodiment of the first aspect and a controller. The controller is electrically connected to the memory array and is used to control reading and writing of the memory array.

[0039] In a fourth aspect, an electronic device is provided, comprising: a memory as described in any embodiment of the third aspect and a circuit board, wherein the circuit board is electrically connected to the memory.

[0040] The technical effects brought about by any design method in the second to fourth aspects can refer to the technical effects brought about by different design methods in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] FIG1 is an architecture diagram of an electronic device provided in an embodiment of the present application;

[0042] FIG2 is an architectural diagram of a memory provided in an embodiment of the present application;

[0043] FIG3 is an architectural diagram of another memory provided in an embodiment of the present application;

[0044] FIG4 is an architectural diagram of another memory provided in an embodiment of the present application;

[0045] FIG5 is an equivalent circuit diagram of a memory cell provided in an embodiment of the present application;

[0046] FIG6 is a schematic diagram of a hysteresis loop of a memory cell provided in an embodiment of the present application;

[0047] FIG7 is a structural diagram of a storage array provided in an embodiment of the present application;

[0048] FIG8 is an equivalent circuit diagram of the memory array shown in FIG7 ;

[0049] FIG9 is a structural diagram of another storage array provided in an embodiment of the present application;

[0050] FIG10 is a structural diagram of another storage array provided in an embodiment of the present application;

[0051] FIG11 is a structural diagram of another storage array provided in an embodiment of the present application;

[0052] FIG12 is an equivalent circuit diagram of a memory array provided in an embodiment of the present application;

[0053] FIG13 is an equivalent circuit diagram of a memory cell chain provided in an embodiment of the present application;

[0054] FIG14a is a cross-sectional structural diagram of a storage array provided in an embodiment of the present application;

[0055] FIG14 b is a cross-sectional structural diagram of another memory array provided in an embodiment of the present application;

[0056] FIG15 is a cross-sectional structural diagram of another memory array provided in an embodiment of the present application;

[0057] FIG16 is a cross-sectional structural diagram of another memory array provided in an embodiment of the present application;

[0058] FIG17 is a top view of a storage capacitor group provided in an embodiment of the present application;

[0059] FIG18 is a top view of a first transistor group according to an embodiment of the present application;

[0060] FIG19 is a timing diagram of a memory array provided in an embodiment of the present application;

[0061] FIG20 is a timing diagram of another memory array provided in an embodiment of the present application;

[0062] FIG21 is a flow chart of a method for preparing a memory array according to an embodiment of the present application;

[0063] 22a to 22d are structural diagrams corresponding to the steps in a method for manufacturing a memory array according to an embodiment of the present application;

[0064] 23a to 23h are structural diagrams corresponding to the steps in another method for manufacturing a memory array provided in an embodiment of the present application;

[0065] 24a to 24b are structural diagrams corresponding to the steps in another method for manufacturing a memory array provided in an embodiment of the present application;

[0066] 25a to 25f are structural diagrams corresponding to the steps in another method for manufacturing a memory array provided in an embodiment of the present application;

[0067] 26a to 26e are structural diagrams corresponding to the steps in another method for manufacturing a memory array provided in an embodiment of the present application;

[0068] 27a to 27b are structural diagrams corresponding to the steps in another method for preparing a memory array provided in an embodiment of the present application. DETAILED DESCRIPTION

[0069] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0070] In the description of this application, unless otherwise specified, "plurality" means two or more than two. "At least one item" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or plural.

[0071] "And / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, and B exists alone. A and B can be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0072] In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, words such as "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. Those skilled in the art will understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit differences. At the same time, in the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete way for easy understanding.

[0073] In this application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed mechanical connection, a detachable mechanical connection, or an integrated connection; or, "connection" can be a direct connection or an indirect connection through an intermediate medium.

[0074] In addition, unless otherwise clearly specified and limited, the term "electrical connection" should be understood in a broad sense. For example, "electrical connection" can be a direct electrical connection, such as physical contact and electrical conduction between two components. It can also be understood as the electrical connection between different components in the circuit structure through physical lines such as printed circuit board (PCB) copper foil or wires that can transmit electrical signals to transmit electrical signals; or, "electrical connection" can be an indirect electrical connection between two components through an intermediate medium; or, "electrical connection" can be an electrical connection between two components in an air / non-contact manner, for example, two components are electrically connected by capacitive coupling to transmit electrical signals.

[0075] In the embodiments of the present application, the descriptions "vertical" and "parallel" respectively indicate approximately vertical and approximately parallel within a certain error range, and the error range may be a range in which the deviation angle relative to absolute vertical and absolute parallel is less than or equal to 5°, 8° or 10°, respectively, and no specific limitation is made here.

[0076] In the embodiments of the present application, "upper," "lower," "left," and "right" are not limited to being defined relative to the orientation of components schematically shown in the drawings. It should be understood that these directional terms can be relative concepts. They are used for relative description and clarification and may change accordingly depending on the orientation of the components in the drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity, and the dimensional ratios between the components in the drawings do not reflect the actual dimensional ratios.

[0077] This application describes exemplary embodiments with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown in this application, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0078] In addition, the architecture and scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field can know that with the evolution of the architecture and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0079] An embodiment of the present application provides an electronic device. The electronic device can be applied to various communication systems or communication protocols, such as: Bluetooth (BT) communication technology, global positioning system (GPS) communication technology, global system of mobile communication (GSM) communication technology, wireless fidelity (WiFi) communication technology, wideband code division multiple access wireless (WCDMA) communication technology, long term evolution (LTE), 5G communication technology, and other future communication technologies.

[0080] The electronic device in the embodiments of the present application may be a mobile phone, a tablet computer (pad), a laptop computer, a smart home, a smart wearable device (e.g., a smart watch, a smart bracelet, smart glasses, a smart helmet), a virtual reality (VR) electronic device, an augmented reality (AR) electronic device, etc. The electronic device may also be a handheld device with wireless communication capabilities, a computing device or other processing device connected to a wireless modem, an in-vehicle device, an electronic device in a 5G network, or an electronic device in a future-evolved public land mobile network (PLMN), etc., and the embodiments of the present application are not limited thereto.

[0081] Figure 1 is an architecture diagram of an electronic device provided in an embodiment of the present application. As shown in Figure 1, the electronic device 1000 may include a circuit board 100, a bus 200 and a processor 300. The bus 200 is located on the circuit board 100 and is electrically connected to the circuit board 100. The processor 300 is located on the circuit board 100 and is connected to the bus 200. Among them, the circuit board 100 is, for example, a PCB, and the processor 300 is, for example, a system on chip (SoC), which can be used to process data, such as processing application data, processing image data, and caching temporary data. Optionally, the system on chip may include an application processor (AP) 310 for processing applications, a graphics processing unit (GPU) 320 for processing image data, and a first RAM 330 for caching high-speed data. The first RAM 330 may be a static random access memory (SRAM) or an embedded flash memory (eFlash), etc. The application processor 300 , the image processing unit 320 , and the first RAM 330 may be integrated into one die, or may be separately provided in multiple die.

[0082] Continuing with FIG1 , the electronic device 1000 may further include a second RAM 400 , which may be connected to the processor 300 via the bus 200 . The second RAM 400 may be a DRAM. The second RAM 400 may be used to store volatile data, such as temporary data generated by the aforementioned system-on-chip. The storage capacity of the second RAM 400 may generally be greater than the storage capacity of the first RAM 330 , but the read speed of the second RAM 400 is generally slower than the read speed of the first RAM 330 .

[0083] In addition, the electronic device 1000 may also include a communication chip 500 and a power management chip 600, and the communication chip 500 and the power management chip 600 are both connected to the processor 300 via the bus 200. The communication chip 500 can be used for processing the protocol stack, or for amplifying, filtering, and other processing of analog radio frequency signals, or for realizing the above functions simultaneously. The power management chip 600 can be used to power other chips. Exemplarily, the above-mentioned system on chip and the second RAM 400 can be packaged in the same packaging structure. For example, the system on chip and the second RAM 400 can be packaged using 2.5D (dimension) or 3D (three-dimensional) packaging to obtain a faster data transmission rate between chips.

[0084] The present application also provides a memory device, including but not limited to ferroelectric random access memory (FRAM), resistive random access memory (RRAM), and phase change memory (PCM). The memory device is used in the electronic device described above. In some embodiments, the memory device can be used as the first RAM 330 or the second RAM 400 in FIG. The present application does not limit the application scenarios of the memory device.

[0085] FIG2 , FIG3 , and FIG4 respectively illustrate a memory architecture.

[0086] In some examples, as shown in Figures 2 and 3 , the memory 700 may include a memory array 710 and a controller 720. The controller 720 is configured to access the memory array 710. The controller 720 is electrically connected to the memory array 710 and may be configured to control read and write operations of the memory array 710. The number of memory arrays 710 may be one, two, three, or even more. Figures 2 and 3 both illustrate four memory arrays 710.

[0087] For example, as shown in FIG2 , in the memory 700, the memory array 710 and the controller 720 can be two independent chips. The memory array 710 and the controller 720 can be separately disposed on a carrier board (e.g., a packaged transistor chain or an adapter board), and the memory array 710 and the controller 720 are electrically connected to the carrier board. In this way, the memory array 710 and the controller 720 can achieve signal transmission via metal traces within the carrier board. Based on this, the memory 700 with the memory array 710 can be referred to as a stand-alone memory.

[0088] Alternatively, for example, in the memory 700, the memory array 710 and the controller 720 may be two independent chips, stacked on the carrier board. The memory array 710 and the controller 720 may be electrically connected via through silicon vias (TSVs) or redistribution layers (RDLs), enabling signal transmission between the memory array 710 and the controller 720 and the carrier board. Similarly, the memory 700 with the memory array 710 may be referred to as a stand-alone memory.

[0089] Alternatively, for another example, as shown in FIG3 , in the above-mentioned memory 700, the memory array 710 is stacked on the controller 720. The memory array 710 and the controller 720 can be integrated into the same chip, and the integrated chip is electrically connected to the above-mentioned carrier board. Based on this, the memory 700 with the above-mentioned memory array 710 can be called an embedded memory. The architecture of the memory 700 can be called a circuit-under-array (CUA) architecture. The controller 720 can be prepared by the front-end of line (FEOL) process, and the memory array 710 can be stacked up layer by layer along the thickness direction of the controller 720 by the back-end process. The memory array 710 is connected to the corresponding circuit of the front-end (i.e., the circuit included in the controller 720) through the back-end metal interconnect layer. The CUA architecture has a relatively high area efficiency. The stacking of the memory array 710 by the back-end process is conducive to further improving the storage density, thereby reducing the cost per bit of the memory unit.

[0090] In some examples, as shown in FIG4 , each memory array 710 includes multiple memory cells MC arranged in an array, each of which can be used to store one or more bits of data. The controller 720 includes, for example, one or more circuit structures including a decoder 721, a driver 722, a timing controller 723, a buffer 724, and an input / output (I / O) driver circuit 725. The circuit structures in the controller 720 are electrically connected to the memory cells MC in the memory array 710 via signal lines. The decoder 721 is used to decode the addresses of the memory cells MC. The decoder 721 is used to decode the received addresses to determine the memory cell MC to be accessed. The driver 722 is used to control the levels of the aforementioned signal lines based on the decoding results generated by the decoder 721, thereby enabling access to the specified memory cell MC. The buffer 724 is used to cache read data, for example, using a FIFO (first-in, first-out) cache. The timing controller 723 is used to control the timing of the buffer 724 and control the driver 722 to drive the signal lines in the storage array 710. The input / output driver circuit 725 is used to drive transmission signals, such as driving received data signals and driving data signals to be transmitted, so that data signals can be transmitted over long distances. The above-mentioned storage array 710, decoder 721, driver 722, timing controller 723, buffer 724 and input / output driver circuit 725 can be integrated into a single chip or integrated into multiple chips. In addition, the controller 720 may also include circuit structures such as a sense amplifier (SA) and a decoder.

[0091] FIG5 is an equivalent circuit diagram of a memory cell provided in an embodiment of the present application. In some examples, as shown in FIG5 , the memory cell MC may include a transistor Tr and a storage capacitor C, wherein the gate of the transistor Tr is electrically connected to a word line (WL), the source (or drain) of the transistor Tr is electrically connected to a plate line (PL), the drain (or source) of the transistor Tr is electrically connected to one electrode of the storage capacitor C, and the other electrode of the storage capacitor C is electrically connected to a bit line (BL). FIG5 is merely an example of a memory cell MC having a 1T1C (one-transistor-one-capacitor) structure. The embodiments of the present application do not limit the number of transistors Tr and storage capacitors C in the memory cell MC.

[0092] Exemplarily, the storage capacitor C includes: a first electrode plate and a second electrode plate disposed opposite each other, and a storage functional layer disposed between the first electrode plate and the second electrode plate. The storage functional layer includes, but is not limited to, a ferroelectric material layer, a resistive material layer, or a phase change material layer. When the storage functional layer is a ferroelectric material layer, the memory is a ferroelectric memory. When the storage functional layer is a resistive material layer, the memory is a resistive memory. When the storage functional layer is a phase change material layer, the memory is a phase change memory.

[0093] The principles of data storage of the above-mentioned types of memories are basically similar. For example, by forming an electric field between the first plate and the second plate of the above-mentioned storage capacitor C, the state of the storage functional layer can be changed. By utilizing the change in the state of the storage functional layer, data storage can be achieved.

[0094] The present application embodiment uses a ferroelectric material layer as the storage functional layer and a ferroelectric memory as an example. The ferroelectric material layer comprises a ferroelectric material, which acts as an insulating dielectric, enabling the storage capacitor C to form a ferroelectric capacitor. Ferroelectric memory utilizes the characteristics of ferroelectric materials that can undergo spontaneous polarization and reorient their polarization state in response to an external electric field to store data.

[0095] For example, when a positive voltage is applied to the first plate and a negative voltage is applied to the second plate, an electric field is formed between the first plate and the second plate. Under the action of this electric field, the polarity of the ferroelectric material in the ferroelectric material layer is directed toward the first plate. When a negative voltage is applied to the first plate and a positive voltage is applied to the second plate, an electric field is formed between the first plate and the second plate. Under the action of this electric field, the polarity of the ferroelectric material in the ferroelectric material layer is directed toward the second plate.

[0096] Specifically, when an electric field is applied to a ferroelectric material, its central atoms follow the electric field and remain in a low-energy state. Conversely, when the electric field is reversed and applied to the same ferroelectric material, its central atoms move within the crystal in the direction of the electric field and remain in another low-energy state. A large number of central atoms move and couple within the crystal unit cell to form ferroelectric domains. Ferroelectric domains, under the action of an electric field, form polarized charges (also called flip charges). The flip charges formed by flipping ferroelectric domains under the action of an electric field are higher, while the flip charges formed by not flipping ferroelectric domains under the action of an electric field are lower. This binary stable state of ferroelectric materials allows ferroelectric materials to be used as memory devices. By taking advantage of the different directions of the remanent polarization intensity, applying an electric field in the same direction produces different flip charges, which can be used to store data '0' and '1', as shown in Figure 6.

[0097] When an electric field is applied to a ferroelectric material crystal, the central atom moves in the crystal along the direction of the electric field. As the atom moves, it passes through an energy barrier, causing charge breakdown. After the electric field is removed, the central atom can maintain its position and the polarization state can be maintained. Therefore, the ferroelectric memory formed by ferroelectric materials has the characteristics of non-volatility, that is, the ferroelectric memory will not lose the stored data when the power is cut off.

[0098] It is understandable that the above-mentioned ferroelectric memories are mostly planar device structures. For example, the transistors in the ferroelectric memories are mostly horizontal channel transistors, and the ferroelectric capacitors are mostly planar MIM (metal-insulator-metal) capacitor structures. This planar device structure is limited by the process and it is difficult to further reduce the area of ​​the memory cell MC and further increase the storage density. In this case, the horizontal channel transistors can be replaced with vertical channel transistors to reduce the area of ​​the memory cell MC. However, compared with horizontal channel transistors, the preparation of vertical channel transistors is more complicated.

[0099] Furthermore, during the data reading and writing process in the ferroelectric memory, the transistor Tr in the memory cell MC participating in the data reading and writing (or "selected") is in the on state, while the transistor Tr in the memory cell MC not participating in the data reading and writing (or "unselected") is in the off state. When signals on the plate line and bit line switch, a voltage drop occurs across the transistor Tr in the memory cell MC not participating in the data reading and writing. This makes it easy for the memory cell MC not participating in the data reading and writing to leak current through the transistor Tr to the storage node (SN), thereby causing crosstalk to the data stored in the memory cell MC not participating in the data reading and writing.

[0100] In this case, an embodiment of the present application provides a memory array. FIG7 is a structural diagram of a memory array provided by an embodiment of the present application; FIG8 is an equivalent circuit diagram of the memory array shown in FIG7 .

[0101] As shown in Figures 7 and 8 , the transistor Tr and storage capacitor C included in a single memory cell MC are arranged in parallel. For example, one electrode of the storage capacitor C is electrically connected to the source of the transistor Tr, and the other electrode of the storage capacitor C is electrically connected to the drain of the transistor Tr. Furthermore, the transistors Tr of multiple memory cells MC are connected in series in a NAND manner, forming a chain storage architecture.

[0102] In FIG7 , the transistor Tr is a horizontal channel transistor, which can reduce the area of ​​the memory cell without increasing the difficulty of manufacturing the memory.

[0103] Furthermore, during data reading and writing in the chained storage architecture, the transistors Tr in the memory cells MC participating in the data reading and writing are in the off state, while the transistors Tr in the memory cells MC not participating in the data reading and writing are in the on state. Therefore, there is virtually no voltage drop across the transistors Tr in the memory cells MC not participating in the data reading and writing, and thus crosstalk is substantially eliminated from the data stored in the memory cells MC not participating in the data reading and writing.

[0104] The storage capacitor C in the chain storage architecture described above uses a planar MIM capacitor structure. Ferroelectric memory has certain requirements for the polarization charge of the storage capacitor C in the memory cell MC, and therefore, the area of ​​the storage capacitor C is also limited. However, the storage capacitor structure of the planar MIM capacitor is difficult to scale down sustainably.

[0105] Figure 9 is a structural diagram of another storage array provided in an embodiment of the present application. In Figure 9, the storage capacitor C adopts a 3D capacitor structure, in which the first plate of the storage capacitor C surrounds the second plate. The storage array includes a dielectric layer located on a plurality of transistors Tr, and the storage capacitor C penetrates the dielectric layer so that the first plate of the storage capacitor C is electrically connected to the source (or drain) of the transistor Tr; the second plate of the storage capacitor C is electrically connected to the drain (or source) of the transistor Tr via a contact structure CT penetrating the dielectric layer.

[0106] For storage capacitors C with a planar MIM capacitor structure and storage capacitors C with a 3D capacitor structure, when both have the same capacitance, the storage capacitor C with a 3D capacitor structure occupies a smaller area on a horizontal plane (e.g., parallel to the substrate mentioned below). This allows for sustainable scaling of the storage capacitor C, based on a certain amount of polarized charge in the storage capacitor C, thereby reducing the size and area of ​​the memory cell MC without affecting the capacity of the memory 700.

[0107] However, to ensure the polarized charge capacity of the storage capacitor C, the height of the storage capacitor C is relatively large, and accordingly, the thickness of the dielectric layer is relatively large. Before forming the contact structure CT, it is necessary to etch contact holes with a high aspect ratio in the dielectric layer, which undoubtedly increases the difficulty of manufacturing the above-mentioned memory array.

[0108] Moreover, the contact structure CT needs to occupy a certain area. In order to make the contact structure CT form a good connection with the transistor Tr, the size of the transistor Tr needs to be increased. This means that the setting of the contact structure CT limits the size and area of ​​the memory cell MC, and limits the memory from achieving a strict 4F 2 Minimum storage unit size.

[0109] Based on this, an embodiment of the present application also provides a storage array, which can be a chain storage architecture. The storage cells in the storage array are, for example, 2T1C (that is, two transistors and one storage capacitor) structures, and the storage capacitor of each storage cell adopts a 3D capacitor structure. The two transistors in each storage cell are respectively located at the upper and lower ends of the storage capacitor, and the multiple transistors located below each storage capacitor are arranged in series, and the multiple transistors located above each transistor are arranged in series. This reduces the setting of the above-mentioned contact structure CT, and can also avoid etching to form contact through holes for accommodating the contact structure CT, thereby reducing the difficulty of preparing the storage array and avoiding increasing the size of the transistor due to the setting of the contact structure CT, which is beneficial to reducing the size and area of ​​the storage cell and facilitating the realization of 4F in a strict sense. 2 Minimum storage unit size.

[0110] Figures 10 and 11 are structural diagrams of a memory array provided in embodiments of the present application. In some examples, as shown in Figures 10 and 11, the memory array 710 includes a substrate 1 and a memory cell chain 2, which is located on one side of substrate 1. Memory cell chain 2 is used to store data. Optionally, the number of memory cell chains 2 can be one, two, three, or even more.

[0111] In the case where there are multiple memory cell chains 2, the multiple memory cell chains 2 can be arranged in a variety of ways, which can be selected according to actual needs. The memory array 710 has a first direction X, a second direction Y, and a third direction Z. The first direction X and the second direction Y are both parallel to the substrate 1 and intersect (e.g., are perpendicular to) the first direction X and the second direction Y. The third direction Z is perpendicular to the substrate 1.

[0112] In some examples, as shown in FIG10 , at least two memory cell chains 2 are sequentially arranged along a first direction X, and at least two memory cell chains 2 are sequentially arranged along a second direction Y. That is, the multiple memory cell chains 2 in the memory array 710 are arranged in an array of multiple rows and columns. In other words, the multiple memory cell chains 2 in the memory array 710 include multiple columns of memory cell chains 2 arranged along the first direction X, and each column of memory cell chains 2 includes multiple memory cell chains 2 arranged along the second direction Y.

[0113] For example, FIG. 10 schematically illustrates twelve memory cell chains 2 , which are arranged in three columns along a first direction X. Each column of memory cell chains 2 includes four memory cell chains 2 arranged along a second direction Y.

[0114] In this way, the size of the memory array can be increased and the storage density of the memory array 710 can be improved while avoiding increasing the thickness of the memory array 710 .

[0115] In other examples, as shown in FIG11 , at least two memory cell chains 2 are sequentially arranged along a first direction X, at least two memory cell chains 2 are sequentially arranged along a second direction Y, and at least two memory cell chains 2 are sequentially arranged along a third direction Z. That is, in addition to being arranged in an array shape within a plane, the multiple memory cell chains 2 in the memory array 710 are also stacked in layers in the third direction Z. In other words, the multiple memory cell chains 2 in the memory array 710 are arranged as multiple layers of memory cell chains 2 along the third direction Z, and the multiple memory cell chains 2 in each layer of memory cell chains 2 include multiple columns of memory cell chains 2 arranged along the first direction X, and each column of memory cell chains 2 includes multiple memory cell chains 2 arranged along the second direction Y.

[0116] For example, FIG11 illustrates twenty-four storage cell chains 2, which are arranged in two layers along a third direction Z. Each layer of storage cell chains 2 includes twelve storage cell chains 2. In each layer of storage cell chains 2, the twelve storage cell chains 2 are arranged in three columns along a first direction X. Each column of storage cell chains 2 includes four storage cell chains 2 arranged along a second direction Y.

[0117] Exemplarily, the memory array 710 further includes a first insulating layer 3. Along the third direction Z, the first insulating layer 3 is located between two adjacent memory cell chains 2. This first insulating layer 3 can separate two adjacent memory cell chains 2 along the third direction Z, thereby improving the structural stability of the upper memory cell chain 2. Figure 11 only illustrates a partial structure of the first insulating layer 3 and does not define the overall structure of the first insulating layer 3.

[0118] In this way, the size of the storage array can be increased, the storage density of the storage array 70 can be improved, the space utilization rate can be improved, and the cost per unit bit of the storage unit can be reduced.

[0119] Figure 12 is an equivalent circuit diagram of a memory array provided in an embodiment of the present application, and Figure 13 is an equivalent circuit diagram of a memory cell chain provided in an embodiment of the present application; Figures 14a, 15, and 16 are respectively cross-sectional structural diagrams of a memory array along a first direction corresponding to the equivalent circuit diagram shown in Figure 12, and Figure 14b is a cross-sectional structural diagram of a memory array along a second direction corresponding to the equivalent circuit diagram shown in Figure 12.

[0120] In some examples, as shown in FIG. 12 to FIG. 16 , the memory cell chain 2 includes a first transistor group 21 , a storage capacitor group 22 , and a second transistor group 23 .

[0121] As shown in Figures 14a, 15, and 16, the first transistor group 21 is located on one side of the substrate 1. The first transistor group 21 includes a plurality of first transistors 211, which are arranged in sequence along the first direction X and connected in series. For example, the first transistor 211 includes a gate 211a, a first electrode 211b, and a second electrode 211c, wherein one of the first electrode 211b of the first transistor 211 and the second electrode 211c of the first transistor 211 is a drain and the other is a source, which can be determined based on the type of the first transistor 211. In the first transistor group 21, the gates 211a of each first transistor 211 are independently arranged, and the second electrode 211c of the i-th first transistor 211 is electrically connected to the first electrode 211b of the i+1-th first transistor 211, so that the plurality of first transistors 211 are connected in series to form a first transistor chain. Wherein, i is a positive integer.

[0122] The first transistor 211 is, for example, a complementary metal-oxide semiconductor (CMOS) transistor.

[0123] As shown in Figures 14a, 15 and 16, the storage capacitor group 22 is located on the side of the first transistor group 21 away from the substrate 1. The storage capacitor group 22 includes a plurality of storage capacitors C, which are arranged in sequence along the first direction X. Different storage capacitors C are not in direct contact. Each storage capacitor C includes a first plate 221, a storage function layer 223 and a second plate 222, wherein, as shown in Figure 17, the storage function layer 223 at least surrounds the second plate 222, and the first plate 221 at least surrounds the storage function layer 223.

[0124] For example, the second electrode plate 222 is provided in a columnar shape, including but not limited to a cylindrical shape, a square column shape, etc. The second electrode plate 222 extends along the third direction Z.

[0125] Optionally, the material of the second electrode 222 includes but is not limited to TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver) and other conductive materials or any combination thereof.

[0126] The structure of the storage function layer 223 includes various types, which can be selected according to actual needs. For example, the storage function layer 223 is arranged in a tubular shape, including but not limited to a circular tubular shape, a square tubular shape, etc. The second electrode 222 is located in the storage function layer 223, so that the storage function layer 223 surrounds the second electrode plate 222. For another example, the storage function layer 223 is in the shape of a long barrel, as shown in Figures 14a, 15 and 16. The cross-sectional shape of the storage function layer 223 along the first direction X is U-shaped, and a portion of the storage function layer 223 surrounds the periphery of the second electrode plate 222, and the other portion is located between the first transistor group 21 and the second electrode plate 222. The storage function layer 223 and the second electrode plate 222 can be in direct contact, or other film layer structures can be provided between the storage function layer 223 and the second electrode plate 222.

[0127] Optionally, the above-mentioned storage function layer 223 includes a ferroelectric material layer, a resistive layer material or a phase change material layer. For example, the ferroelectric material layer includes, for example, a hafnium-based ferroelectric dielectric (or HfO2-based ferroelectric dielectric). The ferroelectric material layer material includes, but is not limited to, HZO, ZrO2 (zirconium oxide), HfO2 (hafnium dioxide), Al-doped HfO2, Si (silicon)-doped HfO2, Zr-doped HfO2, La (lanthanum)-doped HfO2, Y (yttrium)-doped HfO2, etc., or materials doped with other elements based on the material (for example, HfO2) and any combination thereof. The material of the resistive material layer includes, but is not limited to, NiOx, TaOx, TiOx, HfOx, WOx, ZrOx, AlyOx, SrTiOx, etc. The material of the phase change material layer includes, but is not limited to, GeTe alloy, Sb2Te5 alloy, Ge2Sb2Te5, etc.

[0128] The structure of the first electrode plate 221 includes various types, which can be selected according to actual needs. For example, the first electrode plate 221 is configured in a tubular shape, including but not limited to a circular tube shape, a square tube shape, etc. The second electrode plate 222 and the storage function layer 223 are located inside the first electrode plate 221, so that the first electrode plate 221 surrounds the storage function layer 223. For another example, the first electrode plate 221 is in the shape of a long barrel, as shown in Figures 14a, 15 and 16. The cross-sectional diagram of the first electrode plate 221 along the first direction X is U-shaped, and a portion of the first electrode plate 221 surrounds the periphery of the storage function layer 223, and another portion is located between the first transistor group 21 and the storage function layer 223. The first electrode plate 221 and the storage function layer 223 can be in direct contact, or other film layer structures can be provided between the first electrode plate 221 and the storage function layer 223.

[0129] Optionally, the material of the first electrode plate 221 includes but is not limited to TiN, Ti, Au, W, Mo, ITO, Al, Cu, Ru, Ag and other conductive materials or any combination thereof. The material of the first electrode plate 221 and the material of the second electrode plate 222 can be the same or different.

[0130] The storage capacitor C is a 3D capacitor structure. This can reduce the area occupied by the storage capacitor C on a horizontal plane (eg, a surface parallel to the substrate) while ensuring that the storage capacitor C has a certain amount of charge, thereby achieving sustainable miniaturization of the storage capacitor C.

[0131] As shown in Figures 14a, 15 and 16, the second transistor group 23 is located on the side of the storage capacitor group 22 away from the substrate 1. The second transistor group 23 includes a plurality of second transistors 231, which are arranged in sequence along the first direction X and connected in series. For example, the second transistor 231 includes a gate 231a, a first electrode 231b and a second electrode 231c, wherein one of the first electrode 231b of the second transistor 231 and the second electrode 231c of the second transistor 231 is a drain and the other is a source, which can be determined according to the type of the second transistor 231. In the second transistor group 23, the gates 231a of each second transistor 231 are independently arranged, and the second electrode 231c of the i-th second transistor 231 is electrically connected to the first electrode 231b of the i+1-th second transistor 231, so that the plurality of second transistors 231 are connected in series to form a second transistor chain. Wherein, i is a positive integer.

[0132] The second transistor 231 is, for example, a complementary metal oxide semiconductor transistor.

[0133] Continuing to refer to Figures 14a, 15, and 16, the first plates 221 of the plurality of storage capacitors C are electrically connected to the first electrodes 211b of the plurality of first transistors 211, respectively. That is, the plurality of storage capacitors C and the plurality of first transistors 211 are provided in a one-to-one correspondence, and the first plate 221 of each storage capacitor C is electrically connected to the first electrode 211b of the corresponding first transistor 211. The second plates 222 of the plurality of storage capacitors C are electrically connected to the second electrodes 231c of the plurality of second transistors 231, respectively. That is, the plurality of storage capacitors C and the plurality of second transistors 231 are provided in a one-to-one correspondence, and the second plate 222 of each storage capacitor C is electrically connected to the second electrode 231c of the corresponding second transistor 231.

[0134] Exemplarily, as shown in Figures 14a, 15, and 16, the orthographic projection of the storage capacitor C on the substrate 1 and the orthographic projection of the first transistor 211 electrically connected thereto on the substrate 1 at least partially overlap. In other words, the orthographic projection of the storage capacitor C on the substrate 1 is located within the orthographic projection of the first transistor 211 electrically connected thereto on the substrate 1; alternatively, the orthographic projection of the storage capacitor C on the substrate 1 and the orthographic projection of the first transistor 211 electrically connected thereto on the substrate 1 partially overlap.

[0135] As shown in Figures 14a, 15, and 16, the orthographic projection of the storage capacitor C on the substrate 1 and the orthographic projection of the second transistor 231 electrically connected thereto on the substrate 1 at least partially overlap. In other words, the orthographic projection of the storage capacitor C on the substrate 1 is located within the orthographic projection of the second transistor 231 electrically connected thereto on the substrate 1; alternatively, the orthographic projection of the storage capacitor C on the substrate 1 and the orthographic projection of the second transistor 231 electrically connected thereto on the substrate 1 partially overlap.

[0136] It is understood that the storage capacitor C and the first transistor 211 and the second transistor 231 electrically connected thereto are used to form a memory cell MC with a 2T1C architecture. In this case, the first transistor group 21, the second transistor group 23, and the storage capacitor group 22 connected between the first transistor group 21 and the second transistor group 23 can form the above-mentioned chain storage architecture. In this case, the arrangement of the memory cells MC is more compact, which helps to reduce the size of the memory array 710 and the memory 700 having the memory array 710, so that the memory 700 has high density and high speed characteristics.

[0137] During the process of reading and writing data in the above-mentioned memory array 710, the first transistor 211 and the second transistor 231 in the memory cell MC participating in the data reading and writing are both in the off state, and the first transistor 211 and the second transistor 231 in the memory cell MC not participating in the data reading and writing are both in the on state. For example, in FIG13 , the memory cell MC participating in the data reading and writing is the target memory cell MC0. In conjunction with FIG13 and FIG14 a , the first plate 221 of the storage capacitor C in the target memory cell MC0 can receive signals passing through the first transistors 211 on its left side; the second plate 222 of the storage capacitor C in the target memory cell MC0 can receive signals passing through the second transistors 231 on its right side, or transmit signals to the second transistors 231 on its right side, to achieve data writing or reading.

[0138] Since there is almost no voltage drop across the first transistor 211 and the second transistor 231 of the memory cell MC not involved in data reading or writing, crosstalk to the data stored in the memory cell MC not involved in data reading or writing can be avoided.

[0139] In addition, after the architecture of the memory cell MC is improved to a 2T1C architecture, the second electrode 222 of each memory cell MC only needs to be connected to the second electrode 231c of the corresponding second transistor 231, without being connected to the second electrode 211c of the corresponding first transistor 211 through a contact contact, thereby eliminating the need for a contact contact.

[0140] Therefore, the storage array 710 provided in some embodiments of the present application improves the structure of the storage cell chain 2, adds multiple second transistors 231 on the side of the storage capacitor group 22 away from the substrate 1, and arranges the multiple second transistors 231 in series, and adjusts the electrical connection relationship between each storage capacitor C in the storage capacitor group 22 and each first transistor 211 in the first transistor group 21, so that the first plate 221 of each storage capacitor C is electrically connected to the first pole 211b of the first transistor 211, and the second plate 222 of each storage capacitor C is electrically connected to the second pole 231c of the second transistor 231. On the basis of using the first transistor 211 to control the potential on the first plate 221 of the storage capacitor C, the second transistor 231 can be used to control the potential of the second plate 222 of the storage capacitor C, without the need for the first transistor 211 to control the potential of the second plate 222 of the storage capacitor C, thereby avoiding the need to set contact points. On the one hand, this can avoid etching to form a contact hole with a large aspect ratio for accommodating the contact structure, which is conducive to reducing the difficulty of manufacturing the memory array 710. On the other hand, it can avoid increasing the size of the first transistor 211 and / or the second transistor 231 due to the arrangement of the contact structure, which is conducive to reducing the size and area of ​​the memory cell MC and facilitating the realization of a strict 4F 2The minimum memory cell size improves the storage density of the memory array 710 .

[0141] The structure of the first transistor group 21 in the memory cell chain 2 is schematically described below with reference to the accompanying drawings.

[0142] In the above-mentioned first transistor group 21 , there are many ways to connect the multiple first transistors 211 in series, which can be selected and set according to actual needs.

[0143] In some examples, the first electrode 211b and the second electrode 211c of each first transistor 211 are independently provided. The second electrode 211c of the i-th first transistor 211 and the first electrode 211b of the (i+1)-th first transistor 211 can be electrically connected via other conductive structures.

[0144] In other examples, as shown in Figures 13 and 14a, the first electrode 211b of the (i+1)th first transistor 211 is shared as the second electrode 211c of the (i)th first transistor 211. "Shared" means that the first electrode 211b of the (i+1)th first transistor 211 and the second electrode 211c of the (i)th first transistor 211 are integrally structured; the first electrode 211b of the (i+1)th first transistor 211 can serve as both the second electrode 211c of the (i)th first transistor 211 and the first electrode 211b of the (i+1)th first transistor 211. This allows two adjacent first transistors 211 to be connected in series.

[0145] By sharing the first electrode 211b of the (i+1)th first transistor 211 and the second electrode 211c of the i-th first transistor 211, the structure of the first transistor group 21 can be simplified, so that the multiple first transistors 211 in the first transistor group 21 are arranged more compactly, reducing the area occupied by the first transistor group 21, which is beneficial to reducing the area occupied by the memory cell chain 2 and further improving the storage density of the memory array 710.

[0146] There are many ways to configure the first transistor 211 , and the configuration can be selected based on the position of the first transistor 211 or actual needs.

[0147] In some examples, as shown in FIG11 , at least two memory cell chains 2 are sequentially arranged along a third direction Z. In all memory cell chains 2 except the memory cell chain 2 closest to the substrate 1 , the first transistor 211 is located on the substrate 1 . The first transistor 211 can be formed using a back-end process. Accordingly, the first transistor 211 can be referred to as a back-end process transistor.

[0148] In other examples, in the memory cell chain 2 in contact with the substrate 1, the first transistor 211 can be formed using a front-end process or a back-end process. Accordingly, the first transistor 211 can be a front-end process transistor (e.g., a buried-gate transistor) or a back-end process transistor.

[0149] Optionally, as shown in Figures 14a and 14b, the memory cell chain 2 includes a plurality of first gates 24, which are spaced apart along the first direction X, and adjacent first gates 24 are insulated from each other. The plurality of first gates 24 are located between the substrate 1 and the storage capacitor group 22, and the first gates 24 include the gate 211a of the first transistor 211. This means that the first gate 24 is independent of the substrate 1, and the first transistor 211 can be a back-end transistor, which helps to simplify the manufacturing process and manufacturing difficulty of the first transistor 211 and the memory array 710.

[0150] Optionally, the material of the first gate 24 includes but is not limited to TiN, Ti, Au, W, Mo, ITO, Al, Cu, Ru, Ag, heavily-doped poly-Si and other conductive materials or any combination thereof.

[0151] The first gate 24 may be in a block shape to serve as the gate 211a of the first transistor 211. Alternatively, as shown in FIG14b , the first gate 24 may be in a linear shape and extend along the second direction Y. In this case, the first gate 24 may serve as a word line WL, and a portion of the first gate 24 may serve as the gate 211a of the first transistor 211.

[0152] In addition, as shown in FIG. 14 a and FIG. 14 b , the memory cell chain 2 may further include: a first gate dielectric layer 25 , a first channel layer 26 , and first electrodes 211 b of a plurality of first transistors 211 .

[0153] Continuing to refer to Figures 14a and 14b, the first gate dielectric layer 25 is located between the plurality of first gate electrodes 24 and the storage capacitor group 22. The first gate dielectric layer 25, for example, contacts the surface of each first gate electrode 24 away from the substrate 1. The first gate dielectric layer 25, for example, is the gate dielectric layer of the plurality of first transistors 211. In other words, the gate dielectric layers of the plurality of first transistors 211 are an integral structure. Optionally, the material of the first gate dielectric layer 25 includes, but is not limited to, insulating materials such as SiO2 (silicon dioxide), Al2O3 (aluminum oxide), HfO2 (hafnium dioxide), ZrO2 (zirconium oxide), TiO2 (titanium dioxide), Y2O3 (yttrium trioxide), Si3N4 (silicon nitride), or any combination thereof. The structure of the first gate dielectric layer 25 can be a single-layer structure, a stacked structure, or a stacked structure composed of a combination of materials.

[0154] 14a and 14b , the first channel layer 26 is located between the first gate dielectric layer 25 and the storage capacitor group 22. For example, the first channel layer 26 contacts the surface of the first gate dielectric layer 25 facing away from the substrate 1. For example, the first channel layer 26 is strip-shaped and extends along the second direction Y. The orthographic projection of the first channel layer 26 on the substrate 1 partially overlaps with the orthographic projections of the multiple first gate electrodes 24 on the substrate 1. Along the third direction Z, the first channel layer 26 at least partially faces each first gate electrode 24, and the first channel layer 26 covers at least a portion of each first gate electrode 24. The first channel layer 26 serves as the channel for the multiple first transistors 211. In other words, the channels of the multiple first transistors 211 are connected and form an integrated structure. In this case, the multiple first transistors 211 can also be connected in series via the first channel layer 26. This simplifies the structure of the memory cell chain 2, simplifies the fabrication process of the memory array 710, and reduces the difficulty of fabricating the memory array 710.

[0155] Optionally, the material of the first channel layer 26 includes, but is not limited to, a semiconductor material or a metal oxide material. For example, the material of the first channel layer 26 includes, but is not limited to, a silicon-based semiconductor material such as Si (silicon), poly-Si (p-Si, polycrystalline silicon), and amorphous-Si (a-Si, amorphous silicon); or a metal oxide material such as In2O3 (indium oxide), ZnO (zinc oxide), Ga2O3 (gallium oxide), ITO (indium tin oxide), and TiO2 (titanium dioxide); a multinary compound material such as In-Ga-Zn-O (IGZO, indium gallium zinc oxide) and In-Sn-Zn-O (ISZO, indium tin zinc oxide); or a two-dimensional semiconductor material such as graphene, MoS2 (molybdenum disulfide), and black phosphorus, or any combination thereof.

[0156] As shown in FIG14a , the first electrodes 211b of the plurality of first transistors 211 are located between the first channel layer 26 and the storage capacitor group 22. The first electrodes 211b of the plurality of first transistors 211 are spaced apart along the first direction X. The first electrodes 211b of each first transistor 211 are, for example, block-shaped and in contact with a surface of the first channel layer 26 that is away from the substrate 1. The first electrodes 211b of two adjacent first transistors 211 are insulated from each other. As shown in FIG14a and FIG18 , in an orthographic projection on the substrate 1, the first electrodes 211b of the first transistors 211 and the first gates 24 are alternately arranged. That is, along the first direction X, a first gate 24 is arranged between the first electrodes 211b of two adjacent first transistors 211, and a first electrode 211b of the first transistor 211 is arranged between two adjacent first gates 24.

[0157] The first electrodes 211b of the plurality of first transistors 211 are respectively in contact with the first plates 221 of the plurality of storage capacitors C. The first electrodes 211b of the plurality of first transistors 211 and the first plates 221 of the plurality of storage capacitors C are arranged in a one-to-one correspondence, with the first electrode 211b of each first transistor 211 being away from a side surface of the substrate 1, for example, in contact with a side surface of the first plate 221 of the corresponding storage capacitor C that is closer to the substrate 1. In this way, electrical connection between the first transistors 211 and the storage capacitors C is achieved.

[0158] Optionally, the material of the first electrode 211 b of the first transistor 211 includes but is not limited to TiN, Ti, Au, W, Mo, ITO, Al, Cu, Ru, Ag and other conductive materials or any combination thereof.

[0159] Furthermore, the memory cell chain 2 may further include a plurality of second electrodes of first transistors 211 , and the second electrodes of the first transistors 211 are, for example, block-shaped.

[0160] Here, when the first electrode 211b of the (i+1)th first transistor 211 is shared as the second electrode 211c of the i-th first transistor 211, the number of second electrodes of the first transistors 211 can be reduced. For example, for the same memory cell chain 2, only one second electrode 211c of the first transistor 211 can be provided.

[0161] This is beneficial for further simplifying the structure of the memory cell chain 2 , further simplifying the manufacturing process of the memory array 710 , and reducing the difficulty of manufacturing the memory array 710 .

[0162] The structure of the second transistor group 23 in the memory cell chain 2 is schematically described below with reference to the accompanying drawings.

[0163] In the second transistor group 23 , there are many ways to connect the plurality of second transistors 231 in series, which can be selected and set according to actual needs.

[0164] In some examples, the first electrode 231b and the second electrode 231c of each second transistor 231 are independently provided. The second electrode 231c of the i-th second transistor 231 and the first electrode 231b of the (i+1)-th second transistor 231 may be electrically connected via other conductive structures.

[0165] In other examples, as shown in Figures 13 and 16, the second electrode 231c of the i-th second transistor 231 is shared as the first electrode 231b of the i+1-th second transistor 231. "Shared" means that the second electrode 231c of the i-th second transistor 231 and the first electrode 231b of the i+1-th second transistor 231 are integrally structured; the second electrode 231c of the i-th second transistor 231 can serve as both the first electrode 231b of the i+1-th second transistor 231 and the second electrode 231c of the i-th second transistor 231. This allows two adjacent second transistors 231 to be connected in series.

[0166] By sharing the second electrode 231c of the i-th second transistor 231 and the first electrode 231b of the (i+1)-th second transistor 231, the structure of the second transistor group 23 can be simplified, so that the multiple second transistors 231 in the second transistor group 23 are arranged more compactly, reducing the area occupied by the second transistor group 23, which is beneficial to reducing the area occupied by the memory cell chain 2 and further improving the storage density of the memory array 710.

[0167] There are many ways to configure the second transistor 231 , and the configuration can be selected according to actual needs.

[0168] In some examples, as shown in FIG. 14 a , FIG. 15 , and FIG. 16 , the memory cell chain 2 includes: second electrodes 231 c of a plurality of second transistors 231 , a second channel layer 27 , a second gate dielectric layer 28 , and a plurality of second gates 29 .

[0169] As shown in FIG16 , the second electrodes 231 c of the plurality of second transistors 231 are located on a side of the storage capacitor group 22 away from the substrate 1. The second electrodes 231 c of the plurality of second transistors 231 are, for example, spaced apart along the first direction X. The second electrodes 231 c of each second transistor 231 are, for example, block-shaped, and the second electrodes 231 c of two adjacent second transistors 231 are insulated from each other. The second electrodes 231 c of the plurality of second transistors 231 are respectively in contact with the second plates 222 of the plurality of storage capacitors C. The second electrodes 231 c of the plurality of second transistors 231 are arranged in a one-to-one correspondence with the second plates 222 of the plurality of storage capacitors C. The second electrodes 231 c of each second transistor 231 are, for example, at least partially aligned with the second plate 222 of the corresponding storage capacitor C. The second electrode 231 c of each second transistor 231 is located near a side surface of the substrate 1 and in contact with a side surface of the second plate 222 of the corresponding storage capacitor C away from the substrate 1. This allows for electrical connection between the second transistors 231 and the storage capacitors C.

[0170] Optionally, the material of the second electrode 231 c of the second transistor 231 includes but is not limited to TiN, Ti, Au, W, Mo, ITO, Al, Cu, Ru, Ag and other conductive materials or any combination thereof.

[0171] As shown in Figure 16, the second channel layer 27 is located on the side of the second electrode 231c of each second transistor 231 that is away from the substrate 1. For example, the second channel layer 27 contacts the surface of the second electrode 231c of each second transistor 231 that is away from the substrate 1. Referring to Figures 14a and 14b, the second channel layer 27 is, for example, strip-shaped and extends along the second direction Y. The orthographic projection of the second channel layer 27 on the substrate 1 partially overlaps with the orthographic projections of the second electrodes 231c of the plurality of second transistors 231 on the substrate 1. Along the third direction Z, the second channel layer 27 at least partially faces the second electrode 231c of each second transistor 231, and the second channel layer 27 covers at least a portion of the second electrode 231c of each second transistor 231. The second channel layer 27 serves as the channel of the plurality of second transistors 231. In other words, the channels of the plurality of second transistors 231 are connected and form a single integrated structure. In this case, the plurality of second transistors 231 can also be connected in series via the second channel layer 27. This helps to simplify the structure of the memory cell chain 2 , simplify the manufacturing process of the memory array 710 , and reduce the difficulty of manufacturing the memory array 710 .

[0172] Optionally, the material of the second channel layer 27 includes, but is not limited to, a semiconductor material or a metal oxide material. For example, the material of the second channel layer 27 includes, but is not limited to, a silicon-based semiconductor material such as Si, p-Si, or a-Si; or a metal oxide material such as In2O3, ZnO, Ga2O3, ITO, or TiO2; a multi-component compound material such as IGZO or ISZO; or a two-dimensional semiconductor material such as graphene, MoS2, or black phosphorus; or any combination thereof.

[0173] As shown in FIG16 , the second gate dielectric layer 28 is located on the side of the second channel layer 27 away from the substrate 1. The second gate dielectric layer 28 is, for example, in contact with the surface of the second channel layer 27 away from the substrate 1. The second gate dielectric layer 28 is, for example, the gate dielectric layer of the plurality of second transistors 231. In other words, the gate dielectric layers of the plurality of second transistors 231 are an integrated structure. Optionally, the material of the second gate dielectric layer 28 includes, but is not limited to, insulating materials such as SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, Si3N4, or any combination thereof. The structure of the second gate dielectric layer 28 can be a single-layer structure, a stacked structure, or a stacked structure composed of a combination of materials.

[0174] As shown in FIG16 , the plurality of second gate electrodes 29 are located on a side of the second gate dielectric layer 28 away from the substrate 1. The second gate electrodes 29 are, for example, in contact with a surface of the second gate dielectric layer 28 away from the substrate 1. The plurality of second gate electrodes 29 are spaced apart along the first direction X, and adjacent second gate electrodes 29 are insulated from each other. The second gate electrodes 29 include a gate electrode 231 a of the second transistor 231. The second gate electrode 29 may be in a block shape to serve as the gate electrode 231 a of the second transistor 231. Alternatively, as shown in FIG14 b , the second gate electrode 29 may be in a linear shape and extend along the second direction Y. In this case, the second gate electrode 29 may serve as a word line WL, and a portion of the second gate electrode 29 may serve as the gate electrode 231 a of the second transistor 231.

[0175] In an orthographic projection on the substrate 1, the second electrodes 231c and the second gates 29 of the second transistors 231 are alternately arranged. That is, along the first direction X, a second gate 29 is arranged between the second electrodes 231c of two adjacent second transistors 231, and a second electrode 231c of the second transistor 231 is arranged between two adjacent second gates 29.

[0176] Optionally, the material of the second gate 29 includes but is not limited to TiN, Ti, Au, W, Mo, ITO, Al, Cu, Ru, Ag, highly doped polysilicon and other conductive materials or any combination thereof.

[0177] The second transistor 231 is, for example, formed by a back-end process. Accordingly, the second transistor 231 can be a back-end transistor, which helps to simplify the manufacturing process and manufacturing difficulty of the second transistor 231 and the memory array 710 .

[0178] Furthermore, the memory cell chain 2 may further include a plurality of first electrodes of second transistors 231 , and the first electrodes of the second transistors 231 are, for example, block-shaped.

[0179] Here, when the second electrode 231c of the i-th second transistor 231 is shared with the first electrode 231b of the (i+1)-th second transistor 231, the number of first electrodes of the second transistors 231 can be reduced. For example, for the same memory cell chain 2, only one first electrode 231b of the second transistor 231 can be provided.

[0180] This is beneficial for further simplifying the structure of the memory cell chain 2 , further simplifying the manufacturing process of the memory array 710 , and reducing the difficulty of manufacturing the memory array 710 .

[0181] In some examples, as shown in Figures 14a and 15, the second electrode 231c of the second transistor 231 and the second plate 222 of the storage capacitor C in contact therewith are integrally structured. In other words, the second plate 222 of the storage capacitor C can serve as the second electrode 231c of the second transistor 231 in contact therewith.

[0182] This can avoid the additional preparation of the second electrode 231c of the second transistor 231 in contact with the second electrode plate 222 of the storage capacitor C, thereby simplifying the structure of the second transistor group 23, which is beneficial to reducing the thickness of the memory array 710, simplifying the preparation process of the memory array 710, and reducing the difficulty of preparing the memory array 710.

[0183] In this case, as shown in Figures 14a, 15, and 16, along a direction perpendicular to and away from the substrate 1 (i.e., the third direction Z), the second electrode plate 222 of the storage capacitor C protrudes beyond the first electrode plate 221 of the storage capacitor C. At this time, when the second electrode plate 222 is in direct contact with the second channel layer 27, a certain distance exists between the first electrode plate 221 and the second channel layer 27.

[0184] Continuing with Figures 14a, 15, and 16, the memory array 710 further includes an isolation layer 4. The isolation layer 4 is located between the first electrode plate 221 and the second channel layer 27, filling the gap between the first electrode plate 221 and the second channel layer 27. The surface of the isolation layer 4 proximal to the substrate 1, for example, contacts the first electrode plate 221, while the surface of the isolation layer 4 distal to the substrate 1, for example, contacts the second channel layer 27. The isolation layer 4 surrounds the portion of the second electrode plate 222 that protrudes from the first electrode plate 221.

[0185] In this way, the isolation layer 4 can be used to achieve electrical insulation between two adjacent second electrode plates 222 and electrical insulation between the first electrode plate 221 and the second channel layer 27, thereby avoiding crosstalk.

[0186] The isolation layer 4 may have various structures, which can be selected according to actual needs.

[0187] 14a, 15 and 16, the memory array 710 further includes a dielectric layer 5 located between the first transistor group 21 and the second transistor group 23. Each storage capacitor C penetrates the dielectric layer 5.

[0188] For example, as shown in FIG14a , the surface of the first electrode 221 away from the substrate 1, the surface of the storage functional layer 223 away from the substrate 1, and the surface of the dielectric layer 5 away from the substrate 1 are flush. In this case, the isolation layer 4 can be a single film layer structure, and the isolation layer 4 is also located between the storage functional layer 223 and the second channel layer 27, and between the dielectric layer 5 and the second channel layer 27.

[0189] Optionally, the material of the isolation layer 4 includes but is not limited to insulating materials such as SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, Si3N4, or any combination thereof, and the structure of the isolation layer 4 can be a single-layer structure, a stacked structure, or a stacked structure composed of a combination of materials.

[0190] For another example, as shown in Figures 15 and 16 , relative to substrate 1, the surface of the first electrode 221 facing away from substrate 1 is lower than the surface of the dielectric layer 5 facing away from substrate 1. The different storage functional layers 223 are connected and form an integrated structure, and the portion of the storage functional material connecting the different storage functional layers 223 covers the surface of the dielectric layer 5 facing away from substrate 1. The surface of the second electrode 222 facing away from substrate 1 is flush with the portion of the storage functional material covering the surface of the dielectric layer 5 facing away from substrate 1. In this case, the isolation layer 4 can be composed of the portion of the dielectric layer 5 that protrudes from the first electrode 221 and the portion of the storage functional material covering the dielectric layer 5.

[0191] The film layer structures in the first transistor group 21 and the second transistor group 23 can be arranged in a variety of ways, and can be specifically selected according to actual needs.

[0192] In some embodiments, as shown in FIG14 a , based on the electrical connection relationship between the storage capacitor C and the first transistor 211 and the second transistor 231, the orthographic projections of the first transistor 211 and the second transistor 231 electrically connected to the same storage capacitor C are staggered on the substrate 1. Along the first direction X, the gates of the first transistor 211 and the second transistor 231 electrically connected to the same storage capacitor C are located on opposite sides of the storage capacitor C. Furthermore, along the first direction X, two gates are provided between two adjacent storage capacitors C, and the first transistor 211 and the second transistor 231 described by the two gates are respectively connected to different storage capacitors C.

[0193] For example, as shown in FIG14a and FIG14b, along the first direction X, the orthographic projections of the first gate 24 and the second gate 29 located between two adjacent storage capacitors C on the substrate 1 at least partially overlap. That is, along the third direction Z, the first gate 24 and the second gate 29 located between two adjacent storage capacitors C at least partially face each other.

[0194] This can make the arrangement of the first transistor group 21 and the second transistor group 23 more compact, reduce the area occupied by the first transistor group 21 and the second transistor group 23, and thus help reduce the area occupied by the memory cell chain 2, further improving the storage density of the memory array 710.

[0195] In other embodiments, as shown in Figures 14a and 14b, the orthographic projection of the first channel layer 26 on the substrate 1 and the orthographic projection of the second channel layer 27 on the substrate 1 at least partially overlap. That is, along the third direction Z, the first channel layer 26 and the second channel layer 27 are at least partially opposite.

[0196] This allows for a more compact arrangement of the first transistor group 21 and the second transistor group 23, reducing the area occupied by the first transistor group 21 and the second transistor group 23, thereby reducing the area occupied by the memory cell chain 2 and further improving the storage density of the memory array 710. Furthermore, the first channel layer 26 and the second channel layer 27 can be formed using the same mask, which helps reduce the manufacturing cost of the memory array 710.

[0197] In some other embodiments, as shown in FIG14a and FIG14b, the orthographic projection of the first gate dielectric layer 25 on the substrate 1 and the orthographic projection of the second gate dielectric layer 28 on the substrate 1 at least partially overlap. That is, along the third direction Z, the first gate dielectric layer 25 and the second gate dielectric layer 28 at least partially face each other.

[0198] This allows for a more compact arrangement of the first transistor group 21 and the second transistor group 23, reducing the area occupied by the first transistor group 21 and the second transistor group 23, thereby reducing the area occupied by the memory cell chain 2 and further improving the storage density of the memory array 710. Furthermore, the first gate dielectric layer 25 and the second gate dielectric layer 28 can be formed using the same mask, which helps reduce the manufacturing cost of the memory array 710.

[0199] It is understood that during the process of reading and writing data in the memory array 710, the first transistor 211 and the second transistor 231 electrically connected to the same storage capacitor C need to be turned on or off synchronously. In this case, it is necessary to design the performance of the first transistor 211 and the second transistor 231. In the embodiment of the present application, the gate, gate dielectric layer, channel and other structures of the first transistor 211 and the second transistor 231 can be configured to achieve the design of the performance of the first transistor 211 and the second transistor 231.

[0200] In some examples, the first transistor 211 and the second transistor 231 electrically connected to the same storage capacitor C can be referred to as a first target transistor and a second target transistor. The material of the gate 211a of the first target transistor and the material of the gate 231a of the second target transistor are the same. And / or, the size of the gate 211a of the first target transistor and the size of the gate 231a of the second target transistor are the same.

[0201] Optionally, the gate 211 a of the first target transistor and the gate 231 a of the second target transistor are both made of W, or are both made of highly doped polysilicon.

[0202] Optionally, the size of the gate 211a of the first target transistor or the size of the gate 231a of the second target transistor includes thickness, line width, etc. For example, the thickness of the gate 211a of the first target transistor and the gate 231a of the second target transistor are equal; or, along the first direction X, the width of the gate 211a of the first target transistor and the gate 231a of the second target transistor are equal.

[0203] This is beneficial to reducing the difference in performance of the first transistor 211 and the second transistor 231 electrically connected to the same storage capacitor C, improving the consistency of the performance of the first transistor 211 and the second transistor 231 electrically connected to the same storage capacitor C, and facilitating the synchronous turning on or off of the first transistor 211 and the second transistor 231 electrically connected to the same storage capacitor C.

[0204] In some other examples, the material of the first channel layer 26 is the same as that of the second channel layer 27 , and / or the size of the first channel layer 26 is the same as that of the second channel layer 27 .

[0205] Optionally, the materials of the first channel layer 26 and the second channel layer 27 are both p-Si, or both oxide semiconductor materials.

[0206] Optionally, the size of the first channel layer 26 or the second channel layer 27 includes thickness, line width, etc. For example, the thickness of the first channel layer 26 and the second channel layer 27 are equal; or, along the second direction Y, the width of the first channel layer 26 and the second channel layer 27 are equal.

[0207] This is beneficial to reducing the difference in performance of the first transistor 211 and the second transistor 231 electrically connected to the same storage capacitor C, improving the consistency of the performance of the first transistor 211 and the second transistor 231 electrically connected to the same storage capacitor C, and facilitating the synchronous turning on or off of the first transistor 211 and the second transistor 231 electrically connected to the same storage capacitor C.

[0208] In some other examples, the material of the first gate dielectric layer 25 is the same as the material of the second gate dielectric layer 28 , and / or the size of the first gate dielectric layer 25 is the same as the size of the second gate dielectric layer 28 .

[0209] Optionally, the first gate dielectric layer 25 and the second gate dielectric layer 28 are both made of SiO 2 .

[0210] Optionally, the size of the first gate dielectric layer 25 or the size of the second gate dielectric layer 28 includes thickness. When the orthographic projections of the first gate dielectric layer 25 and the first channel layer 26 on the substrate 1 overlap, and the orthographic projections of the second gate dielectric layer 28 and the second channel layer 27 on the substrate 1 overlap, the size of the first gate dielectric layer 25 or the size of the second gate dielectric layer 28 also includes line width, etc.

[0211] This is beneficial to reducing the difference in performance of the first transistor 211 and the second transistor 231 electrically connected to the same storage capacitor C, improving the consistency of the performance of the first transistor 211 and the second transistor 231 electrically connected to the same storage capacitor C, and facilitating the synchronous turning on or off of the first transistor 211 and the second transistor 231 electrically connected to the same storage capacitor C.

[0212] In some possible examples, the potentials of the gate 211a of the first target transistor and the gate 231a of the second target transistor are kept consistent, so as to facilitate synchronous control of turning on or off the first target transistor and the second target transistor.

[0213] In this case, the gate 211a of the first target transistor and the gate 231a of the second target transistor can be connected to corresponding control circuits respectively, or the gate 211a of the first target transistor and the gate 231a of the second target transistor are electrically connected and then connected to corresponding control circuits.

[0214] The memory array 710 may also include other structures. In some examples, as shown in FIG12 , the memory array 710 further includes plate lines PL, word lines WL, bit lines BL, a gate (or block selecting, BS) transistor Tbs, and a selection signal line BSL.

[0215] As shown in FIG13 , in the first transistor group 21, the two first transistors 211 located at opposite ends are respectively a first input transistor 211i and a first output transistor 211o; in the second transistor group 23, the two second transistors 23 located at opposite ends are respectively a second input transistor 231i and a second output transistor 231o. The first input transistor 211i and the second input transistor 231i are electrically connected to the same storage capacitor C, and the first output transistor 211o and the second output transistor 231o are electrically connected to the same storage capacitor C. For example, in FIG13 , the first transistor 211 located at the far left is the first input transistor 211i, and the first transistor 211 located at the far right is the first output transistor 211o; the second transistor 231 located at the far left is the second input transistor 231i, and the second transistor 231 located at the far right is the second output transistor 231o.

[0216] 12 and 13 , the plate line PL is electrically connected to the first electrode 211b of the first input transistor 211i and the first electrode 231b of the second input transistor 231i. A plate line signal from the plate line PL can be transmitted to the first electrode 211b of the first input transistor 211i and the first electrode 231b of the second input transistor 231i, and then transmitted to the other first transistors 211 and the other second transistors 231 through the first input transistors 211i and the second input transistors 231i.

[0217] Alternatively, the plate line PL may be located between the substrate 1 and the storage capacitor group 22 , or the plate line PL may be located on a side of the storage capacitor group 22 away from the substrate 1 .

[0218] 12 and 13 , the first electrode of the gate transistor Tbs is electrically connected to the second electrode 211c of the first output transistor 211o and the second electrode 231c of the second output transistor 231o, and the second electrode of the gate transistor Tbs is electrically connected to the bit line BL. The gate of the gate transistor Tbs is electrically connected to the select signal line BSL. A select signal from the select signal line BSL can be transmitted to the gate of the gate transistor Tbs to control whether the gate transistor Tbs is turned on or off. When the select signal turns the gate transistor Tbs on, the memory cell chain 2 in which the gate transistor Tbs is turned on is selected.

[0219] Alternatively, the gate transistor Tbs, the selection signal line BSL and the bit line BL may be located between the substrate 1 and the storage capacitor group 22 , or the gate transistor Tbs, the selection signal line BSL and the bit line BL may be located on a side of the storage capacitor group 22 away from the substrate 1 .

[0220] 12 and 13 , the word line WL is electrically connected to the gate 211a of the first transistor 211, or the word line WL is electrically connected to the gate 231a of the second transistor 231. A control signal from the word line WL can be transmitted to the gate 211a of the first transistor 211 or the gate 231a of the second transistor 231 to control whether the first transistor 211 is turned on or off, or whether the second transistor 231 is turned on or off.

[0221] For example, the first transistor 211 and the second transistor 231 electrically connected to the same storage capacitor C can be called the first target transistor and the second target transistor, where, as shown in Figure 12, the gate 211a of the first target transistor and the gate 231a of the second target transistor can be connected to different word lines WL respectively, and the two word lines WL are electrically connected together through an electrical contact structure.

[0222] Taking the storage functional layer 223 in the storage capacitor C as a ferroelectric material layer as an example, the operating principle of the memory array 710 is schematically described. The gate of each first transistor 211 and the gate of each second transistor 231 are used to receive control signals. The first electrode of each first transistor 211 is used to receive a plate line signal, and the second electrode of each second transistor 231 is used to receive or output a bit line signal.

[0223] The working principle of the above-mentioned memory array 710 is, for example: in the Idle state, the word line WL electrically connected to the first transistor 211 and the second transistor 231 in each memory cell MC transmits a high-potential control signal to control the first transistor 211 and the second transistor 231 of each memory cell MC to be turned on; the selection signal line BSL transmits a low-potential selection signal to control the selection transistor Tbs to be turned off, thereby disconnecting the memory cell chain 2 from the bit line BL.

[0224] During the "write" process, the word line WL electrically connected to the first transistor 211 and the second transistor 231 of the selected memory cell MC transmits a low-potential control signal to control the first transistor 211 and the second transistor 231 of the memory cell MC to be turned off; the word line WL electrically connected to the first transistor 211 and the second transistor 231 of the unselected memory cell MC transmits a high-potential control signal to control the first transistor 211 and the second transistor 231 of the memory cell MC to be turned on; the selection signal line BSL transmits a high-potential selection signal to control the gate transistor Tbs to be turned on; the plate line signal transmitted by the switching plate line PL and the bit line BL transmit the high-potential selection signal. The bit line signal, for example, the plate line PL transmits a high-potential plate line electrical signal, the first transistor 211 transmits the plate line signal to the first plate 221 of the storage capacitor C of the selected memory cell MC, the bit line BL transmits a low-potential bit line electrical signal, the second transistor 231 transmits the bit line signal to the second plate 222 of the storage capacitor C of the selected memory cell MC, so that the storage function layer 223 in the selected memory cell MC changes (for example, the polarization direction of the selected storage capacitor C is reversed), while the unselected memory cell MC maintains its original state (for example, the unselected storage capacitor C maintains its original polarization state), thereby realizing data writing.

[0225] During the "read" process, in conjunction with Figures 12, 13, 19 and 20, the word line WL (such as Sel-WL in Figure 19) electrically connected to the first transistor 211 and the second transistor 231 of the selected memory cell MC transmits a low-potential control signal to control the first transistor 211 and the second transistor 231 of the memory cell MC to be turned off; the word line WL (such as Unsel-WL in Figure 19) electrically connected to the first transistor 211 and the second transistor 231 of the unselected memory cell MC transmits a high-potential control signal to control the first transistor 211 and the second transistor 231 of the memory cell MC to be turned on; the selection signal line BSL transmits a high-potential selection signal to control the gate transistor Tbs to be turned on; the plate line PL transmits a high-potential plate line electrical signal, and the first transistor 211 transmits the plate line signal to the first plate 221 of the storage capacitor C of the selected memory cell MC, and the second plate 222 of the storage capacitor C of the selected memory cell MC transmits the stored data information to the bit line BL via the second transistor 231. Because ferroelectric memory uses destructive reading, when reading state '0', the state of the memory cell MC remains unchanged, and the signal potential on the bit line BL remains essentially unchanged, as shown in Figure 19. When reading state '1', the polarization state of the storage capacitor C is rewritten from '1' to '0'. Therefore, in the timing diagram shown in Figure 20, the read waveform includes a region of reverse write state '1'. This is the potential on the bit line BL. After being raised to a higher potential relative to the read state '0', the potential on the plate line PL switches to a low potential state. After the write-back of state '1' is completed, the potentials on the bit line BL and the select signal line BSL return to the low potential of the idle state. Simultaneously, the potential on the word line WL rises back to the high potential of the idle state, completing the entire read operation.

[0226] It is understood that in the embodiment of the present application, since the contact structure can be omitted, the size of the memory cell MC can be miniaturized, which can greatly improve the storage density of the memory array 710 in the embodiment of the present application, and make the storage density of the memory array 710 substantially the same as the storage density of advanced DRAM. In this case, the dimensions (e.g., line width or depth) of the word line WL and the bit line BL can be miniaturized to approximately 50nm; the critical dimension (CD) of the storage capacitor C (i.e., the outer diameter of the storage capacitor C) can be miniaturized to approximately 40nm, the height of the storage capacitor C can range from 300nm to 1000nm, and the thickness of the storage functional layer 223 can be miniaturized to less than 10nm.

[0227] Some embodiments of the present application also provide a method for preparing a memory array. This preparation method is used, for example, to prepare the memory array 710 in some of the above-mentioned embodiments. FIG. 21 illustrates a flow chart of a method for preparing a memory array; FIG. 22a to FIG. 22d, FIG. 23a to FIG. 23h, FIG. 24a to FIG. 24b, FIG. 25a to FIG. 25f, FIG. 26a to FIG. 26e, and FIG. 27a to FIG. 27b respectively illustrate the structures corresponding to each step in a method for preparing a memory array. It should be understood that the steps shown in FIG. 21 are not exclusive, and other steps may be performed before, after, or between any of the steps shown in FIG. 21. In addition, some of the steps may be performed simultaneously, or may be performed in an order different from that shown in FIG. 21.

[0228] The following is a schematic illustration of the manufacturing method of the memory array described above with reference to the accompanying drawings. As shown in FIG21 , the manufacturing method includes: S100 to S400.

[0229] S100, as shown in FIG22a, provides a substrate 1.

[0230] For example, the substrate 1 may be a semiconductor substrate, such as a silicon substrate. The substrate 1 may be, for example, a wafer that has undergone front-end processing and has an insulating dielectric material formed on its surface. Of course, the structure of the substrate 1 is not limited thereto.

[0231] S200, as shown in FIG22b, a first transistor group 21 is formed on one side of the substrate 1. The first transistor group 21 includes a plurality of first transistors 211 connected in series.

[0232] For example, regarding the first transistor group 21 and the first transistor 211 , reference may be made to the relevant descriptions above, which will not be repeated here.

[0233] S300, as shown in FIG22c, forms a storage capacitor group 22 on a side of the first transistor group 21 away from the substrate 1. The storage capacitor group 22 includes multiple storage capacitors C, each of which includes a first plate 221, a storage functional layer 223, and a second plate 222. The storage functional layer 223 at least surrounds the second plate 222, and the first plate 221 at least surrounds the storage functional layer 223. The first plates 221 of the multiple storage capacitors C are electrically connected to the first electrodes 211b of the multiple first transistors 211, respectively.

[0234] For example, regarding the storage capacitor group 22 and the storage capacitor C, reference may be made to the relevant descriptions above, which will not be repeated here.

[0235] S400, as shown in FIG22d, forms a second transistor group 23 on a side of the storage capacitor group 22 away from the substrate 1. The second transistor group 23 includes a plurality of second transistors 231 connected in series. The second plates 222 of the plurality of storage capacitors C are electrically connected to the second electrodes 231c of the plurality of second transistors 231, respectively.

[0236] For example, regarding the second transistor group 23 and the second transistor 231 , reference may be made to the relevant descriptions above, which will not be repeated here.

[0237] Some embodiments of the present application provide a method for preparing a storage array, by forming a storage capacitor group 22 on a side of the first transistor group 21 away from the substrate 1, forming a second transistor group 23 on a side of the storage capacitor group 22 away from the substrate 1, and making the first plates 221 of the multiple storage capacitors C electrically connected to the first poles 211b of the multiple first transistors 211, respectively, and making the second plates 222 of the multiple storage capacitors C electrically connected to the second poles 231c of the multiple second transistors 231, respectively. On the basis of using the first transistor 211 to control the potential on the first plate 221 of the storage capacitor C, the second transistor 231 can be used to control the potential of the second plate 222 of the storage capacitor C, without the need for the first transistor 211 to control the potential of the second plate 222 of the storage capacitor C, thereby avoiding the preparation of contact. On the one hand, this can avoid etching to form a contact hole with a large aspect ratio for accommodating the contact structure, which is conducive to reducing the difficulty of manufacturing the memory array 710. On the other hand, it can avoid increasing the size of the first transistor 211 and / or the second transistor 231 due to the arrangement of the contact structure, which is conducive to reducing the size and area of ​​the memory cell MC and facilitating the realization of a strict 4F 2 The minimum memory cell size improves the storage density of the memory array 710 .

[0238] In some embodiments, in the above S200 , forming a first transistor group 21 on one side of the substrate 1 includes: S210 .

[0239] S210, as shown in FIG23c, a plurality of first gates 24 are formed on one side of the substrate 1. The plurality of first gates 24 are spaced apart along a first direction X, which is parallel to the substrate 1. The first gates 24 include the gate 211a of the first transistor 211.

[0240] Exemplarily, a method for forming the above-mentioned multiple first gates 24 includes: as shown in Figure 23a, forming a second insulating layer L1 on one side of the substrate 1; forming a first photoresist layer on a side of the second insulating layer L1 away from the substrate 1, the first photoresist layer having multiple first openings, and the multiple first openings corresponding to the positions of the first gates to be formed; then using the first photoresist layer as a mask, etching the second insulating layer L1 by a dry etching process to form multiple grooves in the second insulating layer L1 (as shown in Figure 23b), the grooves extending, for example, along the second direction Y; then depositing a conductive material in the multiple grooves and on the side of the second insulating layer L1 away from the substrate 1 to form a third conductive film; thereafter, a chemical mechanical polishing (CMP) process can be used for planarization to remove the portion of the third conductive film located on the side of the second insulating layer L1 away from the substrate 1, and retaining the portion of the third conductive film located in the above-mentioned multiple grooves to obtain multiple first gates 24, as shown in Figure 23c.

[0241] Optionally, the material of the first gate 24 includes but is not limited to TiN, Ti, Au, W, Mo, ITO, Al, Cu, Ru, Ag, heavily-doped poly-Si and other conductive materials or any combination thereof.

[0242] The first gate 24 is formed by a back-end process, which is beneficial to simplifying the manufacturing process and difficulty of the first transistor 211 and the memory array 710 .

[0243] In some examples, in the above S200 , a first transistor group 21 is formed on one side of the substrate 1 , and further steps include: S220 to S230 .

[0244] S220, as shown in FIG23e, a first gate dielectric layer 25 and a first channel layer 26 are formed on a side of the plurality of first gate electrodes 24 away from the substrate 1. The orthographic projection of the first channel layer 26 on the substrate 1 partially overlaps with the orthographic projections of the plurality of first gate electrodes 24 on the substrate 1. The first gate dielectric layer 25 serves as the gate dielectric layer of the plurality of first transistors 211, and the first channel layer 26 serves as the channels of the plurality of first transistors 211.

[0245] Exemplarily, the method for forming the first gate dielectric layer 25 and the first channel layer 26 includes, for example: as shown in Figure 23d, depositing a first gate dielectric material on the side of the above-mentioned multiple first gates 24 and the second insulating layer L1 away from the substrate 1 to form a first gate dielectric film 25a, and then depositing a first channel material on the side of the first gate dielectric film 25a away from the substrate 1 to form a first channel film 26a; forming a second photoresist layer on the side of the first channel film 26a away from the substrate 1; and then using the second photoresist layer as a mask, etching the first channel film 26a and the first gate dielectric film 25a by a dry etching process to form multiple first channel layers 26 and multiple first gate dielectric layers 25, as shown in Figure 23e.

[0246] The first channel layer 26 and the first gate dielectric layer 25 are both strip-shaped and extend along the first direction X. Multiple first channel layers 26 are spaced apart along the second direction Y, and multiple first gate dielectric layers 25 are spaced apart along the second direction Y. Each first channel layer 26 and the first gate dielectric layer 25 located below the first channel layer 26 correspond to a first transistor group 21. Accordingly, the multiple first channel layers 26 and the multiple first gate dielectric layers 25 correspond to multiple first transistor groups 21 arranged sequentially along the second direction Y.

[0247] Optionally, the first gate dielectric material includes, but is not limited to, insulating materials such as SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, and Si3N4. The first channel material includes, but is not limited to, semiconductor materials and metal oxide materials. For example, the first channel material includes, but is not limited to, silicon-based semiconductor materials such as Si, p-Si, and a-Si; or metal oxide materials such as In2O3, ZnO, Ga2O3, ITO, and TiO2; multi-component compound materials such as IGZO and ISZO; or two-dimensional semiconductor materials such as graphene, MoS2, and black phosphorus; or any combination thereof.

[0248] Of course, after forming the second photoresist layer, the first channel film 26 a may be etched based on the second photoresist layer alone, and the first gate dielectric film 25 a serves as the first gate dielectric layer 25 of the plurality of first transistor groups 21 .

[0249] In addition, after forming multiple first channel layers 26 and multiple first gate dielectric layers 25, insulating material can be deposited between two adjacent first channel layers 26, between two adjacent first gate dielectric layers 25, and on the side of the first channel layer 26 away from the substrate 1; then a CMP process is used for planarization to remove part of the insulating material located on the side of the first channel layer 26 away from the substrate 1, and retain part of the insulating material located between two adjacent first channel layers 26 and between two adjacent first gate dielectric layers 25 to obtain a third insulating layer L2, as shown in Figure 23e, to achieve electrical insulation between two adjacent first channel layers 26.

[0250] Optionally, the material of the third insulating layer L2 includes but is not limited to insulating materials such as SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, and Si3N4.

[0251] S230, as shown in FIG23h, forms a plurality of first electrodes 211b of first transistors 211 on a side of the first channel layer 26 away from the substrate 1. The first electrodes 211b of the plurality of first transistors 211 are spaced apart along the first direction X. In an orthographic projection on the substrate 1, the first electrodes 211b of the first transistors 211 and the first gates 24 are alternately arranged. The first electrodes 211b of the plurality of first transistors 211 are in contact with the first channel layer 26 and are respectively in contact with the first plates 221 of the plurality of storage capacitors C.

[0252] Exemplary methods for forming the first electrodes 211b of the plurality of first transistors 211 include, for example, depositing an insulating material on a side of the plurality of first channel layers 26 and the third insulating layer L2 away from the substrate 1 to form a fourth insulating layer L3, as shown in FIG23f; and then, using a self-aligned double patterning technique in a first direction X and a second direction Y, as shown in FIG23g. A plurality of second through holes H2 are formed in the fourth insulating layer L3 by using a SADP) patterning and dry etching process, and each second through hole H2 exposes a portion of the first channel layer 26, wherein each first channel layer 26 is provided with a plurality of second through holes H2, and along the first direction X, the plurality of second through holes H2 and the plurality of first gates 24 located on the same first channel layer 26 are alternately arranged; then, a conductive material is deposited in the plurality of second through holes H2 and on the side of the fourth insulating layer L3 away from the substrate 1 to form a fourth conductive film; then, a CMP process can be used for planarization to remove the portion of the fourth conductive film located on the side of the fourth insulating layer L3 away from the substrate 1, and retain the portion of the fourth conductive film located in the above-mentioned plurality of second through holes H2, thereby obtaining the first electrodes 211b of the plurality of first transistors 211, as shown in FIG23h.

[0253] Optionally, the material of the fourth insulating layer L3 includes, but is not limited to, insulating materials such as SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, and Si3N4. The material of the fourth conductive film includes, but is not limited to, conductive materials such as TiN, Ti, Au, W, Mo, ITO, Al, Cu, Ru, Ag, and heavily doped polysilicon (heavily-doped poly-Si), or any combination thereof.

[0254] The use of self-aligned double imaging technology facilitates the realization of smaller-sized second through-holes H2 and a smaller spacing between two adjacent second through-holes H2. In other words, it facilitates the realization of smaller-sized first electrodes 211b of the first transistors 211 and a smaller spacing between the first electrodes 211b of two adjacent first transistors 211. This helps to increase the compactness of the first electrodes 211b of the multiple first transistors 211, reduces the area occupied by the first transistor group 21, and facilitates the realization of higher storage density.

[0255] Here, when the first electrode 211b of the (i+1)th first transistor 211 is used as the second electrode 211c of the i-th first transistor 211, the number of second electrodes of the first transistors 211 can be reduced. For example, for the same first transistor group 21, only one second electrode 211c of the first transistor 211 can be provided, and the second electrode 211c of the first transistor 211 is manufactured and formed simultaneously with the first electrode 211b of the first transistor 211.

[0256] This is beneficial to further improve the structure of the first transistor group 21 , further simplify the manufacturing process of the memory array 710 , and reduce the difficulty of manufacturing the memory array 710 .

[0257] In some embodiments, in the above S300 , forming a storage capacitor group 22 on a side of the first transistor group 21 away from the substrate 1 includes: S310 to S330 .

[0258] S310 , as shown in FIG24 a , a dielectric layer 5 is formed on a side of the first transistor group 21 away from the substrate 1 .

[0259] For example, in the embodiment of the present application, a deposition process may be used to deposit an insulating material on a side of the first transistor group 21 away from the substrate 1 to form a dielectric layer 5. The dielectric layer 5 has a relatively large thickness.

[0260] Optionally, the material of the dielectric layer 5 includes but is not limited to insulating materials such as SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, Si3N4, or any combination thereof, and the structure of the dielectric layer 5 can be a single-layer structure, a stacked structure, or a stacked structure composed of a combination of materials.

[0261] S320 , as shown in FIG24 b , a plurality of first through holes H1 are formed penetrating the dielectric layer 5 . The plurality of first through holes H1 expose the first electrodes 211 b of the plurality of first transistors 211 , respectively.

[0262] For example, in the embodiment of the present application, a self-aligned dual imaging technique in the first direction X and a dry etching process in the second direction Y can be used to etch the dielectric layer 5 to form a plurality of first through holes H1, each of which penetrates the dielectric layer 5. The first through holes H1 are, for example, circular hole structures. Each first channel layer 26 is provided with a plurality of first through holes H1, and the plurality of first through holes H1 are, for example, provided in a one-to-one correspondence with the first electrodes 211b of the plurality of first transistors 211.

[0263] S330, combining Figure 24b and Figure 22c, forming a first electrode 221, a storage function layer 223 and a second electrode 222 in each first through hole H1. The first electrode 221 contacts the first electrode 211b of the first transistor 211 through the first through hole H1.

[0264] Illustratively, the first electrode plate 221 has a long barrel-shaped structure, covering the sidewalls of the first through-hole H1 and the first electrode 211b of the first transistor 211 exposed by the first through-hole H1. The storage function layer 223 has a long barrel-shaped structure and is located within the area defined by the first electrode plate 221. The second electrode plate 222 has a columnar structure and is located within the area defined by the storage function layer 223.

[0265] Since a plurality of first through holes H1 are formed on each first channel layer 26 , the plurality of storage capacitors C formed in the above S330 may constitute a plurality of storage capacitor groups 22 sequentially arranged along the second direction Y, for example.

[0266] The use of self-aligned double imaging technology facilitates the realization of smaller first through-holes H1 and a smaller spacing between two adjacent first through-holes H1; in other words, it facilitates the realization of smaller storage capacitors C and a smaller spacing between two adjacent storage capacitors C. This helps reduce the area occupied by the storage capacitors C, improves the compactness of the storage capacitor group 22, and facilitates the realization of a higher storage density.

[0267] In the above S330 , there are multiple methods for forming the storage capacitor C, which can be selected and set according to actual needs.

[0268] In some examples, in the above S330 , forming the first electrode plate 221 , the storage function layer 223 , and the second electrode plate 222 in each first through hole H1 includes: S331 a to S334 a .

[0269] S331 a , as shown in FIG25 a , a first conductive film 221 a is formed on the inner wall of each first through hole H1 . The first conductive film 221 a is also located on a side of the dielectric layer 5 away from the substrate 1 .

[0270] For example, in the embodiment of the present application, a suitable deposition process such as atomic layer deposition (ALD) can be used to deposit a conductive material on the inner wall of each first through hole H1 and on the surface of the dielectric layer 5 facing away from the substrate 1 to form the first conductive film 221a. The first conductive film 221a is also in contact with the first electrode 211b of the first transistor 211.

[0271] Optionally, the material of the first conductive film 221 a includes but is not limited to TiN, Ti, Au, W, Mo, ITO, Al, Cu, Ru, Ag and other conductive materials or any combination thereof.

[0272] S332a, as shown in FIG25b, remove the portion of the first conductive film 221a located on the side of the dielectric layer 5 away from the substrate 1, and retain the portion of the first conductive film 221a covering the inner wall of each first through hole H1 to obtain the first electrode 221.

[0273] For example, in the embodiment of the present application, a dry etching process can be used to etch the first conductive film 221a, resulting in multiple independent first electrode plates 221. As shown in FIG25b, after etching, along the third direction Z, the surface of the first electrode plate 221 away from the substrate 1 is lower than the surface of the dielectric layer 5 away from the substrate 1.

[0274] S333a, as shown in Figures 25c and 25d, a storage functional film 223a and a second conductive film 222a are sequentially formed in each first through hole H1. The storage functional film 223a and the second conductive film 222a are also located on the side of the dielectric layer 5 away from the substrate 1. The portion of the storage functional film 223a located in the first through hole H1 constitutes the storage functional layer 223.

[0275] For example, the present invention can use an appropriate deposition process such as ALD to form the storage function film 223a and the second conductive film 222a. The storage function film 223a covers the first electrode 221 and the dielectric layer 5, and the second conductive film 222a covers the storage function film 223a.

[0276] Optionally, the material of the storage function film 223 a is the same as that of the storage function layer 223 , and the material of the second conductive film 222 a is the same as that of the second electrode plate 222 , which will not be repeated here.

[0277] S334a, as shown in FIG25e or FIG25f, at least the portion of the second conductive film 222a located on the storage functional film 223a is removed to obtain the second electrode plate 222. The second electrode plate 222 protrudes from the first electrode plate 221.

[0278] For example, as shown in FIG. 25e , in an embodiment of the present application, a CMP process may be used to planarize the second conductive film 222a , and the portion of the second conductive film 222a located on the storage functional film 223a may be removed to obtain a plurality of independent second electrodes 222 .

[0279] For example, as shown in Figure 25f, the embodiment of the present application can use a CMP process to planarize the second conductive film 222a and the storage functional film 223a, remove the parts of the second conductive film 222a and the storage functional film 223a located on the dielectric layer 5, and obtain multiple independent second plates 222 and multiple independent storage functional layers 223.

[0280] In the structures shown in FIG. 25 e and FIG. 25 f , the end of the second electrode plate 222 away from the substrate 1 and the end of the first electrode plate 221 away from the substrate 1 are electrically insulated by the storage function layer 223 .

[0281] For example, in the embodiments of the present application, an etching method with a high selectivity can be used to remove the portions of the second conductive film 222a and the storage functional film 223a located on the dielectric layer 5, thereby obtaining a plurality of independent second electrode plates 222 and a plurality of independent storage functional layers 223. The dielectric layer 5 is then etched so that the surface of the first electrode plate 221 away from the substrate 1, the surface of the storage functional layer 223 away from the substrate 1, and the surface of the dielectric layer 5 away from the substrate 1 are flush. In this case, the second electrode plate 222 still protrudes from the storage functional layer 223 and the dielectric layer 5.

[0282] In this case, an isolation layer may be formed on the side of the first electrode plate 221 , the storage functional layer 223 and the dielectric layer 5 away from the substrate 1 , and the isolation layer surrounds the portion of the second electrode plate 222 protruding from the first electrode plate 221 .

[0283] This facilitates electrical connection between the second plate 222 and the subsequently formed second transistor 231 and ensures electrical insulation between the first plate 221 and the subsequently formed second transistor 231, thereby preventing a short circuit between the two and affecting the storage function of the storage array.

[0284] In some other examples, in the above S330 , the first electrode plate 221 , the storage function layer 223 and the second electrode plate 222 are formed in each first through hole H1 , including: S331 b to S332 b .

[0285] S331b, as shown in Figures 25a, 26a and 26b, a first conductive film 221a, a storage functional film 223a and a second conductive film 222a are formed in sequence in each first through hole H1. The first conductive film 221a, the storage functional film 223a and the second conductive film 222a are also located on the side of the dielectric layer 5 away from the substrate 1.

[0286] For example, in the embodiments of the present application, a suitable deposition process such as an ALD process can be used to sequentially deposit a first conductive film 221a, a memory function film 223a, and a second conductive film 222a. A portion of the first conductive film 221a is located on the inner wall of the first through hole H1 and contacts the first electrode 211b of the first transistor 211, while another portion is located on the dielectric layer 5. The memory function film 223a covers the first conductive film 221a, and the second conductive film 222a covers the memory function film 223a.

[0287] S332b, as shown in Figure 26c, remove the second conductive film 222a, the storage functional film 223a and the portion of the first conductive film 221a located on the side of the dielectric layer 5 away from the substrate 1, and retain the second conductive film 222a, the storage functional film 223a and the portion of the first conductive film 221a located in each first through hole H1 to obtain the first electrode 221, the storage functional layer 223 and the second electrode 222.

[0288] For example, as shown in FIG26c, in an embodiment of the present application, a CMP process can be used to planarize the second conductive film 222a, the storage functional film 223a, and the first conductive film 221a, removing the portions of the second conductive film 222a, the storage functional film 223a, and the first conductive film 221a located on the dielectric layer 5, thereby obtaining a plurality of independent second electrodes 222, a plurality of independent storage functional layers 223, and a plurality of independent first electrodes 221. The surface of the second electrode 222 away from the substrate 1, the surface of the storage functional layer 223 away from the substrate 1, the surface of the first electrode 221 away from the substrate 1, and the surface of the dielectric layer 5 away from the substrate 1 are flush.

[0289] In this case, before the above S400 , that is, before forming the second transistor group 23 on the side of the storage capacitor group 22 away from the substrate 1 , the above manufacturing method further includes: S333 b to S334 b .

[0290] S333 b , as shown in FIG26 d , at least the dielectric layer 5 and the first electrode plate 221 are etched so that the second electrode plate 222 protrudes from the first electrode plate 221 .

[0291] Illustratively, the embodiment of the present application may use an etching method with a high selectivity ratio to etch the dielectric layer 5 and the first electrode 221, or, as shown in FIG26d, to etch the dielectric layer 5, the first electrode 221 and the storage function layer 223.

[0292] S334b, as shown in FIG26e, an isolation layer 4 is formed on the dielectric layer 5 and the first electrode plate 221. The isolation layer 4 surrounds the portion of the second electrode plate 222 protruding from the first electrode plate 221.

[0293] Illustratively, in an embodiment of the present application, insulating material may be deposited on the side of the dielectric layer 5 away from the substrate 1 and on the side of the second electrode 222 away from the substrate 1 to form an isolation film; then a CMP process may be used for planarization to remove the portion of the isolation film located on the side of the second electrode 222 away from the substrate 1, exposing the second electrode 222 to obtain an isolation layer 4.

[0294] In the structure shown in FIG26 e , the end of the second electrode plate 222 away from the substrate 1 and the end of the first electrode plate 221 away from the substrate 1 are electrically insulated by the isolation layer 4 .

[0295] This facilitates electrical connection between the second plate 222 and the subsequently formed second transistor 231 and ensures electrical insulation between the first plate 221 and the subsequently formed second transistor 231, thereby preventing a short circuit between the two and affecting the storage function of the storage array.

[0296] In some embodiments, in the above S400 , forming the second transistor group 23 on the side of the storage capacitor group 22 away from the substrate 1 includes: S410 to S430 .

[0297] S410, as shown in FIG27a, a second channel layer 27 is formed on a side of the storage capacitor group 22 away from the substrate 1. The second channel layer 27 contacts the second plates 222 of the plurality of storage capacitors C. The second channel layer 27 serves as channels for the plurality of second transistors 231.

[0298] For example, the method for forming the second channel layer 27 is the same as the method for forming the first channel layer 26 in S220 .

[0299] In this case, the second plate 222 of the storage capacitor C can be shared as the second electrode of the second transistor 231 .

[0300] S420 , as shown in FIG. 27 b , a second gate dielectric layer 28 is formed on a side of the second channel layer 27 away from the substrate 1 . The second gate dielectric layer 28 is a gate dielectric layer of the plurality of second transistors 231 .

[0301] Exemplarily, the method for forming the second gate dielectric layer 28 is the same as the method for forming the first gate dielectric layer 25 in S220. For details, please refer to the relevant description above and will not be repeated here. The material of the second gate dielectric layer 28 is, for example, the same as that of the first gate dielectric layer 25.

[0302] S430, with reference to FIG. 27b and FIG. 22d , a plurality of second gate electrodes 29 are formed on a side of the second gate dielectric layer 28 away from the substrate 1. The plurality of second gate electrodes 29 are spaced apart along the first direction X. In an orthographic projection on the substrate 1, the second plates 222 and the second gate electrodes 29 are alternately arranged; the first direction X is parallel to the substrate 1, and the second gate electrodes 29 include the gate electrode 231a of the second transistor 231.

[0303] Illustratively, in an embodiment of the present application, a suitable deposition process such as sputtering may be used to deposit a conductive material on the surface of the second gate dielectric layer 28 away from the substrate 1 to form a fifth conductive film; and then the fifth conductive film is etched using a self-aligned dual imaging technique in the first direction X and a dry etching process in the second direction Y to obtain a plurality of second gate electrodes 29.

[0304] The second gate 29 extends, for example, along the second direction Y. In this case, the second gate 29 can serve as a word line WL, electrically connected to corresponding second transistors 231 in a plurality of second transistor groups 23 sequentially arranged along the second direction Y.

[0305] In the embodiment of the present application, the second channel layer 27 is formed directly on the second electrode plate 222 of the storage capacitor C, which can self-align to form the second electrode of the second transistor 231 (i.e., the second electrode plate 222 also serves as the second electrode of the second transistor 231). This avoids the need for additional alignment to prepare the second electrode of the second transistor 231, simplifies the structure of the second transistor group 23, reduces the difficulty of manufacturing the second transistor group 23, and improves the efficiency of manufacturing the second transistor group 23.

[0306] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A storage array, characterized in that, The storage array includes: a substrate, and at least one storage cell chain located on one side of the substrate; The storage cell chain includes: A first transistor group located on one side of the substrate; the first transistor group includes a plurality of first transistors connected in series; A storage capacitor group located on the side of the first transistor group away from the substrate; the storage capacitor group includes a plurality of storage capacitors, each storage capacitor including a first electrode plate, a storage functional layer, and a second electrode plate, the storage functional layer at least surrounds the second electrode plate, and the first electrode plate at least surrounds the storage functional layer; the first electrode plates of the plurality of storage capacitors are respectively electrically connected to the first poles of the plurality of first transistors; A second transistor group located on the side of the storage capacitor group away from the substrate; the second transistor group includes a plurality of second transistors connected in series; the second electrode plates of the plurality of storage capacitors are respectively electrically connected to the second poles of the plurality of second transistors.

2. The storage array according to claim 1, wherein The storage cell chain includes: a plurality of first gates; The plurality of first gates are located between the substrate and the storage capacitor group, the plurality of first gates are arranged at intervals in a first direction, the first direction is parallel to the substrate; the first gate includes the gate of the first transistor.

3. The storage array according to claim 2, wherein, The storage cell chain further includes: A first gate dielectric layer located between the plurality of first gates and the storage capacitor group; the first gate dielectric layer is the gate dielectric layer of the plurality of first transistors; A first channel layer located between the first gate dielectric layer and the storage capacitor group; the orthographic projection of the first channel layer on the substrate overlaps partially with the orthographic projection of the plurality of first gates on the substrate; the first channel layer is the channel of the plurality of first transistors; The first poles of the plurality of first transistors are located between the first channel layer and the storage capacitor group; the first poles of the plurality of first transistors are arranged at intervals in the first direction; in the orthographic projection on the substrate, the first poles of the first transistors and the first gates are arranged alternately; the first poles of the plurality of first transistors are in contact with the first channel layer and are respectively in contact with the first electrode plates of the plurality of storage capacitors.

4. The storage array according to claim 3, wherein The first pole of the (i + 1)-th first transistor is shared as the second pole of the i-th first transistor; i is a positive integer.

5. The storage array according to any one of claims 1 to 4, characterized in that, The storage cell chain includes: The second poles of the plurality of second transistors are located on the side of the storage capacitor group away from the substrate; the second poles of the plurality of second transistors are respectively in contact with the second electrode plates of the plurality of storage capacitors; A second channel layer located on the side of the second poles of the second transistors away from the substrate; the second channel layer is in contact with the second poles of the plurality of second transistors; the second channel layer is the channel of the plurality of second transistors; A second gate dielectric layer located on the side of the second channel layer away from the substrate; the second gate dielectric layer is the gate dielectric layer of the plurality of second transistors; A plurality of second gates, located on a side of the second gate dielectric layer away from the substrate; the plurality of second gates are arranged at intervals in a first direction; in a projection onto the substrate, a second pole of the second transistor and the second gates are alternately arranged; the first direction is parallel to the substrate; the second gate includes a gate of the second transistor.

6. The storage array according to claim 5, wherein The second pole of the second transistor and a second electrode plate in contact therewith are of an integral structure.

7. The storage array according to claim 6, wherein In a direction perpendicular to and away from the substrate, the second electrode plate protrudes from the first electrode plate. The memory array further includes: an isolation layer; the isolation layer is located between the first electrode plate and the second channel layer, and the isolation layer surrounds a portion of the second electrode plate that protrudes from the first electrode plate.

8. The storage array according to any one of claims 5 to 7, characterized in that, The second pole of the i-th second transistor is shared as the first pole of the (i + 1)-th first transistor; i is a positive integer.

9. The storage array according to any one of claims 1 to 8, characterized in that, The memory cell chain includes a plurality of first gates and a plurality of second gates. The plurality of first gates are located between the substrate and the memory capacitor bank, and the plurality of second gates are located on a side of the memory capacitor bank away from the substrate; the first gate includes a gate of the first transistor, and the second gate includes a gate of the second transistor. In the first direction, a projection onto the substrate of the first gate and the second gate located between two adjacent memory capacitors at least partially overlap. The first direction is parallel to the substrate.

10. The storage array according to claim 9, wherein, The first transistor and the second transistor electrically connected to the same memory capacitor are a first target transistor and a second target transistor, respectively. The material of the gate of the first target transistor is the same as the material of the gate of the second target transistor; and / or, the size of the gate of the first target transistor is the same as the size of the gate of the second target transistor.

11. The storage array according to any one of claims 1 to 10, characterized in that, The memory cell chain includes a first channel layer and a second channel layer. The first channel layer is located between the substrate and the memory capacitor bank, and the second channel layer is located on a side of the memory capacitor bank away from the substrate; the first channel layer is a channel of the plurality of first transistors, and the second channel layer is a channel of the plurality of second transistors. A projection of the first channel layer onto the substrate and a projection of the second channel layer onto the substrate at least partially overlap.

12. The storage array according to claim 11, wherein, The material of the first channel layer is the same as that of the second channel layer; and / or, the size of the first channel layer is the same as the size of the second channel layer.

13. The storage array according to any one of claims 1 to 12, characterized in that, The memory array includes a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is located between the substrate and the memory capacitor bank, and the second gate dielectric layer is located on a side of the memory capacitor bank away from the substrate; the first gate dielectric layer is a gate dielectric layer of the plurality of first transistors, and the second gate dielectric layer is a gate dielectric layer of the plurality of second transistors. A projection of the first gate dielectric layer onto the substrate and a projection of the second gate dielectric layer onto the substrate at least partially overlap.

14. The storage array according to claim 13, wherein, The material of the first gate dielectric layer is the same as the material of the second gate dielectric layer; and / or, the size of the first gate dielectric layer is the same as the size of the second gate dielectric layer.

15. The storage array according to any one of claims 1 to 14, characterized in that, The first transistor and the second transistor electrically connected to the same storage capacitor are the first target transistor and the second target transistor, respectively; The gates of the first target transistor and the second target transistor are electrically connected.

16. The storage array according to any one of claims 1 to 15, characterized in that, Both the first transistor and the second transistor are post-process transistors.

17. The storage array according to any one of claims 1 to 16, characterized in that, Two first transistors located at opposite ends of the first transistor group are the first input transistor and the first output transistor, respectively. Two second transistors located at opposite ends of the second transistor group are the second input transistor and the second output transistor, respectively. The first input transistor and the second input transistor are electrically connected to the same storage capacitor, and the first output transistor and the second output transistor are electrically connected to the same storage capacitor; The memory array further includes: A plate line electrically connected to the first pole of the first input transistor and the first pole of the second input transistor; A word line electrically connected to the gates of the first transistor and the second transistor electrically connected to the same storage capacitor; A select transistor, the first pole of the select transistor being electrically connected to the second pole of the first output transistor and the second pole of the second output transistor; A bit line electrically connected to the second pole of the select transistor; A selection signal line electrically connected to the gate of the select transistor.

18. The storage array according to any one of claims 1 to 17, characterized in that, The number of the memory cell chains is multiple; At least two of the memory cell chains are arranged in sequence along the first direction, and at least two of the memory cell chains are arranged in sequence along the second direction; Both the first direction and the second direction are parallel to the substrate and intersect with each other.

19. The storage array according to claim 18, wherein At least two of the memory cell chains are arranged in sequence along the third direction; The third direction is perpendicular to the substrate.

20. The storage array according to any one of claims 1 to 19, wherein The memory function layer includes a ferroelectric material layer, a resistive switching material layer, or a phase change material layer.

21. The storage array according to any one of claims 1 to 20, wherein The gates of the first transistor and the second transistor are used to receive control signals; The first pole of the first transistor is used to receive a plate line signal; The second pole of the second transistor is used to receive or output a bit line signal.

22. A method for preparing a storage array, characterized in that, The manufacturing method includes: Providing a substrate; Forming a first transistor group on one side of the substrate; the first transistor group includes a plurality of first transistors connected in series; Forming a storage capacitor group on the side of the first transistor group away from the substrate; the storage capacitor group includes a plurality of storage capacitors, each storage capacitor including a first electrode plate, a memory function layer, and a second electrode plate. The memory function layer at least surrounds the second electrode plate, and the first electrode plate at least surrounds the memory function layer; the first electrode plates of the plurality of storage capacitors are respectively electrically connected to the first poles of the plurality of first transistors; Forming a second transistor group on the side of the storage capacitor group away from the substrate; the second transistor group includes a plurality of second transistors connected in series; the second electrode plates of the plurality of storage capacitors are respectively electrically connected to the second poles of the plurality of second transistors.

23. The preparation method according to claim 22, characterized in that, The forming of the first transistor group on one side of the substrate includes: Forming a plurality of first gates on one side of the substrate; the plurality of first gates are arranged at intervals along a first direction parallel to the substrate; the first gates include the gates of the first transistors.

24. The preparation method according to claim 23, characterized in that, Forming a first transistor group on one side of the substrate further includes: Forming a first gate dielectric layer and a first channel layer on a side of the plurality of first gates away from the substrate; a positive projection of the first channel layer on the substrate partially overlaps with a positive projection of the plurality of first gates on the substrate; the first gate dielectric layer is the gate dielectric layer of the plurality of first transistors, and the first channel layer is the channel of the plurality of first transistors; Forming a first pole of the plurality of first transistors on a side of the first channel layer away from the substrate; the first poles of the plurality of first transistors are arranged at intervals along the first direction; in a positive projection on the substrate, the first poles and the first gates of the first transistors are alternately arranged; the first poles of the plurality of first transistors are in contact with the first channel layer and are respectively in contact with the first plates of the plurality of storage capacitors.

25. The preparation method according to any one of claims 22 to 24, characterized in that, Forming a storage capacitor group on a side of the first transistor group away from the substrate includes: Forming a dielectric layer on a side of the first transistor group away from the substrate; Forming a plurality of first through holes penetrating the dielectric layer; the plurality of first through holes respectively expose the first poles of the plurality of first transistors; Forming the first plate, the storage function layer, and the second plate in each of the first through holes; the first plate is in contact with the first pole of the first transistor through the first through hole.

26. The preparation method according to claim 25, characterized in that, Forming the first plate, the storage function layer, and the second plate in each of the first through holes includes: Forming a first conductive thin film on the inner wall of each of the first through holes, and the first conductive thin film is also located on a side of the dielectric layer away from the substrate; Removing a part of the first conductive thin film located on a side of the dielectric layer away from the substrate, and retaining a part of the first conductive thin film covering the inner wall of each of the first through holes to obtain the first plate; Sequentially forming a storage function thin film and a second conductive thin film in each of the first through holes, and the storage function thin film and the second conductive thin film are also located on a side of the dielectric layer away from the substrate; a part of the storage function thin film located in the first through hole constitutes the storage function layer; At least removing a part of the second conductive thin film located on the storage function thin film to obtain the second plate; the second plate protrudes from the first plate.

27. The preparation method according to claim 25, wherein, Forming the first plate, the storage function layer, and the second plate in each of the first through holes includes: Sequentially forming a first conductive thin film, a storage function thin film, and a second conductive thin film in each of the first through holes, and the first conductive thin film, the storage function thin film, and the second conductive thin film are also located on a side of the dielectric layer away from the substrate; Removing parts of the second conductive thin film, the storage function thin film, and the first conductive thin film located on a side of the dielectric layer away from the substrate, and retaining parts of the second conductive thin film, the storage function thin film, and the first conductive thin film located in each of the first through holes to obtain the first plate, the storage function layer, and the second plate; Before forming the second transistor group on a side of the storage capacitor group away from the substrate, the manufacturing method further includes: etching at least the dielectric layer and the first electrode plate to make the second electrode plate protrude from the first electrode plate; forming an isolation layer on the dielectric layer and the first electrode plate; the isolation layer surrounds a part of the second electrode plate that protrudes from the first electrode plate.

28. The preparation method according to any one of claims 22 to 27, characterized in that, Forming the second transistor group on a side of the storage capacitor group away from the substrate includes: forming a second channel layer on a side of the storage capacitor group away from the substrate; the second channel layer is in contact with the second electrode plates of a plurality of the storage capacitors; the second channel layer is the channels of a plurality of the second transistors; forming a second gate dielectric layer on a side of the second channel layer away from the substrate; the second gate dielectric layer is the gate dielectric layers of a plurality of the second transistors; forming a plurality of second gate electrodes on a side of the second gate dielectric layer away from the substrate; the plurality of second gate electrodes are arranged at intervals along a first direction; in a front projection on the substrate, the second electrode plates and the second gate electrodes are arranged alternately; the first direction is parallel to the substrate; the second gate electrode includes the gate electrode of the second transistor.

29. A memory, characterized in that, The memory includes: a storage array according to any one of claims 1 to 21; a controller electrically connected to the storage array; the controller is configured to control reading and writing of the storage array.

30. An electronic device, characterized in that, The electronic device includes: a memory according to claim 29; a circuit board electrically connected to the memory.

Images