Control board

Abstract

In the present invention, the joining reliability of a control board is improved by suppressing cracking of a semiconductor element or breakage due to crack growth at a joint portion between a wiring board and the semiconductor element when operating at an extremely low temperature. As a means to achieve the foregoing, provided is a control board that includes: a wiring board provided with a first main surface and a second main surface on the side opposite the first main surface; an electrode formed on the first main surface of the wiring board; and a semiconductor element bonded on the electrode via a conductive joint portion. Conductive particles contained in the joint portion are silver, and the joint portion includes a conductive adhesive and a conductive adhesive disposed so as to surround an outer periphery of the conductive adhesive when viewed planarly.

Description

Control board

[0001] The present invention relates to a control board for a quantum computer realized using a dilution refrigerator or the like, and in particular to a bonding structure between a quantum chip or quantum control chip mounted at extremely low temperatures near absolute zero and a wiring board.

[0002] Quantum computer technology has made remarkable progress in recent years, and expectations for the realization of practical quantum computers are also rising.

[0003] Quantum computers use superconducting logic-based devices, which are typically cooled to cryogenic temperatures to function in a superconducting state. Patent Document 1 (JP 2021-523572 A) discloses a system including at least two sets of superconducting logic devices, a cooling device adapted to cool the logic devices to a first operating temperature, and interconnects coupling the superconducting logic devices. Patent Document 2 (JP 2019-537239 A) discloses a quantum computing device in which a quantum device die and a control circuit die for controlling the operation of the quantum device die are disposed on a substrate. In both patent documents, the quantum device and the substrate are connected to each other by solder bumps or the like.

[0004] Special table 2021-523572 publication Special table 2019-537239 publication

[0005] Quantum computers operate at extremely low temperatures near absolute zero. In control boards that implement quantum chips or quantum control chips, various electronic components such as large-scale integration (LSI) chips are mounted on wiring boards via joints (adhesives). The materials that make up the joints are susceptible to brittle fracture at extremely low temperatures, and even small cracks must be prevented. Furthermore, semiconductor elements are connected to the electrodes of the wiring board using conductive adhesives. However, at extremely low temperatures, the adhesive and the wiring board components shrink, causing cracks between the components due to differences in the linear expansion coefficients of the respective components, leading to problems with the control board failing. Patent documents 1 and 2 mention the reliability of electronic component joints at extremely low temperatures, but do not mention the joint structure.

[0006] An object of the present invention is to improve the bonding reliability of a control board.

[0007] A brief summary of a representative embodiment of the present invention will be given below.

[0008] In one embodiment, the control board includes a wiring board having a first main surface and a second main surface opposite the first main surface, an electrode formed on the first main surface of the wiring board, and a semiconductor element bonded to the electrode via a conductive joint, wherein the conductive particles contained in the joint are silver, and the joint includes a first conductive adhesive and a second conductive adhesive disposed around the periphery of the first conductive adhesive in a plan view.

[0009] The effects obtained by the representative inventions disclosed in this application will be briefly explained as follows.

[0010] According to the present invention, it is possible to improve the joint reliability in the control board.

[0011] Fig. 1 is a cross-sectional view of a control board according to an embodiment. Fig. 2 is a plan view of a control board according to an embodiment. Fig. 3 is a schematic diagram showing a quantum computer. Fig. 4 is a cross-sectional view showing deformation of a control board at cryogenic temperatures. Fig. 5 is a table showing experimental results of a heating and cooling cycle. Fig. 6 is a plan view of a control board according to a first modified example of an embodiment. Fig. 7 is a cross-sectional view of a control board according to a second modified example of an embodiment. Fig. 8 is a cross-sectional view of a control board.

[0012] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. Furthermore, in the following embodiments, explanations of identical or similar parts will not be repeated unless specifically required. Furthermore, in the drawings for explaining the embodiments, hatching may be used even in plan views or perspective views to make the configuration easier to understand. Furthermore, in the drawings for explaining the embodiments, hatching may be omitted in cross-sectional views to make the configuration easier to understand.

[0013] <Details of Room for Improvement> Below, we will explain the room for technical improvement in the control board of the quantum computer.

[0014] In quantum computers, a control board is placed on a stage cooled to an extremely low temperature such as 4 K or 100 mK. The control board includes a wiring board and a semiconductor element mounted on the wiring board. In a structure in which a semiconductor element is bonded to a wiring board, the semiconductor element is mounted by applying a conductive adhesive to an electrode portion on the wiring board and then heating and curing the conductive adhesive to form a bond. Silver particles are thought to be used as the conductive particles in the conductive adhesive, but copper particles are also sometimes used.

[0015] For example, FR-4 (Flame Retardant Type 4) boards are considered to be used for wiring boards. This board is made by weaving glass fibers into a cloth-like material and then soaking it in epoxy resin. However, due to its large linear expansion coefficient, it is prone to bending due to temperature changes. In contrast, semiconductor elements (semiconductor chips) have a small linear expansion coefficient and are less likely to deform even when the temperature changes drastically.

[0016] In a control board, a semiconductor element is connected to a wiring board via a conductive adhesive. However, due to differences in the linear expansion coefficients between components, such as between the semiconductor element and the wiring board, or between the conductive adhesive and the wiring board, at extremely low temperatures, each component may deform, potentially causing cracks to form in the components and between the components. Specifically, cracks may form in the semiconductor element and the conductive adhesive. Furthermore, brittle fracture is likely to occur at extremely low temperatures, which shortens the lifespan of the control board and further reduces the reliability of the control board. Therefore, there is room for improvement in the low reliability of the connection between the wiring board and the semiconductor element in the control board.

[0017] Therefore, in the following embodiment, a device is devised to solve the above-mentioned room for improvement. The technical concept of this embodiment in which this device is devised will be described below.

[0018] (Embodiment) This embodiment relates to an adhesive that connects a semiconductor element (chip) mounted on a wiring substrate that constitutes a control board of a quantum computer to the wiring substrate. Below, we will explain how the adhesive uses materials with different properties as the base resin for the adhesive in the center and periphery of the chip, thereby suppressing stress that occurs in the adhesive and chip in a control board that operates at extremely low temperatures.

[0019] This embodiment will be described with reference to Figures 1 to 4. Of the directions shown in each figure, the X and Y directions are directions along the top surface of the wiring board 1 (see Figure 1) in a flat, unwarped state, and are directions perpendicular to each other in a plan view. The Z direction is a direction perpendicular to the X and Y directions, and is also called the height direction or thickness direction. The plan view here refers to viewing the control board or components of the control board in the Z direction.

[0020] 1 and 2, a control board 10 of this embodiment has a wiring board 1 and a semiconductor element 2. The wiring board 1 has a first main surface 1a and a second main surface 1b opposite the first main surface 1a in the Z direction. Electrodes 4 are provided on the first main surface, which is the upper surface of the wiring board 1. In other words, the wiring board 1 is a printed circuit board in which a wiring pattern such as electrodes 4 is provided on the upper surface of an insulating substrate. An organic substrate such as an FR-4 substrate is used for the wiring board 1.

[0021] The semiconductor element 2 is mounted facing the wiring board 1 via the conductive bonding portions 6 provided on the electrodes 4. In other words, the semiconductor element 2 is bonded to the electrodes 4 provided on the first main surface 1a of the wiring board 1 via the bonding portions 6. The bonding portions 6 are composed of conductive adhesives 5a and 5b. In plan view, the conductive adhesive 5a is surrounded by the conductive adhesive 5b. That is, in plan view, the center of the bonding portion 6 is composed of the conductive adhesive 5a, and the conductive adhesive 5a is surrounded by the conductive adhesive 5b. That is, the conductive adhesive 5b has a ring structure in plan view. The semiconductor element 2 and the bonding portions 6 are each rectangular in plan view, and both the conductive adhesives 5a and 5b overlap the semiconductor element 2 in plan view. In other words, both the conductive adhesives 5a and 5b are covered by the back surface of the semiconductor element 2. However, unlike FIG. 1, as shown in FIG. 2, a portion of the conductive adhesive 5a may extend outside the semiconductor element 2 in plan view. In FIG. 2, the outline of the semiconductor element 2 is indicated by a broken line.

[0022] The conductive adhesive 5a has a higher adhesive strength than the conductive adhesive 5b, and the conductive adhesive 5b has a smaller cure shrinkage rate than the conductive adhesive 5a. In order to realize such a difference in properties between the conductive adhesives 5a and 5b, it is preferable that the base resin of the conductive adhesive 5a is an epoxy-based resin and the base resin of the conductive adhesive 5b is a silicone-based resin, for example.

[0023] The semiconductor element 2 preferably has metallization 3 on its back surface facing the wiring substrate 1. When a back electrode (not shown) of the semiconductor element 2 is provided, the provision of metallization 3 covering the back surface of the semiconductor element 2 improves the electrical conductivity between the back electrode and the bonding portion 6. Furthermore, the provision of metallization 3 improves the thermal conductivity between the semiconductor element 2 and the electrode 4.

[0024] FIG. 3 shows a schematic diagram of a quantum computer. The quantum computer 20 shown in FIG. 3 includes multiple cooling stages (base plates, flanges) 11-15 arranged in layers, spaced apart from one another in the vertical direction. Stage 16 is provided above cooling stage 11. Each cooling stage 11-15 is made of, for example, gold-plated copper, and is cooled to lower temperatures going downwards using a dilution refrigerator system. For example, from top to bottom, cooling stage 11 is cooled to 50 K, cooling stage 12 to 4 K, cooling stage 13 to 1 K, and cooling stage 11 to 100 mK. The cooling stages are connected by multiple wirings (control wiring, readout wiring, etc.) 19 made of a copper-containing alloy or the like. The top of stage 16 is at 300 K (room temperature).

[0025] A quantum control chip 23 is mounted on the cooling stage 12, which is cooled to 4K. A quantum chip 22 is mounted on the cooling stage 15, which is cooled to 100mK. The quantum chip 22 is a quantum bit array chip that performs quantum information processing using quantum bits. The quantum control chip 23 is an extremely low-temperature analog chip that controls the quantum chip 22 and includes an extremely low-temperature DA converter and an extremely low-temperature AD converter. The quantum chip 22 is electrically connected to the quantum control chip 23, and the quantum control chip 23 is electrically connected to an overall control chip (measurement device) 24 provided on the stage 16.

[0026] The semiconductor element 2 shown in FIGS. 1 and 2 is used in the quantum chip 22 or quantum control chip 23 shown in FIG. 3. That is, the control substrate 10 is installed on the cooling stage 12 or the cooling stage 15 and operates at an extremely low temperature of 77 K or less. Specifically, it is conceivable that the quantum control chip 23 is placed between the cooling stage 12 and the cooling stage 11, and the quantum chip 22 is placed below the cooling stage 15. When the semiconductor element 2 is the quantum control chip 23, the wiring substrate 1 is fixed to the cooling stage 12 by bolts or the like that penetrate the wiring substrate 1. Furthermore, when the semiconductor element 2 is the quantum control chip 23, the wiring substrate 1 may be mounted as a daughter substrate on another wiring substrate that is a mother substrate, and the mother substrate may be fixed to the cooling stage 12 by bolts.

[0027] 4 shows how the wiring substrate 1 deforms at cryogenic temperatures. When the wiring substrate 1 is an organic substrate, in a 4 K environment, which is the temperature of the area in the dilution refrigerator where the quantum control chip 23 is mounted, the central portion of the wiring substrate 1 becomes convex upward (toward the first principal surface 1 a), and stress is applied to the central portion. The semiconductor element 2 is affected by the deformation of the wiring substrate 1, and the stress applied to the central portion is greater than that applied to the peripheral portion of the semiconductor element 2. The bonding portion 6 is affected by the deformation of the wiring substrate 1, and the stress applied to the peripheral portion of the bonding portion 6, particularly the corners, is greater than that applied to the central portion. The bonding portion 6 is preferably formed of a conductive adhesive that has high adhesive strength and is less likely to generate voids. However, even small cracks can impair connection reliability at cryogenic temperatures. Therefore, the peripheral portion of the bonding portion 6 is preferably formed of a conductive adhesive that has a low cure shrinkage rate at low temperatures. Therefore, in this embodiment, the central part of the joint 6 covered by the semiconductor element 2 is made of a conductive adhesive 5a which has high adhesive strength and is less likely to produce voids, and the area around the conductive adhesive 5a is made of a conductive adhesive 5b which has a small cure shrinkage rate.

[0028] Specifically, control board 10 of this embodiment includes wiring board 1 having first main surface 1a and second main surface 1b opposite to first main surface 1a, electrode 4 formed on first main surface 1a of wiring board 1, and semiconductor element 2 bonded to electrode 4 via conductive joint 6. Here, the conductive particles contained in joint 6 are silver, and joint 6 includes conductive adhesive 5a and conductive adhesive 5b arranged to surround the outer periphery of conductive adhesive 5a in a plan view.

[0029] 5 shows the evaluation results of element samples that the inventors performed 500 cycles of heating and cooling between 77 K and 289 K. When all of the joints 6 were bonded with an epoxy-based resin conductive adhesive (Comparative Example 1), cracks occurred in four of the six semiconductor elements, and cracks occurred in three of the six joints 6. When all of the joints 6 were bonded with a silicone-based resin conductive adhesive (Comparative Example 2), cracks occurred in two of the six semiconductor elements, and cracks occurred in three of the six joints 6. When the center of the joints 6 was bonded with an epoxy-based resin conductive adhesive and the periphery was bonded with a silicone-based resin conductive adhesive (Example 1), none of the six semiconductor elements cracked, and one of the six joints 6 cracked. When the center of the joint 6 was bonded with a conductive adhesive made of silicone resin and the periphery was bonded with a conductive adhesive made of epoxy resin (Comparative Example 3), cracks occurred in three out of six semiconductor elements, and cracks occurred in two out of six joints 6.

[0030] In the evaluations of Comparative Examples 2 and 3, numerous voids were observed, which connected to the cracks and impaired reliability. This was due to the fact that the central base, which primarily constitutes the joint 6, was made of a silicone-based resin, which is more prone to void formation than epoxy-based resins. These results indicate that the joint 6 must have few voids and be in a good bonded state after the conductive adhesive is heated and cured. Using only an adhesive with a low cure shrinkage rate at low temperatures (Comparative Example 2) or using a large bonding area ratio for bonding at extremely low temperatures (Comparative Example 3) can impair bonding reliability. When using a silicone-based conductive adhesive, it is desirable to apply the silicone-based conductive adhesive only to an area where voids can be easily evacuated to the outside of the joint 6, i.e., the periphery of the joint 6, as in Example 1.

[0031] 5 shows that the generation and persistence of cracks and voids can be reduced by forming the central portion of the joint 6 covered by the semiconductor element 2 with conductive adhesive 5a, which has high adhesive strength and is less likely to generate voids, and forming the area around the conductive adhesive 5a with conductive adhesive 5b, which has a small cure shrinkage rate, as in this embodiment. Therefore, by using the control board 10 of this embodiment, brittle fracture in the semiconductor element 2 and the joint 6 can be suppressed even at extremely low temperatures of 77 K or less. This improves the joint reliability of the control board 10.

[0032] <Modification 1> A control board of this modification will be described with reference to Fig. 6. In Fig. 6, the outline of the semiconductor element 2 is indicated by a broken line.

[0033] As shown in FIG. 6 , the shape of the conductive adhesive 5 a in a plan view may be substantially circular. That is, in this case, in the bonding portion 6, the epoxy-based conductive adhesive 5 a is formed so as to reach the center of the side surface of the semiconductor element 2 in a plan view, and the silicone-based conductive adhesive 5 b is formed so as to cover only the corners of the semiconductor element 2. This reduces the stress load on the bonding portion 6 below the corners of the semiconductor element 2. At extremely low temperatures, the locations where the semiconductor element 2 and bonding portion 6 are particularly subject to high stress are near the corners of the semiconductor element 2 in a plan view. Therefore, by arranging the silicone-based conductive adhesive 5 b directly below the corners (four corners) of the semiconductor element 2, it is possible to prevent a decrease in bonding reliability due to stress, achieve high adhesive strength, and prevent the occurrence of voids.

[0034] The side surface of the bonding portion 6 may be along the end face of the semiconductor element 2, or may be gently inclined toward the electrode 4 (see FIG. 1). It is desirable that the bonding portion 6 be formed according to the size of the electrode 4, which is designed according to the constraints imposed when wire-bonding the semiconductor element 2.

[0035] <Modification 2> A control board of this modification will be described with reference to FIG.

[0036] 7, the area in the planar direction where the silicon-based conductive adhesive 5b is formed is equal to or smaller than the thickness of the bonding portion 6 so as to allow voids 25 to escape. In other words, the width of the conductive adhesive 5b at one end of the bonding portion 6 in the direction along the X-Y plane along the X and Y directions (the direction along the first main surface 1a of the wiring board 1, the horizontal direction, the lateral direction) is equal to or smaller than the thickness of the bonding portion 6 (the thickness of the conductive adhesive 5b).

[0037] Conductive adhesive 5b containing silicone resin is more susceptible to void formation than conductive adhesive 5a containing epoxy resin. The upper limit of the size of voids 25 that can form within joint 6 is determined by the thickness of joint 6. As shown in FIG. 8 , if conductive adhesive 5b is provided with a width equal to or greater than the thickness of joint 6, voids 25 that form within conductive adhesive 5b near the center of semiconductor element 2 may be difficult to remove and remain within joint 6. If the size of the voids 25 is large, the adhesive strength at joint 6 may be reduced, resulting in poor bonding and even impaired thermal conductivity. Depending on the susceptibility of voids 25 to formation in conductive adhesive 5b, the formation area, i.e., width, of conductive adhesive 5b must be appropriately considered.

[0038] Here, the width of the conductive adhesive 5b at one end of the joint 6 in the lateral direction is set to be equal to or less than the thickness of the joint 6, but the width of the conductive adhesive 5b here may be considered to be the width directly below the semiconductor element 2 (the width in the area covered by the semiconductor element 2). In other words, as shown in Figure 2, when a portion of the conductive adhesive 5b is provided outside the semiconductor element 2 in a plan view, even if the width of the conductive adhesive 5b is greater than the thickness of the joint 6, voids 25 can be effectively discharged as long as the width of the conductive adhesive 5b directly below the semiconductor element 2 is equal to or less than the thickness of the joint 6.

[0039] Furthermore, as a result of analysis by the inventors, it has been found that if the ratio of conductive adhesive 5a to conductive adhesive 5b in a predetermined direction in plan view (any direction along the X-Y plane) is 5:1 on the diagonal of joint 6, or if the ratio of the second conductive adhesive is smaller than that, voids 25 occurring in joint 6 can be effectively discharged. In other words, if the width of conductive adhesive 5b adjacent to one side of conductive adhesive 5a in the lateral direction is one-fifth or less of the width of conductive adhesive 5a, voids 25 can be effectively discharged.

[0040] The invention made by the present inventors has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the embodiments and can be modified in various ways without departing from the spirit of the invention.

[0041] The control board of the present invention is configured such that the conductive adhesive used to bond the wiring board and semiconductor element has conductive particles whose main component is silver, and the joint formed with the conductive adhesive has a central portion bonded with a conductive adhesive that has high adhesive strength and good bonding properties, and the periphery is covered with a conductive adhesive that has a low cure shrinkage rate, and the dimensions, ratios, and shapes of each are not limited to the configuration shown in the figure, and the constituent materials such as the semiconductor element and wiring board to be used are arbitrary.

[0042] The present invention can be widely used in control boards.

[0043] REFERENCE SIGNS LIST 1 wiring substrate 1a first main surface 1b second main surface 2 semiconductor element 3 metallization 4 electrodes 5a, 5b conductive adhesive 6 joint 10 control substrate

Claims

1. A control board having a wiring board including a first main surface and a second main surface on the opposite side of the first main surface, an electrode formed on the first main surface of the wiring board, and a semiconductor element adhered onto the electrode via a conductive bonding portion, wherein the conductive particles contained in the bonding portion are silver, and the bonding portion has a first conductive adhesive and a second conductive adhesive disposed so as to surround the outer periphery of the first conductive adhesive in a plan view.

2. The control board according to claim 1, wherein the first conductive adhesive contains an epoxy resin, and the second conductive adhesive contains a silicone resin.

3. The control board according to claim 1, wherein the first conductive adhesive has a higher adhesive strength than the second conductive adhesive, and the second conductive adhesive has a smaller curing shrinkage rate than the first conductive adhesive.

4. The control board according to claim 1, wherein in a direction along the first main surface, the width of the second conductive adhesive adjacent to one side surface of the first conductive adhesive is 1 / 5 or less of the width of the first conductive adhesive.

5. The control board according to claim 1, wherein in a direction along the first main surface, the width of the second conductive adhesive is equal to or less than the thickness of the second conductive adhesive.

6. The control board according to claim 1, which operates at 77K or lower.

7. The control board according to claim 1, wherein the semiconductor element is a quantum chip or a quantum control chip.

Images