Method for manufacturing group iii nitride semiconductor template and group iii nitride semiconductor template manufactured thereby

Abstract

The present invention relates to a method for manufacturing a Group III nitride semiconductor template and a Group III nitride semiconductor template manufactured thereby and, more specifically, to a method for manufacturing a Group III nitride semiconductor template and a Group III nitride semiconductor template manufactured thereby, wherein a seed layer is formed of a single-crystal metal oxide having a corundum crystal structure so that a high-quality Group III nitride semiconductor device active layer can be re-grown.

Description

Method for manufacturing a group III nitride semiconductor template and a group III nitride semiconductor template manufactured thereby

[0001] The present invention relates to a method for manufacturing a group III nitride semiconductor template and a group III nitride semiconductor template manufactured thereby, and more particularly, to a method for manufacturing a group III nitride semiconductor template in which a seed layer is formed of a single crystal metal oxide having a corundum crystal structure, thereby allowing a high-quality group III nitride semiconductor device active layer to be re-grown, and a group III nitride semiconductor template manufactured thereby.

[0002] In a GaN material-based power semiconductor (HEMT, high electron mobility transistor) device with a horizontal channel structure based on a technology that directly grows GaN material on top of a conventional Si single crystal growth substrate wafer, a design that suppresses the leakage current of the power semiconductor device through a high-quality epitaxial thin film growth technology with high breakdown voltage and high reliability characteristics is essential in order for the device to be operated stably at high temperatures with high voltage and / or high-speed switching functions.

[0003] To this end, the conventional group III nitride semiconductor thin film material and its power semiconductor devices have a structure in which 1) a Si single crystal growth substrate wafer having electrically high resistance characteristics is provided, 2) a melt-back etching prevention layer growth including an AlN material system (nitride or nitride oxide containing an Al composition) to suppress the melt-back etching phenomenon through reaction at high temperatures with the surface layer of the Si single crystal growth substrate wafer, 3) a crack prevention condensation stress layer growth including an AlGaN material system (group III nitride containing an Al or Ga composition), and 4) a power semiconductor active layer growth including a GaN material system (group III nitride containing a Ga composition) are sequentially laminated and formed.

[0004] And the power semiconductor active layer (HEMT, high electron mobility transistor) of the horizontal channel structure including the above-described GaN material system is typically formed by stacking four regions: 1) GaN buffer layer, 2) GaN channel layer (horizontal transistor), 3) AlGaN barrier layer, and 4) capping passivation layer (depletion mode) or p-type nitride semiconductor layer (enhancement mode).

[0005] That is, in the group III nitride power semiconductor HEMT device structure in which a GaN material system is grown directly on top of a conventional Si single crystal growth substrate wafer, a high-resistance Si single crystal growth substrate wafer must be applied along with the formation of a high-resistance GaN buffer layer under the GaN channel layer, but there are the following problems.

[0006] First, in the conventional group III nitride (GaN material-based) power semiconductor HEMT device structure, a process is performed to directly grow a GaN material-based single crystal thin film and a power semiconductor device structure on top of a Si single crystal wafer for group III nitride power semiconductor growth substrate using MOCVD (metal organic chemical vapor deposition) equipment. At this time, a high temperature of around 1000°C and a reducing atmosphere (H2, H + , NH3, radical ions) is basically performed in a single crystal thin film growth (film formation) process of GaN material system containing Ga atoms, and a melt-back etching prevention film area is absolutely necessary to block the active occurrence of Si-Ga metallic eutectic reaction with relatively small energy between the Si single crystal wafer surface layer and Ga atoms.

[0007] This melt-back etching prevention film region typically has a thickness of about 100 nm, and is typically formed by an AlN material layer grown in-situ within a MOCVD chamber. However, in addition, an AlN or AlNO material layer can be formed ex-situ on top of a Si single crystal wafer for group III nitride power semiconductor growth substrates before loading into the MOCVD chamber using other external deposition process equipment (sputter, PLD, ALD).

[0008] However, when forming a melt-back etching prevention film region with the above-described AlN material layer on top of a Si single crystal wafer for a growth substrate having electrically high resistance characteristics, although the level of damage to the surface of the Si growth substrate during the AlN growth is less, there is still a problem that a Si-Al metallic process reaction occurs all over the surface or locally on the Si growth substrate surface to form a conductive interface material layer, which causes a deterioration in the crystal quality of the GaN material system grown in the continuous process. In addition, there is a problem that the crystal quality deteriorates (crystallinity decreases) due to the formation of a conductive interface material (disordered SiAlN) due to damage to the surface of the Si growth substrate, and as a result, the leakage current increases due to an increase in the density of “dislocations,” which are major crystal defects, which ultimately promotes the insulation breakdown phenomenon.

[0009] Second, in the conventional group III nitride (GaN material-based) power semiconductor HEMT device structure described above, when growing (or forming) a material, the process must be carried out by considering the lattice constant (LC) and coefficient of thermal expansion (CTE), which are material-specific values ​​between different heterogeneous materials. However, when the difference in the lattice constant (LC) and coefficient of thermal expansion (CTE) between the two materials is large, micro or macro cracks inevitably occur or the crystal quality deteriorates in the grown (formed) material thin film due to structural and thermo-mechanical stress during or after the growth (formation) process. In particular, when directly growing (or forming) a GaN material or an AlN material on top of a Si single crystal wafer for a group III nitride power semiconductor growth substrate, a strong tensile stress is generated in terms of the coefficient of thermal expansion (CTE) and / or lattice constant (LC), so that cracking can be easily observed, and a high breakdown voltage and high reliability device can be realized by growing to a predetermined thickness or more, but the thickness of the group III nitride power semiconductor device structure cannot be increased due to the tensile stress.

[0010] Although various technologies have been devised as a means of relieving the tensile stress or suppressing cracks as described above, a crack prevention condensation stress layer is introduced and used by introducing a material and process that artificially generates compressive stress so as to compensate for and buffer the tensile stress, by laminating an AlGaN material system including an Al or Ga composition in a known multilayer structure on the melt-back etching prevention film area as described above to suppress the crack phenomenon.

[0011] However, the crack prevention condensation stress layer of the conventional group III nitride (GaN material system) power semiconductor HEMT device structure described above has the problem that it is difficult to grow a thick layer with high quality when forming an AlGaN material system with a high Al ratio, and dislocations are generated due to a decrease in crystal quality, which promotes an increase in leakage current.

[0012] Thirdly, in the conventional group III nitride (GaN material) power semiconductor HEMT device structure, a GaN buffer layer is typically formed by heavily doping with impurities such as Fe or C to have high resistance in order to suppress leakage current under the GaN channel layer.

[0013] However, according to the conventional group III nitride (GaN material) power semiconductor HEMT device structure, there is a problem that the crystal quality of the GaN material is greatly degraded due to excessive doping of impurities such as Fe or C, and fatal crystal defects, i.e., an increase in dislocation density, promotes an increase in leakage current. In addition, there is a problem that the GaN channel layer and AlGaN barrier layer grown on top of the GaN buffer layer with low crystal quality also have low crystal quality due to the low crystal quality.

[0014] Accordingly, in order to improve crystal quality, the GaN on Sapphire method, which has the next best crystal quality after the power semiconductor devices manufactured using the GaN on GaN method, is widely used, and the epitaxial film deposition technology for this method has already been developed and matured. However, the only drawback of the GaN on Sapphire method is that the heat dissipation ability of sapphire is poor, which limits its application to high-power products.

[0015] To overcome this, high-output products have been developed using SiC and Si growth substrates with high heat dissipation, but they are inferior to epitaxy grown on sapphire growth substrates in terms of performance, crystal quality, defects, and cost.

[0016] In addition, in order to improve the heat dissipation performance of the power semiconductor device, when the growth substrate is completely removed and a high-heat dissipation support substrate is bonded, there is an advantage that the heat dissipation performance of the power semiconductor device can be significantly improved, but there is a problem that the support substrate may be separated due to thermo-mechanical shock or material diffusion due to the weak bonding strength of the bonding layer during the process of removing the growth substrate and bonding the high-heat dissipation support substrate, which has a negative effect on the long-term reliability of the power semiconductor device.

[0017] The purpose of the present invention is to solve the above-described conventional problems, and to provide a method for manufacturing a group III nitride semiconductor template in which a high-quality group III nitride semiconductor device active layer can be re-grown by forming a seed layer of a single crystal metal oxide having a corundum crystal structure, and a group III nitride semiconductor template manufactured thereby.

[0018] The above object is achieved by a method for manufacturing a group III nitride semiconductor template, comprising: a growth step of growing a sacrificial layer on a growth substrate; a film formation step of forming a seed layer on the sacrificial layer; a bonding step of bonding one surface of the seed layer to a support substrate through a bonding layer; a removal step of removing the growth substrate; and a surface preparation step of removing the sacrificial layer to expose the other surface of the seed layer, characterized in that the seed layer is formed of a single-crystal metal oxide having a corundum crystal structure.

[0019] In addition, the present invention may further include a re-growth step of re-growing the device active layer on the other surface of the exposed seed layer.

[0020] Additionally, the sacrificial layer can be formed of a single crystal material having a hexagonal close packed lattice (HCP) crystal structure.

[0021] Additionally, the above film forming step can perform heat treatment on the formed seed layer.

[0022] In addition, the bonding step may bond one surface of the seed layer to the support substrate by forming a first bonding layer on one surface of the seed layer, forming a second bonding layer on the support substrate, and then bonding the first bonding layer and the second bonding layer to each other.

[0023] Additionally, the bonding step can form a positive or negative pattern at a preset depth on at least one of the seed layer or the first bonding layer.

[0024] Additionally, the bonding step can form a positive or negative pattern at a preset depth on at least one of the support substrate or the second bonding layer.

[0025] In addition, the bonding step may form a first pattern on the seed layer and a second pattern on the first bonding layer, and the first pattern may be formed to penetrate the seed layer but be in communication with the second pattern.

[0026] Additionally, the first pattern and the second pattern may be filled with a masking material to remove an air gap.

[0027] In addition, each of the first bonding layer and the second bonding layer may include a bonding reinforcing layer for reinforcing bonding with the seed layer or the support substrate, a surface planarizing layer for alleviating roughness of the surface of the seed layer or the support substrate, and a bonding layer for bonding the seed layer and the support substrate to each other.

[0028] The above object is achieved by a method for manufacturing a group III nitride semiconductor template, according to the present invention, comprising: a growth step of growing a sacrificial layer on a growth substrate; a deposition step of forming a seed layer on the sacrificial layer; a bonding step of bonding one surface of the seed layer to a temporary substrate through an adhesive layer; a first removal step of removing the growth substrate; an exposure step of removing the sacrificial layer to expose the other surface of the seed layer; a bonding step of bonding the other surface of the seed layer to a support substrate through a bonding layer; a second removal step of removing the temporary substrate; and a surface preparation step of removing the adhesive layer to expose one surface of the seed layer, wherein the seed layer is formed of a single crystal metal oxide having a corundum crystal structure.

[0029] In addition, the present invention may further include a re-growth step of re-growing a device active layer on one surface of the exposed seed layer.

[0030] Additionally, the sacrificial layer can be formed of a single crystal material having a hexagonal close packed lattice (HCP) crystal structure.

[0031] Additionally, the above film forming step can perform heat treatment on the formed seed layer.

[0032] In addition, the bonding step can bond the other surface of the seed layer to the support substrate by forming a first bonding layer on the other surface of the seed layer, forming a second bonding layer on the support substrate, and then bonding the first bonding layer and the second bonding layer to each other.

[0033] Additionally, the bonding step can form a positive or negative pattern at a preset depth on at least one of the seed layer or the first bonding layer.

[0034] Additionally, the bonding step can form a positive or negative pattern at a preset depth on at least one of the support substrate or the second bonding layer.

[0035] In addition, the bonding step may form a first pattern on the seed layer and a second pattern on the first bonding layer, and the first pattern may be formed to penetrate the seed layer but be in communication with the second pattern.

[0036] Additionally, the first pattern and the second pattern may be filled with a masking material to remove an air gap.

[0037] In addition, each of the first bonding layer and the second bonding layer may include a bonding reinforcing layer for reinforcing bonding with the seed layer or the support substrate, a surface planarizing layer for alleviating roughness of the surface of the seed layer or the support substrate, and a bonding layer for bonding the seed layer and the support substrate to each other.

[0038] The above object is achieved by a group III nitride semiconductor template manufactured by a method for manufacturing a group III nitride semiconductor template according to the present invention.

[0039] According to the present invention, a seed layer for group III nitride semiconductor growth formed of a single crystal metal oxide thin film having a corundum crystal structure, which is the most stable at all temperatures and pressures, is bonded to a final support substrate having high heat dissipation performance as a high heat-resistant bonding material layer, thereby enabling single crystal growth of a high-quality group III nitride semiconductor at a high temperature of 700°C or higher.

[0040] In addition, according to the present invention, since the device active layer of the group III nitride single crystal thin film grown on the seed layer formed of the single crystal metal oxide thin film having the corundum crystal structure and the final support substrate have the same or similar thermal expansion coefficients, the thermal stress generated during growth is minimized, and thus the device active layer with minimized crystal defects can be grown thickly.

[0041] In addition, according to the present invention, issues arising from wafer surface roughness and wafer warpage due to a positive or negative pattern formed on a bonding layer, etc., can be resolved, and the bonding strength of the bonding layer can be strengthened by preventing the formation of voids inside the bonding layer (void-free) by facilitating the discharge of gas generated inside the bonding layer.

[0042] Meanwhile, the effects of the present invention are not limited to the effects mentioned above, and various effects may be included within a range obvious to those skilled in the art from the contents described below.

[0043] Figure 1 is a flowchart of a method for manufacturing a group III nitride semiconductor template according to the first embodiment of the present invention.

[0044] FIG. 2 illustrates a process for manufacturing a group III nitride semiconductor template according to a method for manufacturing a group III nitride semiconductor template according to a first embodiment of the present invention.

[0045] FIGS. 3 to 5 illustrate the formation of a positive or negative pattern on at least one of the seed layer or the first bonding layer in a method for manufacturing a group III nitride semiconductor template according to the first embodiment of the present invention.

[0046] FIGS. 6 to 8 illustrate the formation of a positive or negative pattern on at least one of a support substrate or a second bonding layer in a method for manufacturing a group III nitride semiconductor template according to the first embodiment of the present invention.

[0047] FIG. 9 illustrates that the patterns formed in the first bonding layer of the method for manufacturing a group III nitride semiconductor template according to the first embodiment of the present invention are formed at different depths.

[0048] FIG. 10 illustrates an example of a positive or negative pattern shape of a method for manufacturing a group III nitride semiconductor template according to the first embodiment of the present invention.

[0049] FIG. 11 illustrates that after a pattern is formed on the second bonding layer in the method for manufacturing a group III nitride semiconductor template according to the first embodiment of the present invention, an active layer of the device is re-grown on the seed layer.

[0050] FIG. 12 illustrates a method for manufacturing a group III nitride semiconductor template according to a first embodiment of the present invention, in which a pattern is formed on the first bonding layer and the seed layer, and then the device active layer is re-grown on the seed layer.

[0051] FIG. 13 illustrates a method for manufacturing a group III nitride semiconductor template according to a first embodiment of the present invention, in which a masking material is filled in the pattern of the first bonding layer and the seed layer, and then the device active layer is re-grown on the seed layer.

[0052] FIG. 14 illustrates in detail the first bonding layer and the second bonding layer of the method for manufacturing a group III nitride semiconductor template according to the first embodiment of the present invention.

[0053] FIG. 15 is a flowchart of a method for manufacturing a group III nitride semiconductor template according to a second embodiment of the present invention.

[0054] FIG. 16 illustrates a process for manufacturing a group III nitride semiconductor template according to a method for manufacturing a group III nitride semiconductor template according to a second embodiment of the present invention.

[0055] Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. When designating components in each drawing, it should be noted that, where possible, identical components are given the same reference numerals, even if they appear in different drawings.

[0056] In addition, when describing an embodiment of the present invention, if a detailed description of a related known configuration or function is judged to hinder understanding of the embodiment of the present invention, the detailed description is omitted.

[0057] Additionally, when describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only intended to distinguish the components from other components, and the nature, order, or sequence of the components are not limited by the terms.

[0058]

[0059] From now on, with reference to the attached drawings, a method for manufacturing a group III nitride semiconductor template (S100) according to the first embodiment of the present invention will be described in detail.

[0060] FIG. 1 is a flowchart of a method for manufacturing a group III nitride semiconductor template according to a first embodiment of the present invention, and FIG. 2 illustrates a process for manufacturing a group III nitride semiconductor template according to a method for manufacturing a group III nitride semiconductor template according to the first embodiment of the present invention.

[0061] As illustrated in FIGS. 1 and 2, the method (S100) for manufacturing a group III nitride semiconductor template according to the first embodiment of the present invention includes a growth step (S110), a film formation step (S120), a bonding step (S130), a removal step (S140), a surface preparation step (S150), and a re-growth step (S160).

[0062] The growth stage (S110) is the stage in which a sacrificial layer (N) is grown on the initial growth substrate (G).

[0063] When the first growth substrate (G) is removed through the laser lift off (LLO) technique in the removal step (S140) described below, it is preferable that the first growth substrate (G) be formed of an optically transparent and high-temperature heat-resistant substrate that can transmit a laser beam (single wavelength light) 100% (theoretically) without absorption, and may be formed of a material such as sapphire (α-phase Al2O3), ScMgAlO4, 4H-SiC, or 6H-SiC. In addition, it is also preferable that the first growth substrate (G) be formed of a patterned sapphire substrate (PSS) that has a protrusion shape that is regularly or irregularly patterned in various dimensions (sizes and shapes) in the microscale or nanoscale in order to minimize crystal defects inside the group III-nitride semiconductor thin film grown thereon.

[0064] In addition, when the initial growth substrate (G) is removed through a chemical lift off (CLO) technique in the removal step (S140) described later, it is preferable that the initial growth substrate (G) be prepared as a Si substrate that can be removed through wet etching and that allows mechanical polishing and selective etching, and the Si substrate can be formed of Si having a (111) crystal plane so that growth of a high-quality group III nitride semiconductor thin film is possible.

[0065] The sacrificial layer (N) is a layer that is sacrificed and separated to easily separate a thin film grown (film formed) on top of the substrate from the initial growth substrate (G) using a laser beam in the laser lift-off (LLO) technique or an etching solution in the chemical lift-off (CLO) technique. At the same time, in the present invention, the sacrificial layer (N) is formed of a material that promotes the seed layer (140) for group III nitride semiconductor growth formed on top of a metal oxide to have a single-crystal corundum crystal structure (i.e., an epitaxial α-phase microstructure) through a solid phase epitaxy (SPE) mechanism.

[0066] In the existing nucleation and growth technique, the material crystallization step proceeds at a high temperature (high energy) of at least 1000℃, but in most cases, there is a disadvantage in that a polycrystal microstructure is formed preferentially rather than a single crystal. In contrast, the SPE mechanism of the present invention is used to form a single crystal semiconductor thin film, and by making the formed matrix (substrate or buffer layer) prior to thin film crystallization have a single crystal microstructure that is the same crystal structure as the target material of thin film crystallization, it is possible to single crystalize (epitaxy) a thin film material through atomic rearrangement even at a relatively much lower temperature (low activation energy).

[0067] That is, the sacrificial layer (N) of the present invention is formed as a single crystal thin film having the same and / or similar crystal structure as the seed layer (140) on top of the initial growth substrate (G) for single crystallization of the group III nitride semiconductor growth seed layer (140) formed on top.

[0068] To this end, the sacrificial layer (N) can be formed of a single crystal material having a hexagonal close packed lattice (HCP) crystal structure, and the sacrificial layer (N) can be formed of a group III nitride grown on a growth substrate (G) through molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD), or can be formed of a group II oxide grown through sputtering or MOCVD. Here, the group III nitride used as the sacrificial layer (N) can include, for example, GaN, AlGaN, AlN, InGaN, AlInN, InN, AlNO, and GaNO, and the group II oxide can include, but is not limited to, ZnO and MgZnO.

[0069] The membrane formation step (S120) is a step of forming a seed layer (140) on a sacrificial layer (N).

[0070] The seed layer (140) promotes the growth of a high-quality group III nitride semiconductor thin film or a light-emitting element, power semiconductor element, or communication filter structure composed thereof, and may be formed of a single crystal metal oxide having a corundum crystal structure by the above-described sacrificial layer (N) and the SPE mechanism. This seed layer (140) may be formed into a single layer or multiple layers with a preset thickness (for example, 100 nm or less) through techniques such as sputtering, ALD (atomic layer deposition), and PLD (pulsed laser deposition), and the material to be formed may include, but is not limited to, Al2O3, Cr2O3, V2O3, or Fe2O3.

[0071] Meanwhile, in the film formation step (S120), heat treatment (annealing) may be performed on the seed layer (140) formed at a temperature of around 1000°C so that the single crystal microstructure of the corundum crystal structure of the seed layer (140) can be further improved.

[0072] The bonding step (S130) is a step of bonding one surface of the seed layer (140) to the final support substrate (110) through the bonding layer (130).

[0073] Here, the final support substrate (110) is a substrate that supports the seed layer (140) and the device active layer (150) on the upper side of the seed layer (140) after going through each step of the method for manufacturing a group III nitride semiconductor template (S100) according to the first embodiment of the present invention. In this embodiment, the final support substrate (110) has high heat dissipation performance (60 W / mk or more), has a coefficient of thermal expansion (CTE, ppm unit) equal to or similar to that of the device active layer (150), and can be formed of a material that can have a polycrystalline microstructure as a result of a high-temperature sintering process. An example of the corresponding material is SiN. x (90W / mk, 3.7ppm), AlN (170~230W / mk, 4.5 ppm), SiC (300~450W / mk, 4.8 ppm) or Si (149W / mk, 2.6 ppm), but is not limited thereto.

[0074] Conventionally, warpage of an epitaxial wafer occurs due to thermo-mechanical induced stress caused by the difference in lattice constant (LC) and coefficient of thermal expansion (CTE) between the initial growth substrate (G) and the group III nitride semiconductor. However, in the present invention, this can be resolved by strongly bonding the final support substrate (110) to one surface of the seed layer (140) through a bonding layer (130). That is, in the case of an epitaxial wafer to which the final support substrate (110) is bonded, the wafer bow can be minimized to almost zero (0) in a stress-relieved state, so there is an advantage that it can be applied to wafer sizes of 4 inches, 6 inches, 8 inches, and even 12 inches or more.

[0075] More specifically, in the bonding step (S130), a first bonding layer (B1) is formed on one surface of the seed layer (140), a second bonding layer (B2) is formed on the final support substrate (110), and then the first bonding layer (B1) and the second bonding layer (B2) are bonded to each other, thereby bonding one surface of the seed layer (140) to the final support substrate (110).

[0076] Here, the bonding layer (130) (including the first bonding layer (B1) and the second bonding layer (B2)) is preferably made of a dielectric material that has excellent thermal conductivity and no change in physical properties in the MOCVD chamber (at a temperature of 1000°C or higher and a reducing atmosphere) for growing a group III nitride semiconductor, for example, SiO 2( 0.8ppm), SiN x(3.7ppm), SiCN (3.8-4.8ppm), AlN (4.5ppm), Al2O3 (6.8ppm), amorphous Si, and further, FOx (Flowable Oxides) such as SOG (Spin On Glass, liquid SiO2), HSQ (Hydrogen Silsesquioxane) may be included to improve surface roughness. Furthermore, the bonding layer (130) may be formed of a metal such as Al, W, or Mo, or an alloy thereof.

[0077] Accordingly, in the present invention, a seed layer (140) for group III nitride semiconductor growth formed of a single crystal metal oxide thin film having a corundum crystal structure, which is the most stable phase at all temperatures and pressures, is bonded to a final support substrate (110) having high heat dissipation performance as a high heat-resistant bonding material layer, thereby enabling single crystal growth of a high-quality group III nitride semiconductor at a high temperature of 700°C or higher.

[0078] In addition, since the device active layer (150) of the group III nitride single crystal thin film grown on the seed layer (140) formed of a single crystal metal oxide thin film having a corundum crystal structure and the final support substrate (110) have the same or similar thermal expansion coefficients, the thermal stress generated during growth is minimized, and thus the device active layer with minimized crystal defects can be grown thickly.

[0079] Meanwhile, in the bonding step (S130) of the present invention, a reinforcing layer and a first bonding layer (B1) are sequentially laminated and formed on one surface of a seed layer (140), and a reinforcing layer and a second bonding layer (B2) are sequentially laminated and formed on a final support substrate (110), and then the first bonding layer (B1) and the second bonding layer (B2) are pressed against each other to form a bonding layer (130).

[0080] Here, the reinforcement layer is a layer for reinforcing the bonding strength with the support substrate (110) and inducing condensation stress, and the reinforcement layer may include, in more detail, a bonding reinforcement layer and a condensation stress layer.

[0081] The bonding reinforcement layer is a layer introduced to strengthen the bonding strength when the seed layer (140) is bonded to the final support substrate (110) through the bonding layer (130), and the material constituting the bonding reinforcement layer is SiO2, SiN. x It is desirable to select first among the following.

[0082] The condensation stress layer is a layer that causes condensation stress and is a dielectric material having a larger value than the thermal expansion coefficient of the final support substrate (110), for example, AlN (4.6 ppm), AlNO (4.6-6.8 ppm), Al2O 3( It is composed of materials that relieve tensile stress, i.e. induce condensation stress, such as SiC (6.8ppm), SiCN (3.8-4.8ppm), GaN (5.6ppm), and GaNO (5.6-6.8ppm), which play a role in improving product quality through stress control.

[0083] Meanwhile, in the present invention, the bonding reinforcement layer or the condensation stress layer may be omitted in some cases, and in some cases, the entire reinforcement layer may be omitted so that one surface of the seed layer (140) and the bonding layer (130) are in direct contact, or the final support substrate (110) and the bonding layer (130) are in direct contact. In such a case, the bonding layer (130) may be formed by depositing a material having a larger coefficient of thermal expansion than that of the final support substrate (110), thereby inducing a condensation stress along with the bonding function.

[0084] Meanwhile, a positive or negative pattern (P) can be formed on the bonding layer (130) of the present invention.

[0085] FIGS. 3 to 5 illustrate the formation of a positive or negative pattern on at least one of a seed layer or a first bonding layer in a method for manufacturing a group III nitride semiconductor template according to a first embodiment of the present invention, FIGS. 6 to 8 illustrate the formation of a positive or negative pattern on at least one of a support substrate or a second bonding layer in a method for manufacturing a group III nitride semiconductor template according to a first embodiment of the present invention, FIG. 9 illustrates the formation of patterns at different depths on the first bonding layer in a method for manufacturing a group III nitride semiconductor template according to a first embodiment of the present invention, and FIG. 10 illustrates examples of positive or negative pattern shapes in a method for manufacturing a group III nitride semiconductor template according to a first embodiment of the present invention.

[0086] Direct wafer bonding requires strict wafer surface roughness, and there is the problem of weakened bonding strength in the event of wafer warpage. Furthermore, gas generated within the bonding layer (130) during the wafer bonding process can weaken the bonding strength or cause quality issues in subsequent processes.

[0087] Accordingly, in the present invention, a positive or negative pattern (P) is formed by etching the bonding layer (130), and in some cases, the pattern (P) is also formed on the seed layer (140) or the final support substrate (110). By using this pattern (P), issues arising from wafer surface roughness and wafer warpage can be resolved, and the bonding strength of the bonding layer (130) can be strengthened by facilitating the discharge of gas generated within the bonding layer (130) to prevent voids from being generated within the bonding layer (130) (void-free). Furthermore, the thermal ductility stress acting on the wafer can be significantly alleviated by the patterns (P) formed on the bonding layer (130).

[0088] More specifically, in the bonding step (S130) of the present invention, the above-described positive or negative pattern (P) can be formed on the bonding layer (130), the seed layer (140), or the final support substrate (110) in various ways, and the bonding step (S130) can form the positive or negative pattern (P) at a preset depth on at least one of the seed layer (140) or the first bonding layer (B1). For example, as illustrated in FIG. 3, a positive or negative pattern (P) can be formed only on the first bonding layer (B1), and as illustrated in FIG. 4, a positive or negative pattern (P) can be formed only on the seed layer (140), and then the first bonding layer (B1) can be formed along the pattern (P), so that the patterns (P) of the seed layer (140) and the first bonding layer (B1) can be formed to alternate with each other, and as illustrated in FIG. 5, a pattern (P) can be formed on each of the seed layer (140) and the first bonding layer (B1), but the patterns (P) can be formed to be connected to each other.

[0089] In addition, the bonding step (S130) can form a positive or negative pattern (P) at a preset depth on at least one of the final support substrate (110) or the second bonding layer (B2). For example, as illustrated in FIG. 6, a positive or negative pattern (P) can be formed only on the second bonding layer (B2), and as illustrated in FIG. 7, a positive or negative pattern (P) can be formed only on the final support substrate (110), and then the second bonding layer (B2) can be formed along the pattern (P), so that the patterns (P) of the final support substrate (110) and the second bonding layer (B2) can be formed to alternate with each other, and as illustrated in FIG. 8, a pattern (P) can be formed on each of the final support substrate (110) and the second bonding layer (B2), but so that the patterns (P) are connected to each other.

[0090] At this time, as illustrated in FIG. 9, the formed positive or negative pattern (P) may be etched to penetrate the entire first bonding layer (B1) (or the second bonding layer (B2)) or may be etched to penetrate only a portion of the first bonding layer (B1) (or the second bonding layer (B2)), and as illustrated in FIG. 10, the shape of the formed pattern (P) may have, for example, a positive or negative hexagonal, circular, or square shape, but is not limited thereto.

[0091] Meanwhile, each of the first bonding layer (B1) and the second bonding layer (B2) of the present invention may include a bonding reinforcing layer (R), a surface planarizing layer (F), and a bonding layer (J).

[0092] FIG. 14 illustrates in detail the first bonding layer and the second bonding layer of the method for manufacturing a group III nitride semiconductor template according to the first embodiment of the present invention.

[0093] As shown in Fig. 14, the bonding reinforcement layer (R) is for strengthening the bonding with the seed layer (140) or the final support substrate (110), and this bonding reinforcement layer (R) is, for example, SiO x , SiN x , may contain Cr, Ti, Mo or HMDS.

[0094] The surface planarization layer (F) is intended to alleviate the roughness of the surface of the seed layer (140) or the final support substrate (110), and the surface planarization layer (F) may include, for example, a flowable oxide (FOx) such as spin on glass (SOG) or hydrogen silsesquioxane (HSQ) to improve the surface roughness.

[0095] The bonding layer (J) is used to bond the seed layer (140) and the final support substrate (110) to each other by bonding the first bonding layer (B1) and the second bonding layer (B2), and may be formed of a permanent bonding material, for example, SiO.2( 0.8ppm), SiN x( 3.7ppm), SiCN (3.8-4.8ppm), AlN (4.5ppm), Al2O3 (6.8ppm), amorphous Si, and further, FOx (Flowable Oxides) such as SOG (Spin On Glass, liquid SiO2), HSQ (Hydrogen Silsesquioxane) may be included to improve surface roughness. Furthermore, the bonding layer (130) may be formed of a metal such as Al, W, or Mo, or an alloy thereof.

[0096] The above-described bonding reinforcement layer (R) and surface planarization layer (F) can be introduced or deleted depending on the process, and when the bonding reinforcement layer (R) and surface planarization layer (F) are deleted depending on the process, the bonding layer (J) can be directly formed on the seed layer (140) or the final support substrate (110).

[0097] The removal step (S140) is a step of removing the initial growth substrate (G) using a laser lift off (LLO) technique or a chemical lift off (CLO) technique depending on the material of the initial growth substrate (G).

[0098] Here, the laser lift-off technique is a technique for separating an epitaxially grown layer from the initial growth substrate (G) by irradiating the back surface of a transparent initial growth substrate (G) with an ultraviolet (UV) laser beam having a uniform optical output and beam profile and a single wavelength. When the initial growth substrate (G) is separated, the inside of the seed layer (140) transferred to the final support substrate (110) is in a state where stress is completely relieved and remains flat together with the final support substrate (110).

[0099] In addition, the chemical lift-off technique is a technique to separate and remove the Si material of the initial growth substrate (G) by wet etching with a TMAH (tetramethylammonium hydroxide) or HNA (hydrofluoric + nitric + acetic acids) solution to completely remove the thin Si remaining after mechanically grinding and polishing the back surface of the Si initial growth substrate (G) having a (111) crystal plane. When the initial growth substrate (G) is separated, the inside of the seed layer (140) transferred to the final support substrate (110) is in a state where the stress is completely relieved and remains flat together with the final support substrate (110). Meanwhile, before removing the residual Si material after mechanically polishing the initial growth substrate (G), SiO2, SiN x It is desirable to protect the back from the etching solution by depositing a protective film.

[0100] The surface preparation step (S150) is a step for exposing the other surface of the seed layer (140) by removing the damaged area, contaminated surface residue, and low-quality single crystal thin film area of ​​the exposed other surface of the seed layer (140) after removing the sacrificial layer (N). Here, the sacrificial layer (N) and the low-quality single crystal thin film area can be removed through dry etching or wet etching.

[0101] The re-growth step (S160) is a step of re-growing a group III nitride device active layer (150) for a power semiconductor device, a light-emitting device, or a communication filter device on the other surface of the exposed seed layer (140).

[0102] FIG. 11 illustrates that after a pattern is formed in the second bonding layer of the method for manufacturing a group III nitride semiconductor template according to the first embodiment of the present invention, a device active layer is re-grown on the seed layer, and FIG. 12 illustrates that after a pattern is formed in the first bonding layer and the seed layer of the method for manufacturing a group III nitride semiconductor template according to the first embodiment of the present invention, a device active layer is re-grown on the seed layer, and FIG. 13 illustrates that after a masking material is filled in the pattern of the first bonding layer and the seed layer of the method for manufacturing a group III nitride semiconductor template according to the first embodiment of the present invention, a device active layer is re-grown on the seed layer.

[0103] Meanwhile, the device active layer (150) can be grown in various ways depending on the surface state of the group III nitride semiconductor template.

[0104] For example, as illustrated in FIG. 11, when a positive or negative pattern (P) is formed only on the second bonding layer (B2), and the pattern (P) is formed on the bonding layer (130) so as to face the seed layer (140), an appropriate balance control of the growth speed in the horizontal direction of the XY plane and the vertical direction of the Z axis is required.

[0105] In addition, as illustrated in FIG. 12, when a first pattern (P1) is formed to penetrate the entire seed layer (140) and a second pattern (P2) is formed on the bonding layer (130) (first bonding layer (B1)) to be connected to the first pattern (P1), in order to merge the air-gap region, it is necessary to increase the growth speed in the horizontal direction of the XY plane more than in the vertical direction of the Z axis in the early stage of growth.

[0106] In addition, as illustrated in FIG. 13, in the case where the first pattern (P1) is formed to penetrate the entire seed layer (140) and the second pattern (P2) is formed on the bonding layer (130) (the first bonding layer (B1)) to be connected to the first pattern (P1), a masking material (M) for removing an air gap is filled in the interior of the first pattern (P1) and the second pattern (P2), and when the masking material (M) is formed to protrude on the upper surface of the seed layer (140), an ELOG (epitaxial lateral overgrowth) growth technique can be used between the protruding masking materials (M). At this time, the masking material (M) is SiO2, SiN x Or it can be prepared with AlN, etc., but is not limited thereto.

[0107] Meanwhile, the group III nitride semiconductor template manufactured according to the method for manufacturing a group III nitride semiconductor template (S100) according to the first embodiment of the present invention has a structure in which a support substrate (110), a bonding layer (130), and a seed layer (140) are ultimately laminated, and a structure in which an element active layer (150) is re-grown on the seed layer (140).

[0108]

[0109] From now on, with reference to the attached drawings, a method for manufacturing a group III nitride semiconductor template (S200) according to the second embodiment of the present invention will be described in detail.

[0110] FIG. 15 is a flowchart of a method for manufacturing a group III nitride semiconductor template according to a second embodiment of the present invention, and FIG. 16 illustrates a process for manufacturing a group III nitride semiconductor template according to a method for manufacturing a group III nitride semiconductor template according to a second embodiment of the present invention.

[0111] As illustrated in FIGS. 15 and 16, a method (S200) for manufacturing a group III nitride semiconductor template according to a second embodiment of the present invention includes a growth step (S210), a film formation step (S220), an adhesion step (S230), a first removal step (S240), an exposure step (S250), a bonding step (S260), a second removal step (S270), a surface preparation step (S280), and a re-growth step (S290).

[0112] Here, the growth step (S210) to the film formation step (S220) are the same as the method for manufacturing a group III nitride semiconductor template (S100) according to the first embodiment of the present invention described above, so a duplicate description is omitted.

[0113] The bonding step (S230) is a step of bonding one surface of the seed layer (140) to the intermediate temporary substrate (T) through the bonding layer (A).

[0114] Here, the intermediate temporary substrate (T) is formed of a material having a coefficient of thermal expansion (CTE) equal to or similar to that of the final support substrate (110) described later, and it is preferable that the difference in the coefficient of thermal expansion with that of the final support substrate (110) does not exceed 2 ppm at most.

[0115] Conventionally, warpage of an epitaxial wafer occurs due to thermo-mechanical induced stress caused by the difference in lattice constant (LC) and coefficient of thermal expansion (CTE) between the initial growth substrate (G) and the group III nitride semiconductor. However, in the present invention, this can be resolved by strongly bonding an intermediate temporary substrate (T) to one surface of a seed layer (140) through an adhesive layer (A). That is, in the case of an epitaxial wafer to which an intermediate temporary substrate (T) is bonded, the wafer bow can be minimized to almost zero (0) in a stress-relieved state, so there is an advantage that it can be applied to wafer sizes of 4 inches, 6 inches, 8 inches, and even 12 inches or more.

[0116] More specifically, in the bonding step (S230), an epitaxy protection layer and a first adhesive layer (A1) are sequentially laminated and formed on one surface of the seed layer (140), a separation layer and a second adhesive layer (A2) are sequentially laminated and formed on an intermediate temporary substrate (T), and then the first adhesive layer (A1) and the second adhesive layer (A2) are temporarily pressed against each other to form an adhesive layer (A). That is, in the bonding step (S230), the intermediate temporary substrate (T) on which the second adhesive layer (A2) is formed is turned over to separate the initial growth substrate (G), and the first adhesive layer (A1) is bonded to the initial growth substrate (G) by applying pressure at a temperature of less than 300°C.

[0117] The first removal step (S240) is a step of removing the initial growth substrate (G) using a laser lift off (LLO) technique or a chemical lift off (CLO) technique depending on the material of the initial growth substrate (G) to expose the sacrificial layer (N).

[0118] The exposure step (S250) is a step of removing the sacrificial layer (N) to expose the other surface of the seed layer (140). The exposed other surface of the seed layer (140) inevitably has a locally damaged area, and various surface crystal defects are inevitably formed during the growth of the seed layer (140). These crystal defects and damaged surfaces cause great difficulties and quality issues in the final support substrate (110) bonding described later, and therefore, it is essential to perform a surface planarization process through a ceramic material deposition and / or a CMP (chemical-mechanical polishing) process to improve this.

[0119] The bonding step (S260) is a step of bonding the other surface of the seed layer (140) to the final support substrate (110) through the bonding layer (130).

[0120] Here, the final support substrate (110) is a substrate that supports the seed layer (140) and the device active layer (150) on the upper side of the seed layer (140) after going through each step of the method for manufacturing a group III nitride semiconductor template according to the second embodiment of the present invention (S200). In this embodiment, the final support substrate (110) has high heat dissipation performance (60 W / mk or more), has a coefficient of thermal expansion (CTE, ppm unit) equal to or similar to that of the device active layer (150), and can be formed of a material that can have a polycrystalline microstructure as a result of a high-temperature sintering process. An example of the corresponding material is SiN. x (90W / mk, 3.7ppm), AlN (170~230W / mk, 4.5 ppm), SiC (300~450W / mk, 4.8 ppm) or Si (149W / mk, 2.6 ppm), but is not limited thereto.

[0121] Conventionally, warpage of an epitaxial wafer occurs due to thermo-mechanical induced stress caused by the difference in lattice constant (LC) and coefficient of thermal expansion (CTE) between the initial growth substrate (G) and the group III nitride semiconductor. However, in the present invention, this can be resolved by strongly bonding the final support substrate (110) to the other surface of the seed layer (140) through the bonding layer (130). That is, in the case of an epitaxial wafer to which the final support substrate (110) is bonded, the wafer bow can be minimized to almost zero (0) in a stress-relieved state, so there is an advantage that it can be applied to wafer sizes of 4 inches, 6 inches, 8 inches, and even 12 inches or more.

[0122] More specifically, in the bonding step (S260), a first bonding layer (B1) is formed on the other surface of the seed layer (140), a second bonding layer (B2) is formed on the final support substrate (110), and then the first bonding layer (B1) and the second bonding layer (B2) are bonded to each other, thereby bonding the other surface of the seed layer (140) to the final support substrate (110).

[0123] The following details regarding the bonding layer (130) of the bonding step (S260) are the same as those of the method for manufacturing a group III nitride semiconductor template (S100) according to the first embodiment of the present invention described above, and therefore, duplicate descriptions are omitted.

[0124] The second removal step (S270) is a step of removing the intermediate temporary substrate (T) using a laser lift off (LLO) technique or a chemical lift off (CLO) technique depending on the material of the intermediate temporary substrate (T) to expose the adhesive layer (A). When the intermediate temporary substrate (T) is separated, the inside of the seed layer (140) transferred to the final support substrate (110) is in a state where the stress is completely relieved and remains flat together with the final support substrate (110).

[0125] The surface preparation step (S280) is a step of exposing one surface of the seed layer (140) by etching and removing the separation layer, the adhesive layer (A), and the epitaxy protection layer. Here, the separation layer, the adhesive layer (A), and the epitaxy protection layer can be formed through dry etching or wet etching, and it is desirable to completely remove damaged areas, contaminated surface residues, and low-quality single crystal thin film areas resulting from the separation of the intermediate temporary substrate (T).

[0126] The re-growth step (S290) is a step of re-growing a group III nitride-based device active layer (150) for a power semiconductor device, a light-emitting device, or a communication filter device on one surface of the exposed seed layer (140).

[0127] The following contents of the re-growth step (S290) are the same as the method for manufacturing a group III nitride semiconductor template (S100) according to the first embodiment of the present invention described above, so redundant description is omitted.

[0128] Meanwhile, the group III nitride semiconductor template manufactured according to the method for manufacturing a group III nitride semiconductor template (S200) according to the second embodiment of the present invention has a structure in which a support substrate (110), a bonding layer (130), and a seed layer (140) are ultimately laminated, and a structure in which an element active layer (150) is re-grown on the seed layer (140).

[0129]

[0130] Although all components constituting the embodiments of the present invention have been described as being combined or operating in combination as one, the present invention is not necessarily limited to such embodiments. That is, within the scope of the present invention, all of the components may be selectively combined and operated in one or more combinations.

[0131] Furthermore, terms such as "include," "comprise," or "have" described above, unless specifically stated otherwise, imply that the corresponding component may be present, and therefore should be interpreted to include other components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art to which the present invention pertains, unless otherwise defined. Commonly used terms, such as terms defined in dictionaries, should be interpreted to be consistent with the contextual meaning of the relevant technology, and shall not be interpreted in an ideal or overly formal sense, unless explicitly defined in the present invention.

[0132] The above description is merely an example of the technical idea of ​​the present invention, and those skilled in the art will appreciate that various modifications and variations can be made without departing from the essential characteristics of the present invention.

[0133] Accordingly, the embodiments disclosed in the present invention are intended to illustrate, rather than limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the following claims, and all technical concepts within the scope equivalent thereto should be construed as being included within the scope of the present invention.

Claims

1. Growth stage of growing a sacrificial layer on a growth substrate; A deposition step of forming a seed layer on the sacrificial layer; A bonding step of bonding one surface of the seed layer to a support substrate through a bonding layer; A removal step for removing the above growth substrate; and Including a surface preparation step of removing the sacrificial layer to expose the other surface of the seed layer, The above seed layer is, A method for manufacturing a group III nitride semiconductor template, characterized in that it is formed of a single crystal metal oxide having a corundum crystal structure.

2. In claim 1, A method for manufacturing a group III nitride semiconductor template, further comprising a re-growth step of re-growing a device active layer on the other surface of the exposed seed layer.

3. In claim 1, The above sacrificial layer is, A method for manufacturing a group III nitride semiconductor template, characterized in that it is formed of a single crystal material having a hexagonal close packed lattice (HCP) crystal structure.

4. In claim 3, The above tabernacle stage is, A method for manufacturing a group III nitride semiconductor template, characterized by performing heat treatment on the formed seed layer.

5. In claim 1, The above joining step is, A method for manufacturing a group III nitride semiconductor template, characterized in that the first bonding layer is formed on one surface of the seed layer, the second bonding layer is formed on the support substrate, and the first bonding layer and the second bonding layer are bonded to each other, thereby bonding one surface of the seed layer to the support substrate.

6. In claim 5, The above joining step is, A method for manufacturing a group III nitride semiconductor template, characterized in that a positive or negative pattern is formed on at least one of the seed layer and the first bonding layer to a preset depth.

7. In claim 5, The above joining step is, A method for manufacturing a group III nitride semiconductor template, characterized in that a positive or negative pattern is formed on at least one of the support substrate and the second bonding layer to a preset depth.

8. In claim 6, The above joining step is, Forming a first pattern on the seed layer and forming a second pattern on the first bonding layer, The first pattern above is, A method for manufacturing a group III nitride semiconductor template, characterized in that the template is formed to penetrate the seed layer but is formed to be in communication with the second pattern.

9. In claim 8, In the above first pattern and the above second pattern, A method for manufacturing a group III nitride semiconductor template, characterized in that a masking material for removing an air gap is filled.

10. In claim 5, Each of the first bonding layer and the second bonding layer, A method for manufacturing a group III nitride semiconductor template, comprising: a bonding reinforcing layer for reinforcing bonding with the seed layer or the support substrate; a surface planarizing layer for alleviating roughness of a surface of the seed layer or the support substrate; and a bonding layer for bonding the seed layer and the support substrate to each other.

11. Growth stage of growing a sacrificial layer on a growth substrate; A deposition step of forming a seed layer on the sacrificial layer; A bonding step of bonding one side of the seed layer to a temporary substrate through an adhesive layer; A first removal step for removing the above growth substrate; An exposure step of removing the sacrificial layer to expose the other surface of the seed layer; A bonding step of bonding the other surface of the seed layer to a support substrate through a bonding layer; A second removal step for removing the temporary substrate; and Including a surface preparation step of removing the adhesive layer to expose one side of the seed layer, The above seed layer is, A method for manufacturing a group III nitride semiconductor template, characterized in that it is formed of a single crystal metal oxide having a corundum crystal structure.

12. In claim 11, A method for manufacturing a group III nitride semiconductor template, further comprising a re-growth step of re-growing a device active layer on one surface of the exposed seed layer.

13. In claim 11, The above sacrificial layer is, A method for manufacturing a group III nitride semiconductor template, characterized in that it is formed of a single crystal material having a hexagonal close packed lattice (HCP) crystal structure.

14. In claim 13, The above tabernacle stage is, A method for manufacturing a group III nitride semiconductor template, characterized by performing heat treatment on the formed seed layer.

15. In claim 13, The above joining step is, A method for manufacturing a group III nitride semiconductor template, characterized in that the other surface of the seed layer is bonded to the support substrate by forming a first bonding layer on the other surface of the seed layer, forming a second bonding layer on the support substrate, and then bonding the first bonding layer and the second bonding layer to each other.

16. In claim 15, The above joining step is, A method for manufacturing a group III nitride semiconductor template, characterized in that a positive or negative pattern is formed on at least one of the seed layer and the first bonding layer to a preset depth.

17. In claim 15, The above joining step is, A method for manufacturing a group III nitride semiconductor template, characterized in that a positive or negative pattern is formed on at least one of the support substrate and the second bonding layer to a preset depth.

18. In claim 16, The above joining step is, Forming a first pattern on the seed layer and forming a second pattern on the first bonding layer, The first pattern above is, A method for manufacturing a group III nitride semiconductor template, characterized in that the template is formed to penetrate the seed layer but is formed to be in communication with the second pattern.

19. In claim 18, In the above first pattern and the above second pattern, A method for manufacturing a group III nitride semiconductor template, characterized in that a masking material for removing an air gap is filled.

20. In claim 15, Each of the first bonding layer and the second bonding layer, A method for manufacturing a group III nitride semiconductor template, comprising: a bonding reinforcing layer for reinforcing bonding with the seed layer or the support substrate; a surface planarizing layer for alleviating roughness of a surface of the seed layer or the support substrate; and a bonding layer for bonding the seed layer and the support substrate to each other.

21. A group III nitride semiconductor template manufactured by a method for manufacturing a group III nitride semiconductor template according to any one of claims 1 to 20.

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