Expedited equalization filter configuration in a power management circuit

Abstract

Expedited equalization filter configuration in an envelope tracking (ET) integrated circuit (ETIC) is provided. The ETIC is configured to provide an ET voltage to a power amplifier circuit for amplifying a signal. Moreover, the ETIC is further configured to utilize an equalization filter to help compensate for a distortion(s) (e.g., ripple) in the ET voltage. The equalization filter, which is typically a complex filter, is dynamically configured using an optimal set of parameters that best match a specific configuration and / or operating condition (e.g., routing distance, load impedance, modulation bandwidth, etc.) of the ETIC. In embodiments disclosed herein, a search control circuit is provided in the ETIC to help expedite a configuration of the equalization filter. As a result, it is possible to automatically adapt the equalization filter in a timely manner to help improve an overall performance of the ETIC.

Description

EXPEDITED EQUALIZATION FILTER CONFIGURATION IN A POWER MANAGEMENT CIRCUITRelated Applications

[0001] This application claims the benefit of U.S. provisional patent application serial number 63 / 622,612, filed on January 19, 2024, and U.S. provisional patent application serial number 63 / 575,899, filed on April 8, 2024, the disclosures of which are hereby incorporated herein by reference in their entireties.Field of the Disclosure

[0002] The technology of the disclosure relates generally to configuring an equalization filter in a power management circuit.

[0003] Mobile communication devices have become increasingly common in current society for providing wireless communication services. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capability in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences.

[0004] The redefined user experience relies on higher data rates offered by advanced fifth generation (5G) and 5G new radio (5G-NR) technologies, which typically transmit and receive radio frequency (RF) signals in millimeter wave spectrums. Given that the RF signals are more susceptible to attenuation and interference in the millimeter wave spectrums, the RF signals are typically amplified by state-of-the-art power amplifiers to help boost the RF signals to higher power before transmission.

[0005] Envelope tracking (ET) is a power management technology designed to improve operating efficiency and / or linearity performance of the power amplifiers. In an ET power management circuit, an ET integrated circuit (ETIC) isconfigured to generate a time-variant ET voltage based on a time-variant voltage envelope of the RF signals and provide the time-variant ET voltage to a power amplifier(s) via a conductive trace. Understandably, the better the time-variant ET voltage is aligned with the time-variant voltage envelope in time and amplitude, the better the performance (e.g., efficiency and / or linearity) that can be achieved at the power amplifiers. However, the time-variant ET voltage can become misaligned from the time-variant voltage envelope in time and / or amplitude due to a range of factors (e.g., group delay, impedance mismatch, etc.). Moreover, the time-variant ET voltage can be distorted at the power amplifier(s) when a current in the power amplifier(s) interacts with an inherent inductance of the conductive trace. As such, it is desirable to correct the distortion in the time-variant ET voltage and maintain good alignment with the time-variant voltage envelope at all times and across a wide modulation bandwidth of the RF signal.Summary

[0006] Embodiments of the disclosure relate to an expedited equalization filter configuration in an envelope tracking (ET) integrated circuit (ETIC). The ETIC is configured to provide an ET voltage to a power amplifier circuit for amplifying a signal. Moreover, the ETIC is further configured to utilize an equalization filter to help compensate for a distortion(s) (e.g., ripple) in the ET voltage. The equalization filter, which is typically a complex filter, is dynamically configured using an optimal set of parameters that best match a specific configuration and / or operating condition (e.g., routing distance, load impedance, modulation bandwidth, etc.) of the ETIC. In embodiments disclosed herein, a search control circuit is provided in the ETIC to help expedite a configuration of the equalization filter. As a result, it is possible to automatically adapt the equalization filter in a timely manner to help improve an overall performance of the ETIC.

[0007] In one aspect, an ETIC is provided. The ETIC includes a voltage generation circuit. The voltage generation circuit is configured to generate an ET voltage based on an equalized ET target voltage. The ETIC also includes anequalizer circuit. The equalizer circuit is configured to search through multiple sets of parameters to determine an optimal set of parameters to configure an equalization filter to compensate for a distortion in the ET voltage. The equalizer circuit is also configured to apply the equalization filter to an ET target voltage to thereby generate the equalized ET target voltage. The ETIC also includes a search control circuit. The search control circuit is configured to determine a set of reference parameters to thereby expedite a search for the optimal set of parameters.

[0008] In another aspect, a method for expediting an equalization filter configuration in an ETIC is provided. The method includes generating an ET voltage based on an equalized ET target voltage. The method also includes searching through multiple sets of parameters to determine an optimal set of parameters to configure an equalization filter to compensate for a distortion in the ET voltage. The method also includes applying the equalization filter to an ET target voltage to thereby generate the equalized ET target voltage. The method also includes determining a set of reference parameters to thereby expedite a search for the optimal set of parameters.

[0009] In another aspect, a wireless device is provided. The wireless device includes a power amplifier circuit. The power amplifier circuit is configured to amplify a signal based on an ET voltage. The wireless device also includes an ETIC. The ETIC is coupled to the power amplifier circuit via a conductive line. The method includes generating the ET voltage based on an equalized ET target voltage. The method also includes searching through multiple sets of parameters to determine an optimal set of parameters to configure an equalization filter to compensate for a distortion in the ET voltage. The method also includes applying the equalization filter to an ET target voltage to thereby generate the equalized ET target voltage. The method also includes determining a set of reference parameters to thereby expedite a search for the optimal set of parameters. The wireless device also includes a transceiver circuit. The transceiver circuit is configured to generate the signal and the ET target voltage.

[0010] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.Brief Description of the Drawing Figures

[0011] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0012] Figure 1 A is a schematic diagram of an exemplary conventional power management circuit wherein an envelope tracking (ET) integrated circuit (ETIC) is configured to generate an ET voltage;

[0013] Figure 1 B is a schematic diagram illustrating various impedances and / or inductances in the conventional power management circuit of Figure 1 A that can cause a voltage distortion;

[0014] Figure 1 C is a schematic diagram providing an exemplary illustration of the ETIC in Figure 1 A configured to correct the voltage distortion based on an equalization filter;

[0015] Figure 2 is a schematic diagram of an exemplary ETIC wherein a search control circuit is configured according to an embodiment of the present disclosure to expedite the configuration of the equalization filter in Figure 1 C;

[0016] Figure 3 is a schematic diagram of an exemplary power management circuit incorporating the ETIC of Figure 2;

[0017] Figure 4 is a schematic diagram of an exemplary test waveform that can be utilized by the ETIC of Figure 2 to extrapolate a set of reference parameters to help expedite the configuration of the equalization filter;

[0018] Figure 5 is a schematic diagram of an exemplary communication device wherein the power management circuit of Figure 3 can be provided; and

[0019] Figure 6 is a flowchart of an exemplary process whereby the ETIC of Figure 2 can be configured to correct the ET voltage error(s).Detailed Description

[0020] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0021] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0022] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an elementis referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0023] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0026] Embodiments of the disclosure relate to an expedited equalization filter configuration in an envelope tracking (ET) integrated circuit (ETIC). The ETIC is configured to provide an ET voltage to a power amplifier circuit for amplifying a signal. Moreover, the ETIC is further configured to utilize an equalization filter to help compensate for a distortion(s) (e.g., ripple) in the ET voltage. The equalization filter, which is typically a complex filter, is dynamically configured using an optimal set of parameters that best match a specific configurationand / or operating condition (e.g., routing distance, load impedance, modulation bandwidth, etc.) of the ETIC. In embodiments disclosed herein, a search control circuit is provided in the ETIC to help expedite a configuration of the equalization filter. As a result, it is possible to automatically adapt the equalization filter in a timely manner to help improve an overall performance of the ETIC.

[0027] Before discussing the ETIC of the present disclosure, starting at Figure 2, an overview of a conventional power management circuit is first provided with reference to Figures 1A-1 C to help understand the technical problems to be solved herein.

[0028] Figure 1 A is a schematic diagram of an exemplary conventional power management circuit 10 configured to generate an ET voltage Vcc. The conventional power management circuit 10 includes a transceiver circuit 12, an ET integrated circuit (ETIC) 14, a power amplifier circuit 16, and a conductive line 18 (e.g., a conductive trace) that couples the ETIC 14 to the power amplifier circuit 16.

[0029] The transceiver circuit 12 is configured to generate and provide an RF signal 20, which is associated with a time-variant power envelope PENV, to the power amplifier circuit 16. The transceiver circuit 12 is also configured to generate a target voltage VTGT in accordance with (a.k.a. tracks) the time-variant power envelope PENV. The ETIC 14 is configured to generate the ET voltage Vcc based on the target voltage VTGT and the power amplifier circuit 16 is configured to amplify the RF signal 20 based on the ET voltage Vcc. Given that the target voltage VTGT tracks the time-variant power envelope PENV and the ET voltage Vcc is generated based on the target voltage VTGT, the ET voltage Vcc should be aligned with the time-variant power envelope PENV as well.

[0030] However, the ET voltage Vcc can be distorted and / or misaligned from the time-variant power envelope PENV at an input 22 of the power amplifier circuit 16 due to various factors, which are further explained with reference to Figure 1 B. Figure 1 B is a schematic diagram illustrating the various factors that can cause the ET voltage Vcc in Figure 1 A to be distorted and / or misaligned from the time-variant power envelope PENV. Common elements between Figures 1 A and1 B are shown therein with common element numbers and will not be redescribed herein.

[0031] Herein, the ETIC 14 has an inherent impedance that can be modeled by an equivalent inductance LETIC and the conductive line 18 has an inherent trace inductance that can be modeled by an equivalent trace inductance LTRACE. Accordingly, a voltage path 24 between the ETIC 14 and the input 22 of the power amplifier circuit 16 will have a total equivalent inductance LE that equals a sum of the equivalent inductance LETIC and the equivalent trace inductance LTRACE (LE = LETIC + LTRACE).

[0032] The power amplifier circuit 16 can be modeled as a current source with a modulated current Icc and have an equivalent capacitance CPA. Accordingly, an equivalent source impedance ZSOURCE at the input 22 of the power amplifier circuit 16 can be determined as in equation (Eq. 1 ) below.

[0033] In the equation (Eq. 1 ), s represents the s-transform notation, which can be expressed as s = j2nf. The modulated current Icc is somewhat proportional to the target voltage VTGT and can be approximated as in equation (Eq. 2) below.Icc » VTGT I Rice (Eq. 2)

[0034] In the equation (Eq. 2) above, Rice represents an equivalent resistance at the input 22 (e.g., a collector) of the power amplifier circuit 16. Notably, when the power amplifier circuit 16 receives the ET voltage Vcc at the input 22 via the voltage path 24, the modulated current Icc can interact with the total equivalent inductance LE to create a ripple (a.k.a. voltage distortion) in the ET voltage Vcc. The ripple, which can be expressed as ZSOURCE* Icc, can cause a distortion in the RF signal 20 when the power amplifier circuit 16 amplifies the RF signal 20 based on the ET voltage Vcc.

[0035] Fortunately, the voltage distortion in the ET voltage Vcc can be corrected by applying an equalization filter H(s) to the target voltage VTGT. Figure 1C is a schematic diagram of the ETIC 14 wherein an equalizer circuit 26 can be configured to correct the voltage distortion in Figure 1 B based on the equalization filter H(s). Common elements between Figures 1A-1 C are shown therein with common element numbers and will not be re-described herein.

[0036] Specifically, the equalizer circuit 26 is configured to apply the equalization filter H(s) to the target voltage VTGT to thereby generate an equalized target voltage VTGT-E. The ETIC 14 also includes a voltage generation circuit 28, which is configured to generate the ET voltage Vcc based on the equalized target voltage VTGT-E. Thus, by applying the equalization filter H(s) to the target voltage VTGT and generating the ET voltage Vcc based on the equalized target voltage VTGT-E, it is possible to correct the voltage distortion in the ET voltage Vcc.

[0037] In an embodiment, the equalization filter H(s) can be defined in equation (Eq. 3) below.

[0038] The equalization filter H(s) in the equation (Eq. 3) can be further expressed as in equation (Eq. 4) by substituting the Icc in the equation (Eq. 3) with the Icc in the equation (Eq. 2).

[0039] The equalization filter H(s) as shown in the equation (Eq. 4) can be further defined by a pair of parameters Q (Q == 1 / VCPA*LE), as shown in equation (Eq. 5).

[0040] It can be seen from the equation (Eq. 5) that the equalization filter H(s) is a second-order complex zero filter defined by the set of parameters Q and co. In this regard, to properly determine the equalization filter H(s) to correct the voltage distortion, it is necessary to determine the set of parameters Q and to appropriately.

[0041] However, since each of the set of parameters Q and to is a function of the equivalent capacitance CPA, the equivalent resistance Rice, and / or the total equivalent inductance LE, the set of parameters Q and to can vary greatly under different configurations and / or operating conditions of the conventional power management circuit 10. For example, the fabrication process and / or material used to make the ETIC 14 can affect the equivalent inductance LETIC, and the length and / or material of the conductive line 18 can affect the equivalent trace inductance LTRACE. In addition, since the power amplifier circuit 16 can be supplied by different vendors, the equivalent capacitance CPA and the equivalent resistance Rice can also vary significantly. Further, the modulation frequency of the RF signal 20 can also contribute to a variation of the s-transform notation, which can be expressed as s = j2nf, and therefore the modulated current Icc. As such, the ETIC 14 must be configured to cover as many variations as possible.

[0042] Specifically, the ETIC 14 can include a configuration lookup table (LUT) 30. The configuration LUT 30 is pre-configured to store multiple sets of parameters (Qi , c i)- (QN, CON). The equalizer circuit 26 is configured to sweep through the configuration LUT 30 to find an optimal one of the set of parameters (Qi , COI)-(QN, CON) that best matches the configuration and / or operating condition of the ETIC 14 and configure the equalization filter H(s) accordingly. However, since a number of the set of parameters (Qi , COI)-(QN,stored in the configuration LUT 30 can be very large, it will take a longer time for the ETIC 14 to sweep through the configuration LUT 30 and configure the equalization filter H(s). Hence, the technical problem to be solved herein is to expedite the configuration of the equalization filter H(s) with minimal change to the ETIC 14.

[0043] In this regard, Figure 2 is a schematic diagram of an exemplary ETIC 32 wherein a search control circuit 34 is configured according to an embodiment of the present disclosure to expedite a configuration of the equalization filter H(s). In an effort to minimize changes to the ETIC 14 in Figure 1 C, the ETIC 32 reuses the configuration LUT 30 as is. The ETIC 32 also includes an equalizer circuit 36 that can determine an optimal one of the set of parameters (Qi,< ) to thereby configure the equalization filter H(s) and apply the equalization filter H(s) to an ET target voltage VTGT to generate an equalized ET target voltage VTGT-E.

[0044] The ETIC 32 differs from the ETIC 14 in that the search control circuit 34 is configured to determine a set of reference parameters (QR, WR) to help the equalizer circuit 36 to expedite the search for the optimal one of the set of parameters (Qi,in the configuration LUT 30. In an embodiment, the ETIC 32 can replace the ETIC 14 in the conventional power management circuit 10 without a need to change the transceiver circuit 12 and the power amplifier circuit 16. Figure 3 is a schematic diagram of an exemplary power management circuit 38 incorporating the transceiver circuit 12 and the power amplifier circuit 16 in Figure 1 A with ETIC 32 of Figure 2. Common elements between Figures 1A-1 C and 2 are shown therein with common element numbers and will not be re-described herein. By replacing the ETIC 14 with the ETIC 32 in the power management circuit 38, it is possible to effectively solve the above-identified technical problem with minimal change in the conventional power management circuit 10.

[0045] With reference back to Figure 2, the ETIC 32 includes a voltage generation circuit 40. The voltage generation circuit 40 can be configured to include a voltage amplifier 42, an offset capacitor 44, a switcher circuit 46, and a controller 48. The voltage amplifier 42 is powered by a supply voltage VSUP to generate an initial ET voltage VAMP based on the equalized ET target voltage VTGT-E. The offset capacitor 44 is configured to raise the initial ET voltage VAMP by an offset voltage VOFF to thereby generate the ET voltage Vcc at an output 50 of the ETIC 32.

[0046] The switcher circuit 46 is configured to generate a low-frequency current e at the output 50 in accordance with a duty cycle signal 52 that is determined by the controller 48 based on the equalized ET target voltage VTGT-E. The low-frequency current IDC can be used to maintain the offset voltage VOFF across the offset capacitor 44 and provide a direct-current (DC) content in the modulated voltage e when the ET voltage Vcc is below a peak range, whereas the voltage amplifier 42 is further configured to supply an alternating-current (AC) content in the modulated current Ice when the ET voltage Vcc is within the peak range. The voltage amplifier 42 is configured to adjust the AC current IAC based on a feedback voltage VCC-FB from the output 50 and generate a sensed current ISENSE to indicate the amount of the AC current IAC. Since the voltage amplifier 42 will only supply the AC current IAC in the peak region of the ET voltage Vcc, the sensed current ISENSE can thus be used to approximate a maximum amount of the modulated current be.

[0047] In an embodiment, the ETIC 32 also includes a peak detector 54 to detect whether the ET voltage Vcc is withing the peak region. Specifically, the peak detector 54 can generate a sensed voltage VSENSE to indicate the peak of the ET voltage Vcc. Accordingly, the search control circuit 34 can be configured to estimate an output impedance ZEST at the output 50 based on the sensed voltage VSENSE and the sensed current ISENSE (ZEST = VSENSE / ISENSE) and extrapolate the set of reference parameters (QR, COR) from the estimated output impedance ZEST.

[0048] Understandable from previous discussions, the search control circuit 34 must know the equivalent capacitance CPA, the equivalent resistance Rice, and the total equivalent inductance LE to determine the set of reference parametersGiven the three unknown parameters involved in the determination of the set of reference parameters (QR,the search control circuit 34 must estimate at least three different output impedances ZEST under at least three different test conditions to extrapolate the equivalent capacitance CPA, the equivalent resistance Rice, and the total equivalent inductance LE.

[0049] In an embodiment, the ETIC 32 further includes a waveform generator 56, which can be configured to generate a test waveform 58 to modify the equalized ET target voltage VTGT-E. The test waveform 58 can be so generated at different frequencies to thereby change the output impedance ZEST at the output 50 of the ETIC 32.

[0050] Herein, the search control circuit 34 is configured to control the waveform generator 56 to generate the test waveform 58 in at least three different frequencies fi, f2, fa to thereby modify the equalized ET target voltage under the at least three different test conditions. Accordingly, the search control circuit can estimate at least three output impedances ZEST at the output 50 to thereby extrapolate the equivalent capacitance CPA, the equivalent resistance Rice, and the total equivalent inductance LE. In an embodiment, the search control circuit 34 can extrapolate the equivalent capacitance CPA, the equivalent resistance Rice, and the total equivalent inductance LE from the estimated output impedance ZEST using a linear calculation of a network or a lumped element consisting of an inductor, a capacitor, and a resistor.

[0051] In a non-limiting example, the test waveform 58 can be a constant wave (CW) waveform, a pulsed waveform, a square waveform, a multi-CW waveform, and so on. Figure 4 is a schematic diagram providing an exemplary illustration of the test waveform 58 that can be generated to create the at least three test conditions in the ETIC 32 of Figure 2.

[0052] Herein, the test waveform 58 is a square waveform so generated in the frequencies fi, f2, fa (fa > f2 > fi). In an embodiment, the frequencies fi, f2, fa are all located inside a frequency range (a.k.a. bandwidth) wherein the ETIC 32 is configured to operate. More specifically, the frequencies fi, f2, fa are selected to cause a variation in the output impedance ZEST at the output 50 of the ETIC 32. Herein, each of the frequencies fi, f2, fa are spaced from each other by a spacing factor, which can be one-fifth or one-tenth of the highest frequency fa.

[0053] With reference back to Figure 2, upon receiving the set of reference parameters (QR, WR), the equalizer circuit 36 is further configured to search through the configuration LUT 30 to determine the optimal set of parameters thatbest match (identical to or closest to) the set of reference parameters (QR,In an embodiment, the search control circuit 34 may be configured to refine the set of reference parameters (Q , <DR) through multiple iterations. The search control circuit 34 may also deactivate the waveform generator 56 after determining the set of reference parameters (QR, WR).

[0054] The power management circuit 38 of Figure 3 can be provided in a communication device to support the embodiments described above. In this regard, Figure 5 is a schematic diagram of an exemplary communication device 100 wherein the power management circuit 38 of Figure 3 can be provided.

[0055] Herein, the communication device 100 can be any type of communication device, such as mobile terminal, smart watch, tablet, computer, navigation device, access point, base station (e.g., eNB, gNB, etc.), and any other wireless communication device that supports wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, Ultra-wideband (UWB), and near field communications. The communication device 100 will generally include a control system 102, a baseband processor 104, transmit circuitry 106, receive circuitry 108, antenna switching circuitry 1 10, multiple antennas 112, and user interface circuitry 1 14. In a non-limiting example, the control system 102 can be a field-programmable gate array (FPGA), as an example. In this regard, the control system 102 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 108 receives radio frequency signals via the antennas 112 and through the antenna switching circuitry 110 from one or more base stations. A low noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing.Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter(s) (ADC).

[0056] The baseband processor 104 processes the digitized received signal to extract the information or data bits conveyed in the received signal. Thisprocessing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor 104 is generally implemented in one or more digital signal processors (DSPs) and application specific integrated circuits (ASICs).

[0057] For transmission, the baseband processor 104 receives digitized data, which may represent voice, data, or control information, from the control system 102, which it encodes for transmission. The encoded data is output to the transmit circuitry 106, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission, and deliver the modulated carrier signal to the antennas 112 through the antenna switching circuitry 1 10. The multiple antennas 112 and the replicated transmit and receive circuitries 106, 108 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0058] In an embodiment, the transceiver circuit 12 can be provided in the transmit circuitry 106. The ETIC 32 and the power amplifier circuit 16 may be provided in between the transmit circuitry 106 and the antenna switching circuitry 110. More specifically, the ETIC 32 may be coupled to the transmit circuitry 106 and the power amplifier circuit 16 may be coupled to the antenna switching circuitry 110.

[0059] In an embodiment, the ETIC 32 of Figure 2 can be configured to correct the voltage distortion based on a process. In this regard, Figure 6 is a flowchart of an exemplary process 200 whereby the ETIC 32 of Figure 2 can be configured to correct the voltage distortion.

[0060] Herein, the process 200 includes generating the ET voltage Vcc based on the equalized ET target voltage VTGT-E (step 202). The process 200 also includes searching through the set of parameters (Qi,to determine the optimal set of parameters to configure the equalization filter H(s) to compensate for the distortion in the ET voltage Vcc (step 204). The process 200also includes applying the equalization filter H(s) to the ET target voltage VTGT to thereby generate the equalized ET target voltage VTGT-E (step 206). The process 200 also includes determining the set of reference parameters (QR, WR) to thereby expedite the search for the optimal set of parameters (step 208).

[0061] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

ClaimsWhat is claimed is:1 . An envelope tracking (ET) integrated circuit (ETIC) comprising: a voltage generation circuit configured to generate an ET voltage based on an equalized ET target voltage; an equalizer circuit configured to: search through a plurality of sets of parameters to determine an optimal set of parameters to configure an equalization filter to compensate for a distortion in the ET voltage; and apply the equalization filter to an ET target voltage to thereby generate the equalized ET target voltage; and a search control circuit configured to determine a set of reference parameters to thereby expedite a search for the optimal set of parameters.

2. The ETIC of claim 1 , wherein each of the plurality of sets of parameters is a function of one or more of: an equivalent total inductance of the ETIC and a conductive line configured to couple the ETIC to a power amplifier circuit; an equivalent capacitance of the power amplifier circuit; and an equivalent resistance of the power amplifier circuit.

3. The ETIC of claim 2, wherein the search control circuit is further configured to: determine a respective output impedance of the ETIC under each of at least three different test conditions; extrapolate the equivalent total inductance, the equivalent capacitance, and the equivalent resistance based on the respective output impedance determined under each of the at least three different test conditions; anddetermine the set of reference parameters based on the extrapolated equivalent total inductance, the extrapolated equivalent capacitance, and the extrapolated equivalent resistance.

4. The ETIC of claim 3, further comprising a waveform generator configured to generate a test waveform to modify the equalized ET target voltage, wherein the search control circuit is further configured to cause the waveform generator to generate the test waveform in at least three different frequencies to thereby modify the equalized ET target voltage under the at least three different test conditions.

5. The ETIC of claim 4, wherein the waveform generator is configured to generate the test waveform in the at least three different frequencies that fall within a bandwidth of the ETIC.

6. The ETIC of claim 4, wherein the search control circuit is further configured to deactivate the waveform generator after determining the set of reference parameters.

7. The ETIC of claim 3, wherein the search control circuit is further configured to: estimate a respective peak voltage and a respective peak current at an output of the ETIC under each of the at least three different test conditions; and determine the respective output impedance of the ETIC based on the respective peak voltage and the respective peak current estimated under each of the at least three different test conditions.

8. The ETIC of claim 1 , further comprising a configuration lookup table (LUT) preconfigured to store the plurality of sets of parameters, wherein the equalizer circuit is further configured to search through the plurality of sets of parameters inthe configuration LUT to determine the optimal set of parameters that best match the set of reference parameters.

9. A method for expediting an equalization filter configuration in an envelope tracking (ET) integrated circuit (ETIC) comprising: generating an ET voltage based on an equalized ET target voltage; searching through a plurality of sets of parameters to determine an optimal set of parameters to configure an equalization filter to compensate for a distortion in the ET voltage; applying the equalization filter to an ET target voltage to thereby generate the equalized ET target voltage; and determining a set of reference parameters to thereby expedite a search for the optimal set of parameters.

10. The method of claim 9, wherein each of the plurality of sets of parameters is a function of one or more of: an equivalent total inductance of the ETIC and a conductive line configured to couple the ETIC to a power amplifier circuit; an equivalent capacitance of the power amplifier circuit; and an equivalent resistance of the power amplifier circuit.11 . The method of claim 10, further comprising: determining a respective output impedance of the ETIC under each of at least three different test conditions; extrapolating the equivalent total inductance, the equivalent capacitance, and the equivalent resistance based on the respective output impedance determined under each of the at least three different test conditions; and determining the set of reference parameters based on the extrapolated equivalent total inductance, the extrapolated equivalent capacitance, and the extrapolated equivalent resistance.

12. The method of claim 11 , further comprising: modifying the equalized ET target voltage using a test waveform; and generating the test waveform in at least three different frequencies to thereby modify the equalized ET target voltage under the at least three different test conditions.

13. The method of claim 12, further comprising generating the test waveform in the at least three different frequencies that fall within a bandwidth of the ETIC.

14. The method of claim 11 , further comprising: estimating a respective peak voltage and a respective peak current at an output of the ETIC under each of the at least three different test conditions; and determining the respective output impedance of the ETIC based on the respective peak voltage and the respective peak current estimated under each of the at least three different test conditions.

15. The method of claim 9, further comprising: storing the plurality of sets of parameters in a configuration lookup table (LUT); and searching through the plurality of sets of parameters in the configuration LUT to determine the optimal set of parameters that best match the set of reference parameters.

16. A wireless device comprising: a power amplifier circuit configured to amplify a signal based on an envelope tracking (ET) voltage; an ET integrated circuit (ETIC) coupled to the power amplifier circuit via a conductive line and comprising:a voltage generation circuit configured to generate an ET voltage based on an equalized ET target voltage; an equalizer circuit configured to: search through a plurality of sets of parameters to determine an optimal set of parameters to configure an equalization filter to compensate for a distortion in the ET voltage; and apply the equalization filter to an ET target voltage to thereby generate the equalized ET target voltage; and a search control circuit configured to determine a set of reference parameters to thereby expedite a search for the optimal set of parameters; and a transceiver circuit configured to generate the signal and the ET target voltage.

17. The wireless device of claim 16, wherein each of the plurality of sets of parameters is a function of one or more of: an equivalent total inductance of the ETIC and the conductive line; an equivalent capacitance of the power amplifier circuit; and an equivalent resistance of the power amplifier circuit.

18. The wireless device of claim 17, wherein the search control circuit is further configured to: determine a respective output impedance of the ETIC under each of at least three different test conditions; extrapolate the equivalent total inductance, the equivalent capacitance, and the equivalent resistance based on the respective output impedance determined under each of the at least three different test conditions; anddetermine the set of reference parameters based on the extrapolated equivalent total inductance, the extrapolated equivalent capacitance, and the extrapolated equivalent resistance.

19. The wireless device of claim 18, wherein the ETIC further comprises a waveform generator configured to generate a test waveform to modify the equalized ET target voltage, wherein the search control circuit is further configured to cause the waveform generator to generate the test waveform in at least three different frequencies to thereby modify the equalized ET target voltage under the at least three different test conditions.

20. The wireless device of claim 18, wherein the search control circuit is further configured to: estimate a respective peak voltage and a respective peak current at an output of the ETIC under each of the at least three different test conditions; and determine the respective output impedance of the ETIC based on the respective peak voltage and the respective peak current estimated under each of the at least three different test conditions.

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