Envelope tracking voltage error correction in a power management circuit

Abstract

Envelope tracking (ET) voltage error correction in a power management circuit is provided. Herein, a voltage path in the power management circuit is configured to generate and supply an ET voltage to a power amplifier circuit(s) for amplifying a radio frequency (RF) signal(s). The power management circuit is configured to employ a digital equalization filter or an analog equalization filter in the voltage path to help correct an error(s) (e.g., ripple, phase / amplitude misalignment, etc.) in the ET voltage. Specifically, the power management circuit selects either the digital equalization filter or the analog equalization filter based on a modulation bandwidth of the RF signal. By selectively employing the digital or the analog equalization filter based on the modulation bandwidth, it is possible to achieve a significant die size reduction in the voltage path.

Description

ENVELOPE TRACKING VOLTAGE ERROR CORRECTION IN A POWER MANAGEMENT CIRCUITRelated Applications

[0001] This application claims the benefit of U.S. provisional patent application serial number 63 / 622,608, filed on January 19, 2024, and U.S. provisional patent application serial number 63 / 573,077, filed on April 2, 2024, the disclosures of which are hereby incorporated herein by reference in their entireties.Field of the Disclosure

[0002] The technology of the disclosure relates generally to correcting an error(s) in an envelope tracking (ET) voltage.Background

[0003] Mobile communication devices have become increasingly common in current society for providing wireless communication services. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capability in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences.

[0004] The redefined user experience relies on a higher data rate offered by advanced fifth generation (5G) and 5G new radio (5G-NR) technologies, which typically transmit and receive radio frequency (RF) signals in millimeter wave spectrums. Given that the RF signals are more susceptible to attenuation and interference in the millimeter wave spectrums, the RF signals are typically amplified by state-of-the-art power amplifiers to help boost the RF signals to higher power before transmission.

[0005] Envelope tracking (ET) is a power management technology designed to improve operating efficiency and / or linearity performance of the power amplifiers. In an ET power management circuit, an ET integrated circuit (ETIC) isconfigured to generate a time-variant ET voltage based on a time-variant voltage envelope of the RF signals and provide the time-variant ET voltage to a power amplifier(s) via a conductive trace. Understandably, the better the time-variant ET voltage is aligned with the time-variant voltage envelope in time and amplitude, the better the performance (e.g., efficiency and / or linearity) that can be achieved at the power amplifiers. However, the time-variant ET voltage can become misaligned from the time-variant voltage envelope in time and / or amplitude due to a range of factors (e.g., group delay, impedance mismatch, etc.). Moreover, the time-variant ET voltage can be distorted at the power amplifier(s) when a current in the power amplifier(s) interacts with an inherent inductance of the conductive trace. As such, it is desirable to correct the distortion in the time-variant ET voltage and maintain good alignment with the time-variant voltage envelope at all times and across a wide modulation bandwidth of the RF signal.

[0006] Embodiments of the disclosure relate to envelope tracking (ET) voltage error correction in a power management circuit. Herein, a voltage path in the power management circuit is configured to generate and supply an ET voltage to a power amplifier circuit(s) for amplifying a radio frequency (RF) signal(s). The power management circuit is configured to employ a digital equalization filter or an analog equalization filter in the voltage path to help correct an error(s) (e.g., ripple, phase / amplitude misalignment, etc.) in the ET voltage. Specifically, the power management circuit selects either the digital equalization filter or the analog equalization filter based on a modulation bandwidth of the RF signal. By selectively employing the digital or the analog equalization filter based on the modulation bandwidth, it is possible to achieve a significant die size reduction in the voltage path.

[0007] In one aspect, a power management circuit is provided. The power management circuit includes a transceiver circuit. The transceiver circuit includes a signal processing circuit. The signal processing circuit is configured tomodulate a digital signal onto an RF signal. The transceiver circuit also includes a target voltage circuit. The target voltage circuit includes a digital target voltage circuit. The digital target voltage circuit is configured to generate a digital target voltage in accordance with a time-variant amplitude of the digital signal. The target voltage circuit also includes a digital equalizer circuit. The digital equalizer circuit is configured to apply a digital equalization filter to the digital target voltage when a modulation bandwidth of the RF signal is lower than or equal to a predefined bandwidth threshold. The target voltage circuit also includes a digital- to-analog converter (DAC). The DAC is configured to convert the digital target voltage into an analog target voltage. The power management circuit also includes an ET integrated circuit (ETIC). The ETIC includes an analog equalizer circuit. The analog equalizer circuit is configured to apply an analog equalization filter to the analog target voltage when the modulation bandwidth of the RF signal is higher than the predefined bandwidth threshold. The ETIC also includes a voltage generation circuit. The voltage generation circuit is configured to generate an ET voltage based on the analog target voltage.

[0008] In another aspect, a wireless device is provided. The wireless device includes a power management circuit. The power management circuit includes a transceiver circuit. The transceiver circuit includes a signal processing circuit.The signal processing circuit is configured to modulate a digital signal onto an RF signal. The transceiver circuit also includes a target voltage circuit. The target voltage circuit includes a digital target voltage circuit. The digital target voltage circuit is configured to generate a digital target voltage in accordance with a timevariant amplitude of the digital signal. The target voltage circuit also includes a digital equalizer circuit. The digital equalizer circuit is configured to apply a digital equalization filter to the digital target voltage when a modulation bandwidth of the RF signal is lower than or equal to a predefined bandwidth threshold. The target voltage circuit also includes a DAC. The DAC is configured to convert the digital target voltage into an analog target voltage. The power management circuit also includes an ETIC. The ETIC includes an analog equalizer circuit. The analog equalizer circuit is configured to apply an analog equalization filter to the analogtarget voltage when the modulation bandwidth of the RF signal is higher than the predefined bandwidth threshold. The ETIC also includes a voltage generation circuit. The voltage generation circuit is configured to generate an ET voltage based on the analog target voltage. The wireless device also includes a power amplifier circuit. The power amplifier circuit is configured to amplify the RF signal based on the ET voltage and generate a modulated current that is proportional to the analog target voltage.

[0009] In another aspect, a method for correcting an envelope tracking voltage error(s) is provided. The method includes modulating a digital signal onto an RF signal. The method also includes generating a digital target voltage in accordance with a time-variant amplitude of the digital signal. The method also includes applying a digital equalization filter to the digital target voltage when a modulation bandwidth of the RF signal is lower than or equal to a predefined bandwidth threshold. The method also includes converting the digital target voltage into an analog target voltage. The method also includes applying an analog equalization filter to the analog target voltage when the modulation bandwidth of the RF signal is higher than the predefined bandwidth threshold. The method also includes generating an ET voltage based on the analog target voltage.

[0010] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.Brief Description of the Drawing Figures

[0011] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0012] Figure 1 A is a schematic diagram of an exemplary conventional power management circuit wherein an envelope tracking (ET) integrated circuit (ETIC) is configured to generate an ET voltage;

[0013] Figure 1 B is a schematic diagram illustrating various impedances and / or inductances in the conventional power management circuit of Figure 1 A that can cause an error(s) in the ET voltage;

[0014] Figure 1 C is a schematic diagram providing an exemplary illustration of the ETIC in Figure 1 A configured to correct the ET voltage error(s) based exclusively on an analog equalization filter;

[0015] Figure 2 is a schematic diagram of an exemplary power management circuit configured according to embodiments of the present disclosure to correct the ET voltage error(s) in Figures 1 A-1 C based on either a digital equalization filter or an analog equalization filter;

[0016] Figure 3 is a schematic diagram of an exemplary transceiver circuit in the power management circuit of Figure 2 configured according to one embodiment of the present disclosure;

[0017] Figure 4 is a schematic diagram of an exemplary transceiver circuit in the power management circuit of Figure 2 configured according to another embodiment of the present disclosure;

[0018] Figure 5 is a schematic diagram of an exemplary communication device wherein the power management circuit of Figure 2 can be provided; and

[0019] Figure 6 is a flowchart of an exemplary process whereby the power management circuit of Figure 2 can be configured to correct the ET voltage error(s).Detailed Description

[0020] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0021] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0022] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0023] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As usedherein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0026] Embodiments of the disclosure relate to envelope tracking (ET) voltage error correction in a power management circuit. Herein, a voltage path in the power management circuit is configured to generate and supply an ET voltage to a power amplifier circuit(s) for amplifying a radio frequency (RF) signal(s). The power management circuit is configured to employ a digital equalization filter or an analog equalization filter in the voltage path to help correct an error(s) (e.g., ripple, phase / amplitude misalignment, etc.) in the ET voltage. Specifically, the power management circuit selects either the digital equalization filter or the analog equalization filter based on a modulation bandwidth of the RF signal. By selectively employing the digital or the analog equalization filter based on the modulation bandwidth, it is possible to achieve a significant die size reduction in the voltage path.

[0027] Before discussing the power management circuit of the present disclosure, starting at Figure 2, an overview of a conventional power management circuit is first provided with reference to Figures 1A-1 C to help understand the technical problems to be solved herein.

[0028] Figure 1 A is a schematic diagram of an exemplary conventional power management circuit 10 configured to generate an ET voltage Vcc. The conventional power management circuit 10 includes a transceiver circuit 12, an ET integrated circuit (ETIC) 14, a power amplifier circuit 16, and a conductive line 18 (e.g., a conductive trace) that couples the ETIC 14 to the power amplifier circuit 16.

[0029] The transceiver circuit 12 is configured to generate and provide an RF signal 20, which is associated with a time-variant power envelope PENV, to the power amplifier circuit 16. The transceiver circuit 12 is also configured to generate a target voltage VTGT in accordance with (a.k.a. tracks) the time-variant power envelope PENV. The ETIC 14 is configured to generate the ET voltage Vcc based on the target voltage VTGT and the power amplifier circuit 16 is configured to amplify the RF signal 20 based on the ET voltage Vcc. Given that the target voltage VTGT tracks the time-variant power envelope PE V and the ET voltage Vcc is generated based on the target voltage VTGT, the ET voltage Vcc should be aligned with the time-variant power envelope PE V as well.

[0030] However, the ET voltage Vcc can be distorted and / or misaligned from the time-variant power envelope PE V at an input 22 of the power amplifier circuit 16 due to various factors, which are further explained with reference to Figure 1 B. Figure 1 B is a schematic diagram illustrating the various factors that can cause the ET voltage Vcc in Figure 1 A to be distorted and / or misaligned from the time-variant power envelope PENV. Common elements between Figures 1 A and 1 B are shown therein with common element numbers and will not be redescribed herein.

[0031] Herein, the ETIC 14 has an inherent impedance that can be modeled by an equivalent inductance LETIC and the conductive line 18 has an inherent trace inductance that can be modeled by an equivalent trace inductance LTRACE. Accordingly, a voltage path 24 is associated with a total equivalent inductance LE that equals a sum of the equivalent inductance LETIC and the equivalent trace inductance LTRACE (LE = LETIC + LTRACE).

[0032] The power amplifier circuit 16 can be modeled as a current source with a modulated current Icc and have a total equivalent capacitance CPA.Accordingly, an equivalent source impedance ZSOURCE at the input 22 of the power amplifier circuit 16 can be determined as in equation (Eq. 1 ) below.

[0033] In the equation (Eq. 1 ), s represents the s-transform notation, which can be expressed as s = j2 f. The modulated current Icc is somewhat proportional to the target voltage VTGT and can be expressed as in equation (Eq.2) below.

[0034] In the equation (Eq. 2) above, Zicc(s) represents an impedance at the input 22 (e.g., a collector) of the power amplifier circuit 16 and AD represents a group delay between the VTGT and the time-variant power envelope PENV at the input 22 of the power amplifier circuit 16.

[0035] Notably, when the power amplifier circuit 16 receives the ET voltage Vcc at the input 22 via the voltage path 24, the modulated current Icc can interact with the total equivalent inductance LE to create a ripple in the ET voltage Vcc. The ripple, which can be expressed as ZSOURCE*ICC, can cause a distortion in the RF signal 20 when the power amplifier circuit 16 amplifies the RF signal 20 based on the ET voltage Vcc. Moreover, the group delay AD can also cause the ET voltage Vcc to be misaligned from the time-variant power envelope PENV at the input 22 of the power amplifier circuit 16. As a result, the RF signal 20 may further experience amplitude and / or phase distortion. For convenience, the ripple and the amplitude / phase distortion are collectively referred to as an ET voltage error(s) hereinafter.

[0036] Figure 1 C is a schematic diagram of the ETIC 14 in Figures 1 A and 1 B that is configured to correct the ET voltage error(s) based solely on an analog equalization filter H(s). Common elements between Figures 1A-1 C are shown therein with common element numbers and will not be re-described herein.

[0037] The ETIC 14 includes an equalizer circuit 26 and a voltage generation circuit 28. The equalizer circuit 26 is configured to apply the analog equalization filter H(s) to the target voltage VTGT to thereby compensate for the ET voltage error(s) at the input 22 of the power amplifier circuit 16. The voltage generation circuit 28, on the other hand, is configured to generate the ET voltage Vcc based on the equalized target voltage VTGT. For an in-depth description of the analog equalization filter H(s), please refer to U.S. Patent Application Publication Number 2022 / 0407465 A1 , entitled “VOLTAGE RIPPLE SUPPRESSION IN A TRANSMISSION CIRCUIT.”

[0038] Notably, the RF signal 20 may be modulated in a wide range of modulation bandwidth (e.g., > 200 MHz). As such, the analog equalization filter H(s) must be configured to handle the wide range of modulation bandwidth. Understandably, the modulation bandwidth is inversely related to a resistorcapacitor (RC) time constant T that defines a cut-off frequency within the modulation bandwidth. As such, when the modulation bandwidth is lower, the equalizer circuit 26 must operate based on a longer time constant T. Accordingly, the equalizer circuit 26 needs to include a larger resistor and / or capacitor that inevitably increases the footprint of the ETIC 14. Thus, the technical problem to be solved herein is to effectively correct the ET voltage error concurrent to reducing the footprint of the ETIC 14.

[0039] In this regard, Figure 2 is a schematic diagram of an exemplary power management circuit 30 that is configured according to embodiments of the present disclosure to effectively solve the technical problems in the conventional power management circuit 10 of Figure 1 A. As opposed to relying solely on the analog equalization filter H(s), the power management circuit 30 can selectively employ a digital equalization filter HD(S) or an analog equalization filter HA(S) depending on a modulation bandwidth of an RF signal 32 being amplified in thepower management circuit 30. More specifically, the power management circuit 30 employs the digital equalization filter HD(S) when the modulation bandwidth is lower than or equal to a predefined bandwidth threshold (e.g., 100 MHz). When the modulation bandwidth is higher than the predefined bandwidth threshold, the power management circuit 30 will employ the analog equalization filter HA(S). By selectively employing the digital equalization filter HD(S) or the analog equalization filter HA(S) based on the modulation bandwidth of the RF signal 32, the power management circuit 30 can effectively solve the technical problems in the conventional power management circuit 10 of Figure 1A.

[0040] Herein, the power management circuit 30 includes a transceiver circuit 34, an ETIC 36, and a power amplifier circuit 38, which is coupled to the ETIC 36 via a conductive line 40 (e.g., a conductive trace). The transceiver circuit 34 is configured to generate the RF signal 32 associated with a time-variant power envelope PENV and provide the RF signal 32 to the power amplifier circuit 38 via a signal path 42. The transceiver circuit 34 also generates a target voltage VTGT (a.k.a. “analog target voltage”) to track the time-variant power envelope PEN and provides the target voltage VTGT to the ETIC 36.

[0041] Like the power amplifier circuit 16 in Figure 1 A, the power amplifier circuit 38 can be modeled as a current source with a modulated current Icc as described in equation (Eq. 2) and presents an equivalent source impedance ZSOURCE as described in equation (Eq. 1 ). The modulated current Icc can also interact with an equivalent inductance LETIC of the ETIC 36 and an equivalent trace inductance LT ACE of the conductive line 40 to create the ripple in the ET voltage Vcc.

[0042] The ETIC 36 includes an analog equalizer circuit 44 and a voltage generation circuit 46. The analog equalizer circuit 44 is configured to apply the analog equalization filter HA(S) to the target voltage VTGT to compensate for the ripple in the ET voltage Vcc. The voltage generation circuit 46 is configured to generate an ET voltage Vcc based on the equalized target voltage VTGT. In an embodiment, the analog equalization filter HA(S) can be identical to the analog equalization filter H(s) in Figure 1 C.

[0043] In contrast to the equalizer circuit 26 in Figure 1 C, the analog equalizer circuit 44 only applies the analog equalizer filter HA(S) to the target voltage VTGT when the modulation bandwidth of the RF signal 32 is higher than the predefined bandwidth threshold. When the modulation bandwidth of the RF signal 32 is lower than or equal to the predefined bandwidth threshold, the analog equalizer circuit 44 is either deactivated or bypassed such that the analog equalization filter HA(S) will not affect the target voltage VTGT and the ET voltage Vcc. In an embodiment, the ETIC 36 may pre-store the predefined bandwidth threshold in an embedded register(s) or memory device(s) and activate / deactivate the analog equalizer circuit 44 accordingly. In an alternative embodiment, the ETIC 36 may receive a dynamic instruction (e.g., from the transceiver circuit 34) to activate or deactivate the analog equalizer circuit 44.

[0044] Since the analog equalizer circuit 44 is only operable when the modulation bandwidth is higher, the RC time constant T of the analog equalizer circuit 44 will be smaller compared to the equalizer circuit 26 in Figure 1 C. As a result, the analog equalizer circuit 44 can be configured with a smaller resistor and / or capacitor to thereby reduce the footprint of the ETIC 36.

[0045] The transceiver circuit 34 can be configured to include a digital baseband circuit 48, a signal processing circuit 50, and a target voltage circuit 52. The digital baseband circuit 48 is configured to generate a digital signal 54, which can be a quadrature signal with an in-phase (I) component and a quadrature (Q) component. The signal processing circuit 50 is configured to modulate the digital signal 54 onto a carrier or an intermediate frequency to thereby generate the RF signal 32 in the modulation bandwidth and associated with the time-variant power envelope PENV.

[0046] In context of the present disclosure, the target voltage circuit 52, the ETIC 36, and the conductive line 40 collectively form a voltage path 56. In an embodiment, the target voltage circuit 52 includes a digital target voltage circuit 58, a digital equalizer circuit 60, and a digital-to-analog converter (DAC) 62. The digital target voltage circuit 58 is configured to generate a digital target voltage VDTGT based on the l-component and the Q-component of the digital signal 54.The digital equalizer circuit 60 is configured to apply the digital equalization filter HD(S) to the digital target voltage VDTGT when the modulation bandwidth of the RF signal 32 is lower than or equal to the predefined bandwidth threshold. The DAC 62, on the other hand, is configured to convert the equalized digital target voltage VDTGT into the target voltage VTGT.

[0047] Herein, the digital equalizer circuit 60 is either deactivated or bypassed when the modulation bandwidth of the RF signal 32 is higher than the predefined bandwidth threshold to ensure that the digital equalization filter HD(S) will not affect the target voltage VTGT and the ET voltage Vcc. In an embodiment, the transceiver circuit 34 may pre-store the predefined bandwidth threshold in an embedded register(s) or memory device(s) and activate / deactivate the digital equalizer circuit 60 accordingly.

[0048] In an embodiment, the digital equalization filter HD(S) can be configured to create a digital zero in either a first order or a second order. In a non-limiting example, the digital equalization filter HD(S) can be expressed as an equivalent HD(Z) transform in equations (Eq. 3.1 and 3.2) below. (Eq. 3.1 )(Eq. 3.2)

[0049] In the equations (Eq. 3.1 and 3.2), L / R represents a real coefficient. In an embodiment, the digital equalization filter HD(S) is designed to cater to a higher inductance-resistance time constant value, whereas the analog equalization filter HA(S) is designed to cater to a lower inductance-resistance time constant value. In another embodiment, the digital equalization filter HD(S) may also be implemented as described in U.S. Patent Application Publication Number 2022 / 0407478 A1 , entitled “ENVELOPE TRACKING VOLTAGE CORRECTION IN A TRANSMISSION CIRCUIT.”

[0050] The transceiver circuit 34 can be configured according to various embodiments, as further described in Figures 3 and 4. Common elementsbetween Figures 2, 3, and 4 are shown therein with common element numbers and will not be re-described herein.

[0051] Figure 3 is a schematic diagram of an exemplary transceiver circuit 34A configured according to one embodiment of the present disclosure. Herein, the transceiver circuit 34A further includes an amplitude detector 64, which is configured to detect a time-variant amplitude (denoted as Vl2+Q2) of the digital signal 54. The digital target voltage circuit 58 can include a target voltage lookup table (LUT) circuit 66, which is configured to generate the digital target voltage VDTGT based on the detected time-variant amplitude l2+Q2.

[0052] The signal processing circuit 50 includes a memory digital predistortion (mDPD) circuit 68 and an RF modulator 70. The mDPD circuit 68 can perform digital pre-distortion on the digital signal 54. The RF modulator 70, in turn, modulates the digital signal 54 into the RF signal 32.

[0053] In an embodiment, the signal processing circuit 50 may further include a buffer 72 and a signal delay 74, and the digital target voltage circuit 58 may include a voltage delay 76. The signal delay 74 and the voltage delay 76 may be configured to delay the digital signal 54 and the digital target voltage VDTGT, respectively, to ensure that the RF signal 32 and the ET voltage Vcc are time- aligned at the power amplifier circuit 38.

[0054] Figure 4 is a schematic diagram of an exemplary transceiver circuit 34B configured according to another embodiment of the present disclosure. Herein, the transceiver circuit 34B further includes a first ripple compensation circuit 78 and / or a second ripple compensation circuit 80. The first ripple compensation circuit 78, when present, is configured to add to the digital target voltage VDTGT a first digital ripple compensation term VTERM-I determined based on the time-variant amplitude Vl2+Q2of the digital signal 54. The second ripple compensation circuit 80, when present, is configured to add to the digital target voltage VDTGT a second digital ripple compensation term VTERM-2 determined based on the digital target voltage VDTGT.

[0055] Specifically, the first ripple compensation circuit 78 includes an amplitude-based LUT circuit 82 and a first ripple compensator 84. Theamplitude-based LUT circuit 82 is configured to determine the modulated current Icc in the power amplifier circuit 38 based on the time-variant amplitude l2+Q2of the digital signal 54. The first ripple compensator 84 is configured to generate the first digital ripple compensation term VTERM-I based on the modulated current Icc determined by the amplitude-based LUT circuit 82.

[0056] The second ripple compensation circuit 80 includes a voltage-based LUT circuit 86 and a second ripple compensator 88. The voltage-based LUT circuit 86 is configured to determine the modulated current Icc based on the digital target voltage VDTGT. The second ripple compensator 88 is configured to generate the second digital ripple compensation term VTERM-2 based on the modulated current Icc determined by the voltage-based LUT circuit 86.

[0057] In an embodiment, the first digital ripple compensation term VTERM-I is added to the digital target voltage VDTGT after applying the digital equalization filter HD(S) to the digital target voltage DTGT, whereas the second digital ripple compensation term VTERM-2 is added to the digital target voltage VDTGT prior to applying the digital equalization filter HD(S) to the digital target voltage VDTGT. However, the first digital ripple compensation term VTERM-I may also be added to the digital target voltage VDTGT prior to applying the digital equalization filter HD(S) to the digital target voltage VDTGT, whereas the second digital ripple compensation term VTE M-2 may also be added to the digital target voltage VDTGT after applying the digital equalization filter HD(S) to the digital target voltage VDTGT.

[0058] The power management circuit 30 of Figure 2 can be provided in a communication device to support the embodiments described above. In this regard, Figure 5 is a schematic diagram of an exemplary communication device 100 wherein the power management circuit 30 of Figure 2 can be provided.

[0059] Herein, the communication device 100 can be any type of communication device, such as mobile terminal, smart watch, tablet, computer, navigation device, access point, base station (e.g., eNB, gNB, etc.), and any other wireless communication device that supports wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, Ultra-wideband(UWB), and near field communications. The communication device 100 will generally include a control system 102, a baseband processor 104, transmit circuitry 106, receive circuitry 108, antenna switching circuitry 110, multiple antennas 1 12, and user interface circuitry 114. In a non-limiting example, the control system 102 can be a field-programmable gate array (FPGA), as an example. In this regard, the control system 102 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 108 receives radio frequency signals via the antennas 1 12 and through the antenna switching circuitry 110 from one or more base stations. A low noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing.Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter(s) (ADC).

[0060] The baseband processor 104 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor 104 is generally implemented in one or more digital signal processors (DSPs) and application specific integrated circuits (ASICs).

[0061] For transmission, the baseband processor 104 receives digitized data, which may represent voice, data, or control information, from the control system 102, which it encodes for transmission. The encoded data is output to the transmit circuitry 106, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission, and deliver the modulated carrier signal to the antennas 1 12 through the antenna switching circuitry 110. The multiple antennas 1 12 and the replicated transmit and receive circuitries 106, 108 may providespatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0062] In an embodiment, the transceiver circuits 34, 34A, 34B can be provided in the transmit circuitry 106. The ETIC 36 and the power amplifier circuit 38 may be provided in between the transmit circuitry 106 and the antenna switching circuitry 1 10. More specifically, the ETIC 36 may be coupled to the transmit circuitry 106 and the power amplifier circuit 38 may be coupled to the antenna switching circuitry 110.

[0063] In an embodiment, the power management circuit 30 of Figure 2 can be configured to correct an ET voltage error(s) based on a process. In this regard, Figure 6 is a flowchart of an exemplary process 200 whereby the power management circuit 30 of Figure 2 can be configured to correct the ET voltage error(s).

[0064] Herein, the process 200 includes modulating the digital signal 54 onto the RF signal 32 (step 202). The process 200 also includes generating the digital target voltage VDTGT in accordance with a time-variant amplitude l2+Q2of the digital signal 54 (step 204). The process 200 also includes applying the digital equalization filter HD(S) to the digital target voltage VDTGT when the modulation bandwidth of the RF signal 32 is lower than or equal to a predefined bandwidth threshold (step 206). The process 200 also includes converting the digital target voltage VDTGT into the analog target voltage VTGT (step 208). The process 200 also includes applying the analog equalization filter HA(S) to the analog target voltage VTGT when the modulation bandwidth of the RF signal 32 is higher than the predefined bandwidth threshold (step 210). The process 200 also includes generating the ET voltage Vcc based on the analog target voltage VTGT (step 212).

[0065] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

ClaimsWhat is claimed is:1 . A power management circuit comprising: a transceiver circuit comprising: a signal processing circuit configured to modulate a digital signal onto a radio frequency (RF) signal; and a target voltage circuit comprising: a digital target voltage circuit configured to generate a digital target voltage in accordance with a time-variant amplitude of the digital signal; a digital equalizer circuit configured to apply a digital equalization filter to the digital target voltage when a modulation bandwidth of the RF signal is lower than or equal to a predefined bandwidth threshold; and a digital-to-analog converter (DAC) configured to convert the digital target voltage into an analog target voltage; and an envelope tracking (ET) integrated circuit (ETIC) comprising: an analog equalizer circuit configured to apply an analog equalization filter to the analog target voltage when the modulation bandwidth of the RF signal is higher than the predefined bandwidth threshold; and a voltage generation circuit configured to generate an ET voltage based on the analog target voltage.

2. The power management circuit of claim 1 , wherein the transceiver circuit further comprises: a digital baseband circuit configured to generate the digital signal; an amplitude detector configured to detect the time-variant amplitude of the digital signal; anda target voltage lookup table (LUT) circuit configured to generate the digital target voltage based on the detected time-variant amplitude.

3. The power management circuit of claim 2, wherein the transceiver circuit further comprises one or more of: a first ripple compensation circuit configured to add to the digital target voltage a first digital ripple compensation term determined based on the time-variant amplitude of the digital signal; and a second ripple compensation circuit configured to add to the digital target voltage a second digital ripple compensation term determined based on the digital target voltage.

4. The power management circuit of claim 3, wherein the first digital ripple compensation term is added to the digital target voltage before adding the second digital ripple compensation term to the digital target voltage.

5. The power management circuit of claim 3, wherein the first digital ripple compensation term is added to the digital target voltage after adding the second digital ripple compensation term to the digital target voltage.

6. The power management circuit of claim 3, further comprising a power amplifier circuit configured to amplify the RF signal based on the ET voltage and generate a modulated current that is proportional to the analog target voltage.

7. The power management circuit of claim 6, wherein: the first ripple compensation circuit comprises: an amplitude-based LUT circuit configured to determine the modulated current in the power amplifier circuit based on the time-variant amplitude of the digital signal; and a first ripple compensator configured to generate the first digital ripple compensation term based on the modulated current determined by the amplitude-based LUT circuit; and the second ripple compensation circuit comprises:a voltage-based LUT circuit configured to determine the modulated current based on the digital target voltage; and a second ripple compensator configured to generate the second digital ripple compensation term based on the modulated current determined by the voltage-based LUT circuit.

8. The power management circuit of claim 1 , wherein the digital equalizer circuit is deactivated when the modulation bandwidth of the RF signal is higher than the predefined bandwidth threshold.

9. The power management circuit of claim 1 , wherein the digital equalizer circuit is bypassed when the modulation bandwidth of the RF signal is higher than the predefined bandwidth threshold.

10. The power management circuit of claim 1 , wherein the analog equalizer circuit is deactivated when the modulation bandwidth of the RF signal is lower than or equal to the predefined bandwidth threshold.1 1 . The power management circuit of claim 1 , wherein the analog equalizer circuit is bypassed when the modulation bandwidth of the RF signal is lower than or equal to the predefined bandwidth threshold.

12. A wireless device comprising a power management circuit, the power management circuit comprises: a transceiver circuit comprising: a signal processing circuit configured to modulate a digital signal onto a radio frequency (RF) signal; and a target voltage circuit comprising: a digital target voltage circuit configured to generate a digital target voltage in accordance with a time-variant amplitude of the digital signal; a digital equalizer circuit configured to apply a digital equalization filter to the digital target voltage when amodulation bandwidth of the RF signal is lower than or equal to a predefined bandwidth threshold; and a digital-to-analog converter (DAC) configured to convert the digital target voltage into an analog target voltage; an envelope tracking (ET) integrated circuit (ETIC) comprising: an analog equalizer circuit configured to apply an analog equalization filter to the analog target voltage when the modulation bandwidth of the RF signal is higher than the predefined bandwidth threshold; and a voltage generation circuit configured to generate an ET voltage based on the analog target voltage; and a power amplifier circuit configured to amplify the RF signal based on the ET voltage and generate a modulated current that is proportional to the analog target voltage.

13. The wireless device of claim 12, wherein the transceiver circuit further comprises: a digital baseband circuit configured to generate the digital signal; an amplitude detector configured to detect the time-variant amplitude of the digital signal; and a target voltage lookup table (LUT) circuit configured to generate the digital target voltage based on the detected time-variant amplitude.

14. The wireless device of claim 13, wherein the transceiver circuit further comprises one or more of: a first ripple compensation circuit configured to add to the digital target voltage a first digital ripple compensation term determined based on the time-variant amplitude of the digital signal; and a second ripple compensation circuit configured to add to the digital target voltage a second digital ripple compensation term determined based on the digital target voltage.

15. The wireless device of claim 14, wherein the first digital ripple compensation term is added to the digital target voltage before adding the second digital ripple compensation term to the digital target voltage.

16. The wireless device of claim 14, wherein the first digital ripple compensation term is added to the digital target voltage after adding the second digital ripple compensation term to the digital target voltage.

17. The wireless device of claim 14, wherein: the first ripple compensation circuit comprises: an amplitude-based LUT circuit configured to determine the modulated current in the power amplifier circuit based on the time-variant amplitude of the digital signal; and a first ripple compensator configured to generate the first digital ripple compensation term based on the modulated current determined by the amplitude-based LUT circuit; and the second ripple compensation circuit comprises: a voltage-based LUT circuit configured to determine the modulated current based on the digital target voltage; and a second ripple compensator configured to generate the second digital ripple compensation term based on the modulated current determined by the voltage-based LUT circuit.

18. The wireless device of claim 12, wherein the digital equalizer circuit is deactivated or bypassed when the modulation bandwidth of the RF signal is higher than the predefined bandwidth threshold.

19. The wireless device of claim 12, wherein the analog equalizer circuit is deactivated or bypassed when the modulation bandwidth of the RF signal is lower than or equal to the predefined bandwidth threshold.

20. A method for correcting an envelope tracking voltage error(s) comprising: modulating a digital signal onto a radio frequency (RF) signal;generating a digital target voltage in accordance with a time-variant amplitude of the digital signal; applying a digital equalization filter to the digital target voltage when a modulation bandwidth of the RF signal is lower than or equal to a predefined bandwidth threshold; converting the digital target voltage into an analog target voltage; applying an analog equalization filter to the analog target voltage when the modulation bandwidth of the RF signal is higher than the predefined bandwidth threshold; and generating an ET voltage based on the analog target voltage.

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