Array substrate, display panel and display device

Abstract

Provided are an array substrate, a display panel and a display device. The array substrate comprises a base substrate, a plurality of data lines, a plurality of thin film transistors, a common electrode, a plurality of pixel electrodes and an insulating layer, wherein the orthographic projections of the plurality of data lines on the base substrate completely fall within the orthographic projection of the common electrode on the base substrate; the common electrode comprises a plurality of opening portions; the plurality of opening portions correspond to the plurality of thin film transistors on a one-to-one basis; each opening portion comprises a first opening and a second opening; the first opening is configured to expose a portion of one thin film transistor; the second opening is configured to expose a connecting via hole; the orthographic projections of the first openings and the orthographic projections of the second openings along a straight line extending in a second direction overlap each other; and in the second direction, the size of the first openings is smaller than that of the second openings. The array substrate can effectively mitigate a light leakage phenomenon, and the parasitic capacitance between the thin film transistors and a driving electric field is relatively small, such that the quality of a display image is good.

Description

Array substrate, display panel, and display device Technical Field

[0001] At least one embodiment of the present disclosure relates to an array substrate, a display panel, and a display device. Background Art

[0002] With the advancement of technology, the image quality requirements of self-media and film and television professionals for display products are becoming increasingly demanding. The contrast ratio of display products is constantly improving. For example, some display products can achieve a contrast ratio (CR) of 1000:1 to 3000:1. Currently, display products of all sizes are trending towards higher contrast. How to achieve improved contrast while meeting product size requirements and achieving excellent image quality has become a challenge that display R&D personnel must continuously overcome.

[0003] Summary of the Invention

[0004] At least one embodiment of the present disclosure provides an array substrate, a display panel, and a display device.

[0005] At least one embodiment of the present disclosure provides an array substrate, comprising a base substrate, a plurality of data lines, a plurality of thin film transistors, a common electrode, a plurality of pixel electrodes, and an insulating layer, wherein the plurality of data lines are located on the base substrate and arranged along a first direction; a plurality of thin film transistors are located on the base substrate and arranged in an array along the first direction and a second direction, each thin film transistor comprising a first electrode, a second electrode, and a gate, the first electrode being electrically connected to the data line, the first direction and the second direction being parallel to the base substrate, and the first direction intersecting with the second direction; the common electrode being located on a side of the data line and the thin film transistor away from the base substrate; a plurality of pixel electrodes being located on a side of the common electrode away from the base substrate, and being configured to be in contact with the common electrode. An electric field is formed; an insulating layer is located between the common electrode and the thin film transistor, and the pixel electrode is electrically connected to the second electrode through a connecting via in the insulating layer, wherein the orthographic projections of the plurality of data lines on the base substrate completely fall within the orthographic projection of the common electrode on the base substrate; the common electrode includes a plurality of opening portions, and the plurality of opening portions are arranged in a one-to-one correspondence with the plurality of thin film transistors, each opening portion includes a first opening and a second opening, the first opening is configured to expose a portion of the thin film transistor, and the second opening is configured to expose the connecting via, the orthographic projections of the first opening and the second opening on a straight line extending along the second direction overlap with each other, and in the second direction, the size of the first opening is smaller than the size of the second opening.

[0006] For example, according to at least one embodiment of the present disclosure, in the array substrate provided, the first electrode includes a first portion and a second portion connected to each other, the first portion is exposed by the first opening, and the second portion is covered by the common electrode.

[0007] For example, in an array substrate provided according to at least one embodiment of the present disclosure, the first portion is located between the second portion and the second electrode, the orthographic projection of the first portion on the base substrate is a non-closed ring, and at least part of the orthographic projection of the second electrode on the base substrate is located within the area enclosed by the ring, wherein the average ring width of the ring is D1, and D1=f 2 +h 2 +m 2 +n 2 , f represents the fluctuation value of the first opening, h represents the fluctuation value of the first electrode, m represents the alignment deviation of the first opening, and n represents the alignment deviation of the first electrode.

[0008] For example, according to the array substrate provided by at least one embodiment of the present disclosure, the fluctuation value f of the first opening and the fluctuation value h of the first electrode are both 0.5 to 5.0 microns, the alignment deviation m of the first opening and the alignment deviation n of the first electrode are both 1.0 to 3.5 microns, and the average ring width D1 of the ring is 1.7 to 4.2 microns.

[0009] For example, in the array substrate provided according to at least one embodiment of the present disclosure, an orthographic projection area of ​​the first portion on the base substrate is smaller than an orthographic projection area of ​​the second portion on the base substrate.

[0010] For example, in the array substrate provided according to at least one embodiment of the present disclosure, the orthographic projection area of ​​the first portion on the base substrate is 20% to 50% of the orthographic projection area of ​​the second portion on the base substrate.

[0011] For example, according to at least one embodiment of the present disclosure, an array substrate is provided, wherein the first part includes a first sub-part, a second sub-part and a third sub-part, the first sub-part and the second sub-part are arranged relative to each other in the second direction, the third sub-part is located between the first sub-part and the second sub-part, and the first sub-part and the second sub-part are connected through the third sub-part, and the size of the first sub-part in the second direction and / or the size of the second sub-part in the second direction is smaller than the size of the third sub-part in the first direction.

[0012] For example, according to the array substrate provided by at least one embodiment of the present disclosure, the first portion of the first electrode extends along the second direction, and portions of the first electrode located on both sides of the second electrode in the second direction are covered by the common electrode.

[0013] For example, in an array substrate provided according to at least one embodiment of the present disclosure, the thin film transistor includes an active pattern, which is respectively connected to the first electrode and the second electrode and at least partially overlaps with the gate, wherein the active pattern includes a third part and a fourth part connected to each other, the third part is exposed by the first opening, and the fourth part is covered by the common electrode.

[0014] For example, in an array substrate provided according to at least one embodiment of the present disclosure, the fourth part includes a first edge portion and a second edge portion, the first edge portion and the second edge portion are opposite to each other and spaced apart in the second direction, the third part is located between the first edge portion and the second edge portion, and the size of the first edge portion in the second direction and the size of the second edge portion in the second direction are both smaller than the size of the third part in the second direction.

[0015] For example, according to the array substrate provided by at least one embodiment of the present disclosure, in the first direction, the active pattern includes a first edge away from the second electrode, the first electrode includes a second edge away from the second electrode, the gate includes a third edge away from the second electrode, the third edge exceeds the second edge of the first electrode, and the second edge exceeds the first edge of the active pattern.

[0016] For example, in the array substrate provided according to at least one embodiment of the present disclosure, the second edge exceeds the first edge by a dimension E, and E=r 2 +h 2 +t 2 +n 2 , r represents the fluctuation value of the active pattern, h represents the fluctuation value of the first electrode, t represents the alignment deviation of the active pattern, and n represents the alignment deviation of the first electrode.

[0017] For example, according to the array substrate provided by at least one embodiment of the present disclosure, the data line extends along the second direction, the data line is electrically connected to the second part of the first electrode, the data line is arranged in the same layer as the first electrode and the second electrode, and the data line and the first electrode are an integrated structure.

[0018] For example, according to at least one embodiment of the present disclosure, an array substrate is provided, and the array substrate also includes an electrode pattern, which is located on a side of the common electrode away from the thin film transistor, and the electrode pattern is electrically connected to the common electrode, wherein the electrode pattern includes a plurality of first pattern portions and a plurality of second pattern portions, the first pattern portions extend along the first direction, the second pattern portions extend along the second direction, the plurality of first pattern portions are arranged at intervals in the second direction, adjacent first pattern portions are electrically connected through the second pattern portions, and at least a portion of the orthographic projection of the second pattern portion on the base substrate is located outside the orthographic projection of the data line on the base substrate.

[0019] For example, according to at least one embodiment of the present disclosure, an array substrate is provided, which further includes a plurality of gate lines, the gate lines extending along the first direction, the plurality of gate lines being arranged at intervals along the second direction, the gate lines being electrically connected to the gates of the thin film transistors, and at least a portion of the orthographic projection of the first pattern portion on the base substrate being located outside the orthographic projection of the gate lines on the base substrate.

[0020] For example, according to at least one embodiment of the present disclosure, in the array substrate provided, in the second direction, the second opening is farther away from the gate line connected to the thin film transistor exposed by the second opening than the first opening, and the second opening is spaced apart from the gate line.

[0021] For example, according to the array substrate provided by at least one embodiment of the present disclosure, the second electrode includes an extension portion, the extension portion extends along the first direction, and the extension portion extends into the area enclosed by the ring, the extension portion includes a first sub-extension portion and a second sub-extension portion, the first sub-extension portion is exposed by the first opening, the first sub-extension portion is closer to the first electrode than the second sub-extension portion, and the orthographic projection of the first sub-extension portion on the base substrate falls into the orthographic projection of the active pattern on the base substrate, wherein in the second direction, the size of the first sub-extension portion is smaller than the size of the second sub-extension portion.

[0022] For example, according to the array substrate provided by at least one embodiment of the present disclosure, the second sub-extension portion of the second electrode includes a main body portion and at least one protruding portion, the protruding portion is connected to the main body portion, and the protruding portion protrudes relative to the main body portion in the first direction.

[0023] For example, in the array substrate provided according to at least one embodiment of the present disclosure, the second sub-extension portion includes two protrusions, and the two protrusions are respectively located on both sides of the main body, and the orthographic projection of the protrusion on a plane is spaced from the orthographic projection of the first electrode on the plane, and the plane is perpendicular to the second direction.

[0024] For example, in the array substrate provided according to at least one embodiment of the present disclosure, the minimum distance between the connecting via and the second opening is D2, and D2=y 2 +e 2 +s 2 +g 2 , y represents the fluctuation value of the second opening, h represents the fluctuation value of the connecting via, s represents the alignment deviation of the second opening, and g represents the alignment deviation of the connecting via.

[0025] For example, in the array substrate provided according to at least one embodiment of the present disclosure, the minimum distance D2 between the connecting via hole and the second opening is 1.7 to 4.2 micrometers.

[0026] For example, in the array substrate provided according to at least one embodiment of the present disclosure, an orthographic projection area of ​​the first opening on the base substrate is larger than an orthographic projection area of ​​the second opening on the base substrate.

[0027] For example, in the array substrate provided according to at least one embodiment of the present disclosure, the first opening and the second opening are connected to each other, and the first opening and the second opening are arranged along the first direction.

[0028] At least one embodiment of the present disclosure further provides a display panel, comprising the array substrate described in any of the above embodiments.

[0029] At least one embodiment of the present disclosure further provides a display device, comprising the display panel described in any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0031] FIG1 is a schematic structural diagram of an array substrate.

[0032] FIG2 is a schematic structural diagram of an array substrate provided in at least one embodiment of the present disclosure.

[0033] FIG. 3A is an enlarged schematic diagram of a partial structure of the array substrate in FIG. 2 .

[0034] FIG. 3B is an enlarged schematic diagram of a partial structure of the array substrate in FIG. 3A .

[0035] FIG4 is a schematic structural diagram of an opening portion in an array substrate provided in at least one embodiment of the present disclosure.

[0036] FIG5 is a schematic diagram of a partial structure of an array substrate provided in at least one embodiment of the present disclosure.

[0037] FIG6A is a schematic cross-sectional view of some array substrates.

[0038] FIG6B is a schematic cross-sectional view of an array substrate provided in at least one embodiment of the present disclosure.

[0039] 7 to 12 are schematic diagrams of stacked structures in an array substrate provided in at least one embodiment of the present disclosure.

[0040] FIG13 is a schematic structural diagram of a second electrode provided in at least one embodiment of the present disclosure.

[0041] FIG14 is a schematic cross-sectional view of an array substrate provided in at least one embodiment of the present disclosure.

[0042] FIG15 is a schematic structural diagram of a display panel provided in at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0044] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are simply used to distinguish different components. The words "include" or "comprising" and similar terms mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0045] The features "perpendicular," "parallel," and "identical" used in the embodiments of the present disclosure include the features "perpendicular," "parallel," and "identical" in the strict sense, as well as "approximately perpendicular," "approximately parallel," and "approximately identical" that include certain errors, taking into account the errors associated with the measurement of specific quantities (i.e., the limitations of the measurement system), and represent within the acceptable deviation range for the specific value determined by ordinary technicians in this field. The "center" in the embodiments of the present disclosure can include a position strictly at the geometric center and a position approximately at the center of a small area around the geometric center.

[0046] FIG1 is a schematic structural diagram of an array substrate.

[0047] Currently, display products are gradually developing towards higher contrast and better picture quality. With the rapid transmission of information on the Internet, users are becoming more and more familiar with the display industry and paying more attention to their own visual experience.

[0048] However, during the study, the inventors of the present application found that: as shown in FIG1 , for a display product (e.g., a liquid crystal display product), the display panel generally includes an array substrate and an opposing substrate that are arranged relative to each other, and the array substrate may be provided with a pixel electrode 010 and a common electrode 020. An electric field can be formed between the pixel electrode 010 and the common electrode 020 to drive the liquid crystal molecules located between the array substrate and the opposing substrate to rotate, thereby achieving display. When the display panel is in the process of displaying, the area between the pixel circuit (e.g., the thin film transistor 030) and the pixel electrode 010 (see the oval dotted area in FIG1 ) is prone to light leakage, and even when displaying a pure black screen (i.e., performing a dark state display), the light leakage phenomenon is still very serious, thereby causing the contrast of the displayed screen to be destroyed, thereby affecting the quality of the displayed screen. At the same time, the parasitic capacitance between the pixel electrode 010 and the common electrode 020 in the array substrate is also an important factor affecting the picture quality. For example, the rectangular dotted area shown in Figure 1 is the opening area of ​​the common electrode 020 to expose the thin film transistor 030. When the pixel electrode 010 is exposed by the common electrode 020, the parasitic capacitance can be reduced. However, if the common electrode 020 has an overly large opening, it will cause light leakage to worsen, which is not conducive to display.

[0049] Therefore, it is urgent to improve the parasitic capacitance between the pixel circuit and the common electrode while reducing the light leakage phenomenon in the array substrate, so as to improve the contrast of the display image and optimize its image quality.

[0050] At least one embodiment of the present disclosure provides an array substrate, a display panel, and a display device.

[0051] At least one embodiment of the present disclosure provides an array substrate comprising a base substrate, a plurality of data lines, a plurality of thin film transistors, a common electrode, a plurality of pixel electrodes, and an insulating layer, wherein the plurality of data lines are located on the base substrate and arranged along a first direction; the plurality of thin film transistors are located on the base substrate and arranged in an array along a first direction and a second direction, each thin film transistor comprising a first electrode, a second electrode, and a gate electrode, the first electrode being electrically connected to the data line, the first direction and the second direction being parallel to the base substrate, and the first direction intersecting the second direction; the common electrode being located on a side of the data line and the thin film transistor away from the base substrate; the plurality of pixel electrodes being located on a side of the common electrode away from the base substrate, and being configured as follows: An electric field is formed with the common electrode; the insulating layer is located between the common electrode and the thin film transistor, and the pixel electrode is electrically connected to the second electrode through the connecting via in the insulating layer, wherein the orthographic projections of the plurality of data lines on the base substrate completely fall within the orthographic projection of the common electrode on the base substrate; the common electrode includes a plurality of opening portions, and the plurality of opening portions are arranged in a one-to-one correspondence with the plurality of thin film transistors, each opening portion includes a first opening and a second opening, the first opening is configured to expose a portion of the thin film transistor, and the second opening is configured to expose the connecting via, the orthographic projections of the first opening and the second opening on a straight line extending along the second direction overlap with each other, and in the second direction, the size of the first opening is smaller than the size of the second opening.

[0052] The array substrate provided by the embodiment of the present disclosure has a common electrode with a first opening and a second opening of different sizes in the second direction. On the one hand, the common electrode can effectively cover the structure in the pixel circuit, which can reduce its interference with the pixel electrode, thereby reducing the light leakage phenomenon caused by the interference electric field, thereby improving the quality of the display image; on the other hand, the first opening exposes a part of the structure of the thin film transistor (for example, the first electrode, the channel region, etc.), which can reduce the parasitic capacitance between the part of the structure of the thin film transistor and the common electrode, thereby reducing the influence on the electric field formed between the common electrode and the pixel electrode, thereby optimizing the display performance.

[0053] The array substrate, display panel, and display device provided by the embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0054] Figure 2 is a structural schematic diagram of an array substrate provided in at least one embodiment of the present disclosure; Figure 3A is an enlarged schematic diagram of a local structure of the array substrate in Figure 2; and Figure 3B is an enlarged schematic diagram of a local structure of the array substrate in Figure 3A.

[0055] As shown in FIG2 , an array substrate 01 includes a base substrate 10, and a plurality of data lines 100, a plurality of thin film transistors 200, a common electrode 300, a plurality of pixel electrodes 400, and an insulating layer 500 located on the base substrate 10. For example, the array substrate 01 may include a plurality of sub-pixels, each of which includes a thin film transistor 200. The plurality of thin film transistors 200 in the array substrate 01 are arranged in an array along a first direction X and a second direction Y, for example, as a plurality of thin film transistor rows and a plurality of thin film transistor columns.

[0056] As shown in FIG2 , each thin-film transistor 200 includes a first electrode 210, a second electrode 220, and a gate electrode 230. For example, the first electrode 210 may be a source electrode, and the second electrode 220 may be a drain electrode, but the present invention is not limited thereto. The first electrode 210 and the second electrode 220 are merely relative terms, and their names are interchangeable. For example, one of the first electrode 210 and the second electrode 220 of the thin-film transistor 200 may be a source electrode, and the other of the first electrode 210 and the second electrode 220 may be a drain electrode. The gate electrode 230 of the thin-film transistor 200 may be referred to as a control electrode. As shown in FIG2 , a plurality of data lines 100 are arranged along a first direction X. The first electrode 210 is electrically connected to the data lines 100 to receive data signals from the data lines 100.

[0057] As shown in Figure 2, the common electrode 300 is located on the side of the data line 100 away from the base substrate 10, and on the side of the thin film transistor 200 away from the base substrate 10. For example, the common electrode 300 can receive a common voltage signal. A plurality of pixel electrodes 400 are located on the side of the common electrode 300 away from the base substrate 10, and are configured to form an electric field with the common electrode 300. For example, one side of the array substrate 10 can be provided with a liquid crystal layer (not shown in the figure), and the electric field formed between the common electrode 300 and the pixel electrode 400 (hereinafter referred to as the driving electric field) can drive the liquid crystal molecules in the liquid crystal layer to deflect for display. In a direction perpendicular to the base substrate 10, the insulating layer 500 is located between the common electrode 300 and the pixel electrode 400, and the pixel electrode 400 is electrically connected to the second electrode 220 through the connection via 510 in the insulating layer 500.

[0058] For example, as shown in FIG2 , the common electrode 300 may be an integrated structure, for example, it may be provided on the entire surface, so that the orthographic projections of multiple data lines 100 on the base substrate 10 may completely fall within the orthographic projection of the common electrode 300 on the base substrate 10, thereby shielding the signals in the data lines 100 to reduce the influence of the data lines 100 on the driving electric field.

[0059] As shown in Figures 2, 3A, and 3B, the common electrode 300 includes a plurality of openings 305, each of which corresponds to a plurality of thin film transistors 200. Each opening 305 includes a first opening 310 and a second opening 320. The first opening 310 is configured to expose a portion of the thin film transistor 200, thereby reducing the parasitic capacitance between the thin film transistor 200 and the common electrode 300, thereby reducing the impact on the driving electric field. The second opening 320 is configured to expose the connecting via 510, thereby electrically connecting the pixel electrode 400 to the second electrode 220 of the thin film transistor 200. In Figures 3A and 3B, for clarity, the portions of structures such as the data line 100, the gate 230, and the first electrode 210 located outside the opening 305 are represented by dotted lines, and the portions of structures such as the first electrode 210 and the second electrode 220 located within the opening 305 are represented by solid lines.

[0060] Figure 4 is a schematic diagram of the structure of an opening portion in an array substrate provided in at least one embodiment of the present disclosure. Figure 5 is a schematic diagram of a partial structure of an array substrate provided in at least one embodiment of the present disclosure.

[0061] As shown in Figures 2 and 4, the orthographic projections of the first opening 310 and the second opening 320 on a straight line extending along the second direction Y overlap, and in the second direction Y, the dimension L1 of the first opening 310 is smaller than the dimension L2 of the second opening 320. This arrangement allows the position and size of the first opening 310 to adapt to the position and structure of the thin-film transistor 200, thereby ensuring that the first opening 310 can only expose a portion of the structure of the thin-film transistor 200, thereby effectively reducing the parasitic capacitance between the thin-film transistor 200 and the common electrode 300, and reducing the impact of the parasitic capacitance on the driving electric field. At the same time, the position and size of the second opening 320 can adapt to the position and structure of the connecting via 510, thereby exposing it, facilitating a stable connection between the pixel electrode 400 and the second electrode 220, thereby facilitating a display with good quality and stability. On the other hand, the common electrode 300 can effectively cover other structures in the array substrate (such as data lines, gate lines, etc.), which can reduce their interference with the pixel electrodes, thereby reducing light leakage caused by the interference electric field generated by the data lines or gate lines, thereby improving the quality of the display image.

[0062] As shown in FIG. 2 , the first direction X and the second direction Y are both parallel to the base substrate 10 , and the first direction X intersects the second direction Y. The embodiment of the present disclosure is described by taking the first direction X and the second direction Y as being perpendicular to each other as an example.

[0063] For example, as shown in Figures 3A and 3B, the orthographic projection area of ​​the first opening 310 on the base substrate 10 is larger than the orthographic projection area of ​​the second opening 320 on the base substrate 10. Thus, a portion of the first electrode 210, at least a portion of the second electrode 220, and at least a portion of the gate 230 of the thin film transistor 200 can be exposed through the first opening 310, thereby effectively reducing the parasitic capacitance between the thin film transistor 200 and the common electrode 300. For example, the smaller orthographic projection area of ​​the second opening 320 on the base substrate 10 can facilitate shielding of the chaotic electric field inside the thin film transistor 200 through the common electrode 300, thereby reducing its impact on the driving electric field.

[0064] For example, as shown in FIG3A and FIG4 , the first opening 310 and the second opening 320 are connected to each other, and the first opening 310 and the second opening 320 are arranged along the first direction X. Such an arrangement can simplify the manufacturing process of the common electrode 300. For example, in other embodiments of the present disclosure, the first opening 310 and the second opening 320 can also be spaced apart from each other and independent of each other to adapt to changes in the position of the thin film transistor 200 and the position of the connecting via 510. The embodiments of the present disclosure do not limit the positions and shapes of the first opening 310 and the second opening 320.

[0065] For example, as shown in Figures 3A and 3B, the first electrode 210 includes a first portion 201 and a second portion 202 connected to each other, the first portion 201 is exposed by the first opening 310, and the second portion 202 is covered by the common electrode 300. In other words, a portion of the first electrode 210 (i.e., the first portion 201) is exposed by the first opening 310, and another portion of the first electrode 210 (the second portion 202) is not exposed by the first opening 310 but is covered by the common electrode 300, thereby reducing the parasitic capacitance between the first portion 201 of the first electrode 210 and the common electrode 300, and reducing the influence of the second portion 202 of the first electrode 210 on the driving electric field, reducing light leakage, thereby achieving a balance between reducing parasitic capacitance and reducing light leakage, resulting in a higher contrast of the displayed image and a better and more stable display effect.

[0066] For example, as shown in Figures 3A and 3B, the first portion 201 of the first electrode 210 is located between the second portion 202 and the second electrode 220, and the second portion 202 of the first electrode 210 is connected to the first portion 201. The orthographic projection of the first portion 201 on the base substrate 10 is a non-closed ring, and at least a portion of the orthographic projection of the second electrode 220 on the base substrate 10 is located within the area enclosed by the ring. For example, the orthographic projection of the first portion 201 exposed by the first opening 310 on the base substrate 10 is a "U" shape, and the opening of the "U" shape faces the second electrode 220, so that the second electrode 220 can extend into the interior of the "U", thereby reducing the size of the thin film transistor 200 in the first direction X.

[0067] For example, as shown in FIG3A , the average width of the ring is D1, and D1=f 2 +h 2 +m 2 +n 2 In the calculation formula of D1, f represents the fluctuation value of the first opening 310, h represents the fluctuation value of the first electrode 210, m represents the alignment deviation of the first opening 310, and n represents the alignment deviation of the first electrode 210, and the units of f, h, m and n are all micrometers.

[0068] In some embodiments, as shown in FIG3A , the fluctuation value f of the first opening 310 and the fluctuation value h of the first electrode 210 are both 0.5 to 5 microns. For example, the fluctuation value f of the first opening 310 and the fluctuation value h of the first electrode 210 can be equal to or different from each other. For example, the fluctuation value f of the first opening 310 can be 0.5 to 2.5 microns, 1.5 to 3.0 microns, 2.0 to 3.5 microns, 4.0 to 4.5 microns, or 4.5 to 5.0 microns. For example, the fluctuation value h of the first electrode 210 can be 0.5 to 2.5 microns, 1.5 to 3.0 microns, 2.0 to 3.5 microns, 4.0 to 4.5 microns, or 4.5 to 5.0 microns. For example, the alignment deviation m of the first opening 310 and the alignment deviation n of the first electrode 210 are both 1.0 to 3.5 microns. For example, the alignment deviation m of the first opening 310 and the alignment deviation n of the first electrode 210 can be equal to or different from each other. For example, the alignment deviation m of the first opening 310 may be at least one of 1.0 to 1.5 microns, 2.0 to 2.5 microns, 1.5 to 3.0 microns, 2.0 to 3.5 microns, and 3.0 to 3.5 microns. For example, the alignment deviation n of the first electrode 210 may be at least one of 1.0 to 1.5 microns, 2.0 to 2.5 microns, 3.0 to 3.5 microns, 2.0 to 3.5 microns, and 1.5 to 3.0 microns. For example, the average ring width D1 of the orthographic projection (i.e., the ring shape) of the first portion 201 on the base substrate 10 may be 1.7 to 4.2 microns, for example, at least one of 1.7 to 2.0 microns, 1.8 to 2.5 microns, 2.6 to 3.0 microns, 3.2 to 3.5 microns, and 3.8 to 4.0 microns.

[0069] By setting the average ring width D1 of the above-mentioned ring to 1.7 to 4.2 microns, the positive projection area of ​​the second part 202 of the first electrode 210 covered by the common electrode 300 on the base substrate 10 (see Figure 2) can be larger, thereby helping to reduce the risk of light leakage between the structure of the second part 202 on the side away from the first part 201 in the thin film transistor 200 and the second part 202. At the same time, the first electrode 210 can have a first part 201 exposed by the first opening 310, thereby reducing the parasitic capacitance between the first part 201 and the common electrode 300.

[0070] For example, as shown in Figures 3A and 3B, the first portion 201 includes a first sub-portion 211, a second sub-portion 212, and a third sub-portion 213. The first sub-portion 211 and the second sub-portion 212 are arranged opposite to each other in the second direction Y. The third sub-portion 213 is located between the first sub-portion 211 and the second sub-portion 212, and the first sub-portion 211 and the second sub-portion 212 are connected by the third sub-portion 213. For example, the first sub-portion 211, the second sub-portion 212, and the third sub-portion 213 are an integrated structure. The first sub-portion 211 and the second sub-portion 212 extend along the first direction X, and the third sub-portion 213 extends along the second direction Y.

[0071] For example, as shown in Figures 2 and 3B, the array substrate 01 includes multiple display areas A0, and the display area A0 is located between two adjacent data lines 100 in the first direction X and between two adjacent thin film transistors 200 in the second direction Y. Therefore, the first sub-portion 211 is closer to the display area A0 than the third sub-portion 213.

[0072] In some embodiments, as shown in Figures 2, 3A and 3B, the second portion 202 of the first electrode 210 includes a portion of the first sub-portion 211 away from the second electrode 220, and the portion is an integral structure with the first sub-portion 211. Thus, by making the size of the first sub-portion 211 in the second direction Y smaller than the size of the third sub-portion 213 in the second direction Y, the portion of the second portion 202 located on the side of the first sub-portion 211 away from the second electrode 220 can be made relatively larger in the second direction Y. Since this partial structure is close to the display area A0 and is covered by the common electrode 300, the risk of light leakage can be reduced.

[0073] In some embodiments, as shown in Figures 2, 3A and 3B, the second portion 202 of the first electrode 210 includes a portion located on the side of the second sub-portion 212 away from the second electrode 220, and the portion is an integral structure with the second sub-portion 212. Therefore, by making the size of the second sub-portion 212 in the second direction Y smaller than the size of the third sub-portion 213 in the second direction Y, the size of the portion of the second portion 202 located on the side of the second sub-portion 212 away from the second electrode 220 in the second direction Y can be made relatively large. Since this partial structure is close to the display area A0 and is covered by the common electrode 300, the risk of light leakage can be reduced.

[0074] In some embodiments, as shown in Figures 3A and 3B, the orthographic projection area of ​​the first portion 201 of the first electrode 210 on the base substrate 10 is smaller than the orthographic projection area of ​​the second portion 202 on the base substrate 10, so that a large portion of the first electrode 210 can be covered by the common electrode 300 to reduce the risk of light leakage and reduce the impact of the covered portion of the structure on the driving electric field.

[0075] In some embodiments, as shown in Figure 5, in the second direction Y, the portions of the first electrode 210 located on both sides of the second electrode 220 can be covered by the common electrode 300, thereby reducing the risk of light leakage from around the display area A0 and facilitating shielding of the signal in the data line 100 through the common electrode 300 to reduce the impact on the driving electric field; at the same time, the first portion 201 of the first electrode 210 is located on the side of the second electrode 220 close to the second portion 202 in the first direction X, and the first portion 201 extends along the second direction Y. Since the first portion 201 is exposed by the first opening 310, the parasitic capacitance between the portion and the common electrode 300 can be reduced, thereby facilitating the normal display of the picture.

[0076] In some embodiments, as shown in Figures 3A and 3B, the orthographic projection area of ​​the first portion 201 on the base substrate 10 is 20% to 50% of the orthographic projection area of ​​the second portion 202 on the base substrate 10, for example, 20% to 30%, 25% to 35%, 40% to 45%, or 30% to 45%. This configuration can ensure that the first portion 201 of the first electrode 210 exposed by the common electrode 300 and the second portion 202 covered by the common electrode 300 have a suitable ratio, which is conducive to achieving a reasonable balance between reducing the parasitic capacitance between the first electrode 210 and the common electrode 300 and reducing light leakage, thereby facilitating the display of good contrast and display quality.

[0077] For example, as shown in Figures 3A and 3B, the thin film transistor 200 further includes an active pattern 600, which is connected to the first electrode 210 and the second electrode 220, respectively, and at least partially overlaps with the gate 230. For example, in a direction perpendicular to the base substrate 10, the first electrode 210 and the second electrode 220 overlap with the active pattern 600, respectively. For example, the first electrode 210 and the second electrode 220 can be located on the same layer, and an insulating structure can be provided between the layer and the active pattern 600. The first electrode 210 and the second electrode 220 can be connected to the active pattern 600 through vias penetrating the insulating structure, respectively, but are not limited thereto. For example, the active pattern 600 is made of a semiconductor material. For example, the material of the active pattern 600 includes amorphous silicon, low-temperature polysilicon, or an oxide semiconductor material, but is not limited thereto.

[0078] For example, as shown in Figures 3A and 3B, the active pattern 600 includes a third portion 630 and a fourth portion 640 connected to each other. The third portion 630 is exposed by the first opening 310, and the fourth portion 640 is covered by the common electrode 300. The fourth portion 640 is closer to the display area A0 of the array substrate 01 than the third portion 630. By having the fourth portion 640 covered by the common electrode 300, the risk of light leaking from the edge of the active pattern 600 is reduced. At the same time, after the third portion 630 is exposed by the first opening 310, the parasitic capacitance between the third portion 630 and the common electrode 300 when it acts as a conductor can be reduced, thereby facilitating display.

[0079] For example, as shown in Figures 3A and 3B, the fourth portion 640 of the active pattern 600 includes a first edge portion 641 and a second edge portion 642. The first edge portion 641 and the second edge portion 642 are opposite to each other and spaced apart in the second direction Y, and the third portion 630 is located between the first edge portion 641 and the second edge portion 642. For example, the first edge portion 641 is closer to the display area A0 than the third portion 630, and the second edge portion 642 is closer to the display area A0 than the third portion 630. This arrangement can reduce the risk of light emitted from the display area A0 leaking from the edge portion of the fourth portion 640.

[0080] For example, as shown in Figures 3A and 3B, in the second direction Y, the size of the first edge portion 641 and the size of the second edge portion 642 are both smaller than the size of the third portion 630. The middle portion (e.g., the center of gravity) of the active pattern 600 is located in the third portion 630, and at least a portion of the second electrode 220 is located on a side of the third portion 630 away from the base substrate 10 and contacts the third portion 630. In this manner, at least a portion of the third portion 630 and the second electrode 220 are exposed by the first opening 310, thereby reducing the parasitic capacitance between the third portion 630 and the common electrode 300, as well as reducing the parasitic capacitance between the second electrode 220 and the common electrode 300.

[0081] For example, as shown in Figures 3A and 3B, in the first direction X, the active pattern 600 includes a first edge 611 away from the second electrode 220, the first electrode 210 includes a second edge 221 away from the second electrode 220, and the gate 230 includes a third edge 231 away from the second electrode 220. The third edge 231 extends beyond the second edge 221 of the first electrode 210, and the second edge 221 extends beyond the first edge 611 of the active pattern 600. The first edge 611 of the active pattern 600 is covered by the second electrode 220, and the first edge 611 is closer to the second electrode 220 than the second edge 221. The second edge 221 of the first electrode 210 is closer to the second electrode 220 than the third edge 231 of the gate 230.

[0082] Such a setting, on the one hand, can reduce the risk of light leakage near the first edge of the active pattern; on the other hand, can reduce the size of the active pattern in the first direction, so that in the direction perpendicular to the substrate, the area of ​​overlap between the active pattern and the gate is reduced, so that the parasitic capacitance between the active pattern and the gate is reduced, which is beneficial to display.

[0083] Figure 6A is a schematic cross-sectional view of some array substrates. Figure 6B is a schematic cross-sectional view of an array substrate provided in at least one embodiment of the present disclosure.

[0084] For example, as shown in FIG6A , in some array substrates 001 , the second edge 221 of the first electrode 210 is typically closer to the second electrode 220 than the first edge 611 of the active pattern 600 , and the first edge 611 of the active pattern 600 is substantially flush with the third edge 231 of the gate 230 . Therefore, the parasitic capacitance between the active pattern 600 and the gate 230 is relatively large, which is detrimental to display.

[0085] For example, in some embodiments of the present disclosure, FIG6B may be a schematic cross-sectional view of the array substrate in FIG9 (see description below) taken along line AA'. As shown in FIG6B , the second edge 221 of the first electrode 210 extends beyond the first edge 611 of the active pattern 600 by a dimension E, and E=r 2 +h 2 +t 2 +n 2 , where r represents the fluctuation value of the active pattern 600, h represents the fluctuation value of the first electrode 210, t represents the alignment deviation of the active pattern 600, and n represents the alignment deviation of the first electrode 210. For example, E can be 1.7 to 4.2 microns, such as at least one of 1.7 to 2.0 microns, 1.8 to 2.5 microns, 2.6 to 3.0 microns, 3.2 to 3.5 microns, and 3.8 to 4.0 microns. Thus, the second edge 221 of the first electrode 210 can be made smaller beyond the first edge 611 of the active pattern 600, which helps to reduce the size of the first electrode 210 in the first direction X, thereby reducing the parasitic capacitance between the first electrode 210 and the gate 230.

[0086] FIG7 is a schematic diagram of the structure of a first conductive pattern in an array substrate provided in at least one embodiment of the present disclosure; FIG8 is a schematic diagram of the stacking of the first conductive pattern and the semiconductor pattern in an array substrate provided in at least one embodiment of the present disclosure; FIG9 is a schematic diagram of the stacking of the first conductive pattern, the semiconductor pattern, and the third conductive pattern in an array substrate provided in at least one embodiment of the present disclosure; FIG10 is a schematic diagram of the stacking of the first conductive pattern, the semiconductor pattern, the third conductive pattern, and the fourth conductive pattern in an array substrate provided in at least one embodiment of the present disclosure; FIG11 is a schematic diagram of the stacking of the first conductive pattern, the semiconductor pattern, the third conductive pattern, the fourth conductive pattern, and the fifth conductive pattern in an array substrate provided in at least one embodiment of the present disclosure. FIG12 is a schematic diagram of the stacking of the first conductive pattern, the semiconductor pattern, the third conductive pattern, the fourth conductive pattern, the fifth conductive pattern, and the sixth conductive pattern in an array substrate provided in at least one embodiment of the present disclosure.

[0087] For example, as shown in FIG7 to FIG12, the array substrate includes a first conductive pattern LY1, a semiconductor pattern LY2, a third conductive pattern LY3, a fourth conductive pattern LY4, a fifth conductive pattern LY5 and a sixth conductive pattern LY6 sequentially stacked along a direction perpendicular to the base substrate.

[0088] For example, as shown in FIG7 , the first conductive pattern LY1 includes a plurality of gate lines 900 spaced apart along the second direction Y. The gate lines 900 extend along the first direction X and are electrically connected to the gate electrode 230 of the thin-film transistor 200, forming an integrated structure. As shown in FIG8 , the semiconductor pattern LY2 is located on the first conductive pattern LY1. For example, an insulating structure (not shown) may be provided between the first conductive pattern LY1 and the semiconductor pattern LY2. For example, the semiconductor pattern LY2 may be the active pattern 600 described above, which overlaps with the gate electrode 230. As shown in FIG9 , the third conductive pattern LY3 is located on a side of the semiconductor pattern LY2 away from the base substrate and includes a plurality of data lines 100. The data lines 100 extend along the second direction Y and are electrically connected to the second portion 202 of the first electrode 210. The data lines 100 are provided on the same layer as the first electrode 210 and the second electrode 220, and the data lines 100 and the first electrode 210 form an integrated structure. This arrangement helps simplify the fabrication process of the data line 100, the first electrode 210, and the second electrode 220, and facilitates controlling the matching accuracy between the first electrode 210 and the second electrode 220, thereby facilitating the fabrication process. For example, in some embodiments of the present disclosure, the semiconductor pattern LY2 and the third conductive pattern LY3 can be formed sequentially using two separate masks. In some embodiments, the semiconductor pattern LY2 and the third conductive pattern LY3 can also be formed simultaneously using a single mask. The embodiments of the present disclosure do not limit the fabrication process of the semiconductor pattern LY2 and the third conductive pattern LY3.

[0089] For example, as shown in Figure 10, the fourth conductive pattern LY4 is disposed entirely on a side of the third conductive pattern LY3 that is away from the base substrate. For example, an insulating structure (not shown) is disposed between the third conductive pattern LY3 and the fourth conductive pattern LY4. The insulating structure may be made of, but is not limited to, resin. For example, the fourth conductive pattern may include a common electrode. For example, the insulating structure between the first conductive pattern LY1 and the semiconductor pattern LY2 may be referred to as a gate insulating layer, and the insulating structure between the third conductive pattern LY3 and the fourth conductive pattern LY4 may be made of the same material as the gate insulating layer.

[0090] For example, as shown in FIG11 , the fifth conductive pattern LY5 may include an electrode pattern 800. The electrode pattern 800 is located on a side of the common electrode 300 away from the thin-film transistor 200 (see FIG2 ), and the electrode pattern 800 is electrically connected to the common electrode 300. For example, the electrode pattern 800 may contact the common electrode 300, thereby being electrically connected to the common electrode 300. For example, if the electrode pattern is made of a metal material and the common electrode is made of ITO, the electrical connection between the electrode pattern 800 and the common electrode 300 can reduce the square resistance of the common electrode 300, thereby facilitating uniformity of the signal transmitted by the common electrode 300. Of course, in some embodiments, an insulating structure may be provided between the fourth conductive pattern LY4 and the fifth conductive pattern LY5. This insulating structure may include multiple vias, and the fifth conductive pattern LY5 may be electrically connected to the fourth conductive pattern LY4 through these multiple vias. The embodiments of the present disclosure do not limit the connection method between the fourth conductive pattern LY4 and the fifth conductive pattern LY5. For example, in some embodiments of the present disclosure, the fourth conductive pattern LY4 and the fifth conductive pattern LY5 may be formed sequentially using two masks, respectively. In some embodiments, the fourth conductive pattern LY4 and the fifth conductive pattern LY5 may also be formed simultaneously using one mask. The embodiments of the present disclosure do not limit the manufacturing process of the fourth conductive pattern LY4 and the fifth conductive pattern LY5.

[0091] In some embodiments, as shown in FIG11 , an electrode pattern 800 includes a plurality of first pattern portions 810 and a plurality of second pattern portions 820. The first pattern portions 810 extend along a first direction X, and the second pattern portions 820 extend along a second direction Y. The plurality of first pattern portions 810 are arranged at intervals in the second direction Y, and adjacent first pattern portions 810 are electrically connected via the second pattern portions 820. For example, the plurality of first pattern portions 810 and the plurality of second pattern portions 820 are interconnected to form a "net-like" structure to reduce the overall square resistance of the electrode pattern 800.

[0092] For example, as shown in FIG11 , at least a portion of the orthographic projection of the second pattern portion 820 on the base substrate 10 is located outside the orthographic projection of the data line 100 on the base substrate 10. For example, the second pattern portion 820 and the data line 100 are closely adjacent to each other in the first direction X and are spaced apart from each other, thereby reducing parasitic capacitance between the second pattern portion 820 and the data line 100. For example, the second pattern portion 820 and the data line 100 being closely adjacent to each other in the first direction X means that no other components are disposed between them, thereby facilitating an increase in the area of ​​the light-emitting region A0 and a higher pixel aperture ratio.

[0093] In some embodiments, referring to FIG11 , the orthographic projection of the second pattern portion 820 on the base substrate 10 may also partially overlap with the orthographic projection of the data line 100 on the base substrate 10 , thereby ensuring that the parasitic capacitance between the second pattern portion 820 and the data line 100 is within a reasonable range (for example, a range in which the parasitic capacitance between the second pattern portion 820 and the data line 100 does not affect display), thereby increasing the pixel aperture ratio as much as possible to facilitate display. The embodiments of the present disclosure do not limit the overlapping area of ​​the orthographic projection of the second pattern portion 820 on the base substrate 10 and the orthographic projection of the data line 100 on the base substrate 10 .

[0094] For example, as shown in FIG11 , at least a portion of the orthographic projection of the first pattern portion 810 on the base substrate 10 is located outside the orthographic projection of the gate line 900 on the base substrate 10. For example, the first pattern portion 810 and the gate line 900 are closely adjacent to each other in the second direction Y and spaced apart, thereby reducing parasitic capacitance between the first pattern portion 810 and the gate line 900. The first pattern portion 810 and the gate line 900 being closely adjacent to each other in the second direction Y means that no other components are disposed between them, thereby facilitating an increase in the area of ​​the light-emitting region A0 and a pixel aperture ratio.

[0095] In some embodiments, referring to FIG11 , the orthographic projection of the first pattern portion 810 on the base substrate 10 may also at least partially overlap with the orthographic projection of the gate line 900 on the base substrate 10 , thereby ensuring that the parasitic capacitance between the first pattern portion 810 and the gate line 900 is within a reasonable range (for example, a range in which the parasitic capacitance between the first pattern portion 810 and the gate line 900 does not affect the display), thereby increasing the pixel aperture ratio as much as possible to facilitate display. The embodiments of the present disclosure do not limit the overlapping area of ​​the orthographic projection of the first pattern portion 810 on the base substrate 10 and the orthographic projection of the gate line 900 on the base substrate 10.

[0096] For example, as shown in Figures 4 and 11, in the second direction Y, the second opening 320 is farther away from the gate line 900 than the first opening 310, and the second opening 320 is spaced apart from the gate line 900, which is the gate line 900 to which the thin film transistor exposed by the first opening 310 is connected. For example, the first opening 310 includes a protrusion 3101 that protrudes relative to the edge of the second opening 320 extending along the X direction, and the protrusion 3101 does not overlap with the second opening 320 on a plane perpendicular to the first direction X. As shown in Figure 11, the second opening 320 does not expose the gate line 900, that is, the gate line 900 is completely covered by the common electrode 300, thereby reducing the influence of the gate line 900 on the driving electric field, which is beneficial to display.

[0097] For example, as shown in FIG4 and FIG11, the edge 3201 of the second opening 320 close to the first opening 310 is adjacent to the gate 230, and the second opening 320 does not expose the gate 230, thereby reducing the influence of the gate 230 on the driving electric field to facilitate display.

[0098] FIG13 is a schematic structural diagram of a second electrode provided in at least one embodiment of the present disclosure.

[0099] For example, as shown in FIG3A and FIG13 , the second electrode 220 includes an extension portion 225. The extension portion 225 extends along a first direction X. The orthographic projection of the first portion 201 on the base substrate 10 is annular, and the extension portion 225 extends into the area enclosed by the annular shape. The extension portion 225 includes a first sub-extension portion 2211 and a second sub-extension portion 2212. The first sub-extension portion 2211 is exposed by the first opening 310. The first sub-extension portion 2211 is closer to the first electrode 210 than the second sub-extension portion 2212. The orthographic projection of the first sub-extension portion 2211 on the base substrate 10 falls within the orthographic projection of the active pattern 600 on the base substrate 10. For example, the extension portion 225 is a portion of the second electrode 220. For example, the second electrode 220 further includes a contact portion 2213 located on a side of the extension portion 225 away from the first electrode 210. The contact portion 2213 is configured to electrically connect to the pixel electrode 400.

[0100] For example, as shown in Figures 3 and 13 , the size of the first sub-extension 2211 is smaller than the size of the second sub-extension 2212 in the second direction Y. Because the orthographic projection of the first sub-extension 2211 on the base substrate falls within the orthographic projection of the gate 230 on the base substrate, by making the size of the first sub-extension 2211 smaller in the second direction Y, the overlapping area between the first sub-extension 2211 and the gate 230 can be reduced, thereby reducing the parasitic capacitance between the first sub-extension 2211 and the gate 230.

[0101] For example, as shown in Figures 3 and 13, in the first direction X, the size of the first sub-extension 2211 is larger than the size of the second sub-extension 2212. For example, the size of the second sub-extension 2212 can be 1 / 5 to 1 / 2 of the size of the first sub-extension 2211, such as 1 / 5, 1 / 4, 1 / 3 or 1 / 2, which is beneficial to reducing the parasitic capacitance between the first sub-extension 2211 and the gate 230.

[0102] For example, as shown in FIG13 , the second sub-extension 2212 of the second electrode 220 includes a main body 2210 and at least one protruding portion 2220 . The protruding portion 2220 is connected to the main body 2210 and protrudes relative to the main body 2210 in the first direction X. For example, the orthographic projection of the protruding portion 2220 on the base substrate 10 is polygonal, such as a triangle or a quadrilateral. For example, the orthographic projection of the protruding portion 2220 on the base substrate 10 may also be semicircular. The embodiments of the present disclosure are not limited to the shape of the protruding portion 2220 .

[0103] For example, as shown in FIG13 , the protrusion 2220 is located on one side of the main body 2210 in the second direction Y. The protrusion 2220 and the main body 2210 may be integrally formed and made of the same material, but are not limited thereto. For example, by including the protrusion 2220 in the second sub-extension 2212, the current conducting area of ​​the second sub-extension 2212 may be increased, thereby facilitating current transmission and improving the ion transmission efficiency of the thin film transistor 200 (see FIG3 ).

[0104] For example, as shown in FIG13 , the second sub-extension 2212 includes two protrusions 2220, and the two protrusions 2220 are located on either side of the main body 2210. For example, the two protrusions 2220 in the second sub-extension 2212 are symmetrically arranged on either side of the main body 2210, but the present invention is not limited thereto. In some embodiments, the two protrusions 2220 in the second sub-extension 2212 may also be spaced apart in the first direction X. The embodiments of the present disclosure do not limit the positions of the multiple protrusions 2220.

[0105] For example, as shown in Figures 3A and 13, there is a gap between the orthographic projection of the protrusion 2220 on the plane perpendicular to the second direction Y and the orthographic projection of the first electrode 210 on the plane. Such a setting is conducive to reducing the distance between the first sub-extension 2211 and the first part 211 of the first electrode 210 in the second direction Y, thereby facilitating the miniaturization design of the thin film transistor 200 and increasing the pixel aperture ratio.

[0106] For example, as shown in FIG12 , the sixth conductive pattern LY6 is located on a side of the fifth conductive pattern LY5 away from the base substrate 10, and the sixth conductive pattern LY6 includes a pixel electrode 400. For example, as shown in FIG3 and FIG12 , the array substrate 01 further includes an insulating layer 500 located between the common electrode 300 and the pixel electrode 400. The insulating layer 500 includes a connection via 510, and the pixel electrode 400 is connected to the common electrode 300 through the connection via 510. For example, the insulating structure between the third conductive pattern LY3 and the fourth conductive pattern LY4 can be made of the same material as the insulating layer 500.

[0107] For example, as shown in FIG12 , the orthographic projection area of ​​the connecting via 510 on the base substrate 10 is smaller than the orthographic projection area of ​​the second opening 320 on the base substrate 10. For example, the minimum distance between the connecting via 510 and the second opening 320 is D2, and D2=y 2 +e 2 +s 2 +g 2 , where y represents the fluctuation value of the second opening 320 , h represents the fluctuation value of the connecting via 510 , s represents the alignment deviation of the second opening 320 , and g represents the alignment deviation of the connecting via 510 .

[0108] For example, as shown in FIG3A , the fluctuation value y of the second opening 320 and the fluctuation value h of the connecting via 510 are both 0.5 to 5 microns. For example, the fluctuation value y of the second opening 320 and the fluctuation value h of the connecting via 510 can be equal to or different from each other. For example, the fluctuation value y of the second opening 320 can be 0.5 to 2.5 microns, 1.5 to 3.0 microns, 2.0 to 3.5 microns, 4.0 to 4.5 microns, or 4.5 to 5.0 microns. For example, the fluctuation value h of the connecting via 510 can be 0.5 to 2.5 microns, 1.5 to 3.0 microns, 2.0 to 3.5 microns, 4.0 to 4.5 microns, or 4.5 to 5.0 microns. For example, the alignment deviation s of the second opening 320 and the alignment deviation g of the connecting via 510 can be equal to or different from each other. For example, the alignment deviation s of the second opening 320 can be 1.0-1.5 microns, 2.0-2.5 microns, 3.0-3.5 microns, 2.0-3.5 microns, or 1.5-3.0 microns. For example, the alignment deviation g of the connecting via 510 can be 1.0-1.5 microns, 2.0-2.5 microns, 3.0-3.5 microns, 2.0-3.5 microns, or 1.5-3.0 microns. For example, the minimum distance D2 between the connecting via 510 and the second opening 320 is 1.7-2.5 microns, for example, 1.7-2.0 microns, 1.8-2.1 microns, 1.9-2.2 microns, or 2.0-2.4 microns.

[0109] By ensuring that the minimum distance D2 between the connecting via 510 and the second opening 320 satisfies the above range, on the one hand, at least a portion of the insulating layer 500 can be located in the area between the connecting via 510 and the second opening 320, thereby reducing the risk of a short circuit between the common electrode 300 and the pixel electrode 400; on the other hand, the coverage of the thin film transistor 200 by the common electrode 300 can be increased, thereby reducing the influence of the electric field inside the thin film transistor 200 on the driving electric field.

[0110] FIG14 is a schematic cross-sectional view of an array substrate provided in at least one embodiment of the present disclosure.

[0111] For example, as shown in FIG14 , a thin film transistor 200 includes a gate 230, a first electrode 210, and a second electrode 220. A gate insulating layer 1011 is disposed on the gate 230, an active pattern 600 is disposed on the gate insulating layer 1011, an organic insulating layer 1022 is disposed on the first electrode 210 and the second electrode 220, a common electrode 300 is disposed on the insulating structure 1022, an electrode pattern 800 is located on a side of the common electrode 300 away from the base substrate 10 and contacts the common electrode 300, the common electrode 300 and the electrode pattern 800 are both covered by an insulating structure 1033, a pixel electrode 400 is located on the insulating structure 1033, and the pixel electrode 400 is electrically connected to the second electrode 220 via a connecting via 500 penetrating the insulating structure 1033. For example, the insulating structure 1022 may be made of an organic material, and the insulating structure 1033 may be, but is not limited to, a passivation layer PVX.

[0112] FIG15 is a schematic structural diagram of a display panel provided in at least one embodiment of the present disclosure.

[0113] As shown in Figure 15, at least one embodiment of the present disclosure further provides a display panel 1000. The display panel 1000 includes the array substrate 01 and the opposite substrate 02 described in any of the above embodiments, wherein the opposite substrate 02 and the array substrate 01 are arranged opposite to each other to form a box.

[0114] For example, as shown in FIG15 , a liquid crystal layer 03 is provided in the box. The liquid crystal layer 03 includes a plurality of liquid crystal molecules 031. In some embodiments, a filter layer may be provided on the side of the opposing substrate 02 facing the array substrate 01 to achieve color display. For example, the filter layer includes a plurality of filter units, and each filter unit may correspond to a display electrode. For example, the plurality of filter units may include a plurality of red filter units, a plurality of green filter units, and a plurality of blue filter units, but is not limited thereto. Thus, the display panel 1000 includes the above-mentioned array substrate, and therefore, the technical effects of the above-mentioned array substrate can also be reflected on the display panel 1000, which will not be described in detail here.

[0115] For example, referring to Figures 14 and 15, in some embodiments, the elastic coefficient K22 of the liquid crystal molecules 031 is greater than 20, the thickness of the liquid crystal layer 03 is 2.8 microns, the insulating structure 1022 is made of resin, the insulating structure 1033 is a passivation layer PVX and its thickness is 0.25 microns, the first electrode 210 and the second electrode 220 are located on the same layer, and the slope angle λ formed by the patterning of the layer is 40 to 50 degrees, such as 45 degrees. For example, the array substrate also includes a light shielding layer BM (not shown in the figure), which is located on the side of the first electrode 210 away from the base substrate 10 and has a thickness of 1.15 microns. For example, the filter layer in the opposing substrate 02 can include a color filter CF, and its thickness can be 1.55 microns. With this configuration, the contrast of the display panel can reach 2000.

[0116] For example, referring to Figures 14 and 15 , in some embodiments, the elastic coefficient K22 of the liquid crystal molecules 031 is greater than 20, the thickness of the liquid crystal layer 03 is 2.8 microns, the insulating structure 1022 is made of resin, the insulating structure 1033 is a passivation layer PVX and its thickness is 0.25 microns, the first electrode 210 and the second electrode 220 are located on the same layer, and the slope angle λ formed by the patterning of the layer is 20 to 30°, such as 25°. For example, the array substrate also includes a light shielding layer BM (not shown in the figure), which is located on the side of the first electrode 210 away from the base substrate 10 and has a thickness of 1.5 microns. For example, the filter layer in the opposing substrate 02 can include a color filter CF, and its thickness can be 2 microns. With this configuration, the contrast of the display panel can reach 2450.

[0117] For example, referring to Figures 14 and 15 , in some embodiments, the elastic coefficient K22 of the liquid crystal molecules 031 is greater than 20, the thickness of the liquid crystal layer 03 is 2.8 microns, the insulating structure 1022 is made of resin, the insulating structure 1033 is a passivation layer PVX and its thickness is 0.25 microns, the first electrode 210 and the second electrode 220 are located on the same layer, and the slope angle λ formed by the patterning of the layer is 20 to 30°, such as 25°. For example, the array substrate also includes a light shielding layer BM (not shown in the figure), which is located on the side of the first electrode 210 away from the base substrate 10 and has a thickness of 2.0 microns. For example, the filter layer in the opposing substrate 02 can include a color filter CF, and its thickness can be 2.2 microns. With this configuration, the contrast of the display panel can reach 2500.

[0118] In the embodiments of the present disclosure, components located on the same layer may be formed from the same film layer through the same patterning process. For example, components located on the same layer may be located on a surface of the same component away from the base substrate.

[0119] It should be noted that, for the sake of clarity, the thickness of layers or regions in the drawings used to describe the embodiments of the present disclosure are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or intervening elements may be present.

[0120] In the embodiments of the present disclosure, the patterning or patterning process may include only photolithography, or may include photolithography and etching steps, or may include other processes such as printing and inkjet printing to form a predetermined pattern. A photolithography process includes film formation, exposure, and development, and utilizes photoresist, a mask, and an exposure machine to form a pattern. The appropriate patterning process may be selected based on the structure to be formed in the embodiments of the present disclosure.

[0121] In the embodiments of the present disclosure, components located at different layers are formed from different film layers through different patterning processes.

[0122] At least one embodiment of the present disclosure further provides a display device, and the display device includes the display panel described in any of the above embodiments. Therefore, the display device includes the above display panel, and therefore, the technical effects of the above display panel can also be reflected on the display device, which will not be repeated here.

[0123] There are a few points to note:

[0124] (1) The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can refer to general designs.

[0125] (2) In the absence of conflict, features in the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0126] The foregoing description is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure, which is determined by the appended claims.

Claims

1. An array substrate, comprising: A substrate; A plurality of data lines located on the substrate and arranged in a first direction; A plurality of thin film transistors located on the substrate and arranged in an array in the first direction and a second direction. Each thin film transistor includes a first electrode, a second electrode, and a gate. The first electrode is electrically connected to the data line. Both the first direction and the second direction are parallel to the substrate, and the first direction intersects the second direction; A common electrode located on a side of the data line and the thin film transistor away from the substrate; A plurality of pixel electrodes located on a side of the common electrode away from the substrate and configured to form an electric field with the common electrode; An insulating layer located between the common electrode and the thin film transistor. The pixel electrode is electrically connected to the second electrode through a connection via hole in the insulating layer; Wherein, a positive projection of the plurality of data lines on the substrate completely falls within a positive projection of the common electrode on the substrate; The common electrode includes a plurality of openings. The plurality of openings are provided in one-to-one correspondence with the plurality of thin film transistors. Each opening includes a first opening and a second opening. The first opening is configured to expose a part of the thin film transistor, and the second opening is configured to expose the connection via hole. Positive projections of the first opening and the second opening on a straight line extending in the second direction overlap each other, and in the second direction, a size of the first opening is smaller than a size of the second opening.

2. The array substrate according to claim 1, wherein, The first electrode includes a first part and a second part connected to each other. The first part is exposed by the first opening, and the second part is covered by the common electrode.

3. The array substrate according to claim 2, wherein, The first part is located between the second part and the second electrode. A positive projection of the first part on the substrate is a non-closed ring shape, and at least a part of a positive projection of the second electrode on the substrate is located within an area surrounded by the ring; Among them, the average ring width of the ring is D1, and D1 = f 2 + h 2 + m 2 + n 2 , f represents the fluctuation value of the first opening, h represents the fluctuation value of the first electrode, and m represents the alignment deviation of the first opening Difference, where n represents a registration deviation of the first electrode.

4. The array substrate according to claim 3, wherein, A fluctuation value f of the first opening and a fluctuation value h of the first electrode are both 0.5 to 5.0 microns. A registration deviation m of the first opening and a registration deviation n of the first electrode are both 1.0 to 3.5 microns. An average ring width D1 of the ring is 1.7 to 4.2 microns.

5. The array substrate according to any one of claims 2-3, wherein, A positive projection area of the first part on the substrate is smaller than a positive projection area of the second part on the substrate.

6. The array substrate according to claim 5, wherein, The positive projection area of the first part on the substrate is 20% to 50% of the positive projection area of the second part on the substrate.

7. The array substrate according to any one of claims 2-6, wherein, The first part includes a first sub-part, a second sub-part, and a third sub-part. The first sub-part and the second sub-part are oppositely arranged in the second direction. The third sub-part is located between the first sub-part and the second sub-part, and the first sub-part and the second sub-part are connected through the third sub-part. The dimension of the first sub - part in the second direction, and / or the dimension of the second sub - part in the second direction is less than the dimension of the third sub - part in the first direction.

8. The array substrate according to claim 2, wherein The first part of the first electrode extends along the second direction, and the parts of the first electrode on both sides of the second electrode in the second direction are covered by the common electrode.

9. The array substrate according to claim 3, wherein, The thin - film transistor includes an active pattern, which is respectively connected to the first electrode and the second electrode and at least partially overlaps with the gate electrode. Wherein, the active pattern includes a third part and a fourth part connected to each other, the third part is exposed by the first opening, and the fourth part is covered by the common electrode.

10. The array substrate according to claim 9, wherein, The fourth part includes a first edge part and a second edge part, the first edge part and the second edge part are opposite and spaced from each other in the second direction, and the third part is located between the first edge part and the second edge part. The dimension of the first edge part in the second direction and the dimension of the second edge part in the second direction are both less than the dimension of the third part in the second direction.

11. The array substrate according to claim 9, wherein, In the first direction, the active pattern includes a first edge away from the second electrode, the first electrode includes a second edge away from the second electrode, and the gate electrode includes a third edge away from the second electrode. The third edge extends beyond the second edge of the first electrode, and the second edge extends beyond the first edge of the active pattern.

12. The array substrate according to claim 11, wherein, The size by which the second edge exceeds the first edge is E, and E = r 2 + h 2 + t 2 + n 2 , r represents the fluctuation value of the active pattern, h represents the fluctuation value of the first electrode, t represents the alignment deviation of the active pattern, and n represents the alignment deviation of the first electrode.

13. The array substrate according to claim 2, wherein, The data line extends along the second direction, the data line is electrically connected to the second part of the first electrode, the data line is arranged on the same layer as the first electrode and the second electrode, and the data line and the first electrode are of an integral structure.

14. The array substrate according to claim 13, further comprising an electrode pattern, the electrode pattern is located on a side of the common electrode away from the thin - film transistor, and the electrode pattern is electrically connected to the common electrode. Among them, The electrode pattern includes a plurality of first pattern parts and a plurality of second pattern parts, the first pattern parts extend along the first direction, the second pattern parts extend along the second direction, the plurality of first pattern parts are spaced apart in the second direction, and adjacent first pattern parts are electrically connected by the second pattern parts. At least a part of the orthographic projection of the second pattern part on the substrate is located outside the orthographic projection of the data line on the substrate.

15. The array substrate according to claim 14, further comprising a plurality of gate lines, the gate lines extend along the first direction, the plurality of gate lines are spaced apart in the second direction, and the gate lines are electrically connected to the gate electrodes of the thin - film transistors. At least a part of the orthographic projection of the first pattern part on the substrate is located outside the orthographic projection of the gate lines on the substrate.

16. The array substrate according to claim 15, wherein, In the second direction, the second opening is farther away from the gate line connected to the thin film transistor exposed by the first opening than the first opening, and the second opening is spaced from the gate line.

17. The array substrate according to claim 9, wherein, The second electrode includes an extension portion that extends in the first direction and extends into the region surrounded by the ring. The extension portion includes a first sub-extension portion and a second sub-extension portion. The first sub-extension portion is exposed by the first opening, the first sub-extension portion is closer to the first electrode than the second sub-extension portion, and the orthographic projection of the first sub-extension portion on the substrate falls within the orthographic projection of the active pattern on the substrate. Wherein, in the second direction, the size of the first sub-extension portion is smaller than the size of the second sub-extension portion.

18. The array substrate according to claim 17, wherein, The second sub-extension portion of the second electrode includes a main body portion and at least one protruding portion. The protruding portion is connected to the main body portion, and the protruding portion protrudes relative to the main body portion in the first direction.

19. The array substrate according to claim 18, wherein, The second sub-extension portion includes two protruding portions, and the two protruding portions are respectively located on both sides of the main body portion. The orthographic projection of the protruding portion on a plane has a gap with the orthographic projection of the first electrode on the plane, and the plane is perpendicular to the second direction.

20. The array substrate according to claim 1, wherein a minimum distance between the connection via and the second opening is D2, and D2 = y 2 + e 2 + s 2 + g 2 , y represents the fluctuation value of the second opening, h represents the fluctuation value of the connection via, s represents the alignment deviation of the second opening, and g represents the alignment deviation of the connection via.

21. The array substrate according to claim 20, wherein, The minimum distance D2 between the connection via and the second opening is 1.7 to 4.2 micrometers.

22. The array substrate according to any one of claims 1-21, wherein, The orthographic projection area of the first opening on the substrate is larger than the orthographic projection area of the second opening on the substrate.

23. The array substrate according to any one of claims 1-22, wherein, The first opening and the second opening communicate with each other, and the first opening and the second opening are arranged along the first direction.

24. A display panel, comprising the array substrate according to any one of claims 1-23.

25. A display device, comprising the display panel according to claim 24.

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