Array substrate and manufacturing method therefor, and display device

Abstract

An array substrate and a manufacturing method therefor, and a display device. The array substrate comprises a base substrate (30), first conductive parts (17), and second conductive parts (19). The orthographic projections of the second conductive parts (19) on the base substrate (30) at least partially overlap the orthographic projections of the first conductive parts (17) on the base substrate (30), and first overlapping areas are formed. The array substrate comprises an auxiliary layer (40). The auxiliary layer (40) is located between the first conductive parts (17) and the second conductive parts (19) in a direction perpendicular to the base substrate (30). The auxiliary layer (40) comprises a plurality of auxiliary parts (401), and the auxiliary parts (401) and the first conductive parts (17) are arranged in groups in one-to-one correspondence. The orthographic projections of the auxiliary parts (401) on the base substrate (30) at least partially overlap the first overlapping areas. The material of the auxiliary parts (401) is different from that of the first conductive parts (17), and the absolute value of the difference between the sheet resistance of the material of the auxiliary parts (401) and that of the first conductive parts (17) ranges from 0.02 to 0.04.

Description

Array substrate, manufacturing method thereof, and display device Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to an array substrate and a preparation method thereof, and a display device. Background Art

[0002] Liquid crystal displays (LCDs) are a common type of display. LCDs use two polarized materials with a liquid crystal solution (liquid crystal) between them. Applying a voltage across the two polarized materials causes the liquid crystal to deflect. The degree of deflection can be controlled by controlling the applied voltage. Currently, LCDs are being developed to be lightweight, thin, short, and compact.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present disclosure provide an array substrate, a method for manufacturing the same, and a display device.

[0006] In one aspect, embodiments of the present disclosure provide an array substrate. The array substrate includes a substrate, a first conductive portion located on one side of the substrate, and a second conductive portion located on a side of the first conductive portion away from the substrate; an orthographic projection of the second conductive portion on a plane containing the substrate at least partially overlaps with an orthographic projection of the first conductive portion on the plane containing the substrate, forming a first overlapping region;

[0007] The array substrate also includes an auxiliary layer, which is located between the first conductive part and the second conductive part in a direction perpendicular to the substrate. The auxiliary layer includes a plurality of auxiliary parts, and the auxiliary parts are arranged in groups corresponding to the first conductive parts one by one. The orthographic projection of the auxiliary part on the plane where the substrate is located at least partially overlaps with the first overlapping area; the material of the auxiliary part is different from the material of the first conductive part, and the absolute value of the difference between the square resistance of the material of the auxiliary part and the square resistance of the material of the first conductive part is 0.02 to 0.04.

[0008] In an exemplary embodiment, at least one of the first conductive portion and the auxiliary portion includes a transition metal element, and the transition metal element includes at least one of group IVB, group IB, and group IIB materials.

[0009] In an exemplary embodiment, at least a portion of a surface of the auxiliary portion on a side close to the substrate contacts at least a portion of a surface of the first conductive portion on a side away from the substrate.

[0010] In an exemplary embodiment, a ratio of the thickness of the auxiliary layer to the thickness of the first conductive portion is in a range of 0.003 to 0.03.

[0011] In an exemplary embodiment, the first conductive portion extends along a first direction and includes a first edge and a second edge disposed opposite to each other along a second direction, and the first direction intersects the second direction; the auxiliary portion includes a third edge and a fourth edge disposed opposite to each other along the second direction, the third edge being closer to the first edge than the fourth edge, and the fourth edge being closer to the second edge than the third edge;

[0012] There is a first distance along the second direction between the first edge and the third edge, and a second distance along the second direction between the second edge and the fourth edge, and the first distance and the second distance are both greater than or equal to 1.0 micrometer and less than or equal to 2.0 micrometers.

[0013] In an exemplary embodiment, the first conductive portion has a first side surface, the first side surface extends in a direction away from the substrate, and a first slope angle is formed between the first side surface and a plane where the substrate is located, and the first slope angle ranges from 40 degrees to 60 degrees;

[0014] The second conductive portion has a second side surface, the second side surface extends in a direction away from the substrate, and a second slope angle is formed between the second side surface and a plane where the substrate is located, and the second slope angle ranges from 40 degrees to 60 degrees;

[0015] The auxiliary portion has a third side surface, the third side surface extends in a direction away from the substrate, and a third slope angle is formed between the third side surface and a plane where the substrate is located, and the third slope angle ranges from 40 degrees to 60 degrees.

[0016] In an exemplary embodiment, in a plane perpendicular to the substrate, the array substrate further includes a first conductive layer and a second conductive layer sequentially located on one side of the substrate; the first conductive layer includes a plurality of gate lines extending along a first direction, and the second conductive layer includes a plurality of data lines extending along a second direction;

[0017] The portion where the orthographic projection of the gate line on the plane where the substrate is located overlaps with the orthographic projection of the data line on the plane where the substrate is located is the first conductive portion, and the portion where the orthographic projection of the data line on the plane where the substrate is located overlaps with the orthographic projection of the gate line on the plane where the substrate is located is the second conductive portion.

[0018] In an exemplary embodiment, the orthographic projection of the auxiliary portion on the plane where the substrate is located includes the orthographic projection of the first conductive portion on the plane where the substrate is located.

[0019] In an exemplary embodiment, a plurality of the auxiliary portions are arranged at intervals along the first direction.

[0020] In an exemplary embodiment, in a plane perpendicular to the substrate, the array substrate further includes a first conductive layer and a second conductive layer sequentially located on one side of the substrate; the first conductive layer includes a plurality of gate lines extending along a first direction, and the second conductive layer includes a plurality of data lines extending along a second direction;

[0021] Wherein, the gate line is the first conductive portion, and the data line is the second conductive portion.

[0022] In an exemplary embodiment, the auxiliary portion has a first outer edge in its orthographic projection on the plane where the substrate is located, the first conductive portion has a second outer edge in its orthographic projection on the plane where the substrate is located, and the first outer edge surrounds the second outer edge, and there is a gap between the first outer edge and the second outer edge.

[0023] In another aspect, an embodiment of the present disclosure provides a method for preparing an array substrate, comprising:

[0024] forming a first conductive portion on one side of the substrate;

[0025] forming an auxiliary layer on a side of the first conductive portion away from the substrate, the auxiliary layer comprising a plurality of auxiliary portions, and the auxiliary portions are arranged in groups corresponding to the first conductive portions;

[0026] A second conductive portion is formed on a side of the auxiliary layer away from the substrate, the orthographic projection of the first conductive portion on the plane where the substrate is located at least partially overlaps with the orthographic projection of the second conductive portion on the plane where the substrate is located, and a first overlapping area is formed; the orthographic projection of the auxiliary portion on the plane where the substrate is located at least partially overlaps with the first overlapping area; the material of the auxiliary portion is different from the material of the first conductive portion, and the absolute value of the difference between the square resistance of the material of the auxiliary portion and the square resistance of the material of the first conductive portion is 0.02 to 0.04.

[0027] In an exemplary embodiment, forming an auxiliary layer on a side of the first conductive portion away from the substrate includes:

[0028] forming a metal thin film on a side of the first conductive portion away from the substrate;

[0029] forming a second adhesive layer on a side of the metal film away from the substrate, wherein the material of the second adhesive layer includes positive photoresist;

[0030] A patterning process is performed on the second glue layer to form a second photoresist pattern, wherein the orthographic projection of the second photoresist pattern on the plane where the substrate is located includes the orthographic projection of the first conductive portion on the plane where the substrate is located.

[0031] In an exemplary embodiment, forming an auxiliary layer on a side of the first conductive portion away from the substrate includes:

[0032] forming a third glue layer on a side of the first conductive portion away from the substrate, wherein the material of the third glue layer includes a negative photoresist;

[0033] A patterning process is performed on the third glue layer to form a third photoresist pattern, wherein an orthographic projection of the third photoresist pattern on the plane where the substrate is located does not overlap with an orthographic projection of the first conductive portion on the plane where the substrate is located;

[0034] A metal film is formed on a side of the first conductive portion away from the substrate.

[0035] On the other hand, an embodiment of the present disclosure provides a display device, comprising the array substrate described in any of the aforementioned embodiments, or comprising an array substrate manufactured using the method for manufacturing the array substrate described in any of the aforementioned embodiments.

[0036] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0037] Summary of the Figures

[0038] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of one or more components in the accompanying drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0039] FIG1 is a partial cross-sectional schematic diagram of an array substrate;

[0040] FIG2 is a schematic front view of an array substrate according to an embodiment of the present disclosure;

[0041] FIG3 is a partial top view of an array substrate according to an embodiment of the present disclosure;

[0042] FIG3A is a first partial cross-sectional diagram of an array substrate according to an embodiment of the present disclosure;

[0043] FIG3B is a second partial cross-sectional schematic diagram of an array substrate according to an embodiment of the present disclosure;

[0044] FIG4 is a partial top view of an array substrate according to another embodiment of the present disclosure;

[0045] FIG4A is a partial cross-sectional schematic diagram 1 of an array substrate according to another embodiment of the present disclosure;

[0046] FIG4B is a second partial cross-sectional schematic diagram of an array substrate according to another embodiment of the present disclosure;

[0047] FIG5 is a partial top view of an array substrate after forming a first conductive layer pattern according to an embodiment of the present disclosure;

[0048] FIG5A is a first partial cross-sectional diagram of an array substrate after forming a first conductive layer pattern according to an embodiment of the present disclosure;

[0049] 5B is a second partial cross-sectional diagram of the array substrate after forming the first conductive layer pattern according to an embodiment of the present disclosure;

[0050] FIG6 is a partial top view of an array substrate after auxiliary layer patterns are formed according to an embodiment of the present disclosure;

[0051] FIG6A is a first partial cross-sectional diagram of an array substrate after auxiliary layer patterns are formed according to an embodiment of the present disclosure;

[0052] FIG6B is a second partial cross-sectional diagram of the array substrate after forming an auxiliary layer pattern according to an embodiment of the present disclosure;

[0053] FIG7 is a partial top view of an array substrate after a semiconductor layer pattern is formed according to an embodiment of the present disclosure;

[0054] FIG7A is a first partial cross-sectional diagram of an array substrate after a semiconductor layer pattern is formed according to an embodiment of the present disclosure;

[0055] 7B is a second partial cross-sectional diagram of the array substrate after semiconductor layer patterns are formed according to an embodiment of the present disclosure;

[0056] FIG8 is a partial top view of an array substrate after an initial pattern of a third insulating layer is formed in an embodiment of the present disclosure;

[0057] 8A is a partial cross-sectional schematic diagram 1 of an array substrate after an initial pattern of a third insulating layer is formed according to an embodiment of the present disclosure;

[0058] 8B is a second partial cross-sectional diagram of the array substrate after the initial pattern of the third insulating layer is formed according to an embodiment of the present disclosure;

[0059] FIG9 is a partial top view of an array substrate after forming a second conductive layer pattern according to an embodiment of the present disclosure;

[0060] FIG9A is a first partial cross-sectional diagram of an array substrate after forming a second conductive layer pattern according to an embodiment of the present disclosure;

[0061] 9B is a second partial cross-sectional diagram of the array substrate after forming a second conductive layer pattern according to an embodiment of the present disclosure;

[0062] FIG10 is a partial top view of an array substrate after a fourth insulating layer pattern is formed on the array substrate according to an embodiment of the present disclosure;

[0063] FIG10A is a first partial cross-sectional diagram of an array substrate after a fourth insulating layer pattern is formed according to an embodiment of the present disclosure;

[0064] 10B is a second partial cross-sectional diagram of the array substrate after forming a fourth insulating layer pattern according to an embodiment of the present disclosure;

[0065] FIG11 is a partial top view of an array substrate after a third conductive layer pattern is formed on the array substrate according to an embodiment of the present disclosure;

[0066] FIG11A is a first partial cross-sectional diagram of an array substrate after forming a third conductive layer pattern according to an embodiment of the present disclosure;

[0067] FIG11B is a second partial cross-sectional diagram of the array substrate after forming a third conductive layer pattern according to an embodiment of the present disclosure;

[0068] FIG12 is a partial top view of an array substrate after a fourth conductive layer pattern is formed on the array substrate according to an embodiment of the present disclosure;

[0069] FIG12A is a first partial cross-sectional diagram of an array substrate after a fourth conductive layer pattern is formed according to an embodiment of the present disclosure;

[0070] FIG12B is a second partial cross-sectional diagram of the array substrate after forming a fourth conductive layer pattern according to an embodiment of the present disclosure;

[0071] 13A to 13H are schematic diagrams showing a process of preparing auxiliary layer patterns on an array substrate according to an embodiment of the present disclosure;

[0072] 14A to 14D are schematic diagrams showing a process of preparing auxiliary layer patterns on an array substrate according to another embodiment of the present disclosure.

[0073] Figure 101-first conductive layer, 102-second conductive layer, 111-first conductive line, 112-second conductive line, 103-insulating layer; 10-pixel electrode, 10-1-connecting portion, 10-2-comb tooth portion, 20-transistor, 11-first insulating layer, 12-second insulating layer, 13-third insulating layer, 13-1-initial pattern of the third insulating layer, 14-fourth insulating layer, 15-fifth insulating layer, 16-gate, 17-first conductive portion, 17-1-first side, 18-active portion, 18-1-first region, 18-2-second region, 18-3-channel region, 181-first A region, 182-second region, 183-third region, 19-second conductive portion, 19-1-second side, 21-common electrode, GL-gate line, GL-1-first edge, GL-2-second edge, GL10-second outer edge, DL-data line; 30-substrate, 40-auxiliary layer, 401-auxiliary portion, 401-1-third side, 401-3-third edge, 401-4-fourth edge, 401a-first outer edge; 50-ultraviolet light, 60-first mask, 70-second mask, 121-first conductive film, 122-metal film, 131-first glue layer, 131-1-first photoresist pattern, 132-second glue layer, 132-2-second photoresist pattern, 133-third glue layer, 133-1-third photoresist pattern.

[0074] Details

[0075] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other in any way.

[0076] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0077] The ordinal numbers such as "first," "second," and "third" in this disclosure are provided to avoid confusion among constituent elements, and are not intended to limit the number. The "plurality" in this disclosure includes two or more.

[0078] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "center," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inner," and "outer," are used to illustrate the positional relationships of components with reference to the accompanying drawings. This is solely for the purpose of facilitating the description of this specification and simplifying the description. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and are therefore not to be construed as limiting this disclosure. The positional relationships of components may vary depending on the direction in which the components are described. Therefore, the terms and phrases are not limited to those described in the specification and may be appropriately replaced as appropriate.

[0079] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0080] In this disclosure, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.

[0081] In this disclosure, a transistor refers to a device comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0082] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in the present disclosure, "source electrode" and "drain electrode" may be interchanged.

[0083] In this disclosure, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus includes a state where the angle is greater than 85° and less than 95°.

[0084] In this disclosure, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0085] In the present disclosure, “about” and “approximately” refer to values ​​that are not strictly defined but allow for process and measurement errors.

[0086] The triangles, rectangles, trapezoids, pentagons or hexagons in the present disclosure are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0087] Figure 1 is a partial cross-sectional schematic diagram of an array substrate. As shown in Figure 1, the array substrate may include a first conductive layer 101 and a second conductive layer 102, each of which is stacked. The first conductive layer 101 may include a plurality of first conductive lines 111, and the second conductive layer 102 may include a plurality of second conductive lines 112. The array substrate may further include an insulating layer 103 located between the first conductive layer 101 and the second conductive layer 102. The material of the first conductive lines 111 typically contains copper. Since the growth of copper reduces the thickness of the insulating layer 103 between the first conductive layer 101 and the second conductive layer 102, when current flows between the first conductive lines 111 and the second conductive line 112, an electric field similar to a parallel plate capacitor is formed between the first conductive layer 101 and the second conductive layer 102. This formed electric field can break down the insulating layer 103 between the first conductive layer 101 and the second conductive layer 102, causing problems such as dark spots.

[0088] An embodiment of the present disclosure provides an array substrate, comprising a substrate, a first conductive portion located on one side of the substrate, and a second conductive portion located on a side of the first conductive portion away from the substrate; an orthographic projection of the second conductive portion on a plane where the substrate is located at least partially overlaps with an orthographic projection of the first conductive portion on the plane where the substrate is located, forming a first overlapping region;

[0089] The array substrate also includes an auxiliary layer, which is located between the first conductive part and the second conductive part in a direction perpendicular to the substrate. The auxiliary layer includes a plurality of auxiliary parts, and the auxiliary parts are arranged in groups corresponding to the first conductive parts one by one. The orthographic projection of the auxiliary part on the plane where the substrate is located at least partially overlaps with the first overlapping area; the material of the auxiliary part is different from the material of the first conductive part, and the absolute value of the difference between the square resistance of the material of the auxiliary part and the square resistance of the material of the first conductive part is 0.02 to 0.04.

[0090] The array substrate provided by the embodiment of the present disclosure has an auxiliary layer provided between the first conductive part and the second conductive part. The auxiliary layer can block the electric field formed between the first conductive part and the second conductive part, thereby avoiding problems such as dark spots on the array substrate and improving the reliability of the array substrate.

[0091] Figure 2 is a schematic front view of an array substrate according to an embodiment of the present disclosure. As shown in Figure 2, the array substrate may include a display area AA and a border area BB located on at least one side of the display area AA. The border area BB may include a first border area B1 located on one side of the display area AA and a second border area B2 located on the remaining sides of the display area AA. For example, the first border area B1 may include the lower border of the array substrate, and the second border area B2 may include the upper border, left border, and right border of the array substrate. In the embodiment of the present disclosure, the border area may also be referred to as a non-display area.

[0092] In one exemplary embodiment, as shown in FIG2 , the display area AA may include: a plurality of data lines DL and a plurality of gate lines GL disposed on a substrate. The plurality of gate lines GL may extend along a first direction X and be sequentially arranged along a second direction Y different from the first direction X. The plurality of data lines DL may extend along the second direction Y and be sequentially arranged along the first direction X. The first direction X and the second direction Y may intersect; for example, the first direction X may be perpendicular to the second direction Y. The plurality of data lines DL and the plurality of gate lines GL may be located in different film layers; for example, the plurality of data lines DL may be located on a side of the plurality of gate lines GL away from the substrate.

[0093] In an exemplary embodiment, as shown in FIG2 , a plurality of data lines DL and a plurality of gate lines GL may intersect to form a plurality of sub-pixel areas. The area defined by the intersection of adjacent data lines DL and adjacent gate lines GL may be a sub-pixel area. A sub-pixel may be provided in a corresponding sub-pixel area. The sub-pixel area may include an opening area and a non-opening area surrounding the opening area. The non-opening area may be an area blocked by the black matrix of the opposing substrate of the array substrate, and the opening area may be an area not blocked by the black matrix of the opposing substrate. Adjacent gate lines GL and data lines DL may both be located within the non-opening area. The array substrate of the disclosed embodiment may be used to implement a display function, and the opening area of ​​each sub-pixel area may be configured for display. The non-opening area may surround the opening area and not display. However, the disclosed embodiment is not limited to this. In some examples, the array substrate may be used to implement other functions.

[0094] In one exemplary embodiment, the display area AA may include: a plurality of pixel units disposed on a substrate. At least one pixel unit may include: three sub-pixels (e.g., a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged sequentially along a first direction X). The three sub-pixels of the pixel unit may be, for example, a blue sub-pixel, a red sub-pixel, and a green sub-pixel, and the three sub-pixels may be arranged sequentially in the order of blue sub-pixel, red sub-pixel, and green sub-pixel. As shown in FIG2 , at least one sub-pixel may include: a pixel electrode 10 and a common electrode (not shown in FIG2 ), and the orthographic projections of the pixel electrode 10 and the common electrode of the sub-pixel on the substrate may partially overlap. The common electrode of the plurality of sub-pixels in the display area AA may be an integral structure. For example, the common electrode may be located on a side of the pixel electrode 10 away from the substrate. The sub-pixel may also include a transistor 20. The transistor 20 may be located adjacent to the intersection of a data line DL and a gate line GL. The transistor 20 may include a gate, a first electrode, and a second electrode. The gate may be electrically connected to the gate line GL, the first electrode of the transistor 20 may be electrically connected to the data line DL, and the second electrode may be electrically connected to the pixel electrode 10 of a sub-pixel. The transistor 20 may be configured to provide a data signal transmitted by the data line DL to the pixel electrode 10 of the sub-pixel under the control of the gate line GL.

[0095] In an exemplary embodiment, the second border area B2 may include at least a gate drive circuit (e.g., including a plurality of cascaded shift registers), and the plurality of shift registers may be electrically connected to the plurality of gate lines GL in the display area AA. The gate drive circuit may further include a transistor. The structure of the transistor located in the second border area B2 may be the same as or different from the structure of the transistor located in the display area AA.

[0096] Figure 3 is a partial top view of an array substrate according to an embodiment of the present disclosure, Figure 3A is a partial cross-sectional schematic diagram of the array substrate according to an embodiment of the present disclosure, and Figure 3B is a partial cross-sectional schematic diagram of the array substrate according to an embodiment of the present disclosure. Figure 3A is a cross-sectional schematic diagram at the position marked AA in Figure 3, and Figure 3B is a cross-sectional schematic diagram at the position marked BB in Figure 3. As shown in Figure 3, only two pixel units are illustrated. A pixel unit may include three sub-pixels, and the three sub-pixels may be a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged in sequence along a first direction X. For example, the first sub-pixel may be a blue sub-pixel, the second sub-pixel may be a red sub-pixel, and the third sub-pixel may be a green sub-pixel. In the embodiment of the present disclosure, i may be a positive integer greater than or equal to 1, and j may be a positive integer greater than or equal to 2.

[0097] In the embodiment of the present disclosure, the direction perpendicular to the array substrate is defined as a third direction Z, which can also be referred to as the thickness direction of the array substrate. As shown in Figures 3A and 3B, within a plane perpendicular to the array substrate, the array substrate can include a substrate 30 and a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially arranged on one side of the substrate 30. The array substrate can also include a first insulating layer 11 located between the substrate 30 and the first conductive layer, a second insulating layer 12 located between the first conductive layer and the semiconductor layer, a third insulating layer 13 located between the semiconductor layer and the second conductive layer, a fourth insulating layer 14 located between the second conductive layer and the third conductive layer, and a fifth insulating layer 15 located between the third conductive layer and the fourth conductive layer. In the embodiment of the present disclosure, the first insulating layer can also be referred to as a buffer layer, the second insulating layer can also be referred to as a gate insulating (GI) layer, the third insulating layer can also be referred to as a first passivation (PVX1) layer, the fourth insulating layer can also be referred to as a planarization (PLN) layer, and the fifth insulating layer can also be referred to as a second passivation (PVX2) layer.

[0098] As shown in Figures 3A and 3B, the first conductive layer may include a plurality of gate lines GL. The plurality of gate lines GL may extend along the first direction X and be arranged at intervals along the second direction Y. The gate lines GL may be in the form of a straight line or a broken line extending along the first direction X. As shown in Figure 3A, the first conductive layer may further include a plurality of gates 16 and a plurality of first conductive portions 17. The plurality of gates 16 and the plurality of first conductive portions 17 may be an integral structure interconnected with the gate lines GL. For example, a portion of the gate line GL may serve as the gate 16, and a portion of the gate line GL may serve as the first conductive portion 17.

[0099] As shown in Figures 3A and 3B, the semiconductor layer may include an active portion 18 of a plurality of transistors 20. The active portion 18 may include a channel region 18-3, a first region 18-1 and a second region 18-2 located on opposite sides of the channel region 18-3. For example, in the process of preparing the array substrate, a portion of the active portion 18 may be subjected to a conductor treatment so that portions of the active portion 18 form the first region 18-1 and the second region 18-2, respectively. The first region 18-1 of the active portion 18 may be used as the first electrode of the transistor, and the second region 18-2 of the active portion 18 may be used as the second electrode of the transistor. By conducting a conductor treatment on a portion of the active portion to form the first electrode and the second electrode of the transistor, the area of ​​the transistor gate may be reduced, thereby avoiding the influence of the gate on the aperture ratio of the display area, which is beneficial to improving the aperture ratio of the display area.

[0100] As shown in FIG3 , the second conductive layer may include a plurality of data lines DL. The plurality of data lines DL may extend along the second direction Y and be spaced apart along the first direction X. The data lines DL may be in the form of straight lines or zigzag lines extending along the second direction Y. As shown in FIG3A and FIG3B , the second conductive layer may further include a plurality of second conductive portions 19 . The second conductive portions 19 and the data lines DL may be an integral structure connected to each other. For example, portions of the data lines DL may serve as the second conductive portions 19 .

[0101] As shown in Figures 3A and 3B, the orthographic projection of the first conductive portion 17 on the plane of the substrate 30 and the orthographic projection of the second conductive portion 19 on the plane of the substrate 30 may at least partially overlap. In the embodiment of the present disclosure, the region formed by this at least partial overlap may also be referred to as a first overlapping region. The array substrate may further include an auxiliary layer 40. The auxiliary layer 40 may be located between the first conductive layer and the second insulating layer 12. The auxiliary layer 40 may include a plurality of auxiliary portions 401. The plurality of auxiliary portions 401 may extend along the first direction X and be arranged at intervals along the second direction Y. The plurality of auxiliary portions 401 may be provided in a one-to-one correspondence with the plurality of gate lines GL. The orthographic projection of the auxiliary portion 401 on the plane of the substrate 30 may include the orthographic projection of the gate line GL on the plane of the substrate 30, and the orthographic projection area of ​​the auxiliary portion 401 on the plane of the substrate 30 may be greater than the orthographic projection area of ​​the gate line GL on the plane of the substrate 30. The auxiliary portion 401 may be in the shape of a straight line or a broken line extending along the first direction X.

[0102] The orthographic projection of the auxiliary portion 401 on the plane of the substrate 30 may include the orthographic projection of the first conductive portion 17 on the plane of the substrate 30. The auxiliary portion 401 can block the electric field formed between the first conductive portion 17 and the second conductive portion 19, thereby preventing problems such as dark spots. For example, the orthographic projection of the gate line GL on the plane of the substrate 30 and the orthographic projection of the data line DL on the plane of the substrate 30 overlap. The portion of the gate line GL located in the overlapping region is the first conductive portion 17, and the portion of the data line DL located in the overlapping region is the second conductive portion 19.

[0103] As shown in Figure 3A, the third conductive layer may include a pixel electrode 10, and the fourth conductive layer may include a common electrode 21. The orthographic projection of the common electrode 21 on the plane where the substrate 30 is located may at least partially overlap with the orthographic projection of the pixel electrode 10 on the plane where the substrate 30 is located. In the embodiment of the present disclosure, the pixel electrode may also be referred to as the first electrode of a sub-pixel, and the common electrode may also be referred to as the second electrode of a sub-pixel. Alternatively, the pixel electrode may also be referred to as the second electrode of a sub-pixel, and the common electrode may also be referred to as the first electrode of a sub-pixel.

[0104] In an exemplary embodiment, the auxiliary layer 40 may be made of a metal material, such as any one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). Alternatively, the auxiliary layer 40 may be made of an alloy of metal materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), such as aluminum-neodymium alloy (AlNd), molybdenum-niobium alloy (MoNb), or molybdenum-nickel-titanium alloy (MoNiTi). The auxiliary layer may be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, Mo / Nb / Cu, MoNiTi / Cu, MoNb / Cu / MoNiTi, or MoNiTi / Cu / MoNiTi.

[0105] In one exemplary embodiment, the auxiliary layer 40 may have a thickness ranging from 10 nm to 100 nm.

[0106] In an exemplary embodiment, a ratio of the thickness of the auxiliary layer 40 to the thickness of the first conductive portion 17 may be in a range of 0.003 to 0.03.

[0107] In an exemplary embodiment, the absolute value of the difference between the sheet resistance of the material of the auxiliary portion 401 and the sheet resistance of the material of the first conductive portion 17 can be 0.02 to 0.04. For example, the sheet resistance of the material of the first conductive portion 17 can be 0.07 Ω / □, or the sheet resistance of the material of the first conductive portion 17 can be 0.075 Ω / □. For example, the sheet resistance of the material of the auxiliary portion 401 can be 0.1 Ω / □.

[0108] In an exemplary embodiment, at least one of the first conductive portion 17 and the auxiliary portion 401 includes a transition metal element, and the transition metal element includes at least one of Group IVB, Group IB, and Group IIB materials. The transition metal element may include at least one of titanium, zirconium, and hafnium in Group IVB materials, the transition metal element may include at least one of copper, silver, and gold in Group IB materials, and the transition metal element may include at least one of cadmium, mercury, and zinc in Group IIB materials.

[0109] In an exemplary embodiment, the substrate 30 may be a transparent substrate. For example, the substrate 30 may be a rigid substrate or a flexible substrate. For example, the material of the rigid substrate may include, but is not limited to, one or more of glass and quartz. The material of the flexible substrate may include, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. However, the present disclosure is not limited to this.

[0110] In an exemplary embodiment, the materials of the first conductive layer, the second conductive layer, and the third conductive layer can be metal materials, such as any one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). Alternatively, the materials of the first conductive layer, the second conductive layer, and the third conductive layer can be alloy materials of metal materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), such as aluminum-neodymium alloy (AlNd), molybdenum-niobium alloy (MoNb), or molybdenum-nickel-titanium alloy (MoNiTi). The first conductive layer, the second conductive layer, and the third conductive layer can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, Mo / Nb / Cu, MoNiTi / Cu, MoNb / Cu / MoNiTi, or MoNiTi / Cu / MoNiTi, etc.

[0111] In one exemplary embodiment, the fourth conductive layer may be made of a transparent conductive oxide material, which may include indium tin oxide (ITO) or indium zinc oxide (IZO). For example, the fourth conductive layer may be a single-layer structure or a multi-layer composite structure, such as ITO / Al / ITO.

[0112] In an exemplary embodiment, the first insulating layer 11, the second insulating layer 12, the third insulating layer 13 and the fifth insulating layer 15 may be made of inorganic materials. For example, silicon oxynitride (SiO x N y ) or silicon nitride (SiN x ) or silicon oxide (SiO xThe first insulating layer 11, the second insulating layer 12, the third insulating layer 13 and the fifth insulating layer 15 can be a single layer or a multi-layer or composite layer structure.

[0113] In one exemplary embodiment, the fourth insulating layer 14 can be made of an organic material. Examples of such organic materials include any one or more of epoxy resin, phenolic resin, urea-formaldehyde resin, melamine-formaldehyde resin, furan resin, silicone resin, polyester resin, polyamide resin, acrylic resin, polyurethane, vinyl resin, hydrocarbon resin, and polyether resin. The fourth insulating layer 14 can be a single layer, a multilayer structure, or a composite layer structure. In the disclosed embodiment, providing an organic insulating layer can reduce crosstalk from the gate to the common electrode.

[0114] In an exemplary embodiment, the active portion 18 may include two or more sub-active layers. For example, the active portion may include two or three sub-active layers. The materials of the two or more sub-active layers may be the same or different.

[0115] In one exemplary embodiment, the material of the active portion 18 may include one or more of indium gallium zinc oxide (IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), indium gallium zinc tin oxide (IGZTO), indium gallium zinc Y oxide (IGZYO, where Y represents doped tin). In one example, the material of the semiconductor layer may be various materials such as amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, and polythiophene. The array substrate provided in the embodiments of the present disclosure is suitable for transistors manufactured using oxide technology, silicon technology, and organic technology.

[0116] In one exemplary embodiment, the semiconductor layer may have a thickness ranging from 300 angstroms to 800 angstroms.

[0117] Figure 4 is a partial top view of an array substrate according to another embodiment of the present disclosure. Figure 4A is a partial cross-sectional schematic diagram (I) of the array substrate according to another embodiment of the present disclosure. Figure 4B is a partial cross-sectional schematic diagram (II) of the array substrate according to another embodiment of the present disclosure. Figure 4A is a cross-sectional schematic diagram taken at CC in Figure 4 , and Figure 4B is a cross-sectional schematic diagram taken at DD in Figure 4 . As shown in Figures 4 , 4A, and 4B, in a plane perpendicular to the array substrate, the array substrate may include a substrate 30 and a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on one side of the substrate 30. The array substrate may further include a first insulating layer 11 located between the substrate 30 and the first conductive layer, a second insulating layer 12 located between the first conductive layer and the semiconductor layer, a third insulating layer 13 located between the semiconductor layer and the second conductive layer, a fourth insulating layer 14 located between the second and third conductive layers, and a fifth insulating layer 15 located between the third and fourth conductive layers. The first conductive layer may include a plurality of gate lines GL, a plurality of gate electrodes 16, and a plurality of first conductive portions 17. The semiconductor layer may include active portions 18 of a plurality of transistors 20. The active portion 18 may include a channel region 18 - 3 , a first region 18 - 1 and a second region 18 - 2 located on opposite sides of the channel region 18 - 3 . The second conductive layer may include a plurality of data lines DL and a plurality of second conductive portions 19 .

[0118] The array substrate may further include an auxiliary layer 40, which may be located between the first conductive layer and the second insulating layer 12. The auxiliary layer 40 may include a plurality of auxiliary portions 401. The plurality of auxiliary portions 401 may be block-shaped, for example, rectangular or hexagonal. The plurality of auxiliary portions 401 may be arranged in a one-to-one correspondence with the plurality of first conductive portions 17 and the plurality of second conductive portions 19. In the second direction Y, the orthographic projection of the auxiliary portion 401 on the plane of the substrate 30 may include the orthographic projection of the first conductive portion 17 on the plane of the substrate 30. The auxiliary portion 401 may protect the edges of the first conductive portion 17, preventing the first conductive portion 17 from forming an electric field with the second conductive portion 19 in the edge region, thereby preventing problems such as dark spots.

[0119] The following is an exemplary description of the preparation process of the array substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the array substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0120] The preparation process of the array substrate may include the following steps:

[0121] (11) Forming a first conductive layer pattern. Forming the first conductive layer pattern may include: sequentially depositing a first insulating film and a first conductive film on one side of the substrate, and patterning the first conductive film through a patterning process to form a first insulating layer 11 located on one side of the substrate and a first conductive layer pattern located on the side of the first insulating layer 11 away from the substrate. The first conductive layer may include a gate line GL, a gate 16 of a transistor, and a first conductive portion 17, as shown in FIG5 , FIG5A , and FIG5B . FIG5 is a partial top view schematic diagram of the array substrate after forming the first conductive layer pattern, FIG5A is a partial cross-sectional schematic diagram of the portion marked AA in FIG5 , and FIG5B is a partial cross-sectional schematic diagram of the portion marked BB in FIG5 . In FIG5B , the first conductive portion 17 is not pattern-filled to facilitate identification of the first slope angle.

[0122] As shown in FIG. 5 , the gate line GL, the gate 16 of the transistor, and the first conductive portion 17 may be an integrated structure connected to each other.

[0123] As shown in FIG5B , the first conductive portion 17 has a first side surface 17 - 1 extending away from the substrate 30 . A first slope angle α1 is formed between the first side surface 17 - 1 and the plane where the substrate 30 is located. The first slope angle α1 may range from 40 degrees to 60 degrees.

[0124] (12) Forming an auxiliary layer pattern. Forming the auxiliary layer pattern may include: depositing a metal film on one side of the substrate on which the aforementioned pattern is formed, and patterning the metal film through a patterning process to form an auxiliary layer pattern located on the side of the first conductive layer away from the substrate. The auxiliary layer 40 may include a plurality of auxiliary portions 401, as shown in FIG6 , FIG6A , and FIG6B . FIG6 is a partial top view schematic diagram of the array substrate after the auxiliary layer pattern is formed, FIG6A is a partial cross-sectional schematic diagram of the portion marked AA in FIG6 , and FIG6B is a partial cross-sectional schematic diagram of the portion marked BB in FIG6 . In FIG6B , the auxiliary portion 401 is not pattern-filled to facilitate identification of the third slope angle.

[0125] As shown in FIG6 , the auxiliary portion 401 may be in the shape of a line extending along the first direction X. The auxiliary portion 401 and the gate line GL may be provided in a one-to-one correspondence. The orthographic projection of the auxiliary portion 401 on the plane where the substrate is located may include the orthographic projection of the gate line GL on the plane where the substrate is located, and the orthographic projection area of ​​the auxiliary portion 401 on the plane where the substrate is located may be greater than the orthographic projection area of ​​the gate line GL on the plane where the substrate is located.

[0126] As shown in FIG6 , the gate line GL may have a first edge GL-1 and a second edge GL-2 disposed opposite each other along the second direction Y. The auxiliary portion 401 may have a third edge 401-3 and a fourth edge 401-4 disposed opposite each other along the second direction Y. The third edge 401-3 is closer to the first edge GL-1 than the fourth edge 401-4, and the fourth edge 401-4 is closer to the second edge GL-2 than the third edge 401-3. A first distance L1 is defined along the second direction Y between the first edge GL-1 and the third edge 401-3, and a second distance L2 is defined along the second direction Y between the second edge GL-2 and the fourth edge 401-4. The first distance L1 and the second distance L2 are both greater than or equal to 1.0 micrometers and less than or equal to 2.0 micrometers. For example, the first distance L1 may be equal to the second distance L2. By defining the first distance L1 and the second distance L2, the auxiliary portion 401 can block the entire edge of the gate line GL, preventing the formation of an electric field in the area where the gate line GL overlaps with the data line, thereby preventing problems such as dark spots.

[0127] In an exemplary embodiment, the gate line GL is also the first conductive portion 17 .

[0128] In one exemplary embodiment, the auxiliary portion 401 has a first outer edge 401a when projected onto the substrate, and the first conductive portion 17 has a second outer edge GL10 when projected onto the substrate. The first outer edge 401a surrounds the second outer edge GL10, and a gap exists between the first outer edge 401a and the second outer edge GL10. This gap can be greater than zero nanometers and less than or equal to 20 nanometers.

[0129] In an exemplary embodiment, as shown in FIG6B , the auxiliary portion 401 has a third side surface 401 - 1 , which extends away from the substrate 30 , and has a third slope angle α3 with the plane of the substrate 30 , which may range from 40 degrees to 60 degrees.

[0130] (13) Forming a semiconductor layer pattern. Forming a semiconductor layer pattern may include: sequentially depositing a second insulating film and a semiconductor film on one side of the substrate on which the aforementioned pattern is formed, and patterning the semiconductor film through a patterning process to form a second insulating layer 12 located on the side of the auxiliary layer away from the substrate, and a semiconductor layer pattern located on the side of the second insulating layer 12 away from the substrate. The semiconductor layer may include an active portion 18 of a transistor, as shown in FIG7 , FIG7A , and FIG7B . FIG7 is a partial top view schematic diagram of the array substrate after the semiconductor layer pattern is formed, FIG7A is a partial cross-sectional schematic diagram at the position marked AA in FIG7 , and FIG7B is a partial cross-sectional schematic diagram at the position marked BB in FIG7 .

[0131] As shown in FIG7 , the active portion 18 may include a first region 181, a second region 182, and a third region 183 that are connected. The second region 182 may be located between the first region 181 and the third region 183. The orthographic projections of the first region 181 and the third region 183 on the substrate plane may be rectangular, while the orthographic projection of the second region 182 on the substrate plane may be a strip. The orthographic projection of the active portion 18 on the substrate plane may partially overlap with the orthographic projection of the gate line GL on the substrate plane. The overlapping portion of the gate line GL may serve as the gate of the transistor.

[0132] In one exemplary embodiment, forming the semiconductor layer pattern may further include partially conducting the active portion 18 so that portions of the active portion 18 form a first region 18-1 and a second region 18-2, respectively. The first region 18-1 of the active portion 18 may function as a first electrode of a transistor, and the second region 18-2 of the active portion 18 may function as a second electrode of the transistor. The first region 18-1 is configured to connect to a subsequently formed data line, and the second region 18-2 is configured to connect to a subsequently formed pixel electrode.

[0133] (14) Forming an initial pattern of the third insulating layer. Forming the initial pattern of the third insulating layer may include: depositing a third insulating film on one side of the substrate on which the aforementioned pattern is formed, and patterning the third insulating film through a patterning process to form an initial pattern 13-1 of the third insulating layer located on the side of the semiconductor layer away from the substrate, as shown in FIG8 , FIG8A , and FIG8B . FIG8 is a partial top view schematic diagram of the array substrate after the initial pattern of the third insulating layer is formed, FIG8A is a partial cross-sectional schematic diagram of the portion marked AA in FIG8 , and FIG8B is a partial cross-sectional schematic diagram of the portion marked BB in FIG8 .

[0134] As shown in Figure 8, the third insulation layer initial pattern 13-1 can have multiple first vias K1, the third insulation film located in the first vias K1 is etched away, and a portion of the surface of the active part 18 away from the substrate is exposed. The first vias K1 are configured so that the subsequently formed data lines can be connected to the first area 18-1 of the active part 18 through the vias.

[0135] (15) Forming a second conductive layer pattern. Forming the second conductive layer pattern may include: depositing a second conductive film on one side of the substrate on which the aforementioned pattern is formed, and patterning the second conductive film through a patterning process to form a second conductive layer pattern located on the side of the third insulating layer initial pattern 13-1 away from the substrate. The second conductive layer may include a data line DL and a second conductive portion 19, as shown in Figures 9, 9A, and 9B. Figure 9 is a partial top view schematic diagram of the array substrate after the second conductive layer pattern is formed, Figure 9A is a partial cross-sectional schematic diagram at the position marked AA in Figure 9, and Figure 9B is a partial cross-sectional schematic diagram at the position marked BB in Figure 9. In Figure 9A, the second conductive portion 19 is not pattern-filled to facilitate identification of the second slope angle.

[0136] 9 , the data line DL may be in a linear shape extending along the second direction Y. The orthographic projection of the data line DL on the substrate plane may include the orthographic projection of the first via K1 on the substrate plane, and the data line DL may be connected to the first region 18 - 1 of the active portion 18 via the first via K1 .

[0137] In an exemplary embodiment, as shown in FIG9A , the second conductive portion 19 has a second side surface 19 - 1 , which extends away from the substrate 30 , and has a second slope angle α2 between the second side surface 19 - 1 and the plane where the substrate 30 is located. The second slope angle α2 can range from 40 degrees to 60 degrees.

[0138] (16) Forming a fourth insulating layer pattern. Forming the fourth insulating layer pattern may include: depositing a fourth insulating film on one side of the substrate on which the aforementioned pattern is formed, and patterning the fourth insulating film through a patterning process to form a fourth insulating layer pattern located on the side of the second conductive layer away from the substrate and a third insulating layer pattern located on the side of the semiconductor layer away from the substrate. The fourth insulating layer 14 may have a plurality of second vias K2, as shown in Figures 10, 10A, and 10B. Figure 10 is a partial top view schematic diagram of the array substrate after the fourth insulating layer pattern is formed, Figure 10A is a partial cross-sectional schematic diagram of the portion marked AA in Figure 10, and Figure 10B is a partial cross-sectional schematic diagram of the portion marked BB in Figure 10.

[0139] As shown in FIG10A , the fourth insulating film and the third insulating film located in the second via hole K2 are both etched away, and a portion of the surface of the active portion 18 away from the substrate is exposed. The second via hole K2 is configured so that a subsequently formed pixel electrode can be connected to the active portion through the via hole.

[0140] (17) Forming a third conductive layer pattern. Forming the third conductive layer pattern may include: depositing a third conductive film on one side of the substrate on which the aforementioned pattern is formed, and patterning the third conductive film through a patterning process to form a third conductive layer pattern located on a side of the fourth insulating layer away from the substrate. The third conductive layer may include a pixel electrode 10, as shown in FIG11 , FIG11A , and FIG11B . FIG11 is a partial top view schematic diagram of the array substrate after the third conductive layer pattern is formed, FIG11A is a partial cross-sectional schematic diagram of the portion marked AA in FIG11 , and FIG11B is a partial cross-sectional schematic diagram of the portion marked BB in FIG11 .

[0141] As shown in Figure 11, the pixel electrode 10 may include a connecting portion 10-1 and a plurality of comb-tooth portions 10-2. The orthographic projection of the connecting portion 10-1 on the plane where the substrate is located may be rectangular, and the comb-tooth portion 10-2 may be in the shape of an elongated strip extending along the first direction X. The comb-tooth portion 10-2 has a first end and a second end disposed opposite to each other. The first end of the comb-tooth portion 10-2 may be connected to the connecting portion 10-1, and the second end of the comb-tooth portion 10-2 may extend along the first direction X. The plurality of comb-tooth portions 10-2 may be arranged at intervals along the second direction Y. For example, they may be arranged at equal intervals along the second direction Y.

[0142] As shown in FIG11 , the orthographic projection of the connection portion 10 - 1 on the plane where the substrate is located may include the orthographic projection of the second via K2 on the plane where the substrate is located, and the connection portion 10 - 1 may be connected to the active portion 18 via the second via K2 .

[0143] (18) Forming a fourth conductive layer pattern. Forming the fourth conductive layer pattern may include: sequentially depositing a fifth insulating film and a fourth conductive film on one side of the substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film through a patterning process to form a fifth insulating layer pattern located on the side of the third conductive layer away from the substrate, and a fourth conductive layer pattern located on the side of the fifth insulating layer 15 away from the substrate. The fourth conductive layer may include a common electrode 21, as shown in Figures 12, 12A, and 12B. Figure 12 is a partial top view schematic diagram of the array substrate after the fourth conductive layer pattern is formed, Figure 12A is a partial cross-sectional schematic diagram at the position marked AA in Figure 12, and Figure 12B is a partial cross-sectional schematic diagram at the position marked BB in Figure 12.

[0144] As shown in FIG12 , the orthographic projection of the common electrode 21 on the plane where the substrate is located may be a rectangle, and the orthographic projection of the common electrode 21 on the plane where the substrate is located may partially overlap with the orthographic projection of the pixel electrode 10 on the plane where the substrate is located.

[0145] In some exemplary embodiments, preparing an auxiliary layer pattern on an array substrate may include the following steps:

[0146] (21) A first conductive film 121 is formed on one side of the substrate 30, as shown in FIG13A.

[0147] (22) A first adhesive layer 131 is formed on the side of the first conductive film 121 away from the substrate 30, as shown in FIG13B.

[0148] (23) The first mask 60 is used to expose the first glue layer 131 to ultraviolet light 50 to form a first photoresist pattern 131-1, as shown in FIG13B and FIG13C.

[0149] (24) An etching process is performed to form the first conductive film into the first conductive portion 17, as shown in FIG13D.

[0150] (25) A metal film 122 is formed on the side of the first conductive portion 17 away from the substrate 30, as shown in FIG13E.

[0151] (26) A second adhesive layer 132 is formed on the side of the metal film 122 away from the substrate 30, as shown in FIG13F.

[0152] (27) The second mask 70 is used to expose the second glue layer 132 with ultraviolet light 50 to form a second photoresist pattern 132-2, as shown in FIG. 13F and FIG. 13G.

[0153] (28) An etching process is used to form an auxiliary layer 40 from the metal thin film, as shown in FIG13H . The orthographic projection of the auxiliary layer 40 on the plane where the substrate 30 is located may include the orthographic projection of the first conductive portion 17 on the plane where the substrate 30 is located, thereby preventing the formation of an electric field between the first conductive portion and the subsequently formed second conductive portion, thereby preventing the occurrence of problems such as dark spots.

[0154] In an exemplary embodiment, the adhesive materials of the first adhesive layer 131 and the second adhesive layer 132 may include photosensitive resin, additives, solvents, and the like.

[0155] In some exemplary embodiments, preparing an auxiliary layer pattern on an array substrate may include the following steps:

[0156] (31) A first conductive portion 17 is formed on one side of the substrate 30 , and reference may be made to the aforementioned embodiment.

[0157] (32) A third adhesive layer 133 is formed on the side of the first conductive portion 17 away from the substrate 30, as shown in FIG14A.

[0158] (33) Ultraviolet light 50 is used to irradiate the third adhesive layer 133 from the side of the substrate 30 away from the first conductive portion 17, so that a third photoresist pattern 133-1 is formed on the third adhesive layer 133, as shown in Figures 14A and 14B. The third photoresist pattern 133-1 exposes the surface of the first conductive portion 17 away from the substrate 30.

[0159] (34) A metal film 122 is formed on the side of the first conductive portion 17 away from the substrate 30, as shown in FIG14C.

[0160] (35) An etching process is used to form an auxiliary layer 40 from the metal thin film, as shown in FIG14D . The orthographic projection of the auxiliary layer 40 on the plane where the substrate 30 is located may include the orthographic projection of the first conductive portion 17 on the plane where the substrate 30 is located, thereby preventing the formation of an electric field between the first conductive portion and the subsequently formed second conductive portion, thereby preventing the occurrence of problems such as dark spots.

[0161] The present disclosure provides a method for preparing an array substrate, comprising:

[0162] forming a first conductive portion on one side of the substrate;

[0163] forming an auxiliary layer on a side of the first conductive portion away from the substrate, the auxiliary layer comprising a plurality of auxiliary portions, and the auxiliary portions are arranged in groups corresponding to the first conductive portions;

[0164] A second conductive portion is formed on a side of the auxiliary layer away from the substrate, the orthographic projection of the first conductive portion on the plane where the substrate is located at least partially overlaps with the orthographic projection of the second conductive portion on the plane where the substrate is located, and a first overlapping area is formed; the orthographic projection of the auxiliary portion on the plane where the substrate is located at least partially overlaps with the first overlapping area; the material of the auxiliary portion is different from the material of the first conductive portion, and the absolute value of the difference between the square resistance of the material of the auxiliary portion and the square resistance of the material of the first conductive portion is 0.02 to 0.04.

[0165] In some exemplary embodiments, forming an auxiliary layer on a side of the first conductive portion away from the substrate includes:

[0166] forming a metal thin film on a side of the first conductive portion away from the substrate;

[0167] forming a second adhesive layer on a side of the metal film away from the substrate, wherein the material of the second adhesive layer includes positive photoresist;

[0168] A patterning process is performed on the second glue layer to form a second photoresist pattern, wherein the orthographic projection of the second photoresist pattern on the plane where the substrate is located includes the orthographic projection of the first conductive portion on the plane where the substrate is located.

[0169] In some exemplary embodiments, forming an auxiliary layer on a side of the first conductive portion away from the substrate includes:

[0170] forming a third glue layer on a side of the first conductive portion away from the substrate, wherein the material of the third glue layer includes a negative photoresist;

[0171] A patterning process is performed on the third glue layer to form a third photoresist pattern, wherein an orthographic projection of the third photoresist pattern on the plane where the substrate is located does not overlap with an orthographic projection of the first conductive portion on the plane where the substrate is located;

[0172] A metal film is formed on a side of the first conductive portion away from the substrate.

[0173] It can be seen from the structure and preparation process of the array substrate in the aforementioned embodiment that the array substrate of the exemplary embodiment of the present disclosure, by setting an auxiliary layer between the first conductive part and the second conductive part, the auxiliary layer can block the formation of an electric field between the first conductive part and the second conductive part, thereby solving the problems of dark spots in the display of the existing array substrate and improving the reliability of the array substrate.

[0174] The present disclosure also provides a display device. The display device includes the array substrate described in any of the preceding embodiments. The display device can be any product or component with a display function, such as a liquid crystal panel, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. The present disclosure is not limited thereto.

[0175] Although the embodiments disclosed herein are as described above, the contents described are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. It should be noted that the above embodiments or implementations are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to the contents specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the implementations without departing from the scope of the present disclosure.

Claims

1. An array substrate, comprising a substrate, a first conductive portion located on one side of the substrate, and a second conductive portion located on the side of the first conductive portion away from the substrate; a positive projection of the second conductive portion on a plane where the substrate is located overlaps at least partially with a positive projection of the first conductive portion on the plane where the substrate is located, and a first overlapping region is formed; The array substrate further includes an auxiliary layer. In a direction perpendicular to the substrate, the auxiliary layer is located between the first conductive portion and the second conductive portion. The auxiliary layer includes a plurality of auxiliary portions, and the auxiliary portions are correspondingly arranged in groups with the first conductive portion one by one. A positive projection of the auxiliary portion on the plane where the substrate is located overlaps at least partially with the first overlapping region; a material of the auxiliary portion is different from a material of the first conductive portion, and an absolute value of a difference between a sheet resistance of the material of the auxiliary portion and a sheet resistance of the material of the first conductive portion is from 0.02 to 0.

04.

2. The array substrate according to claim 1, wherein At least one of the first conductive portion and the auxiliary portion includes a transition metal element, and the transition metal element includes at least one of materials in Group IVB, Group IB, and Group IIB.

3. The array substrate according to claim 1, wherein, At least a part of a surface of the auxiliary portion close to the substrate side is in contact with at least a part of a surface of the first conductive portion away from the substrate side.

4. The array substrate according to claim 1, wherein, A ratio range of a thickness of the auxiliary layer to a thickness of the first conductive portion is from 0.003 to 0.

03.

5. The array substrate according to any one of claims 1 to 4, wherein, The first conductive portion extends in a first direction, and the first conductive portion includes a first edge and a second edge oppositely arranged in a second direction, and the first direction intersects with the second direction; the auxiliary portion has a third edge and a fourth edge oppositely arranged in the second direction, the third edge is closer to the first edge than the fourth edge, and the fourth edge is closer to the second edge than the third edge; A first distance in the second direction is between the first edge and the third edge, a second distance in the second direction is between the second edge and the fourth edge, and both the first distance and the second distance are greater than or equal to 1.0 micrometer and less than or equal to 2.0 micrometers.

6. The array substrate according to claim 5, wherein, The first conductive portion has a first side surface extending in a direction away from the substrate, and a first slope angle is between the first side surface and a plane where the substrate is located, and the first slope angle ranges from 40 degrees to 60 degrees; The second conductive portion has a second side surface extending in a direction away from the substrate, and a second slope angle is between the second side surface and a plane where the substrate is located, and the second slope angle ranges from 40 degrees to 60 degrees; The auxiliary portion has a third side surface extending in a direction away from the substrate, and a third slope angle is between the third side surface and a plane where the substrate is located, and the third slope angle ranges from 40 degrees to 60 degrees.

7. The array substrate according to claim 5, wherein In a plane perpendicular to the substrate, the array substrate further includes a first conductive layer and a second conductive layer that are sequentially located on one side of the substrate; the first conductive layer includes a plurality of gate lines extending in a first direction, and the second conductive layer includes a plurality of data lines extending in a second direction; Wherein, a portion where the orthographic projection of the gate line on the plane of the substrate overlaps with the orthographic projection of the data line on the plane of the substrate is the first conductive portion, and a portion where the orthographic projection of the data line on the plane of the substrate overlaps with the orthographic projection of the gate line on the plane of the substrate is the second conductive portion.

8. The array substrate according to claim 7, wherein, The orthographic projection of the auxiliary portion on the plane of the substrate includes the orthographic projection of the first conductive portion on the plane of the substrate.

9. The array substrate according to claim 8, wherein, A plurality of the auxiliary portions are arranged at intervals along the first direction.

10. The array substrate according to claim 5, wherein, In a plane perpendicular to the substrate, the array substrate further includes a first conductive layer and a second conductive layer that are sequentially located on one side of the substrate; the first conductive layer includes a plurality of gate lines extending in a first direction, and the second conductive layer includes a plurality of data lines extending in a second direction; Wherein, the gate line is the first conductive portion, and the data line is the second conductive portion.

11. The array substrate according to claim 10, wherein, The orthographic projection of the auxiliary portion on the plane of the substrate includes the orthographic projection of the first conductive portion on the plane of the substrate.

12. The array substrate according to claim 11, wherein, The orthographic projection of the auxiliary portion on the plane of the substrate has a first outer edge, the orthographic projection of the first conductive portion on the plane of the substrate has a second outer edge, and the first outer edge surrounds the second outer edge, and there is a gap between the first outer edge and the second outer edge.

13. A method for manufacturing an array substrate, comprising: Forming a first conductive portion on one side of the substrate; [[ID=A]]Forming an auxiliary layer on a side of the first conductive portion away from the substrate, the auxiliary layer includes a plurality of auxiliary portions, and the auxiliary portions are arranged in one-to-one group correspondence with the first conductive portion; [[ID=B]]Forming a second conductive portion on a side of the auxiliary layer away from the substrate, the orthographic projection of the first conductive portion on the plane of the substrate and the orthographic projection of the second conductive portion on the plane of the substrate at least partially overlap to form a first overlapping region; the orthographic projection of the auxiliary portion on the plane of the substrate and the first overlapping region at least partially overlap; the material of the auxiliary portion is different from the material of the first conductive portion, and the absolute value of the difference between the sheet resistance of the material of the auxiliary portion and the sheet resistance of the material of the first conductive portion is 0.02 to 0.

04.

14. The method for preparing an array substrate according to claim 13, wherein, [[ID=C]]The forming the auxiliary layer on the side of the first conductive portion away from the substrate includes: [[ID=D]]Forming a metal thin film on the side of the first conductive portion away from the substrate; [[ID=E]]Forming a second glue layer on a side of the metal thin film away from the substrate, the material of the second glue layer includes positive photoresist; [[ID=F]]Using a patterning process on the second glue layer to form a second photoresist pattern, and the orthographic projection of the second photoresist pattern on the plane of the substrate includes the orthographic projection of the first conductive portion on the plane of the substrate.

15. The method for preparing an array substrate according to claim 13, wherein, [[ID=G]]The forming the auxiliary layer on the side of the first conductive portion away from the substrate includes: It should be noted that in the translation, for the sake of clarity and compliance with English grammar and usage habits, some adjustments and optimizations have been made in the expression while maintaining the original meaning. Also, in the original text, there is an item which is misspelled as [[ID=A]] in the provided content, and is misspelled as [[ID=B]] in the provided content. The above translation is based on the corrected understanding of the original text. If there are other specific requirements or corrections, please let me know. A third glue layer is formed on a side of the first conductive portion away from the substrate, and the material of the third glue layer includes a negative photoresist; A patterning process is performed on the third glue layer to form a third photoresist pattern, and a positive projection of the third photoresist pattern on a plane where the substrate is located does not overlap with a positive projection of the first conductive portion on the plane where the substrate is located; A metal thin film is formed on a side of the first conductive portion away from the substrate.

16. A display device, comprising the array substrate according to any one of claims 1 to 12, or comprising an array substrate prepared by using the preparation method of the array substrate according to any one of claims 13 to 15.

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