Liquid crystal display apparatus and electronic device

Abstract

Disclosed are a liquid crystal display apparatus and an electronic device. The liquid crystal display apparatus comprises a plurality of display modules (410) with variable refresh rates, a gate driving module (200), a data driving module (300) and a refresh rate control module (500), wherein the gate driving module (200) is connected to the display modules (410) by means of corresponding scanning lines (GL), the data driving module (300) is connected to the display modules (410) by means of corresponding data lines (DL), and the refresh rate control module (500) is connected to the display modules (410) by means of corresponding frequency control lines (SW).

Description

Liquid crystal display device and electronic device

[0001] This application claims priority to Chinese patent application No. 202410115610.X filed on January 26, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present application relates to the field of display technology, and in particular to a liquid crystal display device and an electronic device. Background Art

[0003] With the development of display technology, the application scenarios of display devices are increasing, and the demand for display is becoming more and more diversified.

[0004] However, the same display screen in liquid crystal display technology can only achieve a single refresh rate, which is difficult to meet the needs of different application scenarios. SUMMARY OF THE INVENTION

[0005] The present application provides a liquid crystal display device and an electronic device to alleviate the technical problem of difficulty in achieving partition control of refresh rate in liquid crystal displays.

[0006] In a first aspect, the present application provides a liquid crystal display device, which includes multiple display modules with variable refresh rates, a gate drive module, a data drive module, and a refresh rate control module, wherein the gate drive module is connected to the display module through a corresponding scan line; the data drive module is connected to the display module through a corresponding data line; and the refresh rate control module is connected to the display module through a corresponding frequency control line.

[0007] In a second aspect, the present application provides an electronic device, which includes a terminal and the above-mentioned liquid crystal display device provided in the terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0009] FIG1 is a schematic structural diagram of a liquid crystal display device.

[0010] FIG. 2 is a schematic diagram of a driving method of the sub-pixel shown in FIG. 1 .

[0011] FIG3 is a timing diagram of the sub-pixel shown in FIG2 .

[0012] FIG4 is a schematic structural diagram of an optional liquid crystal display device provided in an embodiment of the present application.

[0013] FIG. 5 is a schematic diagram of an optional driving method for the sub-pixel shown in FIG. 4 .

[0014] FIG. 6 is a first schematic diagram of each display partition shown in FIG. 5 realizing corresponding refresh rates.

[0015] FIG. 7 is another schematic diagram of implementing the refresh rates shown in FIG. 6 .

[0016] FIG8 is a schematic diagram of an optional timing sequence for realizing the refresh rates shown in FIG6 .

[0017] FIG. 9 is a second schematic diagram illustrating how the display partitions shown in FIG. 5 implement corresponding refresh rates.

[0018] FIG10 is another schematic diagram of realizing the refresh rates shown in FIG9 .

[0019] FIG11 is a schematic diagram of an optional timing sequence for realizing the refresh rates shown in FIG9 .

[0020] FIG. 12 is a third schematic diagram showing how the display partitions shown in FIG. 5 implement corresponding refresh rates.

[0021] FIG13 is a schematic diagram of an optional timing sequence for realizing the refresh rates shown in FIG12 .

[0022] FIG. 14 is a fourth schematic diagram of each display partition shown in FIG. 5 achieving corresponding refresh rates.

[0023] FIG. 15 is a fifth schematic diagram showing how the display partitions shown in FIG. 5 implement corresponding refresh rates.

[0024] FIG. 16 is a sixth schematic diagram of each display partition shown in FIG. 5 achieving corresponding refresh rates.

[0025] FIG17 is a schematic structural diagram of an optional electronic device provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0026] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0027] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of the indicated technical features. The features specified as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0028] With the development of display technology, the application scenarios of LCD devices (live broadcast, online classes, online games, chat interaction) are becoming more and more numerous, and the demand for the refresh rate (refresh frequency) of LCD devices is becoming more and more diversified.

[0029] In the same display screen, each display partition needs to display at a corresponding refresh rate. For example, when displaying a game, a corresponding display partition requires a higher refresh rate to ensure smooth display, while other display partitions use a lower refresh rate to meet the corresponding display requirements with lower power consumption. In view of this, the present application proposes a liquid crystal display device and electronic device that not only implements zoned refresh rate control to meet the requirements of multi-frequency driving, but also saves power consumption.

[0030] The liquid crystal display device and electronic device provided in the present application can write the data signal in the data line to the corresponding display module line by line through the gate driving module, and the refresh rate control module can control whether the display module refreshes the connected data signal according to the refresh rate and displays it at the corresponding refresh rate, thereby realizing partitioned control of the refresh rate without changing the line-by-line scanning.

[0031] As an introduction to the embodiments of the present application, a liquid crystal display device is now described. Please refer to Figures 1 to 3. Figure 1 is a schematic structural diagram of the liquid crystal display device. The liquid crystal display device includes a timing control module 100, a gate driver module 200, a data driver module 300, and a liquid crystal display panel 400. The liquid crystal display panel 400 includes a plurality of sub-pixels PL.

[0032] The timing control module 100 is connected to the gate driving module 200 and the data driving module 300. The gate driving module 200 is connected to the sub-pixels PL of the corresponding rows through the scan lines GL, and the data driving module 300 is connected to the sub-pixels PL of the corresponding columns through the data lines DL. Under the control of the timing control module 100, the scan signals in the scan lines GL control the data signals in the data lines DL to be written into the corresponding sub-pixels PL.

[0033] Multiple data lines DL, such as the first data line DL1 and the JNth data line DLJN, are arranged along a first direction DR1. The first data line DL1 can be connected to the sub-pixels PL in the first column, and the JNth data line DLJN can be connected to the sub-pixels PL in the JNth column. JN represents J multiplied by N, and both J and N are integers greater than 1.

[0034] A plurality of scan lines GL, such as a first scan line GL1, a second scan line GL2, an M-1th scan line GLM-1, and an M-th scan line GLM, are arranged along a second direction DR2. The first scan line GL1 can be connected to the sub-pixels PL in the first row, the second scan line GL2 can be connected to the sub-pixels PL in the second row, the M-1th scan line GLM-1 can be connected to the sub-pixels PL in the M-1th row, and the M-th scan line GLM can be connected to the sub-pixels PL in the M-1th row. Wherein, M is an integer greater than or equal to 4.

[0035] Among them, each sub-pixel PL set in the display area AA includes a first transistor T1, a liquid crystal capacitor Clc, a storage capacitor Cst and a common electrode COM, the first electrode of the first transistor T1 is connected to the data line DL, the gate of the first transistor T1 is connected to the scan line GL, the second electrode of the first transistor T1 is connected to one end of the liquid crystal capacitor Clc and one end of the storage capacitor Cst to form a first node NA, and the common electrode COM is connected to the other end of the liquid crystal capacitor Clc and the other end of the storage capacitor Cst.

[0036] The first electrode is one of the source and the drain, and the second electrode is the other of the source and the drain. For example, when the first electrode is the source, the second electrode is the drain; or when the first electrode is the drain, the second electrode is the source.

[0037] As shown in FIG2 , an Nth data line DLN, an N+1th data line DLN+1, a 2Nth data line DL2N, and a KN+1th data line DLKN+1 are disposed between the first data line DL1 and the JNth data line DLJN. The Nth data line DLN, the N+1th data line DLN+1, the 2Nth data line DL2N, and the KN+1th data line DLKN+1 are sequentially connected to the sub-pixels PL in the Nth column, the sub-pixels PL in the N+1th column, the sub-pixels PL in the 2Nth column, and the sub-pixels PL in the KN+1th column, respectively. K is an integer greater than or equal to 2.

[0038] As shown in FIG3 , the gate driver module 200 shifts the clock signals received and outputs them as corresponding scan signals. There may be multiple clock signals, for example, a first clock signal CK1, a second clock signal CK2, a third clock signal CK3, or a fourth clock signal CK4. The first data line DL1, the Nth data line DLN, the N+1th data line DLN+1, the 2Nth data line DL2N, the KN+1th data line DLKN+1, and the JNth data line DLJN sequentially transmit the first data signal D1, the Nth data signal DN, the N+1th data signal DN+1, the 2Nth data signal D2N, the KN+1th data signal DKN+1, and the JNth data signal DJN, respectively.

[0039] In one frame, the first transistors T1 in the sub-pixels PL of the first row are turned on by the first scanning signal G1 in the first scanning line GL1, and the data signals in the data lines DL update the potentials of the first nodes NA of the sub-pixels PL in the first row to N1-1, N1-N, N1-N+1, N1-2N, N1-KN+1 and N1-JN respectively; then, the first transistors T1 in the sub-pixels PL of the second row are turned on by the second scanning signal G2 in the second scanning line GL2, and the data signals in the data lines DL update the potentials of the first nodes NA of the sub-pixels PL in the second row to N2-1, N2-N, N2-N+1, N2-2N, N2-KN+1 and N2-JN respectively; the update of the potentials of the first nodes NA of the sub-pixels PL in other rows is similar.

[0040] However, the above-mentioned liquid crystal display device only supports full-screen switching of refresh rates and cannot satisfy the requirement of realizing partitioned control of refresh rates within a screen.

[0041] In view of this, the present embodiment provides a liquid crystal display device, as shown in Figures 4 to 16. The liquid crystal display device includes multiple display modules 410 with variable refresh rates, a gate driver module 200, a data driver module 300, and a refresh rate control module 500. The gate driver module 200 is connected to the display module 410 via corresponding scan lines GL, the data driver module 300 is connected to the display module 410 via corresponding data lines DL, and the refresh rate control module 500 is connected to the display module 410 via corresponding frequency control lines SW.

[0042] It can be understood that the liquid crystal display device provided in this embodiment can write the data signal in the data line DL to the corresponding display module 410 row by row through the gate driving module 200, and the refresh rate control module 500 can control whether the display module 410 refreshes the connected data signal according to the refresh rate and displays it at the corresponding refresh rate, thereby realizing partitioned control of the refresh rate without changing the row-by-row scanning.

[0043] Each display module 410 may be provided in a display area AA of a liquid crystal display panel 400 of a liquid crystal display device. The display area AA may include one or more display partitions, for example, at least one of a first display partition A1, a second display partition A2, a third display partition A3, and a fourth display partition A4. In other embodiments, the display area AA may further include a fifth display partition or more display partitions.

[0044] Each data line DL can be connected to a column of display modules 410. For example, the first data line DL1 can be connected to the display modules 410 in the first column, and the JN-th data line DLJN can be connected to the display modules 410 in the JN-th column. JN represents J multiplied by N, and both J and N are integers greater than 1. The first data line DL1 and the JN-th data line DLJN are arranged along a first direction DR1.

[0045] Each scan line GL may be connected to a row of display modules 410. For example, the first scan line GL1 may be connected to the display modules 410 in the first row, the second scan line GL2 may be connected to the display modules 410 in the second row, the M-1th scan line GLM-1 may be connected to the display modules 410 in the M-1th row, and the M-th scan line GLM may be connected to the display modules 410 in the M-1th row. M is an integer greater than or equal to 4. The first scan line GL1, the second scan line GL2, the M-1th scan line GLM-1, and the M-th scan line GLM are arranged along the second direction DR2.

[0046] In one embodiment, each frequency control line SW is connected to at least one column of display modules 410 . For example, the first frequency control line SW1 is connected to the display modules 410 in the first column, and the JNth frequency control line SWJN is connected to the display modules 410 in the JNth column.

[0047] It is understood that each frequency control line SW is connected to multiple columns of display modules 410. Although this can reduce the number of frequency control lines SW, it increases the number of frequency control lines SW routed along the first direction DR1 in the display area AA, which reduces the aperture ratio. Therefore, each frequency control line SW is connected to a column of display modules 410, and the frequency control lines SW extend in the same direction as the data lines DL, which can improve the aperture ratio.

[0048] In one embodiment, as shown in Figures 4 and 5, the display module 410 includes a first transistor T1, a second transistor T2, and a liquid crystal capacitor Clc. The gate of the first transistor T1 is connected to the scan line GL, and the first electrode of the first transistor T1 is connected to the data line DL; the first electrode of the second transistor T2 is connected to the second electrode of the first transistor T1, and the gate of the second transistor T2 is connected to the frequency control line SW; one end of the liquid crystal capacitor Clc is connected to the second electrode of the second transistor T2, and the other end of the liquid crystal capacitor Clc is connected to the common electrode COM.

[0049] In one embodiment, the display module 410 further includes a storage capacitor Cst, one end of the storage capacitor Cst is connected to the second electrode of the second transistor T2, and the other end of the storage capacitor Cst is connected to the common electrode COM.

[0050] It should be noted that the common electrodes COM connected to the liquid crystal capacitor Clc and the storage capacitor Cst may be the same or different.

[0051] The connection point between the first electrode of the second transistor T2 and the second electrode of the first transistor T1 can be recorded as a first node NA, and the connection point between one end of the liquid crystal capacitor Clc and the second electrode of the second transistor T2 can be recorded as a second node NB.

[0052] Among them, the timing control module 100 in the liquid crystal display device is also connected to the gate driving module 200 and the data driving module 300, so that under the control of the timing control module 100, the data signal in the data line DL is controlled by the scanning signal in the scanning line GL to be written to the first node NA in the corresponding display module 410.

[0053] The refresh rate control module 500 controls whether the second transistor T2 in the corresponding display module 410 is turned on through the corresponding frequency control line SW according to the refresh rate to determine whether to write the data signal from the first node NA to the second node NB.

[0054] Figure 5 takes the display area AA divided into a first display partition A1, a second display partition A2 and a third display partition A3 in the first direction DR1, and each frequency control line SW is connected to a column of display modules 410 as an example for explanation. The frequency control line SW is used to transmit a refresh rate control signal, and each display module 410 in each display partition is connected to the same refresh rate control signal.

[0055] It should be noted that in other embodiments, the display area AA is divided into a first display partition A1 and a second display partition A2 along the arrangement direction of the multiple frequency control lines SW. Each display module 410 in the first display partition A1 is connected to the first refresh rate control signal SWA, and each display module 410 in the second display partition A2 is connected to the second refresh rate control signal SWB. In this way, independent refresh rates can be achieved for the first display partition A1 and the second display partition A2.

[0056] As shown in Figure 5, each display module 410 in the first display partition A1 is connected to the first refresh rate control signal SWA for display at the first refresh rate; each display module 410 in the second display partition A2 is connected to the second refresh rate control signal SWB for display at the second refresh rate; each display module 410 in the third display partition A3 is connected to the third refresh rate control signal SWC for display at the third refresh rate.

[0057] Among them, the first frequency control line SW1 to the Nth frequency control line SWN in the first display partition A1 are all connected to the first refresh rate control signal SWA. The N+1th frequency control line SWN+1 to the 2Nth frequency control line SW2N in the second display partition A2 are all connected to the second refresh rate control signal SWB. The KN+1th frequency control line SWKN+1 to the JNth frequency control line SWJN in the third display partition A3 are all connected to the third refresh rate control signal SWC.

[0058] The potential of the first node NA in each display module 410 is represented by Nx-yA, and the potential of the second node NB in ​​each display module 410 is represented by Nx-yB, where x represents the row number of the display module 410 and y represents the column number of the display module 410.

[0059] In one embodiment, as shown in Figures 6, 7, and 8, this application uses a maximum refresh rate of 120Hz as an example for illustration. It is understandable that the maximum refresh rate may also be other refresh rates, such as 60Hz, 90Hz, 240Hz, etc. The first display partition A1 displays at a first refresh rate, which is half of the maximum refresh rate, i.e., 60Hz; the second display partition A2 displays at a second refresh rate, which is the maximum refresh rate, i.e., 120Hz; and the third display partition A3 displays at a third refresh rate, which is one-quarter of the maximum refresh rate, i.e., 30Hz.

[0060] The first frame, the second frame, the third frame and the fourth frame of the four consecutive frames may be respectively N-1 frame, N frame, N+1 frame and N+2 frame.

[0061] To achieve a 60Hz refresh rate display in the first display subarea A1, in the N-1 and N+1 frames, the gate driver module 200 controls the first transistor T1 in the first display subarea A1 via corresponding scan signals to write the corresponding data signal to the first node NA. It also controls the second transistor T2 in the first display subarea A1 via the first refresh rate control signal SWA to write the data signal from the first node NA to the second node NB. In the N and N+2 frames, the gate driver module 200 controls the first transistor T1 in the first display subarea A1 via corresponding scan signals to write the corresponding data signal to the first node NA. It also controls the second transistor T2 in the first display subarea A1 to be in an off state via the first refresh rate control signal SWA to prevent the data signal from being written from the first node NA to the second node NB.

[0062] Among them, when the first refresh rate control signal SWA is at a high potential VGH, each second transistor T2 in the first display partition A1 is in an on state; when the first refresh rate control signal SWA is at a low potential VGL, each second transistor T2 in the first display partition A1 is in an off state.

[0063] In order to synchronously realize the display of the second display partition A2 at a refresh rate of 120Hz, in the N-1 frame, the N frame, the N+1 frame and the N+2 frame, the gate driving module 200 controls the first transistor T1 in the second display partition A2 through the corresponding scan signal to write the corresponding data signal to the first node NA; and controls the second transistor T2 in the second display partition A2 through the second refresh rate control signal SWB to write the data signal from the first node NA to the second node NB.

[0064] Among them, when the second refresh rate control signal SWB is at a high potential VGH, each second transistor T2 in the second display partition A2 is in an on state; when the second refresh rate control signal SWB is at a low potential VGL, each second transistor T2 in the second display partition A2 is in an off state.

[0065] To synchronously display the third display subarea A3 at a 30Hz refresh rate, in frame N-1, the gate driver module 200 controls the first transistor T1 in the third display subarea A3 via a corresponding scan signal to write a corresponding data signal to the first node NA; and controls the second transistor T2 in the third display subarea A3 via a third refresh rate control signal SWC to write the data signal from the first node NA to the second node NB. In frames N, N+1, and N+2, the gate driver module 200 controls the first transistor T1 in the third display subarea A3 via a corresponding scan signal to write a corresponding data signal to the first node NA; and controls the second transistor T2 in the third display subarea A3 to be in an off state via the third refresh rate control signal SWC to prevent the data signal from being written from the first node NA to the second node NB.

[0066] Among them, when the third refresh rate control signal SWC is at a high potential VGH, each second transistor T2 in the third display partition A3 is in an on state; when the third refresh rate control signal SWC is at a low potential VGL, each second transistor T2 in the third display partition A3 is in an off state.

[0067] Among them, the first refresh rate control signal SWA, the second refresh rate control signal SWB, and the third refresh rate control signal SWC in Figure 6 maintain a high potential VGH or a low potential VGL in each frame. Different from Figure 6, in Figure 7, except that the second refresh rate control signal SWB is always at a high potential VGH in each frame, the first refresh rate control signal SWA and the third refresh rate control signal SWC perform a potential jump in each frame, for example, switching from a high potential VGH to a low potential VGL, or switching from a low potential VGL to a high potential VGH.

[0068] As shown in FIG8 , in order to synchronously realize the display of the first display partition A1 at a refresh rate of 60 Hz, the display of the second display partition A2 at a refresh rate of 120 Hz, and the display of the third display partition A3 at a refresh rate of 30 Hz, in frame N-1, the first refresh rate control signal SWA, the second refresh rate control signal SWB, and the third refresh rate control signal SWC are all at a high potential VGH, and all the first transistors T1 and the second transistors T2 are synchronously turned on to write the first data signal D1 to the JNth data signal DJN transmitted sequentially from the first data line DL1 to the JNth data line DLJN into the first node NA and the second node NB of the display module 410 in the first row, and then write them into the first node NA and the second node NB of the display module 410 in the second row, and so on, until the writing of all rows is completed.

[0069] In the Nth frame, all the first transistors T1 are turned on, the second refresh rate control signal SWB is at a high potential VGH, and the second transistors T2 in the second display partition A2 are turned on synchronously with the first transistor T1, so that the first data signal D1 to the JNth data signal DJN transmitted in sequence from the first data line DL1 to the JNth data line DLJN in the second display partition A2 are written to the first node NA and the second node NB in ​​the display module 410 of the first row, and then written to the first node NA and the second node NB in ​​the display module 410 of the second row, and so on, until all rows are completed. Writing; the first refresh rate control signal SWA and the third refresh rate control signal SWC are both at the low potential VGL, and the second transistors T2 in the first display partition A1 and the third display partition A3 are in the cut-off state, so that the first data signal D1 to the JN-th data signal DJN transmitted in sequence from the first data line DL1 to the JN-th data line DLJN in the first display partition A1 and the third display partition A3 are written to the first node NA in the display module 410 of the first row, and then written to the first node NA in the display module 410 of the second row, and so on, until the writing of all rows is completed.

[0070] In the N+1 frame, all the first transistors T1 are turned on, the first refresh rate control signal SWA and the second refresh rate control signal SWB are both at the high potential VGH, and the second transistors T2 in the first display partition A1 and the second display partition A2 are turned on synchronously with the first transistor T1, so that the first data signal D1 to the JN-th data signal DJN transmitted in sequence from the first data line DL1 to the JN-th data line DLJN in the first display partition A1 and the second display partition A2 are written to the first node NA and the second node NB in ​​the display module 410 of the first row, and then written to the display module 410 of the second row. The first node NA and the second node NB in ​​block 410, and so on, until the writing of all rows is completed; the third refresh rate control signal SWC is in the low potential VGL, and the second transistor T2 in the third display partition A3 is in the cut-off state, so that the first data signal D1 to the JN-th data signal DJN transmitted in sequence from the first data line DL1 to the JN-th data line DLJN in the third display partition A3 are written to the first node NA in the display module 410 of the first row, and then written to the first node NA in the display module 410 of the second row, and so on, until the writing of all rows is completed.

[0071] In the N+2 frame, all the first transistors T1 are turned on, the second refresh rate control signal SWB is at a high potential VGH, and the second transistors T2 in the second display partition A2 are turned on synchronously with the first transistor T1, so that the first data signal D1 to the JN-th data signal DJN transmitted in sequence from the first data line DL1 to the JN-th data line DLJN in the second display partition A2 are written to the first node NA and the second node NB in ​​the display module 410 of the first row, and then written to the first node NA and the second node NB in ​​the display module 410 of the second row, and so on, until all rows are completed. writing; the first refresh rate control signal SWA and the third refresh rate control signal SWC are both at the low potential VGL, and the second transistors T2 in the first display partition A1 and the third display partition A3 are in the cut-off state, so that the first data signal D1 to the JN-th data signal DJN transmitted in sequence from the first data line DL1 to the JN-th data line DLJN in the first display partition A1 and the third display partition A3 are written to the first node NA in the display module 410 of the first row, and then written to the first node NA in the display module 410 of the second row, and so on, until the writing of all rows is completed.

[0072] In one embodiment, as shown in Figures 9, 10 and 11, the first display partition A1 is displayed at a first refresh rate, which is half of the maximum refresh rate, i.e., 60 Hz; the second display partition A2 is displayed at a second refresh rate, which is the maximum refresh rate, i.e., 120 Hz; and the third display partition A3 is displayed at a third refresh rate, which is half of the maximum refresh rate, i.e., 60 Hz.

[0073] The first frame, the second frame, the third frame and the fourth frame of the four consecutive frames may be respectively N-1 frame, N frame, N+1 frame and N+2 frame.

[0074] To achieve a 60Hz refresh rate display in the first display subarea A1, in the N-1 and N+1 frames, the gate driver module 200 controls the first transistor T1 in the first display subarea A1 via corresponding scan signals to write the corresponding data signal to the first node NA. It also controls the second transistor T2 in the first display subarea A1 via the first refresh rate control signal SWA to write the data signal from the first node NA to the second node NB. In the N and N+2 frames, the gate driver module 200 controls the first transistor T1 in the first display subarea A1 via corresponding scan signals to write the corresponding data signal to the first node NA. It also controls the second transistor T2 in the first display subarea A1 to be in an off state via the first refresh rate control signal SWA to prevent the data signal from being written from the first node NA to the second node NB.

[0075] Among them, when the first refresh rate control signal SWA is at a high potential VGH, each second transistor T2 in the first display partition A1 is in an on state; when the first refresh rate control signal SWA is at a low potential VGL, each second transistor T2 in the first display partition A1 is in an off state.

[0076] In order to synchronously realize the display of the second display partition A2 at a refresh rate of 120Hz, in the N-1 frame, the N frame, the N+1 frame and the N+2 frame, the gate driving module 200 controls the first transistor T1 in the second display partition A2 through the corresponding scan signal to write the corresponding data signal to the first node NA; and controls the second transistor T2 in the second display partition A2 through the second refresh rate control signal SWB to write the data signal from the first node NA to the second node NB.

[0077] Among them, when the second refresh rate control signal SWB is at a high potential VGH, each second transistor T2 in the second display partition A2 is in an on state; when the second refresh rate control signal SWB is at a low potential VGL, each second transistor T2 in the second display partition A2 is in an off state.

[0078] To synchronously display the third display subarea A3 at a 60 Hz refresh rate, in the N-1 and N+1 frames, the gate driver module 200 controls the first transistor T1 in the third display subarea A3 via corresponding scan signals to write the corresponding data signal to the first node NA; and controls the second transistor T2 in the third display subarea A3 via the third refresh rate control signal SWC to write the data signal from the first node NA to the second node NB. In the N and N+2 frames, the gate driver module 200 controls the first transistor T1 in the third display subarea A3 via corresponding scan signals to write the corresponding data signal to the first node NA; and controls the second transistor T2 in the third display subarea A3 to be in an off state via the third refresh rate control signal SWC to prevent the data signal from being written from the first node NA to the second node NB.

[0079] Among them, when the third refresh rate control signal SWC is at a high potential VGH, each second transistor T2 in the third display partition A3 is in an on state; when the third refresh rate control signal SWC is at a low potential VGL, each second transistor T2 in the third display partition A3 is in an off state.

[0080] Among them, the first refresh rate control signal SWA, the second refresh rate control signal SWB, and the third refresh rate control signal SWC in Figure 9 all maintain a high potential VGH or a low potential VGL in each frame. Different from Figure 9, in Figure 10, except that the second refresh rate control signal SWB is always at a high potential VGH in each frame, the first refresh rate control signal SWA and the third refresh rate control signal SWC perform a potential jump in each frame, for example, switching from a high potential VGH to a low potential VGL, or switching from a low potential VGL to a high potential VGH.

[0081] As shown in FIG11 , in order to synchronously realize the display of the first display partition A1 at a refresh rate of 60 Hz, the display of the second display partition A2 at a refresh rate of 120 Hz, and the display of the third display partition A3 at a refresh rate of 60 Hz, in frame N-1, the first refresh rate control signal SWA, the second refresh rate control signal SWB, and the third refresh rate control signal SWC are all at a high potential VGH, and all the first transistors T1 and the second transistors T2 are synchronously turned on to write the first data signal D1 to the JNth data signal DJN transmitted sequentially from the first data line DL1 to the JNth data line DLJN into the first node NA and the second node NB of the display module 410 in the first row, and then write them into the first node NA and the second node NB of the display module 410 in the second row, and so on, until the writing of all rows is completed.

[0082] In the Nth frame, all the first transistors T1 are turned on, the second refresh rate control signal SWB is at a high potential VGH, and the second transistors T2 in the second display partition A2 are turned on synchronously with the first transistor T1, so that the first data signal D1 to the JNth data signal DJN transmitted in sequence from the first data line DL1 to the JNth data line DLJN in the second display partition A2 are written to the first node NA and the second node NB in ​​the display module 410 of the first row, and then written to the first node NA and the second node NB in ​​the display module 410 of the second row, and so on, until all rows are completed. Writing; the first refresh rate control signal SWA and the third refresh rate control signal SWC are both at the low potential VGL, and the second transistors T2 in the first display partition A1 and the third display partition A3 are in the cut-off state, so that the first data signal D1 to the JN-th data signal DJN transmitted in sequence from the first data line DL1 to the JN-th data line DLJN in the first display partition A1 and the third display partition A3 are written to the first node NA in the display module 410 of the first row, and then written to the first node NA in the display module 410 of the second row, and so on, until the writing of all rows is completed.

[0083] In the N+1 frame, the first refresh rate control signal SWA, the second refresh rate control signal SWB and the third refresh rate control signal SWC are all at the high potential VGH, and all the first transistors T1 and the second transistors T2 are synchronously turned on to write the first data signal D1 to the JN data signal DJN transmitted respectively from the first data line DL1 to the JN data line DLJN into the first node NA and the second node NB in ​​the display module 410 of the first row, and then write into the first node NA and the second node NB in ​​the display module 410 of the second row, and so on, until the writing of all rows is completed.

[0084] In the N+2 frame, all the first transistors T1 are turned on, the second refresh rate control signal SWB is at a high potential VGH, and the second transistors T2 in the second display partition A2 are turned on synchronously with the first transistor T1, so that the first data signal D1 to the JN-th data signal DJN transmitted in sequence from the first data line DL1 to the JN-th data line DLJN in the second display partition A2 are written to the first node NA and the second node NB in ​​the display module 410 of the first row, and then written to the first node NA and the second node NB in ​​the display module 410 of the second row, and so on, until all rows are completed. writing; the first refresh rate control signal SWA and the third refresh rate control signal SWC are both at the low potential VGL, and the second transistors T2 in the first display partition A1 and the third display partition A3 are in the cut-off state, so that the first data signal D1 to the JN-th data signal DJN transmitted in sequence from the first data line DL1 to the JN-th data line DLJN in the first display partition A1 and the third display partition A3 are written to the first node NA in the display module 410 of the first row, and then written to the first node NA in the display module 410 of the second row, and so on, until the writing of all rows is completed.

[0085] In one embodiment, as shown in Figures 12 and 13, the first display partition A1 is displayed at a first refresh rate, which is the highest refresh rate, i.e., 120 Hz; the second display partition A2 is displayed at a second refresh rate, which is the highest refresh rate, i.e., 120 Hz; and the third display partition A3 is displayed at a third refresh rate, which is the highest refresh rate, i.e., 120 Hz.

[0086] The first frame, the second frame, the third frame and the fourth frame of the four consecutive frames may be respectively the N-1 frame, the N frame, the N+1 frame and the N+2 frame. The first refresh rate control signal SWA, the second refresh rate control signal SWB and the third refresh rate control signal SWC are all at the high potential VGH in each frame. For example, the first refresh rate control signal SWA, the second refresh rate control signal SWB and the third refresh rate control signal SWC are all at the high potential VGH in the N-1 frame, the N frame, the N+1 frame and the N+2 frame.

[0087] As shown in FIG13 , in order to synchronously realize display at a refresh rate of 120 Hz in the first display partition A1, display at a refresh rate of 120 Hz in the second display partition A2, and display at a refresh rate of 120 Hz in the third display partition A3, in the N-1 frame, the N frame, the N+1 frame, and the N+2 frame, the first refresh rate control signal SWA, the second refresh rate control signal SWB, and the third refresh rate control signal SWC are all at a high potential VGH, and all the first transistors T1 and the second transistors T2 are synchronously turned on to write the first data signal D1 to the JNth data signal DJN transmitted sequentially from the first data line DL1 to the JNth data line DLJN into the first node NA and the second node NB in ​​the display module 410 of the first row, and then write into the first node NA and the second node NB in ​​the display module 410 of the second row, and so on, until writing is completed for all rows.

[0088] As shown in FIG14 , in order to synchronously realize the display of the first display partition A1 at the first refresh rate, the display of the second display partition A2 at the second refresh rate, and the display of the third display partition A3 at the third refresh rate, the first refresh rate is less than the second refresh rate, and the second refresh rate is equal to the third refresh rate.

[0089] The potential of the first frequency control signal can be set to a low potential VGL, whereby each second transistor T2 in the first display subarea A1 is turned off, and the first to JNth data signals D1 to DJN are written to the first node NA in the display module 410 of the first display subarea A1, i.e., each display module 410 does not refresh the data signal. Conversely, if the potential of the second and third frequency control signals is set to a high potential VGH, each second transistor T2 in the second and third display subareas A2 and A3 is turned on, and the first to JNth data signals DJN are written to the first nodes NA and second nodes NB in ​​the display modules 410 of the second and third display subareas A2 and A3, i.e., each display module 410 refreshes the data signal.

[0090] As shown in FIG15 , in order to synchronously realize the display of the first display partition A1 at the first refresh rate, the display of the second display partition A2 at the second refresh rate, and the display of the third display partition A3 at the third refresh rate, the first refresh rate is greater than the second refresh rate and equal to the third refresh rate.

[0091] The potential of the second frequency control signal can be set to a low potential VGL, whereby each second transistor T2 in the second display subarea A2 is turned off, and the first data signal D1 to the JNth data signal DJN are written to the first node NA in the display module 410 of the second display subarea A2, i.e., each display module 410 does not refresh the data signal. Conversely, if the potential of the first and third frequency control signals are set to a high potential VGH, each second transistor T2 in the first and third display subareas A1 and A3 is turned on, and the first data signal D1 to the JNth data signal DJN are written to the first node NA and the second node NB in ​​the display modules 410 of the first and third display subareas A1 and A3, i.e., each display module 410 refreshes the data signal.

[0092] As shown in FIG16 , in order to synchronously realize the display of the first display partition A1 at the first refresh rate, the display of the second display partition A2 at the second refresh rate, and the display of the third display partition A3 at the third refresh rate, the first refresh rate is equal to the second refresh rate, and the second refresh rate is greater than the third refresh rate.

[0093] The potential of the third frequency control signal can be set to a low potential VGL, whereby each second transistor T2 in the third display subarea A3 is turned off, and the first data signal D1 to the JNth data signal DJN are written to the first node NA in the display module 410 of the third display subarea A3, i.e., each display module 410 does not refresh the data signal. Conversely, if the potential of the first frequency control signal and the second frequency control signal are set to a high potential VGH, each second transistor T2 in the first display subarea A1 and the second display subarea A2 is turned on, and the first data signal D1 to the JNth data signal DJN are written to the first node NA and the second node NB in ​​the display modules 410 of the first display subarea A1 and the second display subarea A2, i.e., each display module 410 refreshes the data signal.

[0094] In one embodiment, as shown in FIG. 17 , this embodiment provides an electronic device 3000 , which includes a terminal 2000 and the aforementioned liquid crystal display device 1000 disposed in the terminal 2000 .

[0095] It can be understood that since the electronic device 3000 provided in this embodiment includes the above-mentioned liquid crystal display device 1000, the data signal in the data line DL can also be written to the corresponding display module 410 line by line through the gate driving module 200, and the refresh rate control module 500 can control whether the display module 410 refreshes the connected data signal according to the refresh rate and displays it at the corresponding refresh rate, thereby realizing partitioned control of the refresh rate without changing the line-by-line scanning.

[0096] It should be noted that the above-mentioned electronic device 3000 can be a mobile phone, a bracelet, a watch, a virtual reality device, an augmented reality device, etc.

[0097] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0098] The above is a detailed introduction to the liquid crystal display device and electronic device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A liquid crystal display device, the liquid crystal display device comprising: a plurality of display modules with variable refresh rates; a gate driving module, the gate driving module being connected to the display module through corresponding scan lines; a data driving module, the data driving module being connected to the display module through corresponding data lines; and a refresh rate control module, the refresh rate control module being connected to the display module through corresponding frequency control lines.

2. The liquid crystal display device according to claim 1, wherein The display module includes: a first transistor, a gate of the first transistor being connected to the scan line, a first pole of the first transistor being connected to the data line; a second transistor, a first pole of the second transistor being connected to a second pole of the first transistor, a gate of the second transistor being connected to the frequency control line; and a liquid crystal capacitor, one end of the liquid crystal capacitor being connected to a second pole of the second transistor, the other end of the liquid crystal capacitor being connected to a common electrode.

3. The liquid crystal display device according to claim 2, wherein The display module further includes a storage capacitor, one end of the storage capacitor being connected to a second pole of the second transistor, the other end of the storage capacitor being connected to the common electrode.

4. The liquid crystal display device according to claim 2, wherein, The frequency control line is used to transmit a refresh rate control signal, a display area of the liquid crystal display device includes a plurality of display partitions, and each of the display modules in each of the display partitions is connected to the same refresh rate control signal.

5. The liquid crystal display device according to claim 4, wherein, The plurality of display partitions include a first display partition and a second display partition distributed in a layout direction of the plurality of frequency control lines; each of the display modules in the first display partition is connected to a first refresh rate control signal, and each of the display modules in the second display partition is connected to a second refresh rate control signal.

6. The liquid crystal display device according to claim 4, wherein, The plurality of display partitions include a first display partition, a second display partition, and a third display partition distributed in a layout direction of the plurality of frequency control lines; each of the display modules in the first display partition is connected to a first refresh rate control signal to perform display at a first refresh rate; each of the display modules in the second display partition is connected to a second refresh rate control signal to perform display at a second refresh rate; each of the display modules in the third display partition is connected to a third refresh rate control signal to perform display at a third refresh rate.

7. The liquid crystal display device according to claim 6, wherein, The scan line is used to transmit a scan signal, and the data line is used to transmit a data signal; the first refresh rate is one-half of the highest refresh rate, the second refresh rate is the highest refresh rate, and the third refresh rate is one-fourth of the highest refresh rate; in the first display partition, the gate driving module and the refresh rate control module respectively control each of the display modules through the scan signal and the first refresh rate control signal, write corresponding data signals to the liquid crystal capacitor in both the first frame and the third frame of four consecutive frames, and write corresponding data signals to a first pole of the second transistor in both the second frame and the fourth frame of the four consecutive frames; In the second display partition, the gate driving module and the refresh rate control module respectively control each display module through the scan signal and the second refresh rate control signal, and write corresponding data signals to the liquid crystal capacitors in all of the consecutive four frames; In the third display partition, the gate driving module and the refresh rate control module respectively control each display module through the scan signal and the third refresh rate control signal, write corresponding data signals to the liquid crystal capacitors in the first frame, and write corresponding data signals to the first pole of the second transistor in the second frame, the third frame, and the fourth frame.

8. The liquid crystal display device according to claim 7, wherein, In each frame, the gate driving module controls the first transistor to write corresponding data signals to the first pole of the second transistor row by row through the scan signal; In the first frame, the refresh rate control module controls each second transistor to be synchronously turned on with the first transistor in the same display module through the first refresh rate control signal, the second refresh rate control signal, and the third refresh rate control signal; In the second frame, the refresh rate control module controls the second transistor to be in a cut-off state for at least part of the time through the first refresh rate control signal and the third refresh rate control signal; The refresh rate control module controls the corresponding second transistor to be synchronously turned on with the first transistor in the same display module through the second refresh rate control signal; In the third frame, the refresh rate control module controls the corresponding second transistor to be synchronously turned on with the first transistor in the same display module through the first refresh rate control signal and the second refresh rate control signal; The refresh rate control module controls the corresponding second transistor to be in a cut-off state for at least part of the time through the third refresh rate control signal; In the fourth frame, the refresh rate control module controls the second transistor to be in a cut-off state for at least part of the time through the first refresh rate control signal and the third refresh rate control signal; The refresh rate control module controls the corresponding second transistor to be synchronously turned on with the first transistor in the same display module through the second refresh rate control signal.

9. The liquid crystal display device according to claim 8, wherein, The first refresh rate control signal is at a high potential in both the first frame and the third frame, and at a low potential in both the second frame and the fourth frame; or, the high potential and the low potential of the first refresh rate control signal are alternately distributed in each of the consecutive four frames; The second refresh rate control signal is at a high potential in all of the consecutive four frames; The third refresh rate control signal is at a high potential in the first frame, and at a low potential in the second frame, the third frame, and the fourth frame; or, the high potential and the low potential of the third refresh rate control signal are alternately distributed in each of the consecutive four frames, and the duration of the third refresh rate control signal being at a low potential is greater than the duration of the first refresh rate control signal being at a low potential.

10. The liquid crystal display device according to claim 6, wherein, The scan lines are used to transmit scan signals, and the data lines are used to transmit data signals; the first refresh rate is one-half of the highest refresh rate, the second refresh rate is the highest refresh rate, and the third refresh rate is one-half of the highest refresh rate; In the first display partition, the gate driving module and the refresh rate control module respectively control the corresponding display module through the scan signal and the first refresh rate control signal, write the corresponding data signal to the liquid crystal capacitor in both the first and third frames of four consecutive frames, and write the corresponding data signal to the first pole of the second transistor in both the second and fourth frames of the four consecutive frames; In the second display partition, the gate driving module and the refresh rate control module respectively control each display module through the scan signal and the second refresh rate control signal, and write the corresponding data signal to the liquid crystal capacitor in the four consecutive frames; In the third display partition, the gate driving module and the refresh rate control module respectively control the corresponding display module through the scan signal and the third refresh rate control signal, write the corresponding data signal to the liquid crystal capacitor in the first and third frames, and write the corresponding data signal to the first pole of the second transistor in the second and fourth frames.

11. The liquid crystal display device according to claim 10, wherein, In each frame, the gate driving module controls the first transistor to write the corresponding data signal to the first pole of the second transistor row by row through the scan signal; In the first frame, the refresh rate control module controls each second transistor to conduct synchronously with the first transistor in the same display module through the first refresh rate control signal, the second refresh rate control signal, and the third refresh rate control signal; In the second frame, the refresh rate control module controls the second transistor to be in a cut-off state for at least part of the time through the first refresh rate control signal and the third refresh rate control signal; The refresh rate control module controls the corresponding second transistor to conduct synchronously with the first transistor in the same display module through the second refresh rate control signal; In the third frame, the refresh rate control module controls each second transistor to conduct synchronously with the first transistor in the same display module through the first refresh rate control signal, the second refresh rate control signal, and the third refresh rate control signal; In the fourth frame, the refresh rate control module controls the second transistor to be in a cut-off state for at least part of the time through the first refresh rate control signal and the third refresh rate control signal; The refresh rate control module controls the corresponding second transistor to conduct synchronously with the first transistor in the same display module through the second refresh rate control signal.

12. The liquid crystal display device according to claim 11, wherein, The first refresh rate control signal and the third refresh rate control signal are both at a high potential in the first frame and the third frame, and both at a low potential in the second frame and the fourth frame; or, the high potential and the low potential of the first refresh rate control signal are alternately distributed in each of the four consecutive frames, and the high potential and the low potential of the third refresh rate control signal are alternately distributed in each of the four consecutive frames; The second refresh rate control signal is at a high potential in all of the four consecutive frames.

13. The liquid crystal display device according to claim 6, wherein, The scan lines are used to transmit scan signals, and the data lines are used to transmit data signals; the first refresh rate is the highest refresh rate, the second refresh rate is the highest refresh rate, and the third refresh rate is the highest refresh rate; In the first display partition, the gate driving module and the refresh rate control module respectively control the corresponding display module through the scan signal and the first refresh rate control signal, and write the corresponding data signal into the liquid crystal capacitor in each frame; In the second display partition, the gate driving module and the refresh rate control module respectively control the corresponding display module through the scan signal and the second refresh rate control signal, and write the corresponding data signal into the liquid crystal capacitor in each frame; In the third display partition, the gate driving module and the refresh rate control module respectively control the corresponding display module through the scan signal and the third refresh rate control signal, and write the corresponding data signal into the liquid crystal capacitor in each frame.

14. The liquid crystal display device according to claim 13, wherein, In each frame, the gate driving module controls the first transistor to write the corresponding data signal into the first pole of the second transistor row by row through the scan signal; In each of the frames, the refresh rate control module controls each of the second transistors to be synchronously turned on with the first transistor in the same display module through the first refresh rate control signal, the second refresh rate control signal, and the third refresh rate control signal.

15. The liquid crystal display device according to claim 14, wherein, The first refresh rate control signal, the second refresh rate control signal, and the third refresh rate control signal are all at a high potential in each frame.

16. The liquid crystal display device according to any one of claims 1 to 15, wherein, The extending direction of the frequency control line is the same as the extending direction of the data line, and each frequency control line is connected to at least one column of the display modules.

17. An electronic device, the electronic device includes a terminal and a liquid crystal display device provided on the terminal, and the liquid crystal display device includes: A plurality of display modules with variable refresh rates; A gate driving module, the gate driving module is connected to the display module through a corresponding scan line; A data driving module, the data driving module is connected to the display module through a corresponding data line; And A refresh rate control module, the refresh rate control module is connected to the display module through a corresponding frequency control line.

18. The electronic device according to claim 17, wherein, The display module includes: A first transistor, the gate of the first transistor is connected to the scan line, and the first pole of the first transistor is connected to the data line; A second transistor, a first pole of the second transistor is connected to a second pole of the first transistor, and a gate of the second transistor is connected to the frequency control line; and A liquid crystal capacitor, one end of the liquid crystal capacitor is connected to the second pole of the second transistor, and the other end of the liquid crystal capacitor is connected to the common electrode.

19. The electronic device according to claim 18, wherein, The display module further includes a storage capacitor, one end of the storage capacitor is connected to the second pole of the second transistor, and the other end of the storage capacitor is connected to the common electrode.

20. The electronic device according to claim 18, wherein, The frequency control line is used for transmitting a refresh rate control signal, a display area of the liquid crystal display device includes a plurality of display partitions, and each of the display modules in each of the display partitions is connected to the same refresh rate control signal.

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