Packaging substrate, electronic apparatus, circuit board and electronic device

Abstract

Embodiments of the present application relate to the technical field of electronic devices, and in particular to a packaging substrate, an electronic apparatus, a circuit board and an electronic device. The embodiments of the present application aim to solve the problem of complex structure on a circuit board. According to the packaging substrate, the electronic apparatus, the circuit board and the electronic device provided by the embodiments of the present application, an electronic element is arranged in a substrate body, such that the number of electronic elements and winding resources on the circuit board are reduced, the structure on the circuit board is simplified, and simple miniaturization design is facilitated. In addition, a third connecting part is arranged on a second surface, the electronic element is connected to the third connecting part, and on the basis of application requirements, a circuit on the substrate can be selected to be connected to or not connected to the third connecting part so as to select or bypass the electronic element.

Description

Packaging substrates, electronic devices, circuit boards and electronic equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on January 26, 2024, with application number 202410121410.5 and application name “Packaging substrate, electronic device, circuit board and electronic equipment”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the technical field of electronic equipment, and specifically to a packaging substrate, an electronic device, a circuit board, and an electronic device. Background Art

[0003] Electronic devices typically include a circuit board. The circuit board's substrate is equipped with electronic devices, including a package substrate and a chip mounted on the package substrate. The chip is connected to the circuit board's circuit board via the package substrate. The circuit board's substrate also houses electronic components (such as resistors and inductors), which are electrically connected to the chip to assist in its operation. However, the placement of electronic components on the circuit board's substrate complicates the circuit board's structure, hindering its compact and compact design.

[0004] Summary of the Invention

[0005] The embodiments of the present application provide a packaging substrate, an electronic device, a circuit board, and an electronic device, which can reduce the number of components on the circuit board, simplify the structure of the circuit board, and facilitate a simple and miniaturized design.

[0006] In a first aspect, embodiments of the present application provide a packaging substrate, comprising: a substrate, a conductive portion, and an electronic component. A first connection portion is provided on a first surface of the substrate, the first connection portion being connectable to a chip, and a second connection portion is provided on a second surface of the substrate, the first surface and the second surface being disposed opposite each other. The conductive portion is disposed within the substrate, one end of the conductive portion being connected to the first connection portion, and the other end of the conductive portion being connected to the second connection portion. The electronic component is disposed within the substrate, spaced apart from the conductive portion. A third connection portion is also provided on the second surface of the substrate, one end of the electronic component being connected to the third connection portion.

[0007] Through the above arrangement, the electronic components are arranged inside the board body, which reduces the number of electronic components and winding resources on the circuit board, simplifies the structure on the circuit board, and facilitates a concise and miniaturized design.

[0008] In addition, a third connection portion connected to the electronic component is provided on the second surface of the board. The circuit on the substrate can be connected to or not connected to the third connection portion according to application requirements to select or bypass the electronic component.

[0009] In some embodiments that may include the above embodiments, one end of the electronic component is connected to the conductive portion to achieve a connection between the electronic component and the chip. The other end of the electronic component is connected to a third connection portion, which can be connected to a ground network or a power network, so that the third connection portion has a predetermined potential. This configuration allows the electronic component to assist the chip in operation, thereby improving the performance of the electronic device. The third connection portion can also be left floating, so that the electronic component does not participate in the signal chain operation, avoiding signal loss.

[0010] In some embodiments that may include the above embodiments, one end of the electronic component is configured to have a preset potential and can be connected to a ground circuit on the package substrate, bringing the one end of the electronic component to zero potential. It can also be connected to a circuit in the package substrate that connects to a power supply, bringing the other end of the electronic component to a predetermined potential. The other end of the electronic component is connected to a third connection portion, which can be connected to the second connection portion via a circuit on the substrate to establish a connection between the electronic component and the chip. This arrangement allows the electronic component to be integrated into the signal chain, assisting the chip's operation and improving the performance of the electronic device. The third connection portion can also be configured to have a preset potential. This arrangement prevents the electronic component from affecting signal quality, allowing the chip to connect to electronic components integrated on the substrate that correspond to the electronic device's function.

[0011] In some embodiments that may include the above embodiments, the conductive portion includes a first conductive portion and a second conductive portion, the first conductive portion and the second conductive portion are spaced apart, there are two first connecting portions and two second connecting portions, one end of the first conductive portion is connected to one first connecting portion, the other end of the first conductive portion is connected to one second connecting portion, one end of the second conductive portion is connected to another first connecting portion, and the other end of the second conductive portion is connected to another second connecting portion; the electronic component includes a first electronic component and a second electronic component, the first electronic component is spaced apart from and corresponds to the first conductive portion, and the second electronic component is spaced apart from and corresponds to the second conductive portion. In this arrangement, the conductive portion and the electronic component respectively correspond to the two signal channels that transmit differential signals.

[0012] In some embodiments that may include the above-mentioned embodiments, the board includes multiple conductive layers and multiple dielectric layers, and the multiple conductive layers and multiple dielectric layers are alternately stacked; the electronic component includes an inductor, and the inductor includes a first coil and a second coil arranged in series, at least a portion of the first coil is located in one conductive layer, and at least a portion of the second coil is located in another conductive layer, and the coils in different layers are connected by package layer switching vias. With this arrangement, the inductor in the package substrate can be wound in multiple layers, reducing the winding area and saving space inside the package substrate. In addition, the inductor is arranged inside the board body, which achieves self-shielding, avoids the risk of EMI introduced by the inductor, and does not require an additional shielding cavity compared to integrating the inductor on the substrate.

[0013] In some embodiments that may include the above embodiments, the board includes a first board, an intermediate board, and a second board arranged in a stacked manner. The first board and the second board each include multiple conductive layers and multiple dielectric layers. The intermediate board is located between the first and second boards. The intermediate board is thicker than the first and second boards and is the thickest dielectric layer near the longitudinal center of the board. Physical electronic components may be disposed within the intermediate board. This arrangement fully utilizes the dielectric layers within the package substrate, saving space within the package substrate.

[0014] In a second aspect, an embodiment of the present application further provides an electronic device, comprising: a chip and the packaging substrate described above, wherein the chip is disposed on the first surface and is electrically connected to the first connection portion.

[0015] The electronic device provided in the embodiments of the present application includes the packaging substrate in any of the above embodiments, so the two can solve the same technical problems and achieve the same technical effects.

[0016] In a third aspect, an embodiment of the present application further provides a circuit board, comprising: a substrate and the above-mentioned electronic device, wherein the electronic device is arranged on the circuit board.

[0017] The circuit board provided in the embodiment of the present application includes the electronic device in any of the above embodiments, so the two can solve the same technical problems and achieve the same technical effects.

[0018] In a fourth aspect, an embodiment of the present application further provides an electronic device, comprising: a battery and the above-mentioned circuit board, wherein the battery is electrically connected to the circuit board.

[0019] The electronic device provided in the embodiments of the present application includes the circuit board in any of the above embodiments, so the two can solve the same technical problems and achieve the same technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] FIG1 is a circuit diagram of a DC bias circuit in the related art;

[0021] FIG2 is a schematic diagram showing a structure in which a choke inductor of a DC bias circuit is arranged on a circuit board by winding in the related art;

[0022] FIG3 is a schematic diagram showing a structure in which a choke inductor of a DC bias circuit is provided on a circuit board via a surface-mount device in the related art;

[0023] FIG4 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0024] FIG5 is a schematic structural diagram of a packaging substrate provided in an embodiment of the present application;

[0025] FIG6 is a first schematic diagram of circuit connections inside and on a packaging substrate provided in an embodiment of the present application;

[0026] FIG7 is a second schematic diagram of circuit connections inside and on a packaging substrate provided in an embodiment of the present application;

[0027] FIG8 is a third schematic diagram of circuit connections inside and on a packaging substrate provided in an embodiment of the present application;

[0028] FIG9 is a fourth schematic diagram of circuit connections inside and on a packaging substrate provided in an embodiment of the present application;

[0029] FIG10 is a fifth schematic diagram of circuit connections inside and on a package substrate provided in an embodiment of the present application;

[0030] FIG11 is a sixth schematic diagram of circuit connections inside and on a package substrate provided in an embodiment of the present application;

[0031] FIG12 is a schematic diagram of the internal structure of a package substrate provided in an embodiment of the present application;

[0032] FIG13 is a seventh schematic diagram of circuit connections inside and on a package substrate provided in an embodiment of the present application;

[0033] FIG14 is a diagram showing the insertion loss of a signal of the circuit board corresponding to FIG13;

[0034] FIG15 is a return loss diagram of a signal of the circuit board corresponding to FIG13;

[0035] FIG16 is a schematic diagram eight of circuit connections inside and on a package substrate according to an embodiment of the present application;

[0036] FIG17 is a signal insertion loss diagram of the circuit board corresponding to FIG16;

[0037] FIG18 is a signal return loss diagram of the circuit board corresponding to FIG16;

[0038] FIG19 is a schematic diagram of the internal structural connections of a package substrate provided in an embodiment of the present application;

[0039] FIG20 is a schematic structural diagram of a first electronic component and a second electronic component within a package substrate provided in an embodiment of the present application;

[0040] FIG21 is a schematic diagram of the structure of a package substrate according to an embodiment of the present application;

[0041] FIG22 is a first structural diagram of electronic components inside a package substrate provided in an embodiment of the present application;

[0042] FIG23 is a second structural diagram of electronic components inside a package substrate provided in an embodiment of the present application;

[0043] Figure 24 is a third structural schematic diagram of the electronic components inside the packaging substrate provided in an embodiment of the present application.

[0044] Explanation of reference numerals: 10: DC bias circuit; 11: first RF port; 12: second RF port; 13: DC bias port; 14: choke inductor; 15: DC blocking capacitor; 16: chip; 161: RF chip; 17: antenna; 20: circuit board; 21: substrate; 30: electronic device; 31: packaging substrate; 40: housing; 50: battery; 60: electronic device; 311: board; 312: conductive portion; 313: electronic component; 32: first connecting portion; 33: second connecting portion; 34: third connecting portion; 35: fourth connecting portion; 141: inductor; 3121: first conductive part; 3122: second conductive part; 3131: first electronic component; 3132: second electronic component; 321: a first connecting part; 322: another first connecting part; 331: a second connecting part; 332: another second connecting part; 341: a third connecting part; 342: another third connecting part; 313a: first coil; 313b: second coil; 311a: first plate; 311b: middle plate; 311c: second plate; 3111: conductive layer; 3112: dielectric layer; 3133: physical electronic component. DETAILED DESCRIPTION

[0045] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0046] In the following, the terms "first," "second," etc. are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature specified as "first," "second," etc. may explicitly or implicitly include one or more of the features.

[0047] In addition, in the embodiments of the present application, directional terms such as "up", "down", "left", "right", "horizontal" and "vertical" are defined relative to the orientation of the components in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they can change accordingly according to changes in the orientation of the components in the drawings.

[0048] In the embodiments of the present application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, an electrical connection, a detachable connection, or an integrated connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0049] Referring to Figure 1, when an electronic device communicates (such as sending text messages or making calls via a mobile phone), the RF signal is transmitted to the antenna 17 via the RF chip 161. The antenna 17 converts the RF signal into electromagnetic waves in free space and transmits it to the base station. Since the signal output by the RF chip 161 may include a DC signal in addition to the RF signal, in order to separate the RF signal from the DC signal, the RF chip 161 and the antenna 17 are generally connected via a DC bias circuit 10 (Bias-Tee). The DC bias circuit 10 includes a DC blocking capacitor 15, a choke inductor 14, a first RF port 11, a second RF port 12, and a DC bias port 13. One end of the DC blocking capacitor 15 is connected to the second RF port 12, the other end of the DC blocking capacitor 15 is connected to the first RF port 11 and one end of the choke inductor 14, and the other end of the choke inductor 14 is connected to the DC bias port 13. The first RF port 11 is used to connect to the RF chip 161, the second RF port 12 is used to connect to the antenna 17, and the DC bias port 13 is used to connect to the DC network, which may include a power supply network and a ground network. During operation, a signal is input from the first RF port 11, and the RF signal in the signal is transmitted to the antenna 17 through the DC blocking capacitor 15. The DC signal in the signal is blocked by the DC blocking capacitor 15 and is grounded or flows into the power supply through the choke inductor 14 to prevent the DC component in the signal from affecting the operation of the antenna 17.

[0050] In some related technologies, as shown in Figure 2, the choke inductor 14 in the DC bias circuit 10 shown in Figure 1 is set on the circuit board 20. Accordingly, the choke inductor 14, the line connecting the first RF port 11 and the choke inductor 14, the line connecting the second RF port 12 and the choke inductor 14, and the line connecting the DC bias port 13 and the choke inductor 14 can all be composed of circuit patterns on the circuit board 20. Exemplarily, the circuit board 20 includes a metal layer, and the metal layer is patterned to form a circuit pattern, that is, to form the choke inductor 14.

[0051] In the implementation method in which the signal includes a differential signal, there are two choke inductors 14, two first-end RF ports 11, and two second RF ports 12. One port of the RF chip 161 is connected to a second RF port 12 and one end of a choke inductor 14 through a first RF port 11. Another port of the RF chip 161 is connected to another second RF port 12 and one end of another choke inductor 14 through another first RF port 11. Both second RF ports 12 are connected to the antenna 17. The other ends of the two choke inductors 14 are connected to the same DC bias port 13. The signals sent by the two ports of the RF chip 161 have a certain phase difference.

[0052] In other related technologies, as shown in Figure 3, the circuit board 20 includes a substrate 21 and an electronic device 30 and a choke inductor 14 arranged on the circuit board 20. The electronic device 30 includes a radio frequency chip 161 and a packaging substrate 31. The radio frequency chip 161 is packaged on the packaging substrate 31, and the packaging substrate 31 is electrically connected to the circuit on the substrate 21. The choke inductor 14 includes a chip inductor, which is arranged on the substrate 21 through a surface-mounted device and is electrically connected to the packaging substrate 31 through the circuit on the substrate 21 to achieve electrical connection between the choke inductor 14 and the radio frequency chip 161.

[0053] In the related art shown in FIG. 2 and FIG. 3 , the DC bias circuit 10 (as shown in FIG. 1 ) is disposed on the substrate 21 of the circuit board 20 , resulting in a large number of devices and circuits on the circuit board 20 , leading to a complex structure of the circuit board 20 .

[0054] The present embodiment provides an electronic device 60, which may include a mobile phone, a tablet computer, a smartwatch, a wearable device, etc. The present embodiment does not limit the electronic device 60. The present embodiment will be described using the mobile phone as an example. It is understood that the present embodiment is not limited to this example, and the electronic device 60 may also be other devices.

[0055] Referring to Figure 4 , in this embodiment, the electronic device 60 includes a housing 40, a circuit board 20 disposed within the housing 40, and a battery 50 disposed within the housing 40. The battery 50 is electrically connected to the circuit board 20. The circuit board 20 includes a substrate 21 and an electronic device 30 disposed on the substrate 21. The electronic device 30 is electrically connected to the circuit on the substrate 21. Exemplarily, the electronic device 30 may include a radio frequency electronic device, a charging management electronic device, an audio decoding electronic device, etc. The electronic device 30 includes a chip 16 and a packaging substrate 31. The chip 16 is mounted on the packaging substrate 31. The packaging substrate 31 is connected to the circuit on the substrate 21 to achieve an electrical connection between the chip 16 and the circuit board 20. Exemplarily, in an implementation in which the electronic device 30 includes a radio frequency electronic device, the chip 16 may include a radio frequency chip. The radio frequency chip can transmit radio frequency signals to the antenna 17 shown in Figure 1 of the electronic device 60 to achieve signal transmission. In an implementation in which the electronic device 30 includes a charging management electronic device, the chip 16 may include a charging management chip, through which a control signal may be sent to the battery 50 to implement the function of controlling the charging speed of the battery 50; in an implementation in which the electronic device 30 includes an audio decoding electronic device, the chip 16 may include an audio decoding chip, through which an analog audio signal may be sent to the speaker of the electronic device 60 to implement the function of playing music.

[0056] Referring to FIG5 , in the embodiment of the present application, the package substrate 31 includes a plate body 311. The plate body 311 includes a first surface (the upper surface in FIG5 ) and a second surface (the lower surface in FIG5 ) disposed opposite to each other. A first connecting portion 32 is disposed on the first surface, and a second connecting portion 33 is disposed on the second surface.

[0057] In the above implementation, the first connection portion 32 may include a first pad disposed on the first surface. The first connection portion 32 may be soldered to the chip 16 shown in FIG4 . Of course, the first connection portion 32 may also include a metal layer or a metal block disposed on the first surface. This embodiment of the present application does not limit the first connection portion 32. The second connection portion 33 is connected to the substrate 21 to achieve an electrical connection between the chip 16 and the circuit on the substrate 21. For example, the second connection portion 33 may include a metal layer on the second surface and a second pad disposed on the second surface. Accordingly, a third pad is disposed on the substrate 21, and the second pad and the third pad are soldered together. It is understood that during soldering, solder is formed between the first connection portion 32 and the chip 16, and then the solder is heated to form a solder ball connecting the first connection portion 32 and the chip 16. Solder is also formed between the second connection portion 33 and the third pad, and then the solder is heated to form a solder ball connecting the second connection portion 33 and the third pad.

[0058] The package substrate 31 in the embodiment of the present application further includes a conductive portion 312, which is disposed within the board body 311. One end of the conductive portion 312 (the top end in FIG5 ) is connected to the first connection portion 32, and the other end of the conductive portion 312 (the bottom end in FIG5 ) is connected to the second connection portion 33. The conductive portion 312 is used to electrically connect the first connection portion 32 and the second connection portion 33. A via is provided on the board body 311, which may penetrate the first connection portion 32 and the second connection portion 33. Accordingly, the conductive portion 312 may include a metal sidewall disposed on the wall of the via, one end of the metal sidewall being connected to the first connection portion 32, and the other end of the metal sidewall being connected to the second connection portion 33, to achieve electrical connection between the first connection portion 32 and the second connection portion 33. Of course, the conductive portion 312 may also include a solid via, i.e., a metal pillar, one end of the metal pillar being connected to the first connection portion 32, and the other end of the metal pillar being connected to the second connection portion 33. The first connection portion 32 and the second connection portion 33 are electrically connected via the metal pillar.

[0059] The packaging substrate 31 in the embodiment of the present application further includes an electronic component 313, which is disposed within the board body 311 and spaced apart from the conductive portion 312. The embodiment of the present application does not limit the electronic component 313, and the electronic component 313 may include an inductor, a capacitor, a resistor, etc. It is understood that the number and function of the electronic components 313 can be reasonably set according to the function and structure of the electronic device 30. In an implementation in which there are multiple electronic components 313, the functions of the electronic components 313 can be the same or different.

[0060] In the package substrate 31 of the embodiment of the present application, the first connection portion 32 is disposed on the first surface of the board body 311, the second connection portion 33 is disposed on the second surface of the board body 311, and the conductive portion 312 is disposed within the board body 311, with one end of the conductive portion 312 connected to the first connection portion 32 and the other end of the conductive portion 312 connected to the second connection portion 33. The electronic component 313 is disposed within the board body 311, spaced apart from the conductive portion 312. A third connection portion 34 is also disposed on the second surface of the board body 311, with one end of the electronic component 313 connected to the third connection portion 34. It is understood that the structure of the third connection portion 34 and the second connection portion 33 can be substantially the same, and will not be further described here.

[0061] Compared with the electronic components 313 being arranged on the substrate 21 of the circuit board 20, in the embodiment of the present application, the electronic components 313 are arranged in the board body 311 of the packaging substrate 31, which can reduce the number of electronic components 313 on the circuit board 20, simplify the circuit on the circuit board 20, and facilitate simple and miniaturized design; a third connection part 34 connected to the electronic component 313 is provided on the second surface of the board body 311, and the circuit on the substrate 21 can be connected to or not connected to the third connection part 34 according to application requirements to select or bypass the electronic component 313.

[0062] Continuing with FIG5 , in some implementations, the electronic component 313 is not connected to the chip 16 shown in FIG4 . That is, the electronic component 313 is not connected to the chip 16, the conductive portion 312, the first connection portion 32, and the second connection portion 33. Accordingly, the electronic component 313 can be connected to the circuit on the substrate 21. For example, a third connection portion 34 is provided on the second surface of the board 311, and the third connection portion 34 is connected to both the electronic component 313 and the circuit on the substrate 21. In this way, the electronic component 313 can assist the circuit on the substrate 21 in operating, playing a role corresponding to the circuit's function.

[0063] Referring to Figure 6 , in some embodiments, a third connection portion 34 is provided on the second surface, connected to an electronic component 313. The other end of the third connection portion 34 is connected to the circuit on the substrate 21. The other end of the electronic component 313 can be configured to have a predetermined potential. For example, the other end of the electronic component 313 can be connected to a ground network or a power supply network. It is understood that the other end of the electronic component 313 is connected to the ground network, that is, the other end of the electronic component 313 is connected to the ground circuit on the package substrate 31, so that the other end of the electronic component 313 is at zero potential. The ground circuit can be a circuit or structure on the package substrate 31 for grounding. The other end of the electronic component 313 is connected to the power supply network, that is, the other end of the electronic component 313 is connected to a circuit connected to a power supply in the package substrate 31, so that the other end of the electronic component 313 has a predetermined potential. The package substrate 31 generally has a circuit or structure connected to a power supply to supply power to the chip 16. Accordingly, the other end of the electronic component 313 can be connected to this circuit or structure. In this way, the electronic component 313 can assist the circuit on the substrate 21 in operating, fulfilling a function corresponding to the circuit's function.

[0064] Continuing with FIG6 , in an implementation where electronic device 30 (as shown in FIG4 ) is a radio frequency electronic device and electronic component 313 is an inductor 141, radio frequency chip 161 is connected to first connection portion 32 to achieve a connection between radio frequency chip 161 and package substrate 31. Package substrate 31 is connected to the circuit on substrate 21 via second connection portion 33, and ultimately to antenna 17 to achieve a connection between radio frequency chip 161 and antenna 17. Inductor 141 is connected to the circuit on substrate 21 to assist the circuit in achieving its corresponding function.

[0065] In some implementations, the electronic component 313 is connected to the chip 16. Referring to FIG. 7 , in some embodiments, one end of the electronic component 313 can be configured to have a preset potential. For example, one end of the electronic component 313 can be connected to a ground network or a power network within the package substrate 31; the other end of the electronic component 313 is connected to the third connection portion 34.

[0066] In some embodiments, the third connection portion 34 can be connected to the second connection portion 33 through the circuit on the substrate 21 to achieve a connection between the electronic component 313 and the chip 16. In this way, the electronic component is connected to the signal chain, which can assist the chip in working and improve the performance of the electronic device. Continuing with reference to FIG7 , in an implementation where the electronic device 30 (as shown in FIG4 ) is a radio frequency electronic device and the electronic component 313 is an inductor 141, the radio frequency chip 161 is connected to the first connection portion 32 to achieve a connection between the radio frequency chip 161 and the package substrate 31; the package substrate 31 is connected to the circuit on the substrate 21 through the second connection portion 33 and finally connected to the antenna 17 to achieve a connection between the radio frequency chip 161 and the antenna 17. In an implementation where the signal focuses on high-frequency signals, the inductor 141 has a better effect of biasing the DC component. One end of the inductor 141 is connected to the third connection portion 34, and the third connection portion 34 is connected to the second connection portion 33 to achieve a connection between the inductor 141 and the radio frequency chip 161; the other end of the inductor 141 is configured to have a preset potential. That is, the inductor can transmit the DC signal to the ground network or the power network to eliminate the DC signal, thereby preventing the DC signal from affecting the antenna operation.

[0067] In some embodiments, the third connection portion 34 can be configured to have a preset potential. For example, the third connection portion 34 can be connected to a ground network or a power network on the substrate 21. In this configuration, the electronic components do not affect signal quality, and the chip can be connected to electronic components integrated on the substrate corresponding to the functions of the electronic device.

[0068] Referring to Figure 8 , in the implementation method where the signal focuses on low-frequency signals, the area of ​​the inductor 141 wound inside the package is limited, the inductor 141 has a small inductance, and the inductor 141 is less effective in biasing the DC component. Therefore, the third connection portion 34 is connected to the ground network or the power network (bypassing the inductor 141). This prevents the inductor from transmitting part of the low-frequency RF signal to the ground network or the power network, causing RF signal loss.

[0069] It is understood that in the implementation of the bypass inductor 141, the target network connected to both ends of the inductor 141 remains consistent. In the implementation where one end of the inductor 141 within the package is configured as a ground network, the third connection portion 34 is connected to the ground network on the substrate 21. In the implementation where one end of the inductor 141 within the package is configured as a power network, the third connection portion 34 is connected to the same power network on the substrate 21 to ensure the same voltage across the inductor 141. This prevents voltage from being generated in the inductor 141 path when one end of the inductor 141 is grounded and the other end is connected to the power network, resulting in a short circuit between the power supply and the ground.

[0070] 9 , in other embodiments, one end of the electronic component 313 may be connected to the conductive portion 312 to achieve connection between the electronic component 313 and the chip 16 ; the other end of the electronic component 313 is connected to the third connecting portion 34 .

[0071] In some embodiments, the third connection portion 34 can be connected to a ground network or a power network, so that the third connection portion 34 has a preset potential. In this way, the electronic component can assist the chip to work, thereby improving the performance of the electronic device.

[0072] Continuing with reference to FIG9 , in an implementation where the electronic device 30 (as shown in FIG4 ) is a radio frequency electronic device and the electronic component 313 is an inductor 141, the radio frequency chip 161 is connected to the first connection portion 32 to achieve a connection between the radio frequency chip 161 and the package substrate 31; the package substrate 31 is connected to the circuit on the substrate 21 via the second connection portion 33, and ultimately connected to the antenna 17 to achieve a connection between the radio frequency chip 161 and the antenna 17. In an implementation where the signal focuses on high-frequency signals, the inductor 141 has a better effect of biasing the DC component. One end of the inductor 141 is connected to the radio frequency chip 161 via the conductive portion 312, and the other end is connected to the ground network or power supply network on the substrate 21 via the second connection portion 33 to achieve the function of the inductor 141 of biasing the DC signal component. That is, the inductor can transmit the DC signal to the ground network or power supply network to eliminate the DC signal, thereby preventing the DC signal from affecting the antenna operation.

[0073] In some embodiments, the third connection portion 34 can be suspended, that is, the third connection portion 34 is not connected to the circuit on the substrate. In this way, the electronic component does not participate in the operation of the signal chain, avoiding signal loss.

[0074] Referring to Figure 10 , in the implementation method where the signal focuses on low-frequency signals, the area of ​​the inductor 141 wound inside the package is limited, the inductor 141 has a small inductance, and the inductor 141 is less effective in biasing the DC component. Therefore, the third connection portion 34 is left floating (bypassing the inductor 141). This prevents the inductor from transmitting part of the low-frequency RF signal to the ground network or power network, causing RF signal loss.

[0075] Referring to FIG. 11 , in other embodiments, one end of the electronic component 313 can be connected to the first connection portion 32 to achieve a connection between the electronic component 313 and the chip 16. Alternatively, a fourth connection portion 35 can be provided on the first surface, and the electronic component 313 can be connected to the chip 16 via the fourth connection portion 35. The structure of the fourth connection portion 35 is substantially the same as that of the first connection portion 32 and will not be further described here. In this way, the electronic component can assist the chip in operation, thereby improving the performance of the electronic device.

[0076] It is understood that the signal can be a single-ended signal or a differential signal. Since both signal lines are used to transmit signals in differential transmission, the two transmitted signals have the same amplitude but a certain phase difference. Therefore, two signal channels and two DC bias circuits 10 are provided. Referring to FIG12 , in an implementation in which the signal includes a differential signal, the conductive portion 312 includes a first conductive portion 3121 and a second conductive portion 3122, which are spaced apart. There are two first connecting portions 32 and two second connecting portions 33. One end of the first conductive portion 3121 is connected to one first connecting portion 321, and the other end of the first conductive portion 3121 is connected to one second connecting portion 331. One end of the second conductive portion 3122 is connected to another first connecting portion 322, and the other end of the second conductive portion 3122 is connected to another second connecting portion 332. The electronic component 313 includes a first electronic component 3131 and a second electronic component 3132. The first electronic component 3131 is spaced apart from and corresponds to the first conductive portion 3121, while the second electronic component 3132 is spaced apart from and corresponds to the second conductive portion 3122. There are two third connecting portions 34: the first electronic component 3131 is connected to one third connecting portion 341, and the second electronic component 3132 is connected to the other third connecting portion 342. Thus, the conductive portions and electronic components correspond to the two signal channels for transmitting differential signals.

[0077] It is understandable that the first electronic component 3131 and the second electronic component 3132 may include at least one of a resistor, an inductor, and a capacitor, and the first electronic component 3131 and the second electronic component 3132 may be the same or different.

[0078] Please refer to Figure 13. In some implementations, one end of the first electronic component 3131 is configured to have a preset potential, and the other end is connected to a third connection portion 341; one end of the second electronic component 3132 is configured to have a preset potential, and the other end is connected to another third connection portion 342.

[0079] In some embodiments, the two third connection portions 34 (341 and 342) are connected to the two second connection portions 33 (331 and 332) via circuitry on the substrate 21. In this configuration, the first electronic component 3131 and the second electronic component 3132 are connected to the signal chain, which can assist the chip operation and improve the performance of the electronic device.

[0080] Continuing with FIG13 , in an implementation where the signal includes a differential signal and focuses on high-frequency signals, and both the first electronic component 3131 and the second electronic component 3132 include an inductor 141, the inductor 141 is more effective in biasing the DC component. In this case, the two third connecting portions 34 ( 341 and 342 ) are connected to the two second connecting portions 33 ( 331 and 332 ) on the substrate 21 to connect the inductor 141 to the signal path. That is, the two inductors 141 can respectively transmit the DC signal in the corresponding signal path to the ground network or the power network to eliminate the DC signal, thereby preventing the DC signal from affecting the antenna operation.

[0081] Please refer to Figure 14, which is a signal insertion loss (IL) diagram of the circuit board 20 corresponding to Figure 13. The horizontal axis represents the frequency of the signal, and the vertical axis represents the insertion loss of the signal; the solid line is the curve corresponding to the embodiment of the present application, and the dotted line is the curve corresponding to the circuit board 20 with only a signal path inside the packaging substrate 31 in the related art. When the frequency is 1.8GHz-10GHz, the two curves are highly overlapped. Specifically, when the frequency is 5.71GHz, the insertion loss corresponding to the embodiment of the present application is -2.30dB, and the insertion loss corresponding to the related art is -2.41dB, and the data difference is small. This shows that in the high-frequency band, the inductor 141 has almost no effect on the high-frequency RF signal component. When the frequency is less than 1.8GHz, the curve corresponding to the embodiment of the present application drops, indicating that the DC signal component in the signal is output from the DC bias port 13 through the inductor 141, which is consistent with the purpose to be achieved by the embodiment of the present application. It is explained that in the implementation method where the signal includes a differential signal and the signal includes a high-frequency signal, the inductor 141 located inside the packaging substrate 31 can bias the DC signal component in the signal path without affecting the high-frequency component in the signal path.

[0082] Please refer to Figure 15, which is a signal return loss (RL) diagram of the circuit board 20 corresponding to Figure 13. The horizontal axis represents the frequency of the signal, and the vertical axis represents the return loss of the signal; the solid line is the curve corresponding to the embodiment of the present application, and the dotted line is the curve corresponding to the circuit board with only a signal path inside the packaging substrate 31. In the related art, the DC bias circuit 10 of the radio frequency signal usually requires that the return loss of the signal is less than -10dB. When the return loss corresponding to the embodiment of the present application is -10dB, the covered frequency band is 0.85GHz-10GHz, which meets the index requirements and the signal path can be used normally. Similarly, when the return loss corresponding to the embodiment of the present application is -15dB, the covered frequency band is 1.22GHz-4.39GHz. It can be understood that for frequency band requirements above 10 GHz, it can be achieved by integrating small inductors or by reducing coupling capacitance optimization, including increasing the line spacing of the winding inductor 141 inside the packaging substrate 31 and increasing the size of the anti-pad of the inductor 141; for frequency band requirements below 0.85 GHz, it can be achieved by increasing the length of the winding inductor 141 inside the packaging substrate 31, but due to the size of the packaging substrate 31, the inductor 141 needs to be bypassed at lower frequencies, and a large inductor is integrated on the circuit board 20 to solve the problem.

[0083] In some implementations, the two third connection portions 34 (341 and 342) are configured to have a preset potential, and illustratively, can be connected to a ground network or a power network on the substrate 21. With this configuration, the first electronic component 3131 and the second electronic component 3132 do not affect signal quality, and the chip can be connected to electronic components integrated on the substrate corresponding to the functions of the electronic device.

[0084] Referring to Figure 16 , in an implementation where the signal includes a differential signal and the signal focuses on low-frequency signals, and the first electronic component 3131 and the second electronic component 3132 both include inductors, the area of ​​the winding inductor within the package is limited, the inductor value is small, and the effect of the inductor biasing the DC component is poor. In this case, the two third connecting portions 34 can be connected to the ground network or power network on the substrate 21. It is understandable that the target networks connected to the two ends of the two inductors remain consistent, and this will not be repeated here. In this way, the two inductors are prevented from transmitting part of the low-frequency RF signal in the corresponding signal path to the ground network or power network, causing RF signal loss.

[0085] Please refer to Figure 17, which is a signal insertion loss diagram of the circuit board 20 corresponding to Figure 16. The horizontal axis represents the frequency of the signal, and the vertical axis represents the insertion loss of the signal; the solid line is the curve corresponding to the embodiment of the present application, and the dotted line is the curve corresponding to the circuit board with only a signal path inside the packaging substrate 31. The two curves are almost identical. Specifically, at a frequency of 6.00GHz, the insertion loss corresponding to the embodiment of the present application is -1.05dB, and the insertion loss corresponding to the related art is -1.04dB, and the data difference is small. The signal insertion loss curve corresponding to the embodiment of the present application is smooth, indicating that the signal path is not affected by the Stub. That is to say, when the inductor 141 of the embodiment of the present application is in a non-working state, even if the inductor 141 is connected to the signal path, the signal transmission is not affected by the existence of a branch connected to the inductor 141.

[0086] Please refer to Figure 18, which is a signal return loss diagram of the circuit board 20 corresponding to Figure 16. The horizontal axis represents the frequency of the signal, and the vertical axis represents the return loss of the signal; the solid line is the curve corresponding to the embodiment of the present application, and the dotted line is the curve corresponding to the circuit board with only a signal path inside the packaging substrate 31. The curve corresponding to the embodiment of the present application is highly consistent with the curve corresponding to the related art. Specifically, when the frequency is 6.00GHz, the return loss corresponding to the embodiment of the present application is -19.39dB, and the return loss corresponding to the related art is -19.64dB, and the data difference is relatively small. It shows that in the implementation method where the signal includes a differential signal and the signal includes a low-frequency signal, the inductor 141 located inside the packaging substrate 31 will hardly affect the signal quality.

[0087] 19 , in another implementation, one end of the first electronic component 3131 is connected to the first conductive portion 3121 , and the other end is connected to a third connection portion 341 ; one end of the second electronic component 3132 is connected to the second conductive portion 3122 , and the other end is connected to another third connection portion 342 .

[0088] In some embodiments, the two third connection portions 34 (341 and 342) can be connected to a ground network or a power network so that the two third connection portions 34 (341 and 342) have a preset potential. In this manner, the first electronic component 3131 and the second electronic component 3132 can assist the chip in operation, thereby improving the performance of the electronic device.

[0089] In implementations where the signal includes a differential signal and focuses on high-frequency signals, and both the first electronic component 3131 and the second electronic component 3132 include inductors, the inductors are more effective in biasing the DC component. In this case, the two third connecting portions 34 (341 and 342) are connected to the ground network or the power network via wiring on the substrate 21. In other words, the two inductors can respectively transmit the DC signal in the corresponding signal path to the ground network or the power network, thereby canceling the DC signal and preventing it from affecting antenna operation.

[0090] In some embodiments, the two third connecting portions 34 (341 and 342) are left floating, that is, neither of the two third connecting portions 34 (341 and 342) is connected to the circuit on the substrate. In this configuration, the first electronic component 3131 and the second electronic component 3132 do not participate in the signal chain, thus avoiding signal loss.

[0091] In an implementation where the signal includes a differential signal and the signal focuses on low-frequency signals, and both the first electronic component 3131 and the second electronic component 3132 include inductors, the inductor area of ​​the winding wire within the package is limited, the inductor value is small, and the inductor's effectiveness in biasing the DC component is poor. In this case, the two third connecting portions 34 (341 and 342) are left floating. This prevents the two inductors from transmitting part of the low-frequency RF signal in the corresponding signal path to the ground network or power network, causing RF signal loss.

[0092] Referring to FIG. 20 , in an implementation where both the first electronic component 3131 and the second electronic component 3132 are inductors, the first electronic component 3131 and the second electronic component 3132 can be arranged in a direction perpendicular to the board 311. That is, in a plane parallel to the board 311, the projections of the first electronic component 3131 and the second electronic component 3132 at least partially overlap. Of course, the first electronic component 3131 and the second electronic component 3132 can also be arranged in a direction parallel to the board 311. This can reduce the space occupied by the first electronic component 3131 and the second electronic component 3132, thus conserving space within the package substrate 31.

[0093] Referring to FIG. 21 , in some implementations, the plate 311 includes a first plate 311a, an intermediate plate 311b, and a second plate 311c, which are stacked one on top of the other. The intermediate plate 311b is located between the first plate 311a and the second plate 311c, and the thickness of the intermediate plate 311b is greater than that of the first plate 311a and the second plate 311c. It is understood that multiple conductive layers 3111 and multiple dielectric layers 3112 are alternately stacked within the plate 311, and the intermediate plate 311b is the thickest dielectric layer 3112 located near the longitudinal center of the plate 311. The first plate 311a and the second plate 311c both include multiple conductive layers 3111 and multiple dielectric layers 3112. The electronic components 313 may be disposed within either the conductive layers 3111 or the dielectric layers 3112. The present embodiment does not limit the placement of the electronic components 313.

[0094] In the implementation in which the electronic component 313 is disposed within the dielectric layer 3112, the electronic component 313 includes a physical electronic component 3133. Since the thickness of the intermediate plate 311b is greater than that of the other dielectric layers 3112, the physical electronic component 3133 can be disposed within the intermediate plate 311b. In some embodiments, one pin of the physical electronic component 3133 is connected to the conductive portion 312, and another pin is connected to the third connection portion 34. In other embodiments, one pin of the physical electronic component 3133 can be configured to a preset potential, and the other pin is connected to the third connection portion 34. It is understood that the intermediate plate 311b can include multiple physical electronic components 3133, the multiple physical electronic components 3133 being arranged at intervals, and the multiple physical electronic components 3133 can be the same or different. In this way, the dielectric layer is fully utilized and the internal space of the package substrate is saved.

[0095] In some implementations, at least one conductive layer 3111 within the board 311 is grounded, and at least one conductive layer 3111 is connected to a target power source. In implementations where one end of the electronic component 313 is configured to have a preset potential, one end of the electronic component 313 can be connected within the board 311 to the conductive layer 3111 having the preset potential.

[0096] In the above implementation, the electronic component 313 is surrounded by at least one grounded conductive layer 3111 and wrapped with vias, thereby realizing self-shielding of the electronic component 313. Compared with the electronic component 313 being integrated on the substrate 21, there is no need to set up an additional shielding cavity for the electronic component 313, thereby avoiding the risk of EMI introduced by the electronic component 313.

[0097] Continuing with Figures 21 and 22, in some implementations, the board 311 includes multiple conductive layers 3111 and multiple dielectric layers 3112, with the multiple conductive layers 3111 and the multiple dielectric layers 3112 being alternately stacked. The electronic component 313 includes an inductor 141, which includes a first coil 313a and a second coil 313b arranged in series, with at least a portion of the first coil 313a located within one conductive layer 3111 and at least a portion of the second coil 313b located within another conductive layer 3111. It will be appreciated that in some implementations, the first coil 313a and the second coil 313b are located on different layers, connected by package layer-switching vias. This allows the inductor's inductance to be adjusted by varying the winding lengths of the first and second coils, facilitating the inductor's ability to bias DC signals. Furthermore, the inductor is located within the board 311, achieving self-shielding, preventing the risk of EMI introduced by the inductor. This eliminates the need for an additional shielding cavity, as compared to integrating the inductor on the substrate.

[0098] Referring to FIG. 22 , in some implementations, the projection of the first coil 313a is located within the projection of the second coil 313b in a plane parallel to the plate 311 . It is understood that the embodiments of the present application do not restrict the winding direction of the first coil 313a and the winding direction of the second coil 313b. Taking the orientation shown in FIG. 22 as an example, the first coil 313a with a clockwise winding direction is connected to the second coil 313b with a clockwise winding direction via a package layer switching via. Taking the orientation shown in FIG. 23 as an example, the first coil 313a with a counterclockwise winding direction is connected to the second coil 313b with a counterclockwise winding direction via a package layer switching via. It is understood that the positional relationship between the first coil 313a and the second coil 313b also includes that, in a plane parallel to the plate 311 , at least a portion of the projection of the first coil 313a can overlap with at least a portion of the projection of the second coil 313b. In this way, the inductor in the package substrate can be wound in multiple layers, reducing the winding area of ​​each layer and saving space inside the package substrate.

[0099] Referring to FIG. 24 , in other implementations, the first coil 313a and the second coil 313b are located on the same layer, that is, the first coil 313a and the second coil 313b are located in the same plane parallel to the plate 311. Taking the orientation shown in FIG. 24 as an example, the first coil 313a is wound counterclockwise, and the second coil 313b is wound clockwise. One end of the first coil 313a is connected to one end of the second coil 313b, and the other end of the first coil 313a and the other end of the second coil 313b serve as the two ends of the winding inductor 141, respectively. It should be understood that this embodiment is not limited to this embodiment, and the winding directions of the first coil 313a and the second coil 313b can be other combinations. For example, the winding direction of the first coil 313a can be clockwise, and the winding direction of the second coil 313b can be counterclockwise. The combination of the first coil 313a and the second coil 313b can include two clockwise coils, two counterclockwise coils, etc. In this way, the inductance value can be adjusted by changing the winding lengths of the first coil 313a and the second coil 313b, thereby facilitating the implementation of the inductor bias DC signal function.

[0100] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A packaging substrate, characterized in that: include: A plate body, wherein a first connection portion is provided on a first surface of the plate body, a second connection portion is provided on a second surface of the plate body, and the first surface and the second surface are arranged opposite to each other; A conductive portion, the conductive portion being disposed in the plate body, one end of the conductive portion being connected to the first connecting portion, and the other end of the conductive portion being connected to the second connecting portion; An electronic component, the electronic component being disposed within the board body and spaced apart from the conductive portion; A third connecting portion is provided on the second surface, and the electronic component is connected to the third connecting portion.

2. The packaging substrate according to claim 1, wherein: One end of the electronic component is connected to the conductive portion, and the other end of the electronic component is connected to the third connecting portion.

3. The packaging substrate according to claim 1, wherein: One end of the electronic component is configured to have a preset potential, and the other end of the electronic component is connected to the third connection portion.

4. The packaging substrate according to any one of claims 1 to 3, wherein: The conductive portion includes a first conductive portion and a second conductive portion, the first conductive portion and the second conductive portion are spaced apart, and there are two first connecting portions and two second connecting portions. One end of the first conductive portion is connected to one first connecting portion, and the other end of the first conductive portion is connected to one second connecting portion. One end of the second conductive portion is connected to another first connecting portion, and the other end of the second conductive portion is connected to another second connecting portion. The electronic component includes a first electronic component and a second electronic component, the first electronic component is arranged corresponding to and spaced apart from the first conductive portion, and the second electronic component is arranged corresponding to and spaced apart from the second conductive portion; The third connecting parts include two, the first electronic component is connected to one third connecting part, and the second electronic component is connected to the other third connecting part.

5. The packaging substrate according to any one of claims 1 to 4, characterized in that: The electronic component includes at least one of an inductor, a capacitor, and a resistor.

6. The packaging substrate according to any one of claims 1 to 5, characterized in that: The board body includes multiple conductive layers and multiple dielectric layers, and the multiple conductive layers and the multiple dielectric layers are alternately stacked; the electronic component includes an inductor, and the inductor includes a first coil and a second coil arranged in series, at least a portion of the first coil is located in one of the conductive layers, and at least a portion of the second coil is located in another of the conductive layers.

7. The packaging substrate according to claim 6, wherein: In a plane parallel to the plate, the projection of the first coil is located within the projection of the second coil.

8. The packaging substrate according to any one of claims 1 to 5, characterized in that: The board body includes a first board body, an intermediate board body and a second board body which are stacked together. The intermediate board body is located between the first board body and the second board body. The thickness of the intermediate board body is greater than that of the first board body and the second board body. The electronic component is arranged in the intermediate board body.

9. An electronic device, characterized in that: include: A chip and a packaging substrate according to any one of claims 1 to 8, wherein the chip is arranged on the first surface and is electrically connected to the first connection portion.

10. A circuit board, characterized in that: include: A substrate and the electronic device according to claim 9, wherein the electronic device is provided on the substrate.

11. An electronic device, characterized in that: include: A battery and the circuit board according to claim 10, wherein the battery is electrically connected to the circuit board.

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