Solar cell and manufacturing method therefor

Abstract

The present application belongs to the technical field of semiconductor devices. Provided are a solar cell and a manufacturing method therefor. The solar cell comprises a silicon substrate and semiconductor layers, wherein the silicon substrate comprises a first surface and a second surface which are opposite to each other; the semiconductor layers are located on the first surface; a first semiconductor layer comprises a second structure area and a first structure area, the degree of crystallization of the first structure area being greater than that of the second structure area, and the second structure area being closer to the first surface than the first structure area; and the first semiconductor layer is made of at least one of amorphous silicon, nanocrystalline silicon and microcrystalline silicon. The semiconductor layers in the present application have crystallized structures, and thus the contact resistance between the semiconductor layers and a conductive material layer can be reduced, thereby improving current transmission characteristics, reducing the energy consumption during a current collection process, and improving the cell efficiency.

Description

Solar cell and method for manufacturing the same

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Chinese patent application No. 202410092536.4, filed with the Patent Office of China on January 23, 2024, entitled “A solar cell, its preparation method and battery assembly”, the priority of Chinese patent application No. 202410190935.4, filed with the Patent Office of China on February 20, 2024, entitled “A solar cell, its preparation method and battery assembly”, the priority of Chinese patent application No. 202410961507.7, filed with the Patent Office of China on July 16, 2024, entitled “Solar cell and its manufacturing method”, the priority of Chinese patent application No. 202411131776.7, filed with the Patent Office of China on August 16, 2024, entitled “A solar cell and its manufacturing method”, and the priority of Chinese patent application No. 2024111321, filed with the Patent Office of China on August 16, 2024. 14.1. The priority of the Chinese patent application entitled “A solar cell and its manufacturing method”, the priority of the Chinese patent application No. 202411231370.6 filed with the Chinese Patent Office on September 3, 2024, entitled “Solar cell and its manufacturing method”, the priority of the Chinese patent application No. 202411231916.8 filed with the Chinese Patent Office on September 3, 2024, entitled “Solar cell and its manufacturing method”, the priority of the Chinese patent application No. 202411231906.4 filed with the Chinese Patent Office on September 3, 2024, entitled “Solar cell and its manufacturing method”, and the priority of the Chinese patent application No. 202411230518.4 filed with the Chinese Patent Office on September 3, 2024, entitled “Solar cell and its manufacturing method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the technical field of semiconductor devices, and in particular, to a solar cell and a method for manufacturing the same. Background Art

[0004] Heterojunction cells offer advantages such as high conversion efficiency and a simple process structure. Conventional heterojunction cells are made by depositing intrinsic amorphous silicon layers on both sides of a silicon substrate, followed by doped amorphous silicon layers with different doping types. A transparent conductive film is then formed on top of the doped amorphous silicon layer, and finally the surface of the transparent conductive film is metallized to form metal electrodes.

[0005] Current transfer resistance significantly impacts the performance of heterojunction cells. To reduce this resistance and improve battery output, improvements can be made to the contact structure between the metal electrode and the transparent conductive film. For example, a seed layer can be formed on the surface of the metal electrode and the transparent conductive film to improve adhesion, or new materials such as alloys can be used as the metal electrode material. However, there is still a need to further reduce current transfer resistance. Summary of the Invention

[0006] In view of this, in order to at least partially solve at least one of the above-mentioned technical problems, the present application provides a solar cell and a method for manufacturing the same.

[0007] In order to achieve the above objectives, the technical solutions of this application are as follows:

[0008] According to an embodiment of one aspect of the present application, a solar cell is provided, comprising: a silicon substrate, comprising a first surface and a second surface relative to each other; a first semiconductor layer, located on the first surface of the silicon substrate, the first semiconductor layer comprising a second structure region and a first structure region, the degree of crystallization of the first structure region being greater than the degree of crystallization of the second structure region; wherein the second structure region is closer to the first surface than the first structure region, and the first semiconductor layer comprises at least one of amorphous silicon, nanocrystalline silicon, or microcrystalline silicon.

[0009] According to an embodiment of another aspect of the present application, a method for manufacturing a solar cell is provided, comprising: forming a semiconductor layer on a silicon substrate, wherein the material of the semiconductor layer comprises at least one of amorphous silicon, nanocrystalline silicon or microcrystalline silicon; processing the semiconductor layer using a first laser so that the degree of crystallization of at least a portion of the semiconductor layer becomes greater to form a crystallized region; wherein the semiconductor layer located in the crystallized region comprises a second structure region and a first structure region, and the degree of crystallization of the first structure region is greater than that of the second structure region; wherein the second structure region is closer to the first surface than the first structure region.

[0010] According to the embodiments of the present application, the solar cell provided by the present application can help reduce contact resistance due to partial crystallization of the semiconductor layer, freeing up space for thickening the intrinsic silicon layer, so that energy loss during current collection can be reduced while the passivation effect provided by the intrinsic silicon layer can be improved, thereby improving battery efficiency.

[0011] According to the embodiments of the present application, the crystallized structure of the semiconductor layer of the present application is formed by laser processing the semiconductor layer. It only requires adding the operation of applying laser to the semiconductor layer on the basis of the original battery process, which has the advantage of simple operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0013] FIG1 is a schematic diagram of a partial structure of a solar cell according to an embodiment of the present application;

[0014] FIG2 is a schematic diagram of a partial structure of a solar cell according to another embodiment of the present application

[0015] 3A is a cross-sectional transmission electron microscope (TEM) image of a doped amorphous silicon layer after the first laser treatment under laser condition 1 according to an embodiment of the present application;

[0016] 3B and 3C are respectively partial enlarged TEM images at different positions of FIG. 4A ;

[0017] FIG3D and FIG3E are respectively partial magnified TEM images of different grain portions in FIG4A ;

[0018] 4A is a surface scanning electron microscope (SEM) image of the doped amorphous silicon layer after the first laser treatment under laser condition 1 according to an embodiment of the present application;

[0019] 4B and 4C are respectively successively enlarged microscopic SEM images of the doped amorphous silicon layer in FIG. 4A ;

[0020] 4D to 4F are surface scanning electron microscope (SEM) images of the doped amorphous silicon layer of the present application after the first laser treatment under laser conditions 2 to 4;

[0021] 5A is a cross-sectional transmission electron microscope (TEM) image of an amorphous silicon layer after the first laser treatment under laser condition 1 according to another embodiment of the present application;

[0022] FIG5B is a partially enlarged TEM image of the grain portion on the top of the tower in FIG4A;

[0023] FIG. 5C is a top-down TEM image of the amorphous silicon layer of FIG. 5A .

[0024] 6A is a surface SEM image of an amorphous silicon layer after undergoing a first laser treatment under laser condition 1 according to another embodiment of the present application;

[0025] 6B is a cross-sectional TEM image of the amorphous noble layer after undergoing the first laser treatment under laser condition 1 according to yet another embodiment of the present application;

[0026] FIG7 is a side view of the overall structure of a solar cell according to another embodiment of the present application;

[0027] FIG8 is a transmission electron microscope image of the solar cell of FIG7 after laser crystallization;

[0028] 9 is a schematic top view of the positional relationship between the edge portion and the main portion of the first-type doped amorphous silicon layer or the second-type doped amorphous silicon layer according to yet another embodiment of the present application;

[0029] FIG10 is a side view of the overall structure of a solar cell according to another embodiment of the present application;

[0030] 11 is a schematic top view of the positional relationship between the first-type doped amorphous silicon layer and the second-type doped polysilicon layer according to another embodiment of the present application;

[0031] FIG12A is a schematic diagram of the manufacturing process of a solar cell according to an embodiment of the present application;

[0032] FIG12B is a diagram showing the contact resistance test results of the doped polysilicon layer 103 after being acted upon by the first laser according to an embodiment of the present application;

[0033] 13A to 13E are schematic diagrams of a manufacturing process of a solar cell according to another embodiment of the present application;

[0034] FIG14 is a schematic diagram of a partial structure of a solar cell according to an embodiment of the present application. DETAILED DESCRIPTION

[0035] In order to make the objectives, technical solutions and advantages of this application more clear, this application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0036] The terms used herein are only for describing specific embodiments and are not intended to limit this application. The terms "comprise", "include" and the like used herein indicate the presence of features, steps, operations and / or components, but do not exclude the presence or addition of one or more other features, steps, operations or components. All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having meanings consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0037] The relative position between two components (such as film layers or regions) mentioned in this application, such as "above", "up" or "above", may refer to the two components being in direct contact, or may refer to the two components being in indirect contact. Similarly, the relative position between two components mentioned in this application, such as "below", "down" or "below", may refer to the two components being in direct contact, or may refer to the two components being in indirect contact. For example, when one of the components (such as film layers or regions) is referred to as "on another component", it may be directly on the other component, or there may be other components between the two. On the other hand, when a component is referred to as "directly on another component", there is no component between the two. In addition, when one of the components is referred to as "on another component", the two have an up-down relationship in the top-down direction, and this component may be above or below the other component, so that this up-down relationship depends on the orientation of the device.

[0038] For solar cells, improvements are usually made to the contact structure between, for example, the metal electrode and the transparent conductive film layer in order to reduce contact resistance and thus improve cell performance. However, improvements to the contact structure of the semiconductor layer are less often considered. In the process of implementing the concepts of this application, it was discovered that by laser processing the semiconductor layer on the silicon substrate, crystallization modification of the semiconductor layer can be achieved, such that the semiconductor layer exhibits a specific crystallization morphology along the direction away from the surface of the silicon substrate. Further experiments have verified that laser processing of the semiconductor layer to form a specific crystallization morphology can effectively improve the current transmission characteristics between the semiconductor layer and the conductive material layer, such as the transparent conductive layer or the metal electrode layer, thereby improving cell performance.

[0039] Specifically, according to an embodiment of one aspect of the present application, a solar cell is provided. Figure 1 is a schematic diagram of a partial structure of a solar cell according to an embodiment of the present application, and Figure 2 is a schematic diagram of a partial structure of a solar cell according to another embodiment of the present application. As shown in Figures 1 and 2, the solar cell according to the embodiment of the present application mainly includes a silicon substrate 101 and a first semiconductor layer 102. The silicon substrate includes a first surface 101a and a second surface relative to each other. The first semiconductor layer 102 is located on the first surface 101a. The first semiconductor layer 102 includes a second structure region 102b and a first structure region 102a. The degree of crystallization of the first structure region 102a is greater than the degree of crystallization of the second structure region 102b; wherein the second structure region 102b is closer to the first surface 101a than the first structure region 102a, and the first semiconductor layer 102 includes at least one of amorphous silicon, nanocrystalline silicon or microcrystalline silicon.

[0040] It should be noted that the term "degree of crystallization" is used to characterize the crystallization rate, grain size, and number of grains. Generally speaking, a greater degree of crystallization indicates a greater crystallization rate, grain size, and / or number of grains. For example, when the first semiconductor layer is a nanocrystalline silicon layer (this nanocrystalline silicon layer generally still contains a portion of amorphous silicon, which is unavoidable, but the amorphous silicon content is relatively low, as is known in the art), the first structure region 102a, which has a greater degree of crystallization, has a greater crystallization rate and / or grain size than the second structure region 102b. When the first semiconductor layer is an amorphous silicon layer (this amorphous silicon layer may contain a small amount of nanocrystalline silicon, but the content of this nanocrystalline silicon is very small, for example, less than 5%, as is known in the art), the first structure region 102a, which has a greater degree of crystallization, will generate lattice-ordered grains within it, increasing its degree of crystallization, while the second structure region 102b, which has a lesser degree of crystallization, will remain amorphous silicon material and will not have generated grains after laser treatment or other treatment. For the sampling of crystallization degree, since the sampling in the area with a higher degree of crystallization is also local rather than in the entire laser processing area, the sampling area should be a square area greater than or equal to 5μm*5μm, and the crystallization degree within such an area is compared.

[0041] Preferably, the crystallinity of the second structure region 102b is greater than or equal to 10%, and / or the difference between the crystallinity of the second structure region and the crystallinity of the first structure region is less than or equal to 10%. The higher crystallinity of the second structure region 102b can ensure lower contact resistance, while the difference between the crystallinity of the second structure region and the crystallinity of the first structure region can ensure transmission continuity of the first semiconductor layer and increase current collection efficiency.

[0042] According to an embodiment of the present application, the first structure region 102a and / or the second structure region 102b may be located on at least a portion of the first surface of the silicon substrate 101, that is, may cover the first surface 101a of the silicon substrate 101, as shown in FIG1 , or may be located on a partial area of ​​the first surface 101a of the silicon substrate 101, for example, on the top of at least one pyramid structure of the silicon substrate 101 as indicated by the dotted line, as shown in FIG2 .

[0043] Furthermore, the first structure region 102a and the second structure region 102b can be determined based on the distinct stratification of the crystallization degree of the first semiconductor layer 102. For example, the first structure region 102a includes nanocrystalline silicon, while the second structure region 102b may not include or not significantly include nanocrystalline silicon. For example, a crystallization rate of less than 5%, preferably less than 1%, can be defined as not significantly including nanocrystalline silicon. Of course, the first structure region 102a and the second structure region 102b can also be determined based on the material stratification of the first semiconductor layer 102. For example, when the first semiconductor layer 102 is an amorphous silicon layer, it can be stratified into intrinsic silicon and doped silicon.

[0044] According to an embodiment of the present application, the silicon substrate 101 can be an N-type or P-type crystalline silicon substrate, for example, it can be a semiconductor material selected from single crystal silicon, polycrystalline silicon, and microcrystalline silicon, preferably an N-type or P-type single crystal silicon substrate. The conversion efficiency of cells based on single crystal silicon substrates is higher than that of other types, such as polycrystalline silicon cells. By introducing donor impurities such as phosphorus (P), arsenic (As), or antimony (Sb) into these semiconductor materials, an N-type crystalline silicon substrate is obtained, or by introducing acceptor impurities such as boron (B), aluminum (Al), or gallium (Ga) into these semiconductor materials, a P-type crystalline silicon substrate is obtained.

[0045] According to embodiments of the present application, at least a portion of the first semiconductor layer 102 may be doped or undoped. In the case of doping, the doping type may be N-type or P-type, specifically determined by the cell type and the doping type of the silicon substrate. Similar to the silicon substrate 101, different doping types are achieved by introducing donor impurities or acceptor impurities into the bulk material of the first semiconductor layer 102.

[0046] According to the embodiments of the present application, the solar cell type of the present application is mainly applicable to the heterojunction cell type, which can be a double-sided heterojunction (Heterojunction with Intrinsic Thin-layer, abbreviated as HJT) cell, a back contact heterojunction (Heterojunction Back Contact, abbreviated as HBC) cell, a hybrid HBC cell, such as a hybrid cell combined with TBC (TopCon-BackContact)-HJT, etc. As long as the cell needs to improve the contact performance between the first semiconductor layer and the conductive material layer, it should be applicable.

[0047] According to the embodiments of the present application, the applicant has discovered through experiments that laser treatment of the first semiconductor layer can increase the degree of crystallization in a portion of the first semiconductor layer away from the silicon substrate, thereby facilitating a reduction in the contact resistance of the first semiconductor layer. Meanwhile, other portions of the first semiconductor layer with a lesser degree of crystallization can ensure the passivation effect of the first semiconductor layer, thereby achieving a balance between contact resistance and passivation effect.

[0048] According to an embodiment of the present application, the second structure region preferably includes a first intrinsic silicon layer having a thickness of 5 to 30 nm, for example, 5 nm, 8 nm, 10 nm, 13 nm, 15 nm, 18 nm, 20 nm, 25 nm, 28 nm, 30 nm, etc., preferably a first intrinsic silicon layer of 8 to 20 nm. Due to the reduction in the contact resistance of the first semiconductor layer 102, space is provided for increasing the thickness of the first intrinsic silicon layer, which helps to improve the passivation effect of the first intrinsic silicon layer, thereby improving the battery efficiency.

[0049] According to an embodiment of the present application, there are a plurality of crystal grains in the first semiconductor layer 102 , and the maximum size of the plurality of crystal grains is smaller than the thickness of the first semiconductor layer 102 .

[0050] In terms of grain size, the first portion of the first semiconductor layer 102 contains grains, and the maximum size of the grains can be equal to the thickness of the first portion. In this case, the first portion of the first semiconductor layer 102 has a high conductivity, which can further reduce the transmission loss of carriers collected in the first semiconductor layer 102 to the conductive material. In the actual manufacturing process, the larger the grain size in the first portion of the first semiconductor layer 102, the higher the temperature during the crystallization process of the first portion of the first semiconductor layer 102, which in turn leads to a greater amount of hydrogen overflow in the first semiconductor 102, thereby reducing the passivation effect of the second structure region 102b on the silicon substrate. Therefore, when the grain size in the first portion of the first semiconductor layer 102 is smaller than the thickness of the first portion, the corresponding crystallization temperature of the first semiconductor layer 102 is lower, so that the portion of the first semiconductor layer 102 where the grains are not extended and grown has the effect of passivating the semiconductor substrate, which is conducive to achieving a balance between the passivation effect and transmission loss of the first semiconductor layer 102, further improving the operating performance of the solar cell.

[0051] According to an embodiment of the present application, the material of the second structure region 102b includes intrinsic amorphous silicon, and the material of the first structure region 102a includes amorphous silicon and nanocrystalline silicon, but the possibility of including microcrystalline silicon is small, or even so small that it is considered that there is no microcrystalline silicon. As a result, the crystallization rate of the first structure region 102a is greater than that of the second structure region 102b, thereby taking into account both the passivation effect and the improvement of contact resistance. Further optionally, the material of the first structure region 102a includes amorphous silicon and nanocrystalline silicon with a grain size of 5 to 25 nm (for example, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, etc.).

[0052] According to an embodiment of the present application, the first surface 101a of the silicon substrate 101 may be a polished area having a pyramid base structure or a velvet area having a pyramid structure, and the morphology of the first semiconductor layer 102 formed in different areas is different, specifically in terms of crystallization structure and porous morphology. The pyramid base structure of the polished area referred to in the present application may be a raised, shorter prism structure or a recessed, shallow groove structure.

[0053] Specifically, as shown in FIG1 , taking the polished region having a pyramid base structure on the first surface 101a of the silicon substrate 101 as an example, a first semiconductor layer 102 is formed on the polished region, and the crystallized structure is primarily located in a portion of the first semiconductor layer 102 away from the first surface 101a. In this case, the first structure region 102a and the second structure region 102b can be divided and determined based on the morphology and / or material of the first semiconductor layer 102. The morphology division can be, for example, crystallized and uncrystallized structures, and the material can be, for example, intrinsic silicon and doped silicon.

[0054] Further optionally, the first structure region 102a and the second structure region 102b may be determined based on distinct stratification of the degree of crystallization of the first semiconductor layer 102. In this case, the second structure layer 102b may include an intrinsic silicon layer and may further include a portion of a doped silicon layer, and the first structure layer 102a may include at least a portion of a doped silicon layer.

[0055] Of course, the first structure region 102a and the second structure region 102b can also be layered based on intrinsic silicon and doped silicon. Since for the polishing area, the crystallized structure of the amorphous silicon layer 102 is mainly located in the doped silicon layer, it is also considered that the degree of crystallization of the first structure region 102a is greater than that of the second structure region 102b.

[0056] For example, taking the first semiconductor layer 102 as an amorphous silicon layer, a transmission electron microscope was used to observe the cross-sectional micromorphology of the first semiconductor layer 102 after the first laser treatment. Specifically, a first intrinsic amorphous silicon layer (abbreviated as ia-Si) and a P-type doped amorphous silicon layer (abbreviated as pa-Si) were first deposited sequentially on the polished surface of the silicon substrate 101. The P-type doped amorphous silicon layer with a thickness of 10 to 40 nm was then treated using the first laser of laser condition 1 to form a P-type doped amorphous silicon layer with a porous structure. SiN and Pt layers were then sequentially deposited on the surface of the P-type doped amorphous silicon layer to obtain a silicon wafer suitable for inspection by transmission electron microscopy (TEM). Figure 3A is a cross-sectional transmission electron microscope (TEM) image of the amorphous silicon layer of the embodiment of the present application after the first laser treatment of laser condition 1. Figures 3B and 3C are enlarged TEM images of different locations in Figure 3A. Figures 3D and 3E are enlarged TEM images of different grain portions in Figure 3A, respectively. SiN is a protective layer used during testing.

[0057] As shown in Figures 3A to 3E , the first semiconductor layer 102 partially crystallizes after the first laser treatment, producing a layered structure, namely a first structure region 102a and a second structure region 102b. As shown in Figure 3B , the rectangular box encircles the second structure region 102b (i.e., i,pa-Si), with the first structure region 102a (i.e., pa-Si) located above the rectangular box. Circular grains can be observed in the first structure region 102a, as shown in Figures 3B and 3C , while an ordered lattice structure can be observed in the grains, as shown in Figures 3D and 3E , indicating that the amorphous silicon in the first structure region 102a has partially crystallized, and this ordered lattice structure is nanocrystalline silicon. It can be seen that the material of the first structure region 102a can include not only the retained amorphous silicon but also crystallized nanocrystalline silicon. This is where laser treatment of an amorphous silicon layer surpasses that of a nanocrystalline or microcrystalline silicon layer. This allows the amorphous silicon layer to be partially crystallized, achieving similar current collection effects as nanocrystalline and microcrystalline silicon layers, while also taking into account the advantages of amorphous silicon layers, such as fast deposition rate and low cost.

[0058] Preferably, the crystallization degree of the first structure region 102a and the second structure region 102b is gradual, that is, the crystallization degree of the first semiconductor layer 102 gradually increases along the first surface away from the silicon substrate, and the grain size also gradually increases.

[0059] According to an embodiment of the present application, the first semiconductor layer 102 located on the polished area can form a porous structure while crystallizing. That is, the first semiconductor layer 102 located on the polished area can further have a porous structure, thereby increasing the contact area between the first semiconductor layer 102 and the conductive material layer, which helps to further improve the current transmission characteristics of the first semiconductor layer 102. Further optionally, the first structure area 101a has a porous structure, and the second structure area 102b has a porous structure or a non-porous structure, thereby facilitating contact with the conductive material layer.

[0060] Further optionally, as shown in FIG1 , the solar cell of the present application may further include a transparent conductive layer 103, serving as the aforementioned conductive material layer, located on the surface of the first semiconductor layer 102 away from the silicon substrate 101. The transparent conductive layer 103 may contact the porous structure of the first semiconductor layer 102, specifically, the porous structure of the first structure region 101a, to increase the contact area and improve the current transmission performance between the first semiconductor layer 102 and the transparent conductive layer 103. The transparent conductive layer 103 completely covers the first structure region 102a, so that the region with a higher degree of crystallization can completely overlap with the transparent conductive layer 103, thereby reducing the contact resistance.

[0061] According to an embodiment of the present application, through appropriate laser processing conditions, a porous structure can be formed in a portion of the first semiconductor layer 101. It is speculated that after the laser energy is absorbed by the film layer, the film layer temperature increases, a molten state occurs, and hydrogen in the film layer escapes, thereby generating a porous structure. Therefore, it is proposed to use laser processing to form a porous structure in the first semiconductor layer 102. Since the first semiconductor layer 102 has a porous structure, the contact area with the transparent conductive layer 103 can be increased, thereby reducing the current transmission resistance between the transparent conductive layer 103 and the transparent conductive layer 103, thereby reducing energy loss during the current collection process and improving battery efficiency.

[0062] According to an embodiment of the present application, the first structure region 102a has a first porous structure, and the second structure region 102b has a second porous structure, wherein the pore size of the second porous structure is smaller than that of the first porous structure. Because the porous structure can weaken the passivation effect and reduce the current collection efficiency of the solar cell, by setting the pore size of the second porous structure to be smaller than that of the first porous structure, the contact performance of the first semiconductor layer 102 can be improved while maintaining the passivation effect of the first semiconductor layer 102.

[0063] Further optionally, the first porous structure includes a plurality of first pores extending therethrough, and the second porous structure includes a plurality of second pores, with the plurality of second pores emerging from the plurality of first pores. The through-hole morphology of the first structural region 102a enables the transparent conductive layer 103 to contact the first structural region 102a and the second structural region 102b, respectively, thereby increasing the contact area with the transparent conductive layer 104 while ensuring that the formation of the porous morphology of the first structural region 102a does not adversely affect the layer structure located below the second structural region 102b. This arrangement is more conducive to achieving a balanced improvement in contact performance and passivation effect.

[0064] For ease of illustration, the surface morphology of the first semiconductor layer 102, also taking an amorphous silicon layer as an example, was observed using a scanning electron microscope. FIG4A is a surface scanning electron microscope (SEM) image of the amorphous silicon layer after the first laser treatment under laser condition 1 according to an embodiment of the present application. FIG4B and FIG4C are respectively magnified microscopic SEM images of the amorphous silicon layer in FIG4A . As shown in FIG4A to FIG4C , the darker areas are the second structure regions 102b, and the lighter areas are the first structure regions 102a, showing a distinct porous structure.

[0065] According to embodiments of the present application, the second structural region 102b may have a non-porous or porous morphology. Preferably, as shown in FIG4C , the second structural region 102b is configured to have a second porous structure, wherein the pore size of the second porous structure is smaller than the pore size of the first porous structure. Further preferably, as indicated by the circle in FIG4C , the second structural region 102b has a plurality of second pores, which are exposed from the plurality of first pores, thereby forming a layered and nested porous structure between the first structural region 102a and the second structural region 102b.

[0066] According to an embodiment of the present application, the second structural region 102b is constructed to have a second porous structure and to form a layered and nested porous structure with the first structural region 102a, which can further increase the contact area with the transparent conductive layer 103, thereby helping to reduce the current transfer resistance and achieve improved battery efficiency.

[0067] According to an embodiment of the present application, further optionally, the pore size of the first porous structure is less than or equal to 1 μm, for example, the pore size can be less than 1 μm, less than 0.8 μm, less than 0.5 μm, less than 0.3 μm, or less than 0.1 μm, and the pore size is preferably less than or equal to less than 0.3 μm.

[0068] According to an embodiment of the present application, further optionally, the pore size of the second porous structure is less than or equal to 300 nm, for example, the pore size may be less than 0.3 μm, less than 0.1 μm, less than 0.08 μm, less than 0.06 μm, or less than 0.04 μm, and the pore size is preferably less than or equal to 0.3 μm.

[0069] It should be noted that the "pore size" of the first porous structure or the second porous structure refers to the pore size range of the main pores of the porous structure. For a pore, the pore size can be the diameter of the shape of the pore along the surface direction after it is equivalent to a circle. The main pores can be pores that account for more than 50% of the total number of pores, preferably more than 80%, and more preferably more than 90%.

[0070] According to the embodiment of the present application, by controlling the pore size of the first semiconductor layer 102 within the above range, it is more conducive to improving the contact resistance and enhancing the battery efficiency.

[0071] According to an embodiment of the present application, the first surface 101a of the silicon substrate 101 may be a velvet area having multiple pyramid structures, as shown in Figure 2, the first structure area 102a and the second structure area 102b are located on a partial area of ​​the first surface 101a, and further, may be determined based on material layering, for example, the first structure area 102a is a doped silicon layer, the second structure area 102b is an intrinsic silicon layer, and the degree of crystallization of the doped silicon layer is greater than that of the intrinsic silicon layer.

[0072] Furthermore, along the direction away from the first surface 101a, the pyramid structure includes a base 1011 and a top 1012; wherein the first structure region 102a and the second structure region 102b are both located on the top 1012, and the degree of crystallization of the second structure region 102b located on the top 1012 is greater than the degree of crystallization of the first semiconductor layer 102 located on the base 1011.

[0073] For example, taking the first semiconductor layer 102 as an amorphous silicon layer as an example, a transmission electron microscope is used to observe the cross-sectional micromorphology of the first semiconductor layer 102 after the first laser action. Specifically, a first intrinsic amorphous silicon layer (abbreviated as ia-Si) and a P-type doped amorphous silicon layer (abbreviated as pa-Si) are first deposited in sequence on the velvet surface of the silicon substrate 101; then the P-type doped amorphous silicon layer with a thickness of 10 to 40 nm is treated using the first laser of laser condition 1 to form a P-type doped amorphous silicon layer with a crystallized structure. Then, SiN and Pt layers are deposited in sequence on the surface of the P-type doped amorphous silicon layer to obtain a silicon wafer suitable for detection by transmission electron microscopy (TEM). Figure 5A is a cross-sectional transmission electron microscope (TEM) image of an amorphous silicon layer after being treated with the first laser of laser condition 1 according to another embodiment of the present application, Figure 5B is a locally enlarged TEM image of the grain portion on the top of the tower in Figure 5A, and Figure 5C is a top-down TEM image of the amorphous silicon layer in Figure 5A.

[0074] As shown in Figures 5A and 5B, it can be observed that the first semiconductor layer 102 undergoes partial crystallization after the first laser treatment, and a crystalline structure different from that shown in Figures 3A and 3B is produced. Specifically, the degree of crystallization increases primarily in the first semiconductor layer 102 above the spire 1012, further including nanocrystalline silicon. Furthermore, it can be observed that the degree of crystallization (i.e., crystallization rate, number of grains, and grain size) of the first structure region 102a is greater than that of the second structure region 102b. As shown in Figure 5A, the first semiconductor layer 102 located above the spire 1012 is circled, and circular grains can be observed. As shown in Figure 5B, the grains of the first semiconductor layer 102 located above the spire exhibit an ordered lattice structure, indicating that the amorphous silicon located above the spire 1012 has undergone partial crystallization, and this ordered lattice structure is nanocrystalline silicon. Similarly, it has been found that the partial crystallization of the first semiconductor layer 102 can help improve current collection. The thickness of the first structure region 102a can be greater than 25 nm, that is, it can be greater than 25 nm away from the silicon substrate pyramid surface in the thickness direction of the first semiconductor layer 102, and it only includes a doped silicon layer. The thickness of the second structure region 102b can be less than 15 nm, that is, it can be less than 15 nm close to the silicon substrate pyramid surface in the thickness direction of the first semiconductor layer 102. Preferably, there is no obvious interface between the first structure region 102a and the second structure region 102b in the pyramid structure (the same applies to the pyramid top with a hole structure). As shown in FIG5A, the degree of crystallization of the first semiconductor layer 102 gradually increases along the pyramid surface away from the silicon substrate, and the grain size also gradually increases.

[0075] According to the embodiments of the present application, experiments have shown that a polished surface with a pyramidal base structure on the silicon substrate 101 is conducive to the formation of a porous structure in the first semiconductor layer 102 thereon, while a textured surface is less likely to produce a porous structure. However, by selecting appropriate laser treatment conditions, it is still possible to manipulate the formation of a porous structure in specific areas of the first semiconductor layer 102 on the textured first surface.

[0076] Further optionally, the first semiconductor layer 102 located on the top of the tower 1012 can form a porous structure or a non-porous structure while crystallizing. The first semiconductor layer 102 with a non-porous structure is easier to obtain by laser processing. As shown in Figure 5C, no obvious porous structure is observed in the first semiconductor layer 102 located on the top of the tower.

[0077] Further optionally, as shown in FIG5C , the first semiconductor layer 102 located on the pyramid structure has a side surface extending from the top to the bottom; wherein, in the extension direction of the side surface, the ratio between the maximum extension length L1 of the first semiconductor layer located on the top of the pyramid and the length L2 of the side surface is less than or equal to 0.3, for example, it can be 0.05, 0.1, 0.15, 0.2, 0.25, or 0.3. With this configuration, the first semiconductor layer located on the base of the pyramid can mainly play a passivation role, while the first semiconductor layer located on the top of the pyramid can also optimize contact performance.

[0078] In other embodiments, by selecting appropriate laser processing conditions, the first semiconductor layer 102 located on the top of the tower 1012 can form a porous structure 102c. The first semiconductor layer 102 with the porous structure 102c is more conducive to further increasing the contact area between the first semiconductor layer 102 and the transparent conductive layer, which helps to further improve the current transmission characteristics of the first semiconductor layer 102.

[0079] According to an embodiment of the present application, in order to further illustrate the porous structure of the first semiconductor layer 102 of the present application, Figure 6A is a surface SEM image of the doped amorphous silicon layer of another embodiment of the present application after the first laser treatment under laser condition 1; Figure 6B is a cross-sectional TEM image of the doped amorphous silicon layer of another embodiment of the present application after the first laser treatment under laser condition 1.

[0080] As shown in Figures 6A and 6B, at least one of the holes included in the porous structure is a blind hole that does not penetrate the first semiconductor layer 102. Since the portion of the first semiconductor layer 102 corresponding to the blind hole still retains a certain thickness, it is possible to passivate a portion of the surface of the silicon substrate 101, thereby achieving both improved current transmission performance and passivation effect. Furthermore, optionally, the pore diameter of at least one hole included in the porous structure 102c is less than 100 nm, for example, less than or equal to 80 nm, less than or equal to 60 nm, less than or equal to 50 nm, etc. As shown in Figure 6A, the first semiconductor layer located on the pyramid structure has a side surface extending from the top of the pyramid to the bottom of the pyramid; wherein, along the extension direction of the side surface, the ratio between the distribution length L1 of the porous structure 102c on the side surface and the length L2 of the side surface is less than or equal to 0.5. For example, it can be 0.05, 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, 0.5, etc. With such an arrangement, the first semiconductor layer located on the tower base can mainly play a passivation effect, while the first semiconductor layer located on the tower top can optimize the contact performance.

[0081] As shown in FIG6C , the thickness of the portion of the first semiconductor layer 102 not provided with the porous structure 102c is greater than or equal to 10 nm; and / or the thickness of the portion of the first semiconductor layer 102 not provided with the porous structure is less than or equal to 45 nm. For example, the thickness of the first semiconductor layer can be 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, etc.

[0082] On the one hand, because the light absorption intensity of the film decreases exponentially with depth, the thicker the film, the lower the interface temperature between the silicon substrate and the first semiconductor layer 102 when the surface film reaches the same high temperature, and the less damage to the passivation. This can avoid the situation where the laser treatment causes the silicon substrate 101 and the first semiconductor layer 102 to overheat when the thickness is too thin, resulting in a poor passivation effect. On the other hand, as the film becomes thicker, it helps to slow down heat dissipation and is more conducive to achieving a high temperature on the film surface.

[0083] According to an embodiment of the present application, as shown in Figures 1 and 2 , the solar cell may further include an electrode 104, which is located on the surface of the transparent conductive layer 103. The electrode 104 may be made of, for example, silver, copper, silver-coated copper, aluminum, or the like, and may be patterned by vacuum evaporation, electroplating, screen printing, or the like.

[0084] According to an embodiment of the present application, along a direction parallel to the first surface 101a, the first semiconductor layer 102 includes a main portion and an edge portion adjacent to the periphery of the main portion, and the main portion has a higher degree of crystallization than the edge portion. Here, "adjacent" means that the main portion and the edge portion are in contact, thereby forming the first semiconductor layer 102 as a whole.

[0085] For example, taking the main body portion as an example, which is roughly a strip or rectangle extending along the first direction, the edge portion can be distributed on both side edges of the main body portion along the first direction, or distributed on both side edges of the main body portion along a second direction perpendicular to the first direction, or can be surrounded by the periphery of the main body portion to form a ring shape.

[0086] Such an arrangement can, on the one hand, reduce damage to the thinner edge portion caused by, for example, laser processing to ensure the passivation effect, and on the other hand, can further isolate defects in the edge portion to suppress carrier recombination.

[0087] According to the embodiment of the present application, the solar cell of the present application is further explained by taking a double-sided heterojunction cell as an example. Figure 7 is a side view of the overall structure of a solar cell according to another embodiment of the present application. As shown in Figures 1 and 7, the silicon substrate 101 includes a first surface 101a and a second surface 101b relative to each other, wherein the first surface 101a of the silicon substrate 101 is a polished surface containing a pyramid base structure, which can be used as a backlight surface. At this time, the first structure area 102a includes a first type doped amorphous silicon layer 1021a, which is located on the first surface 101a of the silicon substrate 101, and the second structure area 102b includes a first intrinsic amorphous silicon layer 1021b, which forms an amorphous silicon layer with the first type doped amorphous silicon layer 1021a. The amorphous silicon layer serves as the first semiconductor layer 102.

[0088] Figure 8 is a transmission electron microscope image of the solar cell shown in Figure 7 after laser crystallization. As shown in Figure 8, under the action of the laser, the amorphous silicon in the solar cell of this embodiment, located on the side of the first semiconductor layer 102 closest to the first transparent conductive layer 103a (i.e., the side of the first semiconductor layer 102 away from the first surface 101a), is converted into crystallized silicon.

[0089] According to an embodiment of the present application, the thickness of the first-type doped amorphous silicon layer 1021 a is 10-45 nm, for example, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, etc.

[0090] The thickness of the first-type doped amorphous silicon layer 1021a is within the above range. On the one hand, because the light absorption intensity of the film decreases exponentially with depth, the thicker the film, the lower the interface temperature between the silicon substrate and the first intrinsic amorphous silicon layer when the surface film reaches the same high temperature, and the weaker the passivation damage. This can avoid the situation where the laser treatment causes the silicon substrate 101 and the first intrinsic amorphous silicon layer 1021b to overheat when the thickness is too thin, resulting in a poor passivation effect. On the other hand, as the film thickness increases, it helps to reduce heat dissipation and is more conducive to achieving a high temperature on the film surface.

[0091] As shown in FIG7 , according to an embodiment of the present application, the solar cell further includes a second intrinsic amorphous silicon layer 1022 b and a second-type doped amorphous silicon layer 1022 a sequentially disposed on the second surface 101 b . The two layers together form another amorphous silicon layer, namely, a second semiconductor layer 102 ′. The second semiconductor layer 102 ′ may or may not have a crystallized structure similar to that of the first semiconductor layer 102 .

[0092] When the second semiconductor layer 102' adopts a crystallized structure similar to that of the first semiconductor layer 102, the solar cell further includes a second semiconductor layer 102' located on the second surface 101b. The second semiconductor layer 102' includes a fourth structure region (i.e., a second intrinsic amorphous silicon layer 1022b) and a third structure region (i.e., a second-type doped amorphous silicon layer 1022a). The degree of crystallization of the third structure region is greater than that of the fourth structure region. The fourth structure region is closer to the second surface 101b than the third structure region. The second semiconductor layer 102' includes at least one of amorphous silicon, nanocrystalline silicon, or microcrystalline silicon. Here, the first-type doping and the second-type doping are of opposite doping types. For example, the first-type doped amorphous silicon layer 1021a can be an N-type doped amorphous silicon layer, and the second-type doped amorphous silicon layer 1022a can be a P-type doped amorphous silicon layer. Alternatively, the polarities of the first-type doping and the second-type doping can be reversed.

[0093] Since the nanocrystalline silicon is mainly located in the doped silicon layer, the crystallization structure of the first-type doped amorphous silicon layer or the second-type doped amorphous silicon layer is further described. Figure 9 is a top view schematic diagram of the positional relationship between the edge portion and the main portion of the first-type doped amorphous silicon layer or the second-type doped amorphous silicon layer in another embodiment of the present application. As shown in Figure 9, the first semiconductor layer 102 is entirely covered on the first surface 101a, or the second semiconductor layer 102' is entirely covered on the second surface 101b. From a top view, it can be observed that the corresponding first-type doped amorphous silicon layer 1021a and / or the second-type doped amorphous silicon layer 1022a respectively include a main portion A and an edge portion B arranged around the periphery of the main portion, and the edge portion B is annular in shape. Further optionally, the main portion A contains nanocrystalline silicon and the edge portion B does not contain nanocrystalline silicon, so that the degree of crystallization of the main portion A is greater than that of the edge portion B. Since the edge portion B is thin and has more defects, and the electron-hole recombination rate is large, by setting the edge portion B to not contain nanocrystalline silicon, on the one hand, the damage caused by, for example, laser processing to the thinner edge portion of B can be reduced to ensure the passivation effect, and on the other hand, the defects of the edge portion can be further isolated to suppress the recombination of carriers.

[0094] Further optionally, the main portion A is primarily located in the electrode contact region of the solar cell, while the edge portion B is primarily located in the non-electrode contact region of the solar cell, thereby making the degree of crystallization in the electrode contact region greater than that in the non-electrode contact region, thereby further facilitating improvement of the current transmission characteristics of the doped amorphous silicon layer. Here, the "electrode contact region" refers to the region where the electrode can contact the doped amorphous silicon layer.

[0095] According to an embodiment of the present application, when the first surface 101a of the silicon substrate 101 is a velvet surface containing a pyramid structure, the above-mentioned structural settings of the edge portion and the main portion are also applicable and will not be described in detail here.

[0096] According to an embodiment of the present application, it is further preferred that the second surface 101b of the silicon substrate 101 is a velvet surface containing a pyramid structure, which can serve as the light-receiving surface, and the second-type doped amorphous silicon layer 1022b may or may not contain nanocrystalline silicon. In the case where the second-type doped amorphous silicon layer 1022b contains nanocrystalline silicon, a crystallized structure similar to that shown in Figures 2, 5A, and 5B is obtained. This results in a higher light utilization rate on the light-receiving surface, while reducing contact resistance on the backlight surface, thereby improving battery efficiency.

[0097] According to an embodiment of the present application, the solar cell of the present application may further include a first transparent conductive layer 103a and a second transparent conductive layer 103b, wherein the first transparent conductive layer 103a is located on the surface of the first-type doped amorphous silicon layer 1021a away from the silicon substrate 101; the second transparent conductive layer 103b is located on the surface of the second-type doped amorphous silicon layer 1022a away from the silicon substrate 101.

[0098] According to an embodiment of the present application, the solar cell of the present application may further include a first electrode 104a and a second electrode 104b, wherein the first electrode 104a is located on the first transparent conductive layer 103a, and the second electrode 104b is located on the second transparent conductive layer 103b.

[0099] According to the embodiments of the present application, the solar cell of the present application is further explained by taking the hybrid back-contact heterojunction cell as an example. Figure 10 is a side view of the overall structure of a solar cell of another embodiment of the present application, and Figure 11 is a top view schematic diagram of the positional relationship between the first-type doped amorphous silicon layer and the second-type doped polycrystalline silicon layer of another embodiment of the present application. As shown in Figures 10 and 11, the silicon substrate 101 includes a first surface 101a and a second surface 101b relative to each other, and the first surface 101a includes a first region 101a' and a second region 101a", which are spaced apart. The first region 101a' is a polished region with a pyramid base structure; the first semiconductor layer 102 is located in the first region 101a' of the silicon substrate 101; the solar cell also includes a second semiconductor layer 102', which is located in the second region 101a", of the silicon substrate 101. The second semiconductor layer 102' has a different conductivity type from the first semiconductor layer 102.

[0100] The first semiconductor layer 102 extends above the second semiconductor layer 102' to overlap with the second semiconductor layer 102' to form an overlapping portion C. The first semiconductor layer 102 in the overlapping portion C belongs to the edge portion B. The location corresponding to the overlapping portion C is the location circled in Figure 10. By setting the first semiconductor layer 102 in the overlapping portion to a lower degree of crystallization than the main portion, leakage between the first semiconductor layer 102 and the second semiconductor layer 102' can be improved, while also increasing the reverse conduction voltage, providing a larger reverse voltage for hot spot prevention.

[0101] According to an embodiment of the present application, as shown in FIG11 , the first semiconductor layer 102 and the second semiconductor layer 102′ are strip-shaped portions extending along a first direction and alternately arranged along a second direction perpendicular to the first direction. The first semiconductor layer 102 may further include edge portions B extending along the first direction along both side edges of the first semiconductor layer 102, which together with the overlapping portion C form an annular shape surrounding the periphery of the main portion A.

[0102] According to an embodiment of the present application, the width of the edge portion, directed from the main portion A toward the edge portion B, is less than or equal to 500 μm. This configuration minimizes the width of the edge portion to increase the area of ​​the main portion, reduce contact resistance, and improve current collection capability. Preferably, the width of the edge portion is greater than or equal to 100 microns to ensure that the laser does not affect the performance of other layers due to precision issues, such as irradiating the boundary of the second semiconductor layer.

[0103] According to an embodiment of the present application, when the first region 101 a ′ of the silicon substrate 101 is a textured region containing a pyramid structure, the above-mentioned structural arrangement of the overlapping portion is also applicable and will not be described in detail here.

[0104] According to an embodiment of the present application, the solar cell of the present application may further include a transparent conductive layer 103, which is located on a surface of a first region 101a' of the first-type doped amorphous silicon layer 1021a facing away from the silicon substrate 101 and a surface of a second region 101a" of the second-type doped polycrystalline silicon layer 1023 facing away from the silicon substrate 101. It can be understood that the transparent conductive layer 103 here is a patterned layer structure.

[0105] According to an embodiment of the present application, exemplarily as shown in FIG10 and FIG11 , taking the example of the first structure region 102a of the first semiconductor layer 102 including the first-type doped amorphous silicon layer 1021a and the second semiconductor layer 102′ including the second-type doped polycrystalline silicon layer 1023, the solar cell of the present application further includes a first intrinsic amorphous silicon layer 1021b, a tunneling oxide layer 105, and an electrode 104, wherein the first intrinsic amorphous silicon layer 1021b is located between the silicon substrate 101 and the first-type doped polycrystalline silicon layer 1021a, the tunneling oxide layer 105 is located between the silicon substrate 101 and the second-type doped polycrystalline silicon layer 1023, and the electrode 104 is located on the transparent conductive layer 103. A heterojunction can be formed by the first intrinsic amorphous silicon layer 1021b, the first-type doped amorphous silicon layer 1021a, and the silicon substrate 101, while a tunneling oxide layer 105 and the second-type doped polycrystalline silicon layer 1023 form a tunneling oxide passivation structure.

[0106] According to the embodiments of the present application, the material of the transparent conductive layer 103 is not particularly limited. For example, a transparent conductive oxide (TCO) can be used, such as indium tin oxide (ITO), tungsten-doped tin oxide (VTTO), tungsten-doped indium oxide (IWO), molybdenum-doped indium oxide (IMO), or tin oxide fluoride (TOF). The transparent conductive layer 103 is conformally formed on the first semiconductor layer 102 and covers the porous structure of the first semiconductor layer 102, thereby forming a relatively close contact with the first semiconductor layer 102.

[0107] According to an embodiment of the present application, the first intrinsic amorphous silicon layer 1021b extends above the second-type doped polysilicon layer 1023. In this case, the first intrinsic amorphous silicon layer 1021b located between the first-type doped amorphous silicon layer 1021a and the second-type doped polysilicon layer 1023 serves as an insulator. The thinner the first intrinsic amorphous silicon layer 1021b, the thinner the lateral wall thickness of the first intrinsic amorphous silicon layer 1021b, resulting in a poorer insulation effect and, in turn, greater leakage current, reducing battery efficiency. "Lateral" refers to the direction from the sidewall of the first-type doped amorphous silicon layer 1021a toward the sidewall of the second-type doped polysilicon layer 1023.

[0108] According to some embodiments of the present application, a method for manufacturing a solar cell is also provided. FIG12A is a schematic diagram of the manufacturing process of the solar cell according to the embodiment of the present application. As shown in FIG12A , the method for manufacturing the solar cell according to the embodiment of the present application mainly includes operations S1101 to S1102.

[0109] In operation S1101, a semiconductor layer is formed on the first surface of the silicon substrate, wherein the "semiconductor layer" has the same meaning as above, and the semiconductor layer is an amorphous silicon layer as an example for further description.

[0110] In operation S1102 , the semiconductor layer is processed using a first laser to increase the degree of crystallization of at least a portion thereof to form a crystallized region.

[0111] The semiconductor layer in the crystallized region includes a second structure region and a first structure region, the crystallization degree of the first structure region is greater than that of the second structure region; and the second structure region is closer to the first surface than the first structure region.

[0112] According to the embodiments of the present application, the present application uses laser to process the amorphous silicon layer, so that part of the amorphous silicon layer forms a porous structure or crystallizes. It only requires adding the operation of applying laser to the amorphous silicon layer on the basis of the original process of the battery, which has the advantage of simple operation.

[0113] According to an embodiment of the present application, the semiconductor layer is crystallized so that the intrinsic silicon layer in the semiconductor layer is thickened to a thickness of 8 to 20 nm, for example, 8 nm, 10 nm, 13 nm, 15 nm, 18 nm, or 20 nm.

[0114] According to an embodiment of the present application, the wavelength of the first laser is 325-532 nm, for example, 325 nm, 350 nm, 400 nm, 450 nm, 500 nm, 532 nm, the pulse width is in the order of picoseconds to nanoseconds, and the energy density is 200-6000 mJ / cm 2 , for example, 200 mJ / cm 2 , 500mJ / cm 2 、1000mJ / cm 2 , 2000mJ / cm 2 、3000mJ / cm 2 , 4000mJ / cm 2 , 5000mJ / cm 2 、6000mJ / cm 2 The laser overlap ratio is 60% to 95%, for example, 60%, 65%, 70%, 75%, 80%, 85%, 90%, or 95%.

[0115] In some exemplary embodiments, the laser conditions of the laser used can be adjusted to laser conditions 1 to laser conditions 4, respectively. Specific parameters of laser conditions 1 to laser conditions 4 are shown in Table 1 below.

[0116] Table 1

[0117] The contact resistance of the amorphous silicon layer was tested using current-voltage tests without laser treatment and after the first laser treatment under laser conditions 1 to 4. Specifically, the test was conducted on a bilaterally symmetrical P-type doped amorphous silicon / intrinsic amorphous silicon / P-type doped amorphous silicon / TCO layer / electrode structure. It was found that the contact resistance of the amorphous silicon layer after the first laser treatment under different laser conditions showed a relatively significant decrease. Figure 12B is a graph showing the contact resistance test results after the amorphous silicon layer after the first laser treatment was covered with a TCO layer and a metal electrode was formed, showing the contact resistance of the amorphous silicon layer after the more preferred laser condition 1. As shown in Figure 12B, compared to the contact resistance without laser treatment, the contact resistance of the amorphous silicon layer after the first laser treatment under laser condition 1 showed a relatively significant decrease. This is because the formation of a crystallized structure was observed in the amorphous silicon layer after the first laser treatment.

[0118] According to an embodiment of the present application, along a direction parallel to the first surface, the semiconductor layer includes a main body portion and an edge portion adjacent to the periphery of the main body portion; operation S1102 specifically includes: using a first laser to irradiate the main body portion of the semiconductor layer, so that the degree of crystallization of the main body portion is greater than the degree of crystallization of the edge portion, and so that the degree of crystallization of the first structure area in the main body portion is greater than the degree of crystallization of the second structure area.

[0119] According to an embodiment of the present application, the semiconductor layer is amorphous silicon, and operation S1102 specifically includes: processing the semiconductor layer with a first laser to crystallize a portion of the amorphous silicon in the semiconductor layer to form nanocrystalline silicon in the crystallized region of the semiconductor layer.

[0120] According to an embodiment of the present application, the preparation method of the present application further includes operation S1103 of forming a transparent conductive layer on the surface of the semiconductor layer that has been processed by laser and is away from the silicon substrate.

[0121] According to an embodiment of the present application, to further understand the overall manufacturing process of the solar cell of the present application, a specific method for preparing a hybrid back-contact heterojunction cell as shown in Figure 10 is used as an example for description. Figures 13A to 13E are schematic diagrams of the manufacturing process of a solar cell according to another embodiment of the present application. As shown in Figures 13A to 13E, the manufacturing method of the solar cell according to the embodiment of the present application includes operations S1201 to S1205.

[0122] In operation S1201 , a tunneling oxide layer 1205 and a second type doped polysilicon layer 12023 are formed on a first surface 1201 a of a silicon substrate 1201 .

[0123] In operation S1202 , the tunneling oxide layer 1205 and the second type doped polysilicon layer 12023 are patterned, and the tunneling oxide layer 1205 and the second type doped polysilicon layer 12023 remain on the second region 1201 a ″ of the first surface 1201 a .

[0124] In operation S1203, the areas other than the second area 1201a" of the first surface 1201a are subjected to texturing and polishing treatments to obtain a polished surface having a pyramid base structure.

[0125] In operation S1204, an intrinsic amorphous silicon layer 12021 and a first-type doped amorphous silicon layer 12022 are sequentially formed on the polishing surface, and the first-type doped amorphous silicon layer 12022 is processed using a first laser; preferably, the processed boundary does not reach the boundary of the adjacent second-type doped polycrystalline silicon layer 12023, and there is a certain distance between the boundary of the first-type doped amorphous silicon 12022 processed by the first laser and the boundary of the second-type doped polycrystalline silicon 12023, for example, it can be 50-200 microns.

[0126] In operation S1205 , a patterned transparent conductive layer 1203 and an electrode 1204 are formed on the surfaces of the first-type doped amorphous silicon layer 1203 a and the second-type doped polysilicon layer 12023 that have been subjected to laser treatment.

[0127] According to an embodiment of the present application, as shown in FIG13A , operation S1201 may specifically include the following: (1) Polishing: Double-sided polishing of the silicon substrate 1201 is performed to make its surface flat and smooth. (2) First Chemical Vapor Deposition (CVD1): A tunneling oxide layer 1205 and a polysilicon or amorphous silicon layer 12031 are sequentially deposited on the first surface 1201a of the double-sided polished silicon substrate 1201 using a chemical vapor deposition method. The deposition conditions are not critical to the present application and are not described in detail here. (3) Doping: A diffusion process is used to transform the polysilicon or amorphous silicon layer 12031 into a second-type doped polysilicon layer 12023. The diffusion conditions are not critical to the present application and are not described in detail here.

[0128] It can be understood that different doping types and diffusion processes will form different doping sources 12032 on the surface of the second-type doped polysilicon layer 12023. For example, the phosphorus diffusion process will form phosphorus silicon glass on the surface of the second-type doped polysilicon layer 12023, and the boron diffusion process will form borosilicate glass on the surface of the second-type doped polysilicon layer 12023.

[0129] According to an embodiment of the present application, as shown in FIG13B , operation S1202 may specifically include:

[0130] (1) First wet treatment (wet process 1): wet removal of the doping source 12032, for example, by an acid wash process to remove phosphosilicate glass or borosilicate glass.

[0131] (2) Second chemical vapor deposition (CVD2): A mask layer 1208 is deposited on the surface of the second type doped polysilicon layer 12023 away from the silicon substrate 101 using a chemical vapor deposition method. For example, a silicon nitride layer can be deposited. The deposition conditions are not critical to this application and are not described here.

[0132] (3) Second laser treatment (laser 2): A second laser is used to perform laser opening on the tunneling oxide layer 1205, the second-type doped polysilicon layer 12023, and the mask layer 1208, thereby removing the tunneling oxide layer 1205 and the second-type doped polysilicon layer 12023 on the remaining areas of the first surface 1201a except the second area 1201a″. The laser opening conditions are not critical to the present application and are not described in detail here.

[0133] According to an embodiment of the present application, as shown in FIG13C , operation S1203 may specifically include:

[0134] (1) Second wet treatment (wet method 2): Double-sided texturing is used to perform wet texturing on the other areas of the first surface 1201a except the second area 1201a″ and the second surface 1201b of the silicon substrate. For example, wet texturing can be performed using an alkaline bath device.

[0135] (2) Second chemical vapor deposition (CVD2-2): A passivation anti-reflection layer is deposited on the wet-textured second surface 1201b of the silicon substrate 1201 using a chemical vapor deposition method, for example, a third intrinsic amorphous silicon layer 1206 and a silicon nitride layer 1207 are deposited in sequence.

[0136] (3) Second wet treatment (wet method 2-2): Alkaline polishing is performed on the first surface 1201a except the second region 1201a″ by using a chain device to obtain a polished surface, and the mask layer on the surface of the second type doped polysilicon layer 12023 is acid-washed and removed by using a chain device.

[0137] According to an embodiment of the present application, in other implementations, the polishing process in operation S1203 can be omitted, thereby obtaining a textured surface with a pyramid structure, and then sequentially forming an intrinsic amorphous silicon layer 12021 and a first-type doped amorphous silicon layer 12022 on the textured surface.

[0138] According to an embodiment of the present application, as shown in FIG13D , operation S1204 may specifically include:

[0139] (1) Third Chemical Vapor Deposition (CVD3): Chemical vapor deposition is used to sequentially deposit an intrinsic amorphous silicon layer 12021 and a first-type doped amorphous silicon layer 12022 on the polished surface of the silicon substrate 1201 and the surface of the second-type doped polysilicon layer 12023. The intrinsic amorphous silicon layer 12021 can form an isolation region between the first-type doped amorphous silicon layer 12022 and the second-type doped polysilicon layer 12023, thereby providing insulation.

[0140] (2) Laser and third wet treatment (Laser3+laser1+wet 3): First, the third laser is used to remove the intrinsic amorphous silicon layer 12021 and the first-type doped amorphous silicon layer 12022 on the surface of the second-type doped polycrystalline silicon layer 12023. The retained first-type doped amorphous silicon layer 12022 and the second-type doped polycrystalline silicon layer 12023 form an overlap, and the overlapping portion can reduce the damage to the second-type doped polycrystalline silicon layer 12023 when the transparent conductive layer of the isolation region is subsequently opened. Secondly, the first laser is used to treat at least a portion of the remaining portion of the first-type doped amorphous silicon layer 12022 except the overlapping portion, so that the first-type doped amorphous silicon layer 12022 forms a crystallized region. Thirdly, acid pickling is used to remove the silicon oxide formed on the surface of the film layer after the third laser and the first laser are applied.

[0141] According to an embodiment of the present application, as shown in Figure 13E, in operation S1205, it specifically includes: physical vapor deposition (PVD): using physical vapor deposition to deposit a transparent conductive layer 1203 on the exposed surface of the second-type doped polycrystalline silicon layer 12023 and the exposed surface of the first-type doped amorphous silicon layer 12022 treated with the first laser. The deposition conditions are not critical to the present application and will not be elaborated here.

[0142] According to an embodiment of the present application, as shown in FIG13E , after operation S1205, the following steps may be further included:

[0143] (1) Insulation treatment (TCO insulation): The transparent conductive layer 1203 located at the isolation position between the first-type doped amorphous silicon layer 12022 and the second-type doped polysilicon layer 12023 is removed, for example, by laser film opening.

[0144] (2) Screen printing: Electrodes 1204 are made on the transparent conductive layer 1203 by screen printing, and a solar cell having a structure as shown in FIG10 is obtained.

[0145] According to the embodiments of the present application, the solar cell obtained by the above-mentioned manufacturing method reduces the contact resistance with the transparent conductive layer based on the porous structure and / or crystallized structure of the first-type doped amorphous silicon, thereby freeing up space for thickening the intrinsic amorphous silicon layer, thereby taking into account the three aspects of contact resistance, passivation effect and leakage current, so that the battery efficiency can be optimized.

[0146] In other embodiments of the present application, a solar cell is further provided. As shown in FIG14 , the solar cell includes a silicon substrate 101 , wherein a surface of one side of the silicon substrate 101 includes a first region, a second region, and a third region adjacent to each other in sequence.

[0147] In the first region, a first doped layer (i.e., a first semiconductor layer 102) and a third electrode 141 are sequentially stacked on a silicon substrate 101; in the third region, a second doped layer (i.e., a second semiconductor layer 102') and a fourth electrode 142 are sequentially stacked on the silicon substrate 101; the first doped layer and the second doped layer have opposite conductivity.

[0148] At least one of the first doped layer in the first region and the second doped layer in the third region has a crystallized region; a projection of the crystallized region on the silicon substrate 101 at least partially overlaps with a projection of the third electrode 141 on the silicon substrate 101, and / or a projection of the crystallized region on the silicon substrate 101 at least partially overlaps with a projection of the fourth electrode 142 on the silicon substrate 101;

[0149] And wherein the first doped layer and the second doped layer extend to the second region; wherein, within the second region, at least a portion of the first doped layer is an amorphous region, and at least a portion of the second doped layer is an amorphous region.

[0150] In the solar cell provided in this embodiment, since photogenerated carriers migrate and diffuse laterally (perpendicular to the thickness direction of the doping layer) and longitudinally (parallel to the thickness direction of the doping layer) in doping layers of different doping types, the present application provides a second region with high resistivity between the first doping layer in the first region and the second doping layer in the third region for isolation, thereby reducing lateral carrier migration and leakage. In addition, at least one of the first doping layer in the first region and the second doping layer in the third region comprises a crystallized region, which has good conductivity and is conducive to carrier collection. In addition, in the second region, at least a portion of the first doping layer is an amorphous region, and at least a portion of the second doping layer is an amorphous region. The amorphous region has lower carrier mobility and lower sheet resistance than the crystalline region, which can greatly reduce leakage current.

[0151] The silicon substrate includes a light-receiving surface and a backlight surface, which are arranged relative to each other. The backlight surface of the silicon substrate includes a first region, a second region, and a third region that are adjacent to each other in sequence. Adjacent here means that the first region, the second region, and the third region are adjacent to each other in sequence but do not overlap.

[0152] The silicon substrate, the first doped layer, and the second doped layer all have a velvet structure; or, the silicon substrate, the first doped layer, and the second doped layer all have a smooth surface; or, the silicon substrate and the first doped layer in the first region have a velvet surface, and the functional layers in the third region have a smooth surface; or, the silicon substrate and the first doped layer in the first region have a smooth surface, and the functional layers in the third region all have a velvet structure.

[0153] In the solar cell shown in Figure 14, within the first region, the first doped layer includes a first crystallized region 12 and a first amorphized region A16; at least the portion of the first crystallized region 12 facing away from the silicon substrate contains crystals. Within the third region, the second doped layer includes a second crystallized region 5. Within the second region, at least the side of the first doped layer closest to the first region is a first amorphized region B18, and at least the side of the second doped layer closest to the first region is a second amorphized region B17. A light-entering passivation layer 13 and an anti-reflection layer 14 are sequentially formed on the light-receiving surface of the silicon substrate.

[0154] A transmission electron microscope image of the second doped layer in the third region of this embodiment is shown in Figure 8. As shown in Figure 8, in the solar cell of this embodiment, under the action of laser, the amorphous silicon on the side away from the silicon wafer in the first doped layer is converted into crystalline silicon.

[0155] The method for preparing a solar cell of this embodiment includes the following steps:

[0156] Step 1: Polish and clean the silicon wafer, and perform texturing on the light-incident surface.

[0157] Step 2: PECVD is used to deposit a 5nm intrinsic hydrogenated amorphous silicon passivation layer, a 30nm amorphous n layer, a 100nm SiNx layer (refractive index 2.5), and a 30nm laser absorption layer on the back of the battery.

[0158] Step 3: Use laser to remove the laser absorption layer in the first region, thereby forming a laser opening to expose the SiNx layer.

[0159] Step 4: Perform a wet process, use 10% concentration hydrofluoric acid to remove the SiNx layer in the laser opening to expose the amorphous n layer, and use 10% concentration potassium hydroxide to remove the exposed amorphous n layer, the intrinsic hydrogenated amorphous silicon passivation layer underneath, and the laser absorption layer in the second and third regions, thereby exposing the silicon wafer in the first region and the silicon nitride layer in the second and third regions.

[0160] Step 5: On the back of the cell, a 5nm intrinsic hydrogenated amorphous silicon passivation layer and a 30nm amorphous p-layer are sequentially deposited on the silicon wafer in the first area, the silicon nitride layer in the second area, and the silicon nitride layer in the third area using PECVD technology.

[0161] Step 6: Use laser (the energy density of the laser spot is 200mJ / cm 2 ) removing the amorphous p-layer and the intrinsic hydrogenated amorphous silicon passivation layer in the third region to form an opening, thereby exposing the SiNx layer in the third region.

[0162] Step 7: Perform wet treatment and use 10% concentration hydrofluoric acid to remove the SiNx layer in the third area.

[0163] Step 8: Use PECVD to deposit an intrinsic hydrogenated amorphous silicon passivation layer and a SiNx anti-reflection film on the light-incident surface, with a refractive index of 2 and a thickness of 70nm.

[0164] Step 9: Perform laser crystallization treatment, using laser to crystallize the middle area of ​​the amorphous p layer in the first region into a nanocrystalline p region, that is, the first nanocrystalline silicon p-doped region and the first amorphous silicon p-doped region exist in the first region at the same time, the first amorphous silicon p-doped region surrounds the first nanocrystalline silicon p-doped region, and the part of the amorphous n layer and the electrode layer stacked in the third region is crystallized into a nanocrystalline n region.

[0165] Step 10: sequentially depositing a TCO layer and an Ag electrode (third electrode 141 ) on the nanocrystalline p-layer; and sequentially depositing a TCO layer and an Ag electrode (fourth electrode 142 ) on the nanocrystalline n-layer.

[0166] It should be noted that the various technical features described in this specification based on a specific embodiment or implementation are not only applicable to the specific embodiment or implementation, but can also be used in other embodiments or implementations.

[0167] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of this application. It should be understood that the above is only a specific embodiment of this application and is not intended to limit this application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application should be included in the scope of protection of this application.

Claims

1. A solar cell, wherein: The solar cell comprises: a silicon substrate comprising a first surface and a second surface opposite to each other; and A first semiconductor layer is located on the first surface; the first semiconductor layer includes a second structure region and a first structure region, and the degree of crystallization of the first structure region is greater than the degree of crystallization of the second structure region; wherein the second structure region is closer to the first surface than the first structure region, and the first semiconductor layer includes at least one of amorphous silicon, nanocrystalline silicon or microcrystalline silicon.

2. The solar cell according to claim 1, wherein The second structure region includes a first intrinsic silicon layer with a thickness of 5 to 30 nm, preferably 8 to 20 nm.

3. The solar cell according to claim 1, wherein The material of the second structure region includes intrinsic amorphous silicon, and the material of the first structure region includes amorphous silicon and nanocrystalline silicon.

4. The solar cell according to claim 1, wherein The material of the first structural region includes amorphous silicon and nanocrystalline silicon with a grain size of 5 to 25 nm.

5. The solar cell according to claim 1, wherein The first semiconductor layer has a plurality of crystal grains therein, and the maximum size of the plurality of crystal grains is smaller than the thickness of the first semiconductor layer.

6. The solar cell according to claim 1, wherein The solar cell further includes a transparent conductive layer located on a surface of the first semiconductor layer away from the silicon substrate, and the first structure region is covered by the transparent conductive layer.

7. The solar cell according to claim 1, wherein Along a direction parallel to the first surface, the first semiconductor layer includes a main portion and an edge portion adjacent to a periphery of the main portion, and a crystallization degree of the main portion is greater than a crystallization degree of the edge portion.

8. The solar cell according to claim 7, wherein The first semiconductor layer entirely covers the first surface, and the edge portion is in a ring shape surrounding the main portion.

9. The solar cell according to claim 7, wherein The first surface of the silicon substrate includes a first region and a second region spaced apart from each other, and the first semiconductor layer is located on the first region; The solar cell further includes a second semiconductor layer located on the second region, the second semiconductor layer having a conductivity type different from that of the first semiconductor layer; The first semiconductor layer is located on the first region and extends onto the second semiconductor layer to overlap with the second semiconductor layer to form an overlapping portion, and the first semiconductor layer in the overlapping portion belongs to the edge portion.

10. The solar cell according to any one of claims 7 to 9, wherein In a direction from the main portion to the edge portion, a width of the edge portion is less than or equal to 500 μm.

11. The solar cell according to any one of claims 1 to 6, wherein The first surface of the silicon substrate has a polished area with a pyramid base structure, The first semiconductor layer is located on the polishing area, and has a porous structure.

12. The solar cell according to claim 11, wherein The first structural region has a first porous structure, and the second structural region has a second porous structure. The pore size of the second porous structure is smaller than that of the first porous structure.

13. The solar cell according to claim 12, wherein: The first porous structure has a plurality of first pores disposed therethrough, and the second porous structure includes a plurality of second pores, wherein the plurality of second pores are exposed from the plurality of first pores.

14. The solar cell according to claim 12, wherein The pore size of the first porous structure is less than or equal to 1 μm, and the pore size of the second porous structure is less than or equal to 300 nm.

15. The solar cell according to claim 11, wherein The first structural region has a porous structure, and the second structural region has a non-porous structure.

16. The solar cell according to any one of claims 1 to 6, wherein The first surface of the silicon substrate has a velvet area containing a plurality of pyramid structures, and along a direction away from the first surface, the pyramid structures include a base and a top. The first structure region and the second structure region are both located on the tower top, and the degree of crystallization of the second structure region is greater than the degree of crystallization of the first semiconductor layer located on the tower base.

17. The solar cell according to claim 16, wherein The first semiconductor layer located on the pyramid structure is a non-porous structure and has a side surface extending from the top to the bottom; Wherein, in the extension direction of the side surface, a ratio between a maximum extension length of the first semiconductor layer located on the tower top on the side surface and a length of the side surface is less than or equal to 0.

3.

18. The solar cell according to claim 16, wherein The portion of the first semiconductor layer located on the tower top has a porous structure.

19. The solar cell according to claim 18, wherein At least one hole included in the porous structure is a blind hole that does not penetrate the first semiconductor layer, and / or the pore diameter of at least one hole included in the porous structure is less than 100 nm.

20. The solar cell according to claim 18, wherein The first semiconductor layer located on the pyramid structure has a side surface extending from the top of the pyramid to the bottom of the pyramid; Wherein, along the extension direction of the side surface, the ratio of the distribution length of the porous structure on the side surface to the length of the side surface is less than or equal to 0.

5.

21. The solar cell according to claim 18, wherein The thickness of the portion of the first semiconductor layer where the porous structure is not provided is greater than or equal to 10 nm; and / or the thickness of the portion of the first semiconductor layer where the porous structure is not provided is less than or equal to 45 nm.

22. The solar cell according to claim 1, wherein The crystallization rate of the second structure region is greater than or equal to 10%, and / or the difference between the crystallization rate of the second structure region and the crystallization rate of the first structure region is less than or equal to 10%.

23. The solar cell according to claim 1, wherein The solar cell also includes a second semiconductor layer located on the second surface; the second semiconductor layer includes a fourth structure region and a third structure region, and the degree of crystallization of the third structure region is greater than the degree of crystallization of the fourth structure region; wherein the fourth structure region is closer to the second surface than the third structure region, and the second semiconductor layer includes at least one of amorphous silicon, nanocrystalline silicon or microcrystalline silicon.

24. A method for manufacturing a solar cell, wherein: The manufacturing method comprises: forming a semiconductor layer on the first surface of the silicon substrate, wherein the material of the semiconductor layer comprises at least one of amorphous silicon, nanocrystalline silicon or microcrystalline silicon; Processing the semiconductor layer with a first laser to increase the degree of crystallization of at least a portion of the semiconductor layer to form a crystallized region; The semiconductor layer located in the crystallized region includes a second structure region and a first structure region, the crystallization degree of the first structure region is greater than that of the second structure region; and the second structure region is closer to the first surface than the first structure region.

25. The manufacturing method according to claim 24, wherein: The wavelength of the first laser is 325-532 nm, the pulse width is in the order of picoseconds to nanoseconds, and the energy density is 200-6000 mJ / cm 2 .

26. The manufacturing method according to claim 24, wherein: Along a direction parallel to the first surface, the semiconductor layer includes a main portion and an edge portion adjacent to a periphery of the main portion; The step of processing the semiconductor layer with the first laser to increase the degree of crystallization of at least a portion of the semiconductor layer to form a crystallized region includes: The main portion of the semiconductor layer is irradiated with the first laser so that the main portion is more crystallized than the edge portion and the first structure region in the main portion is more crystallized than the second structure region.

27. The manufacturing method according to claim 24, wherein: The semiconductor layer is amorphous silicon, and the processing of the semiconductor layer with a first laser to increase the degree of crystallization of at least a portion of the semiconductor layer to form a crystallized region includes: The semiconductor layer is processed by using a first laser to crystallize a portion of amorphous silicon in the semiconductor layer, so as to form nanocrystalline silicon in the crystallized region of the semiconductor layer.

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