Load instruction execution method, processor, apparatus, device, and storage medium

Abstract

The present application relates to the technical fields of chips and semiconductors, and provides a load instruction execution method, a processor, an apparatus, a device, and a storage medium. The method comprises: in the process of executing a first load instruction, when a first event entry exists in a plurality of event entries in an execution information table, querying a storage instruction queue on the basis of the first event entry; if a first storage instruction exists in the storage instruction queue, when a memory address to be accessed by the first load instruction is different from a memory address to be accessed by the first storage instruction, setting the state of the first event entry in the execution information table to be an invalid state; and when the state of the first event entry in the execution information table is an invalid state, according to the current execution progress of the first load instruction, continuing to execute the first load instruction. The technical solution improves the execution efficiency of load instructions, so that the performance of executing instructions by a processor is improved.

Description

Load instruction execution method, processor, device, equipment and storage medium

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on January 23, 2024, with application number 202410101120.4 and application name “Method, processor, device, equipment and storage medium for executing load instructions”. The entire contents of the application are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of chips and semiconductors, and in particular to a method, processor, device, equipment and storage medium for executing a load instruction. Background Art

[0003] With the development of computer technology, computer devices are able to process instructions in programs triggered by users through their own processors. Instructions in a program usually include load instructions and store instructions. Load instructions and store instructions may conflict due to accessing the same memory address. For example, data a is stored in memory address A. The store instruction is used to write data b in the register to memory address A. The load instruction writes the data in memory address A to the processor's register. Under normal circumstances, the load instruction needs to obtain data b from memory address A, which means it needs to be executed after the store instruction. If the load instruction is executed before the store instruction, data a will be obtained. This will cause an error, which can be regarded as a conflict between the load instruction and the store instruction. Therefore, how to execute the load instruction is a research focus in this field.

[0004] Currently, the commonly used method is to record the load instructions and store instructions that have conflicted in the past. When the same load instruction is executed next time, it is checked whether the store instruction that conflicted with the load instruction currently being executed has been executed. Only when the store instruction is executed, the load instruction will be executed.

[0005] However, since the memory addresses to be accessed by the conflicting load instructions and store instructions will change as the program runs, there is no longer a dependency between the load instruction and the store instruction. In the above technical solution, the load instruction still needs to wait until the above store instruction is executed before it can be executed, which reduces the performance of the processor in executing instructions. Summary of the Invention

[0006] The embodiments of the present application provide a method, processor, apparatus, device, and storage medium for executing a load instruction, which improves the execution efficiency of the load instruction, thereby improving the performance of the processor in executing instructions. The technical solution is as follows:

[0007] In one aspect, a method for executing a load instruction is provided, the method comprising:

[0008] During execution of a first load instruction, if a first event entry exists among a plurality of event entries in an execution information table, querying a storage instruction queue based on the first event entry, wherein each event entry in the execution information table indicates a second load instruction and a second storage instruction having a conflicting event during a historical execution process, the second load instruction indicated by the first event entry is the same as the first load instruction, and the storage instruction queue includes a plurality of second storage instructions;

[0009] If a first storage instruction exists in the storage instruction queue, and if the memory address to be accessed by the first load instruction is different from the memory address to be accessed by the first storage instruction, setting the state of the first event entry in the execution information table to an invalid state, the first storage instruction being the second storage instruction indicated by the first event entry, the first storage instruction being not successfully executed, and the invalid state being used to indicate that the conflict event corresponding to the first event entry will not occur during the current execution of the first load instruction;

[0010] When the state of the first event entry in the execution information table is an invalid state, the first load instruction continues to be executed according to the current execution progress of the first load instruction.

[0011] In another aspect, a processor is provided, comprising: an instruction query unit, an entry processing unit, and an execution unit;

[0012] The instruction query unit is configured to query a storage instruction queue based on a first event entry if a first event entry exists among multiple event entries in an execution information table during execution of a first load instruction, wherein each event entry in the execution information table indicates a second load instruction and a second storage instruction having a conflicting event during a historical execution process, the second load instruction indicated by the first event entry being the same as the first load instruction, and the storage instruction queue including a plurality of second storage instructions;

[0013] the entry processing unit being configured to, if a first storage instruction exists in the storage instruction queue and a memory address to be accessed by the first load instruction is different from a memory address to be accessed by the first storage instruction, set the state of the first event entry in the execution information table to an invalid state, the first storage instruction being the second storage instruction indicated by the first event entry, the first storage instruction being not successfully executed, the invalid state being used to indicate that a conflict event corresponding to the first event entry will not occur during the current execution of the first load instruction;

[0014] The execution unit is configured to continue executing the first load instruction according to the current execution progress of the first load instruction when the state of the first event entry in the execution information table is invalid.

[0015] In another aspect, a device for executing a load instruction is provided, the device comprising:

[0016] a first query module configured to query a storage instruction queue based on a first event entry if a first event entry exists in a plurality of event entries in an execution information table during execution of a first load instruction, wherein each event entry in the execution information table indicates a second load instruction and a second storage instruction having a conflicting event in a historical execution process, the second load instruction indicated by the first event entry being the same as the first load instruction, and the storage instruction queue including a plurality of second storage instructions;

[0017] a first processing module configured to, if a first storage instruction exists in the storage instruction queue and a memory address to be accessed by the first load instruction is different from a memory address to be accessed by the first storage instruction, set a state of the first event entry in the execution information table to an invalid state, the first storage instruction being the second storage instruction indicated by the first event entry, the first storage instruction being not successfully executed, the invalid state being used to indicate that a conflict event corresponding to the first event entry will not occur during the current execution of the first load instruction;

[0018] An execution module is configured to continue executing the first loading instruction according to a current execution progress of the first loading instruction when the state of the first event entry in the execution information table is an invalid state.

[0019] On the other hand, a computer device is provided, comprising a processor and a memory, wherein the memory is used to store at least one computer program, and the at least one computer program is loaded and executed by the processor to implement the execution method of the loading instruction in the embodiment of the present application, and the processor is the processor provided in the various optional implementations described above.

[0020] On the other hand, a computer-readable storage medium is provided, in which at least one computer program is stored. The at least one computer program is loaded and executed by a processor to implement the execution method of the loading instruction in the embodiment of the present application.

[0021] On the other hand, a computer program product is provided, including a computer program, which is stored in a computer-readable storage medium. A processor of a computer device reads the computer program from the computer-readable storage medium, and the processor executes the computer program, so that the computer device executes the execution method of the loading instruction provided in the above-mentioned various aspects or various optional implementations of various aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0023] FIG1 is a schematic diagram of an implementation environment of a method for executing a load instruction according to an embodiment of the present application;

[0024] FIG2 is a flowchart of a method for executing a load instruction according to an embodiment of the present application;

[0025] FIG3 is a flowchart of another method for executing a load instruction according to an embodiment of the present application;

[0026] FIG4 is a schematic diagram of a query execution information table provided according to an embodiment of the present application;

[0027] FIG5 is a schematic diagram of an update execution information table provided according to an embodiment of the present application;

[0028] FIG6 is a schematic diagram of an execution information table provided according to an embodiment of the present application;

[0029] FIG7 is a schematic diagram of executing a load instruction according to an embodiment of the present application;

[0030] FIG8 is a block diagram of a processor provided according to an embodiment of the present application;

[0031] FIG9 is a block diagram of another processor provided according to an embodiment of the present application;

[0032] FIG10 is a block diagram of a device for executing a load instruction according to an embodiment of the present application;

[0033] FIG11 is a block diagram of another apparatus for executing a load instruction according to an embodiment of the present application;

[0034] FIG12 is a structural block diagram of a terminal provided according to an embodiment of the present application;

[0035] FIG13 is a schematic diagram of the structure of a server provided according to an embodiment of the present application. DETAILED DESCRIPTION

[0036] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0037] In this application, the terms "first", "second", etc. are used to distinguish identical or similar items with substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is there any limitation on the quantity and execution order.

[0038] In the present application, the term "at least one" means one or more, and the term "plurality" means two or more.

[0039] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the load instructions and store instructions involved in this application are obtained with full authorization.

[0040] The execution method of the load instruction provided in the embodiment of the present application can be applied to a dedicated artificial intelligence chip or any other chip, and the embodiment of the present application is not limited to this.

[0041] The execution method of the load instruction provided in the embodiment of the present application can be executed by a computer device. In some embodiments, the computer device is a terminal or a server. First, taking the computer device as an example, the implementation environment of the execution method of the load instruction provided in the embodiment of the present application is introduced. Figure 1 is a schematic diagram of the implementation environment of the execution method of the load instruction provided in the embodiment of the present application. Referring to Figure 1, the implementation environment includes a terminal 101 and a server 102. The terminal 101 and the server 102 can be directly or indirectly connected via wired or wireless communication, and this application does not limit this.

[0042] In some embodiments, the terminal 101 is a smart phone, a tablet computer, a laptop computer, a desktop computer, a smart speaker, a smart watch, an intelligent voice interaction device, a smart home appliance, a car terminal, etc., but is not limited thereto. The terminal 101 is equipped with a processor. Schematically, the terminal 101 is a terminal used by a user. The terminal 101 can obtain multiple instructions from the server 102. The multiple instructions can be obtained by compiling the language of the machine learning model, which is not limited in this embodiment of the present application. The multiple instructions include load instructions and store instructions. Then, the terminal 101 can execute the load instruction obtained from the server 102 by executing the execution method of the load instruction provided in this application through the processor.

[0043] Those skilled in the art will appreciate that the number of the above-mentioned terminals may be more or less. For example, the above-mentioned terminal may be only one, or the above-mentioned terminals may be dozens or hundreds, or a larger number. The embodiments of the present application do not limit the number of terminals and device types.

[0044] In some embodiments, the server 102 is an independent physical server, or it can be a server cluster or distributed system composed of multiple physical servers. It can also be a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN (Content Delivery Network), big data and artificial intelligence platforms. The server 102 can provide multiple instructions to the terminal 101. Alternatively, the server 102 executes the execution method of the loading instruction provided in the embodiment of the present application, and the embodiment of the present application is not limited to this. In some embodiments, the server 102 undertakes the main computing work and the terminal 101 undertakes the secondary computing work; or, the server 102 undertakes the secondary computing work and the terminal 101 undertakes the main computing work; or, the server 102 and the terminal 101 adopt a distributed computing architecture for collaborative computing.

[0045] FIG2 is a flow chart of a method for executing a load instruction according to an embodiment of the present application. Referring to FIG2 , the present embodiment of the present application is described using the execution by a terminal as an example. The method for executing the load instruction includes the following steps:

[0046] 201. During the execution of a first load instruction, if a first event entry exists among multiple event entries in an execution information table, the terminal queries a storage instruction queue based on the first event entry. Each event entry in the execution information table is used to indicate a second load instruction and a second storage instruction in which a conflicting event exists during the historical execution process. The second load instruction indicated by the first event entry is the same as the first load instruction, and the storage instruction queue includes multiple second storage instructions.

[0047] In an embodiment of the present application, the execution information table includes multiple event entries. Each event entry is used to indicate a conflict event between a load instruction and a store instruction during a historical execution process. A conflict event refers to a situation where an instruction execution error occurs because the execution order violates the dependency relationship between instructions. A conflict event can also be referred to as a violation phenomenon that occurs between instructions. For any two conflict events during a historical execution process, the load instructions and store instructions indicated by the two conflict events may not be exactly the same. That is, the second load instruction and the second store instruction indicated by each event entry may not be exactly the same as the second load instruction and the second store instruction indicated by other entries.

[0048] In the process of executing multiple instructions in the terminal program, for a conflict event that occurs between any load instruction and any storage instruction, the terminal can record the conflict event in the form of an event entry in the execution information table. In addition, the terminal can also record the storage instruction where the conflict event occurs in the storage instruction queue. The first load instruction can be any original load instruction in the program, or it can be a second load instruction that was not successfully executed due to a conflict event, or it can be an instruction newly added to the program. The embodiment of the present application does not limit this. The terminal queries the execution information table based on the first load instruction to determine whether there is a conflict event in the historical execution process for instructions like the first load instruction. If there is a first event entry among the multiple event entries in the execution information table, in the process of executing the first load instruction, the terminal queries the storage instruction queue based on the first event entry to determine the second storage instruction that has a conflict event with an instruction like the first load instruction.

[0049] 202. If there is a first storage instruction in the storage instruction queue, and the memory address to be accessed by the first load instruction is different from the memory address to be accessed by the first storage instruction, the terminal sets the status of the first event entry in the execution information table to an invalid state. The first storage instruction is the second storage instruction indicated by the first event entry. The first storage instruction is not successfully executed. The invalid state is used to indicate that the conflict event corresponding to the first event entry will not occur during the current execution of the first load instruction.

[0050] In an embodiment of the present application, a second storage instruction that causes a conflict event with an instruction such as a first load instruction is considered the first storage instruction. If the first storage instruction exists in the storage instruction queue, the terminal determines whether the memory address to be accessed by the first load instruction is the same as the memory address to be accessed by the first storage instruction. For any instruction, the memory address to be accessed by the instruction is the physical address (PA) storing the data to be operated on by the instruction. If the memory address to be accessed by the first load instruction is different from the memory address to be accessed by the first storage instruction, the terminal determines that there is no dependency relationship between the first load instruction and the first storage instruction. In other words, the data to be retrieved from the memory by the first load instruction is not the data stored by the first storage instruction. Accordingly, whether the first load instruction can be successfully executed is independent of the execution status of the first storage instruction. In other words, the conflict event indicated by the first event entry will not occur during the execution of the first load instruction. In this case, the terminal sets the status of the first event entry in the execution information table to invalid. Alternatively, the terminal determines that the conflict event indicated by the first event entry is invalid and will not occur.

[0051] 203. When the state of the first event entry in the execution information table is invalid, the terminal continues to execute the first loading instruction according to the current execution progress of the first loading instruction.

[0052] In an embodiment of the present application, if the state of the first event entry in the execution information table is invalid, the terminal continues to execute the first loading instruction according to the current execution progress of the first loading instruction until the first loading instruction is completed.

[0053] An embodiment of the present application provides a method for executing a load instruction. During the execution of any load instruction, if it is determined that a conflict event has occurred with a load instruction similar to the load instruction, a storage instruction queue is queried based on the event entry corresponding to the conflict event in an execution information table to determine the storage instruction in which the conflict event has occurred. Since the memory access addresses of instructions in the program will change as the program runs, after determining the storage instruction in which the conflict event has occurred, it is determined whether the memory address to be accessed by the load instruction and the memory address to be accessed by the storage instruction are the same. If the memory addresses to be accessed by the two instructions are different, it indicates that there is no longer a dependency relationship between the load instruction and the storage instruction, that is, the execution of the load instruction is unrelated to the storage instruction. Accordingly, during the execution of the load instruction, the same conflict event will not occur. In this case, the event entry corresponding to the conflict event in the execution information table is set to an invalid state, so that the load instruction continues to be executed according to the current execution progress of the load instruction, without waiting for the storage instruction to be executed before executing the load instruction, thereby improving the execution efficiency of the load instruction and thus improving the performance of the processor in executing instructions.

[0054] FIG3 is a flow chart of another method for executing a load instruction according to an embodiment of the present application. Referring to FIG3 , the present embodiment is described using execution by a terminal as an example. The method for executing the load instruction includes the following steps:

[0055] 301. During the execution of a first load instruction, if a first event entry exists among multiple event entries in an execution information table, the terminal queries a storage instruction queue based on the first event entry. Each event entry in the execution information table is used to indicate a second load instruction and a second storage instruction in which a conflicting event exists during the historical execution process. The second load instruction indicated by the first event entry is the same as the first load instruction, and the storage instruction queue includes multiple second storage instructions.

[0056] In an embodiment of the present application, the execution information table includes multiple event entries, and the embodiment of the present application does not limit the number of event entries in the execution information table. For example, the execution information table includes 1024 event entries. For any event entry, the event entry includes a corresponding event identifier. The event identifier is unique and is used to indicate the corresponding conflict event and the load instruction and store instruction in which the conflict event occurred. The execution information table can be an SSIT (Store Set ID Table), and the event identifier can be an SSID (Store Set ID), which is not limited in the embodiment of the present application.

[0057] In the process of executing multiple instructions in the terminal execution program, for a conflict event occurring between any load instruction and any store instruction, the terminal assigns an event identifier to the conflict event and records it in the execution information table. The store instruction queue (Store Queue) includes multiple second store instructions and event identifiers corresponding to each second store instruction. In the process of executing the first load instruction, if there is a first event entry among the multiple event entries in the execution information table, the terminal queries the store instruction queue based on the event identifier in the first event entry. Then, if the event identifier exists in the store instruction queue, it is determined that the second store instruction corresponding to the event identifier is the first store instruction. If the event identifier does not exist in the store instruction queue, the terminal continues to execute the first load instruction according to the current execution progress of the first load instruction.

[0058] In some embodiments, each event entry in the execution information table contains the instruction address of the second load instruction corresponding to the event entry. The instruction address is used to indicate the location of the corresponding second load instruction. The terminal can query whether the first event entry exists in the execution information table through the instruction address. Accordingly, the terminal queries the execution information table based on the instruction address of the first load instruction. In the case where the instruction address exists in the execution information table, the terminal determines that the event entry where the instruction address is located is the first event entry. The solution provided by the embodiment of the present application records the instruction address of the load instruction corresponding to the event entry in each event entry of the execution information table. For any load instruction to be executed, the instruction address of the load instruction is used to query whether the same instruction address exists in the execution information table, thereby more accurately determining whether a load instruction such as the load instruction has occurred a conflict event, thereby facilitating the subsequent more accurate execution of the load instruction based on whether a conflict event has occurred.

[0059] If the instruction address does not exist in the execution information table, the terminal will continue to execute the first load instruction according to its current execution progress. In other words, if a load instruction such as the first load instruction has not experienced a conflict event, the terminal can continue to execute the first load instruction without worrying about other storage instructions. If, after executing the first load instruction, the terminal determines that a conflict event has occurred between the first load instruction and other storage instructions, the terminal will record the conflict event as an event entry in the execution information table.

[0060] The instruction address can be represented by the instruction PC (Program Counter), which is not limited in this embodiment of the present application. In the process of obtaining the instruction address of the first load instruction, the terminal obtains the current instruction address. The current instruction address is used to indicate the instruction address of the next instruction of the first load instruction. Then, the terminal subtracts the offset from the current instruction address to obtain the instruction address of the first load instruction. The offset is used to indicate the difference between the instruction address of the first load instruction and the instruction address of the next instruction. In other words, the offset is used to indicate the position occupied by the next instruction of the first load instruction. Among them, "subtracting the offset from the current instruction address" can be regarded as shifting left on the basis of the current instruction address to obtain the instruction address of the previous instruction of the instruction indicated by the current instruction address. The terminal obtains the current PC value (current instruction address) of the instruction counter. Then, the terminal subtracts the offset from the current PC value to obtain the PC value corresponding to the first load instruction. The instruction address in the execution information table can also be determined in the above manner. The solution provided in the embodiment of the present application can more accurately determine the instruction address of the first load instruction by subtracting the offset from the current instruction address; and by recording the instruction address in the execution information table in the above manner, it is possible to accurately record the location of the load instruction where the conflict event occurs, thereby facilitating subsequent more accurate query of the execution information table.

[0061] The embodiment of the present application does not limit the form of storing instruction addresses in the execution information table. Optionally, the instruction address contained in each event entry in the execution information table is an address identifier. Each address identifier is obtained by hashing the instruction address of the corresponding second load instruction. Accordingly, the process of the terminal querying the execution information table based on the instruction address of the first load instruction includes: the terminal performs a hash operation on the instruction address of the first load instruction to obtain the address identifier of the first load instruction. Then, the terminal queries the execution information table based on the address identifier. The amount of data occupied by the address identifier is less than the amount of data occupied by the instruction address. The solution provided in the embodiment of the present application stores the instruction address by performing a hash operation on the instruction address to obtain the address identifier, which can reduce the amount of data occupied by the execution information table, thereby saving storage space; since the hash operation has the function of data integrity verification, the address identifier after the hash operation can also indicate the uniqueness of the instruction address, so that the corresponding event entry can be accurately found according to the address identifier, which is conducive to the subsequent more accurate execution of the load instruction, so as to improve the execution efficiency of the load instruction.

[0062] The embodiment of the present application does not limit the specific operation process of the hash operation. Optionally, the terminal can use 20 bits as a reference, perform folded OR on the PC value corresponding to the instruction address, then perform zero extension, and finally perform XOR operations based on a 3-bit width to obtain the instruction identifier.

[0063] Figure 4 is a schematic diagram of a query execution information table provided according to an embodiment of the present application. Referring to Figure 4, the terminal determines the instruction address (PC value) of the first load instruction. The size of the instruction address can be 39 bits, which is not limited by the embodiment of the present application. Then, the terminal performs a hash operation on the instruction address of the first load instruction to obtain the address identifier of the first load instruction. The size of the address identifier can be 3 bits, which is not limited by the embodiment of the present application. Then, the terminal queries the execution information table based on the address identifier of the first load instruction. When the address identifier exists in the execution information table, it is determined that the event entry where the address identifier is located is the first event entry. Then, the terminal obtains the event identifier in the first event entry and queries the storage instruction queue. The size of the event identifier can be 5 bits, which is not limited by the embodiment of the present application.

[0064] The execution information table also includes a counter between the second load instruction and the second storage instruction indicated by the event entry. The counter is used to indicate the degree of correlation between the corresponding second load instruction and the second storage instruction. The terminal can execute the first load instruction based on the counter corresponding to the first load instruction. In some embodiments, each event entry in the execution information table includes a counter. Continuing with Figure 4, the counter of each event entry is used to indicate the degree of correlation between the corresponding second load instruction and the second storage instruction. In this case, the terminal can execute the first load instruction according to steps 302, 303, and 306. In other embodiments, the multiple event entries in the execution information table are divided into multiple event sets, each event set corresponds to a counter, and each counter is used to indicate the degree of correlation between the corresponding second load instruction and the second storage instruction in the corresponding event set. In this case, the terminal can execute the first load instruction according to steps 304, 305, and 306.

[0065] 302. If there is a first storage instruction in the storage instruction queue, and the memory address to be accessed by the first load instruction is different from the memory address to be accessed by the first storage instruction, the terminal determines the correlation between the first load instruction and the first storage instruction based on the execution information table, the first storage instruction is the second storage instruction indicated by the first event entry, and the first storage instruction is not successfully executed. The correlation is used to indicate the degree of correlation between the first load instruction and the first storage instruction, and the correlation is positively correlated with the probability of the conflict event corresponding to the first event entry occurring in the first load instruction.

[0066] In an embodiment of the present application, the terminal uses the second storage instruction whose event identifier is the same as the event identifier of the first event entry and has not yet been executed as the first storage instruction. When the first storage instruction exists in the storage instruction queue, the terminal determines whether the memory address to be accessed by the first load instruction is the same as the memory address to be accessed by the first storage instruction. When the memory address to be accessed by the first load instruction is different from the memory address to be accessed by the first storage instruction, the terminal determines that there is no dependency relationship between the first load instruction and the first storage instruction. Accordingly, the terminal re-determines the degree of association between the first load instruction and the first storage instruction based on the original degree of association in the first event entry in the execution information table. That is, when it is determined that there is no dependency relationship between the first load instruction and the first storage instruction, the terminal updates the degree of association in the execution information table for indicating the degree of correlation between the first load instruction and the first storage instruction. This degree of association can also be called a dependency, which is used to reflect the degree of dependence of the first load instruction on the first storage instruction.

[0067] Among them, the dependency relationship between the load instruction and the store instruction refers to the data that the load instruction wants to obtain from the memory address is the data stored at the memory address by the store instruction. For example, the load instruction is load R0, [R1], which is used to read data from the memory address indicated by register R1 and write it to register R0. The store instruction is store R2, [R1], which is used to read data in register R2 and write it to the memory address indicated by register R1. It can be seen that the data that the load instruction wants to obtain from the memory address is the data stored at the memory address by the store instruction. In other words, there is a dependency relationship between the load instruction and the store instruction.

[0068] During the query of the store instruction queue, the second store instruction in the store instruction queue may be classified into the following five types based on the first load instruction:

[0069] A first type of second storage instruction includes an event identifier of the second storage instruction that is the same as the event identifier of the first load instruction; the age of the second storage instruction is greater than the age of the first load instruction; the memory address to be accessed by the second storage instruction is valid; and the memory address to be accessed by the second storage instruction is the same as the memory address to be accessed by the first load instruction. The age of an instruction is used to indicate a precedence order among multiple instructions in a program. The older the instruction, the earlier the instruction is executed; the younger the instruction, the later the instruction is executed.

[0070] A second type of second storage instruction, wherein the event identifier of the second storage instruction is the same as the event identifier of the first load instruction; the age of the second storage instruction is older than the age of the first load instruction; the memory address to be accessed by the second storage instruction is valid; and the memory address to be accessed by the second storage instruction is different from the memory address to be accessed by the first load instruction.

[0071] A third type of second storage instruction, wherein the event identifier of the second storage instruction is the same as the event identifier of the first load instruction; the age of the second storage instruction is greater than the age of the first load instruction; and the memory address to be accessed by the second storage instruction is invalid.

[0072] A fourth type of second storage instruction, wherein the event identifier of the second storage instruction is the same as the event identifier of the first load instruction; and the age of the second storage instruction is younger than the age of the first load instruction.

[0073] A fifth type of second storage instruction, wherein the event identifier of the second storage instruction is different from the event identifier of the first load instruction.

[0074] Accordingly, in a case where the first storage instruction is the third type of second storage instruction, the terminal determines the association degree between the first load instruction and the first storage instruction based on the execution information table.

[0075] In the process of determining the correlation between the first load instruction and the first store instruction based on the execution information table, if the first store instruction exists in the store instruction queue, the terminal determines the first correlation based on the first event entry in the execution information table. Then, if the memory address to be accessed by the first load instruction is different from the memory address to be accessed by the first store instruction, the terminal reduces the first correlation to obtain a second correlation. The first correlation is the correlation between the load instruction and the store instruction when the corresponding conflict event occurs in the historical execution process. The second correlation is the correlation between the first load instruction and the first store instruction in the current execution process. That is, the first correlation is the original correlation between the first load instruction and the first store, and the second correlation is the correlation updated according to the current situation. If the memory address to be accessed by the first load instruction is different from the memory address to be accessed by the first store instruction, the terminal determines that there is a high probability that there is no dependency relationship between the first load instruction and the first store, and accordingly reduces the correlation between the first load instruction and the first store.

[0076] In some embodiments, when the memory address to be accessed by the first load instruction and the memory address to be accessed by the first store instruction are the same, the terminal enhances the first correlation to obtain a third correlation, which is the correlation between the first load instruction and the first store instruction during the current execution process.

[0077] The solution provided in the embodiment of the present application timely updates the correlation in the execution information table according to the memory addresses to be accessed by the current first load instruction and the first store instruction. That is, when the memory addresses to be accessed are the same, the correlation is enhanced; when the memory addresses to be accessed are different, the correlation is reduced, so that the execution information table can accurately reflect the dependency relationship (degree of correlation) between the load instruction and the store instruction in real time. Since the dependency relationship will directly affect whether a conflict event will occur between the load instruction and the store instruction, it is beneficial to subsequently execute the load instruction according to the accurate correlation, thereby ensuring the correctness of the instruction execution.

[0078] For example, the association degree in the execution information table can be 0, 1, 2, and 3. When the association degree is 3, it indicates that there is a strong dependency between the load instruction and the store instruction corresponding to the association degree; when the association degree is 0, it indicates that there is almost no dependency between the load instruction and the store instruction corresponding to the association degree. When the memory address to be accessed by the first load instruction and the memory address to be accessed by the first store instruction are different, the terminal reduces the first association degree to obtain a third association degree. For example, the association degree is reduced from 3 to 2, or from 2 to 1, or from 1 to 0, and this embodiment of the present application is not limited to this. When the memory address to be accessed by the first load instruction and the memory address to be accessed by the first store instruction are the same, the terminal enhances the first association degree to obtain a third association degree. For example, the association degree is increased from 0 to 1, or from 1 to 2, or from 2 to 3, and this embodiment of the present application is not limited to this. Alternatively, when the memory address to be accessed by the first load instruction and the memory address to be accessed by the first store instruction are the same, the terminal sets the association degree to a preset value. The preset value is used to represent the value with the strongest correlation, which may be 3, and the embodiment of the present application does not limit this. The size of the correlation degree in the execution information table may be 2 bits, and the embodiment of the present application does not limit this.

[0079] 303. When the correlation degree satisfies the first condition, the terminal sets the state of the first event entry in the execution information table to an invalid state, where the invalid state indicates that the conflict event corresponding to the first event entry will not occur during the current execution of the first load instruction.

[0080] In an embodiment of the present application, the first condition may be that the correlation reaches a certain correlation threshold, or that the correlation reaches a preset correlation range, which is not limited in this embodiment of the present application. When the correlation in the first event entry satisfies the first condition, the terminal sets the status of the first event entry in the execution information table to invalid. If the correlation in the first event entry does not satisfy the first condition, the terminal maintains the status of the first event entry in the execution information table in a valid state. The valid state indicates that the conflict event corresponding to the first event entry may still occur during the current execution of the first load instruction. The status and correlation of the first event entry in the execution information table can be considered as prediction information for the first load instruction. That is, the terminal compares the event identifiers and the memory space to be accessed between the load instruction and the storage instruction, and predicts the correlation and status of the event entry during the current execution based on the existing information in the execution information table. The correlation and status of the event entry reflect whether a conflict event will occur during the current execution. In other words, the terminal predicts whether the conflict event corresponding to the first event entry will occur during the execution of the first load instruction.

[0081] In some embodiments, each event entry in the execution information table further includes a utility value (valid). The utility value of each event entry is used to indicate whether a conflict event corresponding to the event entry will occur. Accordingly, the process of the terminal setting the state of the first event entry in the execution information table to an invalid state includes: when the correlation degree meets the first condition, the terminal changes the utility value of the first event entry in the execution information table from a first value to a second value, where the first value is used to indicate a valid state. The valid state is used to indicate that the conflict event corresponding to the first event entry will occur during the current execution of the first load instruction. The second value is used to indicate an invalid state.

[0082] For example, referring to Figure 4 , the size of each utility value can be 1 bit, which is not limited in the present embodiment. Each utility value can be 0 or 1. 0 indicates an invalid state, and 1 indicates a valid state.

[0083] In some embodiments, if the association does not satisfy the first condition, the terminal stops the current execution of the first load instruction. The terminal stores the first load instruction in a load instruction queue, awaiting re-execution. That is, if the association does not satisfy the first condition, a conflict event corresponding to the first event entry may still occur during the current execution of the first load instruction, so the terminal stops the current execution of the first load instruction.

[0084] FIG5 is a schematic diagram of an execution information table update according to an embodiment of the present application. Referring to FIG5 , during the execution of a first load instruction, if a first event entry exists among multiple event entries in the execution information table, the terminal queries a storage instruction queue based on the event identifier of the first event entry. The terminal determines whether a storage instruction with the same event identifier exists in the storage instruction queue. If no storage instruction with the same event identifier exists in the storage instruction queue, the terminal continues to execute the first load instruction according to the current execution progress of the first load instruction. If the first storage instruction exists in the storage instruction queue, the terminal determines whether the memory address to be accessed by the first storage instruction is ready. If it is determined that the memory address to be accessed by the first storage instruction is ready, the terminal determines whether the memory address to be accessed by the first load instruction is the same as the memory address to be accessed by the first storage instruction. The event identifier of the first storage instruction is the same as the event identifier of the first event entry. If the memory address to be accessed by the first load instruction is the same as the memory address to be accessed by the first storage instruction, the terminal executes the first load instruction according to the first storage instruction. In other words, after the execution of the first storage instruction is completed, the first load instruction is executed. When the memory address to be accessed by the first load instruction is different from the memory address to be accessed by the first storage instruction, the correlation between the first load instruction and the first storage instruction in the execution information table is updated. When the correlation satisfies the first condition, the terminal sets the status of the first event entry in the execution information table to an invalid state. Then, the terminal continues to execute the first load instruction according to the updated execution information table. When it is determined that the memory address to be accessed by the first storage instruction is not ready, the terminal stores the first load instruction in the load instruction queue and waits for re-execution. The terminal calculates the memory address to be accessed by the first storage instruction, that is, determines the memory address that the first load instruction is waiting for. Then, the terminal can re-execute the first load instruction based on the memory address.

[0085] In the solution provided by the embodiment of the present application, each event entry in the execution information table includes an association degree. When the memory address to be accessed by any load instruction is different from the memory address to be accessed by the corresponding store instruction, the association degree corresponding to the load instruction can be updated. Therefore, when the association degree meets the first condition, the event entry where the load instruction is located is set to an invalid state, thereby achieving the purpose of accurately updating the status of each event entry. There is no need to update the status of all event entries in the execution information table at a fixed time, thereby improving the update efficiency of the execution information table and providing a basis for the execution of subsequent load instructions.

[0086] 304. If there is a first storage instruction in the storage instruction queue, and the memory address to be accessed by the first load instruction is different from the memory address to be accessed by the first storage instruction, the terminal determines the correlation corresponding to the event set where the first event entry is located based on the execution information table.

[0087] In an embodiment of the present application, multiple event entries in the execution information table are divided into multiple event sets, and the embodiment of the present application does not limit the size and number of the time range. Each event set includes multiple event entries. Each event set corresponds to a correlation. Each correlation is used to indicate the degree of correlation between the corresponding second load instruction and the second storage instruction in the corresponding event set. In the case where the memory address to be accessed by the first load instruction is different from the memory address to be accessed by the first storage instruction, the terminal can reduce the correlation corresponding to the event set where the first event entry is located. In the case where the memory address to be accessed by the first load instruction is the same as the memory address to be accessed by the first storage instruction, the terminal can enhance the correlation corresponding to the event set where the first event entry is located. The principle of the terminal updating the correlation in the execution information table is similar to the principle of updating the correlation in step 302, and will not be repeated here.

[0088] For example, Figure 6 is a schematic diagram of an execution information table provided according to an embodiment of the present application. Referring to Figure 6, the execution information table includes multiple event entries. Each event entry includes an event identifier, an address identifier, and a utility value. The multiple event entries in the execution information table are divided into four event sets. Each event set corresponds to a correlation degree. The amount of data occupied by the correlation degree of each event set can be 9 bits, which is not limited by the embodiment of the present application. In the case where the memory address to be accessed by the first load instruction is different from the memory address to be accessed by the first storage instruction, the terminal can reduce the correlation degree corresponding to the event set where the first event entry is located by one; in the case where the memory address to be accessed by the first load instruction is the same as the memory address to be accessed by the first storage instruction, the terminal can increase the correlation degree corresponding to the event set where the first event entry is located by one.

[0089] 305. When the correlation degree satisfies the second condition, the terminal sets the states of multiple event entries in the event set where the first event entry is located to an invalid state, where the invalid state indicates that the conflict event corresponding to the first event entry will not occur during the current execution of the first load instruction.

[0090] In an embodiment of the present application, the second condition may be that the degree of correlation reaches a certain correlation threshold, or that the degree of correlation reaches a preset correlation range, and the embodiment of the present application does not limit this. When the degree of correlation of the event set meets the second condition, the terminal sets the status of multiple event entries in the event set where the first event entry in the execution information table is located to an invalid state. In the case where the degree of correlation of the event set does not meet the second condition, the terminal sets the status of multiple event entries in the event set where the first event entry in the execution information table is located to remain unchanged. The principle of the terminal setting the event entry to an invalid state is similar to the principle of setting the event entry to an invalid state in step 303, and will not be repeated here.

[0091] For example, the second condition is a correlation threshold of 512. When the correlation degree of the event set reaches 512, the terminal sets the status of all event entries in the event set where the first event entry is located to an invalid state.

[0092] Since in the solution corresponding to steps 302 to 303, the utility value in each event entry occupies 2 bits of data. An execution information table includes 1024 event entries, and the utility value in the execution information table requires 2*1024 bits of storage space. In the solution corresponding to steps 304 to 303, the multiple event entries in the execution information table are divided into multiple event sets, and the utility value corresponding to each event set occupies 9 bits of data. An execution information table includes 4 event sets, and the utility value in the execution information table requires 4*9 bits of storage space, which is much smaller than the above-mentioned 2*1024 bits of storage space, saving storage space.

[0093] 306. When the state of the first event entry in the execution information table is invalid, the terminal continues to execute the first loading instruction according to the current execution progress of the first loading instruction.

[0094] In this embodiment of the present application, if the state of the first event entry in the execution information table is invalid, it is determined that there is no dependency relationship between the first load instruction and the first store instruction. In this case, the execution of the first load instruction is independent of the first store instruction. Therefore, the terminal continues to execute the first load instruction according to the current execution progress of the first load instruction.

[0095] To more clearly illustrate the solution provided by the embodiments of the present application, the following further describes the method for executing a load instruction in conjunction with the accompanying drawings. Figure 7 is a schematic diagram of a method for executing a load instruction according to an embodiment of the present application. Referring to Figure 7, during the process of a terminal executing multiple instructions in a program, for any conflict event that occurs between any load instruction and any store instruction, the terminal assigns an event identifier to the conflict event and records it in an execution information table. For any load instruction, the terminal performs a hash operation based on the instruction address of the load instruction to obtain the address identifier of the load instruction. The terminal then queries the execution information table based on the address identifier of the load instruction. If the address identifier exists in the execution information table, the terminal obtains the event identifier from the event entry containing the address identifier. During the process of executing the load instruction according to the pipeline, the terminal queries the store instruction queue based on the event identifier. If a store instruction with the same event identifier exists in the store instruction queue, the terminal determines whether the memory address to be accessed by the load instruction is the same as the memory address to be accessed by the store instruction. If the memory address to be accessed by the load instruction is different from the memory address to be accessed by the store instruction, the terminal updates the execution information table. If the corresponding event entry in the execution information table is in an invalid state, the terminal continues to execute the first load instruction according to the current execution progress of the load instruction. Otherwise, the terminal stops the current execution progress of the load instruction and stores the load instruction in the load instruction queue, awaiting re-execution. The pipeline includes multiple stages during the execution of the load instruction.

[0096] An embodiment of the present application provides a method for executing a load instruction. During the execution of any load instruction, if it is determined that a conflict event has occurred with a load instruction similar to the load instruction, a storage instruction queue is queried based on the event entry corresponding to the conflict event in an execution information table to determine the storage instruction in which the conflict event has occurred. Since the memory access addresses of instructions in the program will change as the program runs, after determining the storage instruction in which the conflict event has occurred, it is determined whether the memory address to be accessed by the load instruction and the memory address to be accessed by the storage instruction are the same. If the memory addresses to be accessed by the two instructions are different, it indicates that there is no longer a dependency relationship between the load instruction and the storage instruction, that is, the execution of the load instruction is unrelated to the storage instruction. Accordingly, during the execution of the load instruction, the same conflict event will not occur. In this case, the event entry corresponding to the conflict event in the execution information table is set to an invalid state, so that the load instruction continues to be executed according to the current execution progress of the load instruction, without waiting for the storage instruction to be executed before executing the load instruction, thereby improving the execution efficiency of the load instruction and thus improving the performance of the processor in executing instructions.

[0097] FIG8 is a block diagram of a processor according to an embodiment of the present application. The processor is configured to execute the steps of the aforementioned method for executing a load instruction. Referring to FIG8 , the processor includes an instruction query unit 801, an entry processing unit 802, and an execution unit 803.

[0098] an instruction query unit 801 configured to query a storage instruction queue based on the first event entry when a first event entry exists among multiple event entries in an execution information table during execution of a first load instruction, wherein each event entry in the execution information table indicates a second load instruction and a second store instruction having a conflicting event during a historical execution process, the second load instruction indicated by the first event entry being the same as the first load instruction, and the storage instruction queue including multiple second store instructions;

[0099] an entry processing unit 802 configured to, if a first storage instruction exists in the storage instruction queue and a memory address to be accessed by the first load instruction is different from a memory address to be accessed by the first storage instruction, set the state of the first event entry in the execution information table to an invalid state, the first storage instruction being the second storage instruction indicated by the first event entry, the first storage instruction being not successfully executed, and the invalid state indicating that a conflict event corresponding to the first event entry will not occur during the current execution of the first load instruction;

[0100] The execution unit 803 is configured to continue executing the first load instruction according to the current execution progress of the first load instruction when the state of the first event entry in the execution information table is invalid.

[0101] In some embodiments, each event entry in the execution information table includes the instruction address of the second load instruction corresponding to the event entry, and the instruction address is used to indicate the location of the corresponding second load instruction. FIG9 is a block diagram of another processor provided according to an embodiment of the present application. Referring to FIG9 , the processor further includes: an address query unit 804 and an entry determination unit 805.

[0102] An address query unit 804 is configured to query an execution information table based on an instruction address of the first load instruction;

[0103] The entry determining unit 805 is configured to determine, when the instruction address exists in the execution information table, that the event entry where the instruction address is located is the first event entry.

[0104] In some embodiments, the instruction address included in each event entry in the execution information table is an address identifier, and each address identifier is obtained by performing a hash operation on the instruction address of the corresponding second load instruction;

[0105] The address query unit 804 is configured to perform a hash operation on the instruction address of the first load instruction to obtain an address identifier of the first load instruction; and query the execution information table based on the address identifier.

[0106] In some embodiments, referring to FIG. 9 , the processor further includes an address obtaining unit 806 and an address processing unit 807 .

[0107] An address acquisition unit 806 is used to acquire a current instruction address, where the current instruction address is used to indicate an instruction address of the next instruction after the first load instruction;

[0108] The address processing unit 807 is configured to subtract an offset from a current instruction address to obtain an instruction address of a first load instruction, where the offset indicates a difference between the instruction address of the first load instruction and an instruction address of a next instruction.

[0109] In some embodiments, referring to FIG9 , the entry processing unit 802 includes: a determining subunit 8021 and a processing subunit 8022 ;

[0110] a determining subunit 8021 configured to, if the first store instruction exists in the store instruction queue and the memory address to be accessed by the first load instruction is different from the memory address to be accessed by the first store instruction, determine, based on the execution information table, a correlation between the first load instruction and the first store instruction, wherein the correlation indicates a degree of correlation between the first load instruction and the first store instruction, and the correlation is positively correlated with a probability of the first load instruction generating a conflict event corresponding to the first event entry;

[0111] The processing sub-unit 8022 is configured to set the state of the first event entry in the execution information table to an invalid state when the correlation degree satisfies the first condition.

[0112] In some embodiments, each event entry in the execution information table includes a correlation degree, and the correlation degree of each event entry is used to indicate a degree of correlation between the corresponding second load instruction and the second store instruction;

[0113] Determine sub-unit 8021, for determining a first degree of association based on a first event entry in an execution information table if a first storage instruction exists in the storage instruction queue, the first degree of association being the degree of association between the load instruction and the storage instruction when a corresponding conflict event occurs during a historical execution process; and for reducing the first degree of association to obtain a second degree of association when a memory address to be accessed by the first load instruction is different from a memory address to be accessed by the first storage instruction, the second degree of association being the degree of association between the first load instruction and the first storage instruction during a current execution process.

[0114] In some embodiments, the determination subunit 8021 is also used to enhance the first correlation when the memory address to be accessed by the first load instruction and the memory address to be accessed by the first storage instruction are the same, and obtain a third correlation, where the third correlation is the correlation between the first load instruction and the first storage instruction in the current execution process.

[0115] In some embodiments, each event entry in the execution information table includes a utility value, and the utility value of each event entry is used to indicate whether a conflict event corresponding to the event entry will occur;

[0116] The processing sub-unit 8022 is used to change the utility value of the first event entry in the execution information table from a first value to a second value when the correlation degree meets the first condition, wherein the first value is used to indicate a valid state, and the valid state is used to indicate that a conflict event corresponding to the first event entry will occur during the current execution of the first load instruction, and the second value is used to indicate an invalid state.

[0117] In some embodiments, the processor further includes: a progress processing unit 808 .

[0118] The progress processing unit 808 is configured to stop the current execution progress of the first load instruction if the correlation does not satisfy the first condition; and store the first load instruction in a load instruction queue to wait for re-execution.

[0119] In some embodiments, the plurality of event entries in the execution information table are divided into a plurality of event sets, each event set corresponds to a correlation degree, and each correlation degree is used to indicate a degree of correlation between a corresponding second load instruction and a corresponding second store instruction in the corresponding event set;

[0120] The entry processing unit 802 is used to determine the correlation corresponding to the event set where the first event entry is located based on the execution information table if there is a first storage instruction in the storage instruction queue and the memory address to be accessed by the first load instruction is different from the memory address to be accessed by the first storage instruction; and if the correlation satisfies the second condition, set the status of multiple event entries in the event set where the first event entry is located to an invalid state.

[0121] An embodiment of the present application provides a processor. During the execution of any load instruction, if it is determined that a conflict event has occurred with a load instruction similar to the load instruction, a storage instruction queue is queried based on the event entry corresponding to the conflict event in an execution information table to determine the storage instruction in which the conflict event has occurred. Since the memory access addresses of instructions in the program will change as the program runs, after determining the storage instruction in which the conflict event has occurred, it is determined whether the memory address to be accessed by the load instruction and the memory address to be accessed by the storage instruction are the same. If the memory addresses to be accessed by the two instructions are different, it indicates that there is no longer a dependency relationship between the load instruction and the storage instruction, that is, the execution of the load instruction is unrelated to the storage instruction. Accordingly, during the execution of the load instruction, the same conflict event will not occur. In this case, the event entry corresponding to the conflict event in the execution information table is set to an invalid state, so that the load instruction continues to be executed according to the current execution progress of the load instruction, without waiting for the execution of the storage instruction before executing the load instruction, thereby improving the execution efficiency of the load instruction and thus improving the performance of the processor in executing instructions.

[0122] Figure 10 is a block diagram of a load instruction execution device provided according to an embodiment of the present application. The load instruction execution device is used to execute the steps of the above-mentioned load instruction execution method. Referring to Figure 10, the load instruction execution device includes: a first query module 1001, a first processing module 1002, and an execution module 1003.

[0123] A first query module 1001 is configured to query a storage instruction queue based on the first event entry when a first event entry exists among multiple event entries in an execution information table during execution of a first load instruction, wherein each event entry in the execution information table indicates a second load instruction and a second storage instruction having a conflicting event during a historical execution process, the second load instruction indicated by the first event entry is the same as the first load instruction, and the storage instruction queue includes multiple second storage instructions;

[0124] A first processing module 1002 is configured to, if a first storage instruction exists in the storage instruction queue and a memory address to be accessed by the first load instruction is different from a memory address to be accessed by the first storage instruction, set the state of a first event entry in the execution information table to an invalid state, the first storage instruction being the second storage instruction indicated by the first event entry, the first storage instruction being not successfully executed, and the invalid state being used to indicate that a conflict event corresponding to the first event entry will not occur during the current execution of the first load instruction;

[0125] The execution module 1003 is configured to continue executing the first load instruction according to the current execution progress of the first load instruction when the state of the first event entry in the execution information table is invalid.

[0126] In some embodiments, each event entry in the execution information table includes the instruction address of the second load instruction corresponding to the event entry, and the instruction address is used to indicate the location of the corresponding second load instruction; Figure 11 is a block diagram of another load instruction execution device provided according to an embodiment of the present application. Referring to Figure 11, the device also includes:

[0127] A second query module 1004 is configured to query the execution information table based on the instruction address of the first load instruction;

[0128] The determining module 1005 is configured to determine, when the instruction address exists in the execution information table, that the event entry where the instruction address is located is the first event entry.

[0129] In some embodiments, the instruction address included in each event entry in the execution information table is an address identifier, and each address identifier is obtained by performing a hash operation on the instruction address of the corresponding second load instruction;

[0130] Continuing to refer to FIG. 11 , the second query module 1004 is configured to perform a hash operation on the instruction address of the first load instruction to obtain an address identifier of the first load instruction; and query the execution information table based on the address identifier.

[0131] In some embodiments, referring to FIG11 , the apparatus further includes:

[0132] An acquisition module 1006 is configured to acquire a current instruction address, where the current instruction address is used to indicate an instruction address of the next instruction after the first load instruction.

[0133] The second processing module 1007 is configured to subtract the offset from the current instruction address to obtain the instruction address of the first load instruction. The offset is used to indicate the position of the next instruction after the first load instruction.

[0134] In some embodiments, referring to FIG. 11 , the first processing module 1002 includes:

[0135] a determining unit 10021 configured to, if the first store instruction exists in the store instruction queue and the memory address to be accessed by the first load instruction is different from the memory address to be accessed by the first store instruction, determine, based on the execution information table, a degree of association between the first load instruction and the first store instruction, wherein the degree of association indicates a degree of correlation between the first load instruction and the first store instruction, and the degree of association is positively correlated with a probability of the first load instruction causing a conflict event corresponding to the first event entry;

[0136] The processing unit 10022 is configured to set the state of the first event entry in the execution information table to an invalid state when the correlation degree satisfies the first condition.

[0137] In some embodiments, each event entry in the execution information table includes a correlation degree, and the correlation degree of each event entry is used to indicate a degree of correlation between the corresponding second load instruction and the second store instruction;

[0138] Continuing to refer to Figure 11, the determination unit 10021 is used to determine a first correlation degree based on the first event entry in the execution information table if there is a first storage instruction in the storage instruction queue, the first correlation degree being the correlation degree between the load instruction and the storage instruction when the corresponding conflict event occurs in the historical execution process; and when the memory address to be accessed by the first load instruction is different from the memory address to be accessed by the first storage instruction, reducing the first correlation degree to obtain a second correlation degree, the second correlation degree being the correlation degree between the first load instruction and the first storage instruction in the current execution process.

[0139] In some embodiments, referring to Figure 11, the determination unit 10021 is also used to enhance the first correlation when the memory address to be accessed by the first load instruction and the memory address to be accessed by the first storage instruction are the same, and obtain a third correlation. The third correlation is the correlation between the first load instruction and the first storage instruction in the current execution process.

[0140] In some embodiments, each event entry in the execution information table includes a utility value, and the utility value of each event entry is used to indicate whether a conflict event corresponding to the event entry will occur;

[0141] Continuing to refer to FIG11 , the processing unit 10022 is configured to change the utility value of the first event entry in the execution information table from a first value to a second value when the correlation degree satisfies the first condition. The first value is used to indicate a valid state, which indicates that a conflict event corresponding to the first event entry will occur during the current execution of the first load instruction. The second value is used to indicate an invalid state.

[0142] In some embodiments, referring to FIG11 , the apparatus further includes:

[0143] The third processing module 1008 is configured to stop the current execution progress of the first load instruction if the correlation does not satisfy the first condition; and store the first load instruction in a load instruction queue to wait for re-execution.

[0144] In some embodiments, the plurality of event entries in the execution information table are divided into a plurality of event sets, each event set corresponds to a correlation degree, and each correlation degree is used to indicate a degree of correlation between a corresponding second load instruction and a corresponding second store instruction in the corresponding event set;

[0145] Continuing to refer to Figure 11, the first processing module 1002 is used to determine the correlation corresponding to the event set where the first event entry is located based on the execution information table if there is a first storage instruction in the storage instruction queue and the memory address to be accessed by the first load instruction is different from the memory address to be accessed by the first storage instruction; and when the correlation satisfies the second condition, set the status of multiple event entries in the event set where the first event entry is located to an invalid state.

[0146] An embodiment of the present application provides an execution device for a load instruction. During the execution of any load instruction, if it is determined that a conflict event has occurred with a load instruction similar to the load instruction, a storage instruction queue is queried based on the event entry corresponding to the conflict event in an execution information table to determine the storage instruction in which the conflict event has occurred. Since the memory access addresses of instructions in the program change as the program runs, after determining the storage instruction in which the conflict event has occurred, it is determined whether the memory address to be accessed by the load instruction and the memory address to be accessed by the storage instruction are the same. If the memory addresses to be accessed by the two instructions are different, it indicates that there is no longer a dependency relationship between the load instruction and the storage instruction, that is, the execution of the load instruction is unrelated to the storage instruction. Accordingly, during the execution of the load instruction, the same conflict event will not occur. In this case, the event entry corresponding to the conflict event in the execution information table is set to an invalid state, so that the load instruction continues to be executed according to the current execution progress of the load instruction, without waiting for the storage instruction to be executed before executing the load instruction, thereby improving the execution efficiency of the load instruction and thus improving the performance of the processor in executing instructions.

[0147] It should be noted that the aforementioned embodiments of the apparatus for executing a load instruction provide only an example of the division of the aforementioned functional modules when running an application program. In actual applications, the aforementioned functions can be assigned to different functional modules as needed, i.e., the internal structure of the apparatus can be divided into different functional modules to complete all or part of the functions described above. Furthermore, the apparatus for executing a load instruction provided in the aforementioned embodiments and the embodiment of the method for executing a load instruction share the same concept. The specific implementation process is detailed in the method embodiment and will not be further elaborated here.

[0148] In the embodiments of the present application, the computer device can be configured as a terminal or a server. When the computer device is configured as a terminal, the terminal can be used as the execution subject to implement the technical solution provided in the embodiments of the present application. When the computer device is configured as a server, the server can be used as the execution subject to implement the technical solution provided in the embodiments of the present application. The technical solution provided in the present application can also be implemented through interaction between the terminal and the server. The embodiments of the present application do not limit this.

[0149] Figure 12 is a block diagram of a terminal 1200 according to an embodiment of the present application. Terminal 1200 may be a portable mobile terminal, such as a smartphone, a tablet computer, an MP3 player (Moving Picture Experts Group Audio Layer III), an MP4 player (Moving Picture Experts Group Audio Layer IV), a laptop computer, or a desktop computer. Terminal 1200 may also be referred to as user equipment, a portable terminal, a laptop terminal, a desktop terminal, or other similar names.

[0150] Typically, the terminal 1200 includes a processor 1201 and a memory 1202 .

[0151] Processor 1201 may include one or more processing cores, such as a quad-core processor or an octa-core processor. Processor 1201 may be implemented in at least one hardware form: a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), or a PLA (Programmable Logic Array). Processor 1201 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, processor 1201 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content required to be displayed on the display screen. In some embodiments, processor 1201 may also include an AI (Artificial Intelligence) processor, which is responsible for processing computing operations related to machine learning. Processor 1201 may be any of the processors shown in Figures 8 and 9, and this embodiment of the present application is not limited to this.

[0152] The memory 1202 may include one or more computer-readable storage media, which may be non-transitory. The memory 1202 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 1202 is used to store at least one computer program, which is executed by the processor 1201 to implement the execution method of the load instruction provided in the method embodiment of the present application.

[0153] In some embodiments, terminal 1200 may optionally include a peripheral device interface 1203 and at least one peripheral device. The processor 1201, memory 1202, and peripheral device interface 1203 may be connected via a bus or signal lines. Each peripheral device may be connected to peripheral device interface 1203 via a bus, signal lines, or circuit boards. Specifically, the peripheral device may include at least one of a radio frequency circuit 1204, a display screen 1205, a camera assembly 1206, an audio circuit 1207, and a power supply 1208.

[0154] The peripheral device interface 1203 can be used to connect at least one I / O (Input / Output)-related peripheral device to the processor 1201 and the memory 1202. In some embodiments, the processor 1201, the memory 1202, and the peripheral device interface 1203 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 1201, the memory 1202, and the peripheral device interface 1203 can be implemented on separate chips or circuit boards, which is not limited in this embodiment.

[0155] The RF circuit 1204 is used to receive and transmit RF (Radio Frequency) signals, also known as electromagnetic signals. The RF circuit 1204 communicates with communication networks and other communication devices via electromagnetic signals. The RF circuit 1204 converts electrical signals into electromagnetic signals for transmission, or converts received electromagnetic signals into electrical signals. In some embodiments, the RF circuit 1204 includes an antenna system, an RF transceiver, one or more amplifiers, a tuner, an oscillator, a digital signal processor, a codec chipset, a user identity module card, and the like. The RF circuit 1204 can communicate with other terminals via at least one wireless communication protocol. Such wireless communication protocols include, but are not limited to, the World Wide Web, metropolitan area networks, intranets, various generations of mobile communication networks (2G, 3G, 4G, and 5G), wireless local area networks, and / or WiFi (Wireless Fidelity) networks. In some embodiments, the RF circuit 1204 may also include circuitry related to Near Field Communication (NFC), although this application does not limit this.

[0156] The display screen 1205 is used to display a UI (User Interface). The UI may include graphics, text, icons, videos, and any combination thereof. When the display screen 1205 is a touch screen display, the display screen 1205 also has the ability to collect touch signals on the surface or above the surface of the display screen 1205. The touch signal can be input as a control signal to the processor 1201 for processing. At this time, the display screen 1205 can also be used to provide virtual buttons and / or virtual keyboards, also known as soft buttons and / or soft keyboards. In some embodiments, there can be one display screen 1205, which is set on the front panel of the terminal 1200; in other embodiments, there can be at least two display screens 1205, which are respectively set on different surfaces of the terminal 1200 or in a folding design; in other embodiments, the display screen 1205 can be a flexible display screen, which is set on the curved surface or folding surface of the terminal 1200. Even more, the display screen 1205 can be set to a non-rectangular irregular shape, that is, a special-shaped screen. The display screen 1205 can be made of materials such as LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode).

[0157] The camera assembly 1206 is used to capture images or videos. In some embodiments, the camera assembly 1206 includes a front camera and a rear camera. Typically, the front camera is arranged on the front panel of the terminal, and the rear camera is arranged on the back of the terminal. In some embodiments, there are at least two rear cameras, which are any one of a main camera, a depth of field camera, a wide-angle camera, and a telephoto camera, so as to realize the fusion of the main camera and the depth of field camera to realize the background blur function, the fusion of the main camera and the wide-angle camera to realize panoramic shooting and VR (Virtual Reality) shooting function or other fusion shooting functions. In some embodiments, the camera assembly 1206 may also include a flash. The flash can be a single-color temperature flash or a dual-color temperature flash. A dual-color temperature flash refers to a combination of a warm light flash and a cold light flash, which can be used for light compensation at different color temperatures.

[0158] The audio circuit 1207 may include a microphone and a speaker. The microphone is used to collect sound waves from the user and the environment, and convert the sound waves into electrical signals that are input into the processor 1201 for processing, or input into the RF circuit 1204 to achieve voice communication. For the purpose of stereo sound collection or noise reduction, there may be multiple microphones, each located in different parts of the terminal 1200. The microphone may also be an array microphone or an omnidirectional collection microphone. The speaker is used to convert electrical signals from the processor 1201 or the RF circuit 1204 into sound waves. The speaker may be a traditional thin film speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can not only convert electrical signals into sound waves audible to humans, but also convert electrical signals into sound waves inaudible to humans for purposes such as distance measurement. In some embodiments, the audio circuit 1207 may also include a headphone jack.

[0159] Power supply 1208 is used to power various components in terminal 1200. Power supply 1208 can be AC ​​power, DC power, a disposable battery, or a rechargeable battery. When power supply 1208 includes a rechargeable battery, the rechargeable battery can be wired or wirelessly rechargeable. A wired rechargeable battery is charged via a wired line, while a wireless rechargeable battery is charged via a wireless coil. The rechargeable battery can also support fast charging technology.

[0160] In some embodiments, the terminal 1200 further includes one or more sensors 1209 , including but not limited to: an acceleration sensor 1210 , a gyroscope sensor 1211 , a pressure sensor 1212 , an optical sensor 1213 , and a proximity sensor 1214 .

[0161] The accelerometer 1210 can detect the magnitude of acceleration along the three coordinate axes of the coordinate system established by the terminal 1200. For example, the accelerometer 1210 can be used to detect the components of gravity acceleration along the three coordinate axes. The processor 1201 can control the display screen 1205 to display the user interface in a landscape or portrait view based on the gravity acceleration signal collected by the accelerometer 1210. The accelerometer 1210 can also be used to collect game or user motion data.

[0162] The gyroscope sensor 1211 can detect the orientation and rotation angle of the terminal 1200. It can also work with the accelerometer 1210 to collect the user's 3D movements on the terminal 1200. Based on the data collected by the gyroscope sensor 1211, the processor 1201 can implement the following functions: motion sensing (for example, changing the UI based on the user's tilt operation), image stabilization during shooting, game control, and inertial navigation.

[0163] The pressure sensor 1212 can be provided on the side frame of the terminal 1200 and / or below the display screen 1205. When the pressure sensor 1212 is provided on the side frame of the terminal 1200, it can detect the user's gripping signal of the terminal 1200. The processor 1201 performs left and right hand recognition or shortcut operations based on the gripping signal collected by the pressure sensor 1212. When the pressure sensor 1212 is provided below the display screen 1205, the processor 1201 controls the operable controls on the UI interface based on the user's pressure operation on the display screen 1205. Operable controls include at least one of a button control, a scroll bar control, an icon control, and a menu control.

[0164] Optical sensor 1213 is used to detect ambient light intensity. In one embodiment, processor 1201 can control the display brightness of display screen 1205 based on the ambient light intensity detected by optical sensor 1213. Specifically, when the ambient light intensity is high, the display brightness of display screen 1205 is increased; when the ambient light intensity is low, the display brightness of display screen 1205 is decreased. In another embodiment, processor 1201 can also dynamically adjust the shooting parameters of camera assembly 1206 based on the ambient light intensity detected by optical sensor 1213.

[0165] Proximity sensor 1214, also known as a distance sensor, is typically located on the front panel of terminal 1200. Proximity sensor 1214 is used to detect the distance between the user and the front of terminal 1200. In one embodiment, when proximity sensor 1214 detects that the distance between the user and the front of terminal 1200 is gradually decreasing, processor 1201 controls display screen 1205 to switch from the screen-on state to the screen-off state. When proximity sensor 1214 detects that the distance between the user and the front of terminal 1200 is gradually increasing, processor 1201 controls display screen 1205 to switch from the screen-off state to the screen-on state.

[0166] Those skilled in the art will understand that the structure shown in FIG12 does not constitute a limitation on the terminal 1200 , and the terminal 1200 may include more or fewer components than shown in the figure, or combine certain components, or adopt a different component arrangement.

[0167] Figure 13 is a structural diagram of a server provided according to an embodiment of the present application. The server 1300 may have relatively large differences due to different configurations or performances, and may include one or more processors (Central Processing Units, CPU) 1301 and one or more memories 1302, wherein the processor 1301 may be the processor shown in any of Figures 8 and 9, and the embodiment of the present application is not limited to this. At least one computer program is stored in the memory 1302, and the at least one computer program is loaded and executed by the processor 1301 to implement the execution method of the loading instruction provided by the above-mentioned various method embodiments. Of course, the server 1300 may also have components such as a wired or wireless network interface, a keyboard, and an input and output interface for input and output. The server 1300 may also include other components for implementing device functions, which will not be described here.

[0168] The present application also provides a computer-readable storage medium having at least one computer program stored therein, which is loaded and executed by a processor of a computer device to implement the operations performed by the computer device in the method for executing the loading instruction of the above embodiment. For example, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0169] The present application also provides a computer program product, including a computer program stored in a computer-readable storage medium. A processor of a computer device reads the computer program from the computer-readable storage medium and executes the computer program, causing the computer device to execute the method for executing a load instruction provided in the various optional implementations described above.

[0170] Those skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware, or by a program to instruct the relevant hardware, and the program may be stored in a computer-readable storage medium, which may be a read-only memory, a disk, or an optical disk, etc.

[0171] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A method for executing a load instruction, which is executed in a computer device, and the method includes: During the execution of a first load instruction, when there is a first event entry among multiple event entries in an execution information table, query a store instruction queue based on the first event entry. Each event entry in the execution information table is used to indicate a second load instruction and a second store instruction that have conflict events during a historical execution process. The second load instruction indicated by the first event entry is the same as the first load instruction, and the store instruction queue includes multiple second store instructions; If there is a first store instruction in the store instruction queue, when the memory address to be accessed by the first load instruction is different from the memory address to be accessed by the first store instruction, set the status of the first event entry in the execution information table to an invalid status. The first store instruction is the second store instruction indicated by the first event entry, and the first store instruction has not been successfully executed. The invalid status is used to indicate that the conflict event corresponding to the first event entry will not occur during the current execution process of the first load instruction; When the status of the first event entry in the execution information table is in an invalid status, continue to execute the first load instruction according to the current execution progress of the first load instruction.

2. The method according to claim 1, wherein Each event entry in the execution information table includes the instruction address of the second load instruction corresponding to the event entry, and the instruction address is used to indicate the location where the corresponding second load instruction is located; The method further includes: Query the execution information table based on the instruction address of the first load instruction; When there is the instruction address in the execution information table, determine the event entry where the instruction address is located as the first event entry.

3. The method according to claim 2, wherein The instruction address included in each event entry in the execution information table is an address identifier, and each address identifier is obtained by performing a hash operation on the instruction address of the corresponding second load instruction; The querying the execution information table based on the instruction address of the first load instruction includes: Performing a hash operation on the instruction address of the first load instruction to obtain the address identifier of the first load instruction; Querying the execution information table based on the address identifier.

4. The method according to any one of claims 1-3, wherein, The method further includes: Obtaining a current instruction address, where the current instruction address is used to indicate the instruction address of the next instruction of the first load instruction; Subtracting an offset from the current instruction address to obtain the instruction address of the first load instruction, and the offset is used to indicate the difference between the instruction address of the first load instruction and the instruction address of the next instruction.

5. The method according to any one of claims 1 to 4, wherein The step of if there is a first store instruction in the store instruction queue, when the memory address to be accessed by the first load instruction is different from the memory address to be accessed by the first store instruction, setting the status of the first event entry in the execution information table to an invalid status includes: If the first store instruction exists in the store instruction queue, when the memory address to be accessed by the first load instruction is different from the memory address to be accessed by the first store instruction, based on the execution information table, determine the correlation degree between the first load instruction and the first store instruction, where the correlation degree is used to indicate the degree of correlation between the first load instruction and the first store instruction, and the correlation degree is positively correlated with the probability of the conflict event corresponding to the first event entry occurring for the first load instruction; When the correlation degree meets the first condition, set the status of the first event entry in the execution information table to the invalid status.

6. The method according to claim 5, wherein Each event entry in the execution information table includes a correlation degree, and the correlation degree of each event entry is used to indicate the degree of correlation between the corresponding second load instruction and the second store instruction; The step of, if the first store instruction exists in the store instruction queue, when the memory address to be accessed by the first load instruction is different from the memory address to be accessed by the first store instruction, based on the execution information table, determine the correlation degree between the first load instruction and the first store instruction, includes: If the first store instruction exists in the store instruction queue, based on the first event entry in the execution information table, determine the first correlation degree, where the first correlation degree is the correlation degree between the load instruction and the store instruction when the corresponding conflict event occurred in the historical execution process; When the memory address to be accessed by the first load instruction is different from the memory address to be accessed by the first store instruction, reduce the first correlation degree to obtain the second correlation degree, where the second correlation degree is the correlation degree between the first load instruction and the first store instruction in the current execution process.

7. The method according to claim 6, the method further includes: When the memory address to be accessed by the first load instruction is the same as the memory address to be accessed by the first store instruction, enhance the first correlation degree to obtain the third correlation degree, where the third correlation degree is the correlation degree between the first load instruction and the first store instruction in the current execution process.

8. The method according to any one of claims 5-7, wherein, Each event entry in the execution information table includes a utility value, and the utility value of each event entry is used to indicate whether the conflict event corresponding to the event entry will occur; The step of, when the correlation degree meets the first condition, set the status of the first event entry in the execution information table to the invalid status, includes: When the correlation degree meets the first condition, change the utility value of the first event entry in the execution information table from the first value to the second value, where the first value is used to represent the valid status, and the valid status is used to indicate that the conflict event corresponding to the first event entry will occur in the current execution process of the first load instruction, and the second value is used to represent the invalid status.

9. The method according to any one of claims 5-8, the method further includes: When the correlation degree does not meet the first condition, stop the current execution progress of the first load instruction; Store the first load instruction in the load instruction queue and wait for re - execution.

10. The method according to any one of claims 1-9, wherein Multiple event entries in the execution information table are divided into multiple event sets, each event set corresponding to an association degree, and each association degree is used to indicate the correlation degree between the corresponding second load instruction and the second store instruction in the corresponding event set; If there is a first store instruction in the store instruction queue, when the memory address to be accessed by the first load instruction is different from the memory address to be accessed by the first store instruction, setting the status of the first event entry in the execution information table to an invalid status includes: If there is a first store instruction in the store instruction queue, when the memory address to be accessed by the first load instruction is different from the memory address to be accessed by the first store instruction, based on the execution information table, determine the association degree corresponding to the event set where the first event entry is located; When the association degree meets the second condition, set the status of multiple event entries in the event set where the first event entry is located to an invalid status.

11. A processor, the processor comprising: An instruction query unit, an entry processing unit, and an execution unit; The instruction query unit is configured to, during the execution of the first load instruction, when there is a first event entry among multiple event entries in the execution information table, query the store instruction queue based on the first event entry. Each event entry in the execution information table is used to indicate a second load instruction and a second store instruction with a conflict event in the historical execution process. The second load instruction indicated by the first event entry is the same as the first load instruction, and the store instruction queue includes multiple such second store instructions; The entry processing unit is configured to, if there is a first store instruction in the store instruction queue, when the memory address to be accessed by the first load instruction is different from the memory address to be accessed by the first store instruction, set the status of the first event entry in the execution information table to an invalid status. The first store instruction is the second store instruction indicated by the first event entry, and the first store instruction has not been successfully executed. The invalid status is used to indicate that the conflict event corresponding to the first event entry will not occur during the current execution process of the first load instruction; The execution unit is configured to, when the status of the first event entry in the execution information table is an invalid status, continue to execute the first load instruction according to the current execution progress of the first load instruction.

12. The processor according to claim 11, wherein, Each event entry in the execution information table contains the instruction address of the second load instruction corresponding to the event entry, and the instruction address is used to indicate the location where the corresponding second load instruction is located; The processor further includes: an address query unit and an entry determination unit; The address query unit is configured to query the execution information table based on the instruction address of the first load instruction; The entry determination unit is configured to, when the instruction address exists in the execution information table, determine the event entry where the instruction address is located as the first event entry.

13. The processor according to claim 12, wherein, The instruction address included in each event entry in the execution information table is an address identifier, and each address identifier is obtained by performing a hash operation on the instruction address of the corresponding second load instruction; The address query unit is configured to perform a hash operation on the instruction address of the first load instruction to obtain the address identifier of the first load instruction; and query the execution information table based on the address identifier.

14. The processor according to any one of claims 11-13, the processor further comprising: An address acquisition unit and an address processing unit; The address acquisition unit is configured to acquire a current instruction address, and the current instruction address is used to indicate the instruction address of the next instruction of the first load instruction; The address processing unit is configured to subtract an offset from the current instruction address to obtain the instruction address of the first load instruction, and the offset is used to indicate the difference between the instruction address of the first load instruction and the instruction address of the next instruction.

15. The processor according to any one of claims 11-14, wherein, The entry processing unit includes: a determination subunit and a processing subunit; The determination subunit is configured to, if the first store instruction exists in the store instruction queue and the memory address accessed by the first load instruction is different from the memory address accessed by the first store instruction, determine, based on the execution information table, the association degree between the first load instruction and the first store instruction, where the association degree is used to indicate the correlation degree between the first load instruction and the first store instruction, and the association degree is positively correlated with the probability of a conflict event corresponding to the first event entry occurring for the first load instruction; The processing subunit is configured to, when the association degree meets a first condition, set the status of the first event entry in the execution information table to an invalid status.

16. The processor according to claim 15, wherein, Each event entry in the execution information table includes an association degree, and the association degree of each event entry is used to indicate the correlation degree between the corresponding second load instruction and the second store instruction; The determination subunit is configured to, if the first store instruction exists in the store instruction queue, determine a first association degree based on the first event entry in the execution information table, where the first association degree is the association degree between the load instruction and the store instruction when a corresponding conflict event occurred in the historical execution process; When the memory address accessed by the first load instruction is different from the memory address accessed by the first store instruction, reduce the first association degree to obtain a second association degree, where the second association degree is the association degree between the first load instruction and the first store instruction in the current execution process.

17. An execution device for a load instruction, the device includes: A first query module, configured to, during the execution of a first load instruction, query a store instruction queue based on the first event entry when there is a first event entry among multiple event entries in an execution information table, where each event entry in the execution information table is used to indicate a second load instruction and a second store instruction that had a conflict event during the historical execution process, the second load instruction indicated by the first event entry is the same as the first load instruction, and the store instruction queue includes multiple of the second store instructions; A first processing module, configured to, if there is a first storage instruction in the storage instruction queue, when the memory address to be accessed by the first load instruction is different from the memory address to be accessed by the first storage instruction, set the status of the first event entry in the execution information table to an invalid status, where the first storage instruction is the second storage instruction indicated by the first event entry, and the first storage instruction has not been successfully executed, and the invalid status is used to indicate that the conflict event corresponding to the first event entry will not occur during the current execution process of the first load instruction; An execution module, configured to, when the status of the first event entry in the execution information table is an invalid status, continue to execute the first load instruction according to the current execution progress of the first load instruction.

18. A computer device, comprising a processor and a memory, where the memory is configured to store at least one segment of computer program, and the at least one segment of computer program is loaded and executed by the processor to execute the execution method of the load instruction according to any one of claims 1 to 10.

19. A computer-readable storage medium, configured to store at least one segment of computer program, and the at least one segment of computer program is used to execute the execution method of the load instruction according to any one of claims 1 to 10.

20. A computer program product, comprising a computer program, where when the computer program is executed by a processor, it implements the execution method of the load instruction according to any one of claims 1 to 10.

Images