Semiconductor device and method for manufacturing semiconductor device

Abstract

The present invention provides a semiconductor device including a first semiconductor element and a second semiconductor element on a substrate. The first semiconductor element has a first laminate composed from a channel layer and a first gate electrode that covers the periphery of the channel layer in a cross section of the first semiconductor element in a gate width direction thereof. The second semiconductor element has a second gate electrode formed on the substrate via a second gate insulating film, and a channel region formed in the substrate below the second gate electrode.

Description

Semiconductor device and method for manufacturing the same

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002] In a semiconductor device having a GAA-FET (Gate All Around Field Effect Transistor) using a nanosheet structure, an input / output (IO) device is formed near a logic device using a GAA-FET. The I / O device needs to operate at a voltage higher than that of the GAA-FET that constitutes the logic device. For this reason, when forming an I / O device using a GAA-FET, it is necessary to make the gate insulating film thicker than conventional devices.

[0003] However, when manufacturing an input / output device with a GAA-FET structure using a conventional nanosheet-based GAA-FET manufacturing method, it is difficult to form a gate insulating film thick enough to withstand high voltages. For example, if a thick gate insulating film is formed on a GAA-FET using nanosheets in the input / output section, the insulating film will fill the spaces between the stacked Si layers (Si nanosheet layers). In this case, it is difficult to form a gate electrode between the Si layers, significantly reducing the performance of the semiconductor device.

[0004] To address these issues, a configuration has been proposed in which, in an input / output device with a GAA-FET structure using a nanosheet structure, all Si nanosheet layers except the bottom layer are removed, and only the bottom Si nanosheet layer is used as the input / output device (see, for example, Patent Document 1). In a semiconductor device with this configuration, the Si layer and SiGe layer are removed except for the bottom Si nanosheet layer, leaving a large space around the bottom Si nanosheet layer. This makes it possible to form a thick gate insulating film in the input / output device.

[0005] U.S. Pat. No. 10,229,971

[0006] However, in the semiconductor device having the configuration described in Patent Document 1, etching must be stopped reliably within the SiGe layer having a thickness of several tens of nanometers. Such precise control of etching is practically very difficult. Therefore, it is difficult to stably realize the semiconductor device having the configuration described in Patent Document 1.

[0007] In order to solve the above-mentioned problems, the present invention provides a semiconductor device having a thick gate insulating film that can be more stably produced, and a method for manufacturing the semiconductor device.

[0008] The semiconductor device of the present invention includes a first semiconductor element and a second semiconductor element on a substrate. The first semiconductor element has a first stacked body including a channel layer and a first gate electrode covering the periphery of the channel layer in a cross section in the gate width direction of the first semiconductor element, and a first gate insulating film interposed between the channel layer and the first gate electrode. The second semiconductor element has a second gate electrode formed on the substrate via a second gate insulating film, and a channel region formed in the substrate below the second gate electrode.

[0009] A semiconductor device manufacturing method of the present invention manufactures a semiconductor device including a first semiconductor element and a second semiconductor element on a substrate. The manufacturing method includes a step of forming a channel region by implanting impurity ions into the substrate in a formation region for the second semiconductor element. The manufacturing method also includes a step of stacking a Si layer and a SiGe layer in the formation region for the first semiconductor element and the formation region for the second semiconductor element to form a Si / SiGe stack. The manufacturing method also includes a step of removing the SiGe layer and forming a first gate insulating film in the formation region for the first semiconductor element. The manufacturing method further includes a step of removing the SiGe layer, removing the Si layer, and forming a second gate insulating film thicker than the first gate insulating film in the formation region for the second semiconductor element. The manufacturing method also includes a step of forming a metal layer and forming a first gate electrode and a second gate electrode in the formation region for the first semiconductor element and the formation region for the second semiconductor element.

[0010] According to the present invention, it is possible to provide a semiconductor device that can be manufactured through simple steps and that allows the formation of a thick gate insulating film, and a method for manufacturing the semiconductor device.

[0011] 1 is a diagram (plan view) showing a schematic configuration of a semiconductor device of a first embodiment. FIG. 1 is a cross-sectional view (cross-sectional view in the gate length direction) of a first semiconductor element shown in FIG. 1 . FIG. 2 is a cross-sectional view (cross-sectional view in the gate width direction) of the first semiconductor element shown in FIG. 1 . FIG. 3 is a cross-sectional view (cross-sectional view in the gate length direction) of a second semiconductor element shown in FIG. 1 . FIG. 4 is a cross-sectional view (cross-sectional view in the gate width direction) of a second semiconductor element shown in FIG. 1 . FIG. 5 is a cross-sectional view (cross-sectional view in the gate length direction) of a second semiconductor element shown in FIG. 1 . FIG. 6 is a cross-sectional view (cross-sectional view in the gate width direction) of a second semiconductor element shown in FIG. 1 . FIG. 7 is a diagram explaining a manufacturing process of a semiconductor device of a first embodiment. FIG. 8 is a diagram explaining a manufacturing process of a semiconductor device of a first embodiment. FIG. 9 is a diagram explaining a manufacturing process of a semiconductor device of a first embodiment. FIG. 10 is a diagram explaining a manufacturing process of a semiconductor device of a first embodiment. FIG. 11 is a diagram explaining a manufacturing process of a semiconductor device of a first embodiment. FIG. 12 is a diagram explaining a manufacturing process of a semiconductor device of a first embodiment. 1 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment. FIG. 2 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment. FIG. 3 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment. FIG. 4 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment. FIG. 5 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment. FIG. 6 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment. FIG. 7 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment. FIG. 8 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment. FIG. 9 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment. FIG. 10 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment. FIG. 11 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment. FIG. 12 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment. FIG. 13 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment. FIG. 14 is a diagram for explaining a manufacturing process of the semiconductor device of the first embodiment. FIG. 15 is a cross-sectional view (cross-sectional view in the gate length direction) of a first semiconductor element of a semiconductor device of a second embodiment.1 is a cross-sectional view (cross-sectional view in the gate width direction) of a semiconductor device according to a second embodiment; FIG. 2 is a cross-sectional view (cross-sectional view in the gate length direction) of a second semiconductor element of the semiconductor device according to the second embodiment; FIG. 3 is a cross-sectional view (cross-sectional view in the gate width direction) of the semiconductor device according to the second embodiment; FIG. 4 is a cross-sectional view (cross-sectional view in the gate width direction) of the semiconductor device according to the second embodiment; FIG. 5 is a cross-sectional view (cross-sectional view in the gate width direction) of the semiconductor device according to the third embodiment; FIG. 6 is a cross-sectional view (cross-sectional view in the gate length direction) of a first semiconductor element of a semiconductor device according to a third embodiment; FIG. 7 is a cross-sectional view (cross-sectional view in the gate width direction) of the semiconductor device according to the third embodiment; FIG. 8 is a cross-sectional view (cross-sectional view in the gate length direction) of a second semiconductor element of the semiconductor device according to the third embodiment; FIG. 9 is a cross-sectional view (cross-sectional view in the gate width direction) of the semiconductor device according to the third embodiment; 10 is a diagram for explaining a manufacturing process of the semiconductor device of the third embodiment. FIG. 11 is a diagram for explaining a manufacturing process of the semiconductor device of the third embodiment. FIG. 12 is a diagram for explaining a manufacturing process of the semiconductor device of the third embodiment. FIG. 13 is a diagram for explaining a manufacturing process of the semiconductor device of the third embodiment. FIG. 14 is a diagram for explaining a manufacturing process of the semiconductor device of the third embodiment. FIG. 15 is a diagram for explaining a manufacturing process of the semiconductor device of the third embodiment. FIG. 16 is a diagram for explaining a manufacturing process of the semiconductor device of the third embodiment. FIG. 17 is a diagram for explaining a manufacturing process of the semiconductor device of the third embodiment. FIG. 18 is a diagram for explaining a manufacturing process of the semiconductor device of the third embodiment. FIG. 19 ...

[0012] Hereinafter, examples of embodiments for carrying out the present invention will be described, but the present invention is not limited to the following examples. The description will be given in the following order: 1. Semiconductor device of first embodiment 2. Method for manufacturing the semiconductor device of first embodiment 3. Semiconductor device of second embodiment 4. Method for manufacturing the semiconductor device of second embodiment 5. Semiconductor device of third embodiment 6. Method for manufacturing the semiconductor device of third embodiment 7. Semiconductor device of fourth embodiment

[0013] 1. Semiconductor Device of First Embodiment Below, specific embodiments of the semiconductor device of the present invention will be described. FIGS. 1-5 show schematic configuration diagrams of the semiconductor device of the first embodiment. [Configuration of the Semiconductor Device] FIG. 1 is a plan view (top view) of the semiconductor device. FIG. 2 is a cross-sectional view (cross-sectional view in the gate length direction) of the semiconductor device shown in FIG. 1 taken along line X1. FIG. 3 is a cross-sectional view (cross-sectional view in the gate width direction) of the semiconductor device shown in FIG. 1 taken along line Y1. FIG. 4 is a cross-sectional view (cross-sectional view in the gate length direction) of the semiconductor device shown in FIG. 1 taken along line X2. FIG. 5 is a cross-sectional view (cross-sectional view in the gate width direction) of the semiconductor device shown in FIG. 1 taken along line Y2.

[0014] The semiconductor device 10 shown in FIG. 1 includes a first semiconductor element 100 and a second semiconductor element 200 on a substrate 11. As shown in FIGS. 2 and 3, the first semiconductor element 100 is a Gate All Around (GAA)-FET having a first stack formed by stacking semiconductor nanosheet layers (first Si layers) 101, 102, and 103 and a gate electrode 112. As shown in FIGS. 4 and 5, the second semiconductor element 200 is a planar MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) having a gate electrode 212 formed on the substrate 11 via a gate insulating film 210 (second gate insulating film). The semiconductor nanosheet layer may be made of Si or other semiconductor materials such as SiGe, if necessary.

[0015] 1, the first semiconductor element 100 includes a gate electrode 112 (first gate electrode) and a source / drain region 108 (first source / drain region) formed on a substrate 11. The second semiconductor element 200 includes a gate electrode 212 (second gate electrode) and a source / drain region 208 (second source / drain region) formed on the substrate 11.

[0016] 1 , the second semiconductor element 200 has a larger gate length than the first semiconductor element 100. Because the second semiconductor element 200 is an input / output device, the voltage applied to the gate electrode 212 is higher than the voltage applied to the gate electrode 112 of the first semiconductor element 100. For this reason, it is preferable that the second semiconductor element 200 has a larger gate length than the first semiconductor element 100 in order to suppress a through current between the source / drain regions 208, known as punch-through. On the other hand, it is preferable that the first semiconductor element 100, which will be a logic device, has a shorter gate length in order to improve switching speed.

[0017] 2 and 4 , in cross-sectional views of the first semiconductor element 100 and the second semiconductor element 200 in the gate length direction, the first semiconductor element 100 and the second semiconductor element 200 are entirely sealed by an insulating layer 41 on a substrate 11. In addition, an STI (Shallow Trench Isolation) 42 is formed on the surface of the substrate 11 as an element isolation region. The STI 42 is composed of the insulating layer 41 embedded in the substrate 11. The STI 42 is formed between the first semiconductor element 100 and the second semiconductor element 200. The STI 42 is formed in a region other than the region where the first semiconductor element 100 and the second semiconductor element 200 are formed.

[0018] 2 , the first semiconductor element 100 has a gate electrode 112 in the lowermost layer on a substrate 11. The first semiconductor element 100 has a first stacked body having a stacked structure including the gate electrode 112, that is, [gate electrode 112 / Si layer 101 / gate electrode 112 / Si layer 102 / gate electrode 112 / Si layer 103].

[0019] 2 , the first semiconductor element 100 has a gate electrode 112 and sidewalls 106 above the uppermost Si layer 103. The gate electrode 112 is formed in the center of the Si layer 103, and the sidewalls 106 are formed around the gate electrode 112. The gate electrode 112 includes a metal layer 104. A high-dielectric-constant material layer (first high-dielectric-constant layer) 105 is provided on the bottom and side surfaces of the gate electrode 112, i.e., on the contact surfaces between the Si layer 103 and the sidewalls 106. The metal layer 104 is filled in the high-dielectric-constant material layer 105. In the first semiconductor element 100, the high-dielectric-constant material layer 105 may be formed in combination with a low-dielectric-constant material layer (not shown) that is thinner than the high-dielectric-constant material layer 105 and has a lower dielectric constant than the high-dielectric-constant material layer 105. In the first semiconductor element 100, the stacked film of the high-dielectric-constant material layer 105 and the low-dielectric-constant material layer functions as a gate insulating film (first gate insulating film).

[0020] The first semiconductor element 100 includes independent source / drain regions 108 on both side surfaces of a first stack consisting of Si layers 101, 102, and 103 and a gate electrode 112. The Si layers 101, 102, and 103 are connected to the source / drain regions 108 on both side surfaces. In addition, an inner spacer 107 (first inner spacer) made of an insulating layer (first insulating layer) is formed between the gate electrode 112, which is disposed between the substrate 11 and the Si layers 101, 102, and 103, and the source / drain region 108.

[0021] 2, the gate electrode 112 formed between the substrate 11 and the Si layers 101, 102, and 103 is formed of the metal layer 104. The contact surfaces of the gate electrode 112 with the Si layers 101, 102, and 103 and the inner spacer 107 are covered with the high-dielectric-constant material layer 105 and a low-dielectric-constant material layer (not shown). The metal layer 104 is filled inside the high-dielectric-constant material layer 105.

[0022] 3 , the first semiconductor element 100 has a high-dielectric-constant material layer 105 formed on the substrate 11 and the STI 42. The first semiconductor element 100 also has Si layers 101, 102, and 103 stacked on the high-dielectric-constant material layer 105 via a metal layer 104 that constitutes a gate electrode 112. The high-dielectric-constant material layer 105 and a low-dielectric-constant material layer (not shown) are formed between the metal layer 104 and the Si layers 101, 102, and 103. Therefore, in the cross-sectional view in the gate width direction, the Si layers 101, 102, and 103 are surrounded by the high-dielectric-constant material layer 105 and a low-dielectric-constant material layer (not shown), respectively.

[0023] 2. As can be seen from the cross-sectional view in the gate width direction shown in FIG. 3, the metal layer 104 is formed continuously on all of the gate electrodes 112 shown in FIG. 2. Therefore, in the cross-sectional view in the gate width direction shown in FIG. 3, the peripheries of the Si layers 101, 102, and 103 are covered by the gate electrodes 112. That is, in the first semiconductor element 100, the Si layers 101, 102, and 103 constituting the first stacked body are channel layers in which a channel is formed. In the first semiconductor element 100, the entire cross-section in the gate width direction of the Si layers 101, 102, and 103 that form the channel portion is surrounded by the gate electrodes 112, as shown in FIG.

[0024] (Second Semiconductor Element) In the cross-sectional view in the gate length direction shown in FIG. 4 , the second semiconductor element 200 has a gate insulating film 210 and a high-dielectric-constant material layer 205 on a substrate 11, and a gate electrode 212 therebetween. The substrate 11 has a trench 211 in the region where the gate insulating film 210, the high-dielectric-constant material layer 205, and the gate electrode 212 are formed, which is dug deeper than the surrounding region. Therefore, the substrate 11 has a step between the region where the gate insulating film 210, the high-dielectric-constant material layer 205, and the gate electrode 212 are formed and the surrounding region. In the trench 211 of the substrate 11, the gate insulating film 210, the high-dielectric-constant material layer 205, and the gate electrode 212 are formed in a low-position region (low-position region) formed lower by the step. Note that the trench forming this step is sufficiently shallower than the STI 42.

[0025] The second semiconductor element 200 also has Si layers (second Si layers) 201, 202, and 203 and an inner spacer 207 (second inner spacer) made of an insulating layer (second insulating layer) on the side surfaces of the gate insulating film 210, the high-dielectric-constant material layer 205, and the gate electrode 212. Therefore, the second semiconductor element 200 has a second stacked body made of a stacked structure of [inner spacer 207 / Si layer 201 / inner spacer 207 / Si layer 202 / inner spacer 207 / Si layer 203] on the side surface of the gate insulating film 210 on the substrate 11. The inner spacer 207 and the Si layers 201, 202, and 203 are arranged on a high-position region (high-position region) formed higher than the groove 211 by a step, around a low-position region where the gate electrode 212 and the like are arranged on the surface of the substrate 11.

[0026] Furthermore, the thickness of the Si layers 201, 202, and 203 in the gate length direction is smaller than that of the inner spacer 207. Therefore, the gate insulating film 210 and the Si layers 201, 202, and 203 are disposed between the stacked layers of the inner spacer 207. In the gate length direction, the gate insulating film 210 is disposed toward the center of the element, and the Si layers 201, 202, and 203 are disposed outside the gate insulating film 210.

[0027] 4 , the second semiconductor element 200 has sidewalls 206 above the uppermost Si layer 203. The sidewalls 206 are formed on the outer surfaces of the gate electrode 212, the high-dielectric-constant material layer 205, and the gate insulating film 210. The side surfaces of the sidewalls 206 are in contact with the gate insulating film 210, and the bottom surfaces are in contact with the Si layer 203 and the gate insulating film 210.

[0028] The second semiconductor element 200 includes source / drain regions 208 on the side surfaces of a stack consisting of Si layers 201, 202, and 203 and an inner spacer 207. The inner spacer 207 and the Si layers 201, 202, and 203 are in contact with the source / drain regions 208. The source / drain regions 208 are also formed in contact with the surface of the substrate 11. The source / drain regions 208 are disposed on the substrate 11 around the region where the gate electrode 212, the high-dielectric-constant material layer 205, and the gate insulating film 210 are in contact. Therefore, the source / drain regions 208 are disposed in elevated regions (high-position regions) formed by steps on the surface of the substrate 11. Contacts 209 for connection to external wiring are connected to the source / drain regions 208. The contacts 209 are formed of a metal material embedded in through holes that penetrate from the top of the insulating layer 41 of the second semiconductor element 200 to the source / drain regions 208.

[0029] The gate electrode 212 is composed of a metal layer 204. A high-dielectric-constant material layer 205 (second high-dielectric-constant material layer) is provided on the bottom and side surfaces of the gate electrode 212, i.e., on the contact surface with the gate insulating film 210. The metal layer 204 is filled in the high-dielectric-constant material layer 205.

[0030] The substrate 11 is a region between the pair of source / drain regions 208, and has an impurity diffusion region (not shown) below the gate insulating film 210 and the gate electrode 212. The impurity diffusion region is formed to a predetermined depth on the surface side of the substrate 11. For example, if the second semiconductor element 200 is a PMOS, the substrate 11 has a diffusion region containing an n-type impurity such as phosphorus. Also, if the second semiconductor element 200 is an NMOS, the substrate 11 has a diffusion region containing a p-type impurity such as boron. In the second semiconductor element 200, the impurity diffusion region of the substrate 11 becomes a region (channel region) where a channel is formed when the second semiconductor element 200 is operating.

[0031] The gate insulating film 210 is formed between the gate electrode 212 and the substrate 11, between the gate electrode 212 and the Si layers 201, 202, and 203 and the inner spacer 207, and between the gate electrode 212 and the sidewall 216. The gate insulating film 210 has a sufficient thickness to withstand the high voltage applied to the second semiconductor element 200 which serves as an input / output device. For this reason, the gate insulating film 210 is formed to be sufficiently thicker than the high-dielectric-constant material layer 205.

[0032] 5 , the second semiconductor element 200 has a gate insulating film 210 formed on the substrate 11 and the STI 42, and a high-dielectric-constant material layer 205. The second semiconductor element 200 has a metal layer 204 that forms a gate electrode 212 on the high-dielectric-constant material layer 205.

[0033] The second semiconductor element 200 has a gate electrode 212 formed on a substrate 11 with a gate insulating film 210 interposed therebetween. Furthermore, the second semiconductor element 200 has a pair of source / drain regions 208 on the substrate 11, positioned opposite each other with the gate electrode 212 interposed therebetween and sandwiching a channel region. Therefore, when a gate voltage is applied to the gate electrode 212, a channel is formed in the substrate 11 of the second semiconductor element 200. The source / drain regions 208 are formed so as to be in direct contact with the channel region of the substrate 11. In the second semiconductor element 200, the Si layers 201, 202, and 203 are in contact with the source / drain regions 208 at their side edges, but are separated by the gate insulating film 210 and the gate electrode 212 at the center of the element. Therefore, the Si layers 201, 202, and 203 are not formed continuously between the pair of source / drain regions 208. For this reason, in the second semiconductor element 200, no channel is formed in the Si layers 201, 202, and 203. That is, in the first semiconductor element 100, a channel is formed in the Si layers 101, 102, and 103 that constitute the first stack, whereas in the second semiconductor element 200, a channel is formed in the substrate 11.

[0034] Furthermore, in the second semiconductor element 200, the central portions of the Si layers 201, 202, and 203 constituting the stack are removed compared to the first semiconductor element 100. In the central portion of the element, the gate insulating film 210, the high-dielectric-constant material layer 205, and the gate electrode 212 are continuously formed from the top of the element to the surface of the substrate 11 without any Si layer or the like inside. In this manner, the second semiconductor element 200 has a configuration in which the Si layers 201, 202, and 203 are removed in the central portion of the element, thereby providing a large space for forming the gate insulating film 210 and the gate electrode 212. As a result, the second semiconductor element 200 has an area secured for forming a gate insulating film of sufficient thickness to withstand the high voltage applied to the input / output device.

[0035] (Layer Configuration of Second Semiconductor Element) The Si layers 201 , 202 , and 203 of the second semiconductor element 200 are formed at approximately the same height as the Si layers 101 , 102 , and 103 of the first semiconductor element 100 with respect to the upper surface of the substrate 11 .

[0036] In the second semiconductor element 200, the inner spacer 207 is divided into two or more parts at least in the stacking direction by the Si layers 201 and 202. Therefore, the inner spacer 207 is formed so as to be divided into two or more parts in the stacking direction. The Si layers 201 and 202 are interposed between the stacked parts of the inner spacer 207.

[0037] The Si layers 201, 202, and 203 are formed so that their thickness in the surface direction of the substrate 11 (gate length direction) is smaller than that of the inner spacer 207. Therefore, in the cross-sectional view in the gate width direction shown in FIG. 3 , the Si layers 201, 202, and 203 and the inner spacer 207 have steps on their wall surfaces toward the center of the second semiconductor element 200. These steps form recesses on the inner side surfaces of the Si layers 201, 202, and 203. An insulating film 210 is embedded in the recesses on the side surfaces of the Si layers 201, 202, and 203. As a result, the Si layers 201, 202, and 203 and the insulating film 210 are disposed between the stacked inner spacers 207. The Si layers 201, 202, and 203 are in contact with the insulating film 210, the inner spacer 207, and the source / drain regions 208.

[0038] The Si layers 201, 202, and 203 may have the same thickness as the inner spacer 207, as long as they are equal to or thinner than the inner spacer 207. If the Si layers 201, 202, and 203 and the inner spacer 207 have the same thickness, the recesses described above are not formed. Therefore, the gate insulating film 210 embedded in the recesses is also not present. Only the Si layers 201 and 202 are disposed between the stacked inner spacers 207.

[0039] Furthermore, the source / drain regions 208 are not exposed because the Si layers 201, 202, and 203 remain between the stacked layers of the inner spacers 207. Therefore, in the manufacturing process of the semiconductor device described below, damage to the source / drain regions 208 can be suppressed in the steps of removing the Si layers 201, 202, and 203, removing the SiGe layer, forming the gate electrode, and the like.

[0040] According to the above-described configuration, the second semiconductor element 200 has an area for forming a gate insulating film of sufficient thickness to withstand the high voltage applied to the second semiconductor element 200, which serves as an input / output device. With this structure, the second semiconductor element 200 has a shape similar to that of a GAA-FET in a portion between the gate insulating film 210 and the source / drain regions 208, and yet can be operated at a voltage higher than that of the first semiconductor element 100 that constitutes the logic device. This makes it possible to suppress a decrease in the reliability of the second semiconductor element 200.

[0041] Furthermore, in the first semiconductor element 100 and the second semiconductor element 200, the Si layers 101, 102, 103 and the Si layers 201, 202, 203 are formed to the same height. Therefore, the first semiconductor element 100 and the second semiconductor element 200 can share the same process for forming the Si layers 101, 102, 103 and the Si layers 201, 202, 203. As a result, variations in height between the Si layers 101, 102, 103 and the Si layers 201, 202, 203 can be suppressed. Furthermore, by sharing the same process for forming the Si layers 101, 102, 103 and the Si layers 201, 202, 203, it is possible to suppress the complexity of the manufacturing process and the increase in manufacturing costs.

[0042] 2. Manufacturing Method of Semiconductor Device Next, a manufacturing method of the semiconductor device 10 shown in FIGS. 1-5 will be described. Figures 6 to 33 show manufacturing process diagrams of the semiconductor device 10. In the manufacturing process of the semiconductor device 10 shown in Figures 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, and 32, the left side of the figure shows a cross-sectional view (cross-sectional view in the gate length direction) of the first semiconductor element 100 of the semiconductor device 10 shown in Figure 1 along line X1, and the right side of the figure shows a cross-sectional view (cross-sectional view in the gate length direction) of the second semiconductor element 200 along line X2. In addition, in the manufacturing process of the semiconductor device 10 shown in Figures 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, and 33, a cross-sectional view taken along line Y1 (cross-sectional view in the gate width direction) of the first semiconductor element 100 of the semiconductor device 10 shown in Figure 1 is shown on the left side of the drawing, and a cross-sectional view taken along line Y2 (cross-sectional view in the gate width direction) of the second semiconductor element 200 is shown on the right side of the drawing.

[0043] First, as shown in FIGS. 6 and 7 , impurities for forming a PTS (Punch Through Stopper) are implanted into the substrate 11 in the region where the first semiconductor element 100 will be formed. This forms a PTS layer in the substrate 11, which has a gentle concentration gradient from the surface toward the interior. When forming the PTS layer as a p-type, boron is implanted as the impurity, and when forming the PTS layer as an n-type, phosphorus is implanted as the impurity. At this time, a resist layer 12 is patterned over the entire surface of the substrate 11, except for the region where the PTS will be formed. The patterning of the resist layer 12 is performed, for example, by forming the resist layer 12 over the entire surface, followed by exposure and development using a photomask on which a predetermined pattern has been formed.

[0044] Next, as shown in FIGS. 8 and 9 , impurities for channel formation are implanted into the substrate 11 in the region where the second semiconductor element 200 will be formed. This forms an impurity diffusion region in the substrate 11 that will become the channel region. The channel region is formed continuously at least in the range from the bottom of the gate electrode 212 to the bottom of the region where the source / drain regions 208 will be formed. Furthermore, impurity ions are implanted into the substrate 11 in the region where the second semiconductor element 200 will be formed separately for NMOS and PMOS. When the second semiconductor element 200 is formed as an NMOS, boron is implanted as the impurity, and when the second semiconductor element 200 is formed as a PMOS, phosphorus is implanted as the impurity. At this time, a resist layer 13 is patterned and formed on the entire surface of the substrate 11 except for the region where the impurities are implanted. The patterning of the resist layer 13 is performed, for example, by forming the resist layer 13 on the entire surface, and then performing exposure and development processes using a photomask on which a predetermined pattern is formed. Here, the amount of impurity injected for forming the PTS is different from the amount of impurity injected for forming the channel, and the amount of impurity injected for forming the PTS is larger than the amount of impurity injected for forming the channel.

[0045] 10 and 11 , a Si / SiGe stacked body, a dummy gate insulating film 22, a dummy gate 20, a hard mask 21, sidewalls 106, 206, inner spacers 107, 207, and source / drain regions 108, 208 are formed on the substrate 11 by the following processes. First, a SiGe layer 14, Si layers 17, 101, a SiGe layer 15, Si layers 18, 102, a SiGe layer 16, and Si layers 19, 103 are stacked on the substrate 11. The SiGe layers 14, 15, 16, and the Si layers 17, 18, 19, 101, 102, 103 are formed by epitaxial growth of Si and SiGe. The Si layers 17 and 101, the Si layers 18 and 102, and the Si layers 19 and 103 are each formed by epitaxial growth as the same layer in the same process. Then, by separating each element in a later process, the Si layers 101, 102, and 103 are formed on the first semiconductor element 100 side, and the Si layers 17, 18, and 19 are formed on the second semiconductor element 200 side. The SiGe layers 14, 15, and 16 are formed to a thickness of, for example, about 10-15 nm. The Si layers 17, 18, 19, 101, 102, and 103 are formed to a thickness of, for example, about 5 nm.

[0046] Next, an STI is formed on the substrate 11, and a dummy gate insulating film 22, a dummy gate 20, a hard mask 21, and sidewalls 106 and 206 are formed. Then, the stack of the SiGe layers 14, 15, and 16 and the Si layers 17, 18, 19, 101, 102, and 103 is etched using reactive ion etching (RIE) or the like. As a result, as shown in FIGS. 10 and 11 , independent Si / SiGe stacks (pillars) are formed in the first semiconductor element 100 and the second semiconductor element 200. Here, a stack of the SiGe layer 14, the Si layer 101, the SiGe layer 15, the Si layer 102, the SiGe layer 16, and the Si layer 103 is formed in the first semiconductor element 100. In addition, a stack of a SiGe layer 14 , a Si layer 17 , a SiGe layer 15 , a Si layer 18 , a SiGe layer 16 , and a Si layer 19 is formed in the second semiconductor element 200 .

[0047] Next, in the formation region of the first semiconductor element 100 and the formation region of the second semiconductor element 200, the side surfaces of the SiGe layers 14, 15, and 16 exposed in the gate length direction of the Si / SiGe stack are selectively etched to partially remove the side surfaces of the SiGe layers 14, 15, and 16. Then, recesses are formed in the side surfaces of the SiGe layers 14, 15, and 16 relative to the side surfaces of the Si layers 17, 18, and 19 and the Si layers 101, 102, and 103. Note that in the selective etching process for the side surfaces of the SiGe layers 14, 15, and 16, the side surfaces of the SiGe layers 14, 15, and 16 in the gate width direction are covered by the dummy gate 20. Therefore, the side surfaces of the SiGe layers 14, 15, and 16 in the gate width direction are not etched. The SiGe layers 14, 15, and 16 are etched using isotropic etching, such as atomic layer etching (ALE), quasi-ALE, or selective vapor-phase etching. These techniques have selectivity for Si relative to SiGe and the reverse selectivity for SiGe relative to Si during the etching process. Therefore, these techniques can selectively etch the side surfaces of the SiGe layers 14, 15, and 16, forming recesses on the side surfaces of the Si / SiGe stack. The depth of the recesses is adjusted taking into account the thicknesses of the inner spacers 107 and 207 of the first semiconductor element 100 and the second semiconductor element 200. Next, an insulating layer is formed using SiN or the like to selectively cover the dummy gate insulating film 22, the dummy gate 20, the hard mask 21, and the sidewalls 106 and 206, and anisotropic etching, such as RIE, is performed. This removes the insulating layer exposed from the side surfaces of the Si / SiGe stack, leaving inner spacers 107 and 207 made of the insulating layer in the recesses on the side surfaces of the SiGe layers 14, 15, and 16. Through the above steps, the inner spacers 107 and 207 are formed on the Si / SiGe stack.

[0048] Then, an STI 42 is formed in the substrate 11 between the region where the first semiconductor element 100 is to be formed and the region where the second semiconductor element 200 is to be formed. Then, an insulating layer 41 is formed to cover the entire substrate 11, and then the insulating layer 41 is polished and planarized by CMP or the like to expose and planarize the upper surface of the hard mask 21. Furthermore, source / drain regions 108, 208 are formed on the side surfaces of the Si / SiGe stack. Each of these steps is performed by a conventionally known method.

[0049] Next, a resist layer 23 is formed over the entire surface of the substrate 11, and then, as shown in FIGS. 12 and 13, the resist layer 23 is patterned to open only the region where the second semiconductor element 200 will be formed. Then, as shown in FIGS. 14 and 15, the hard mask 21 of the second semiconductor element 200 and the dummy gate 20 are removed. The hard mask 21 is formed of, for example, SiN. Therefore, the hard mask 21 is selectively etched using a chemical such as hydrogen fluoride, which can selectively wet etch SiN relative to SiO and Si. The dummy gate 20 is formed of, for example, polysilicon (p-Si) or amorphous silicon (α-Si). Therefore, a method capable of selectively etching polysilicon (p-Si) or amorphous silicon (α-Si), such as plasma etching, is used.

[0050] 16 and 17 , the dummy gate insulating film 22 of the second semiconductor element 200 is removed. Furthermore, the SiGe layers 14, 15, and 16 of the second semiconductor element 200 are selectively etched, thereby exposing the Si layers 17, 18, and 19 of the second semiconductor element 200. The selective etching of the SiGe layers 14, 15, and 16 is performed, for example, by dry etching using a mixed gas containing hydrogen fluoride and oxygen, or by wet etching using a mixed solution of hydrogen fluoride and hydrogen peroxide.

[0051] Next, the Si layers 17, 18, and 19 of the second semiconductor element 200 are selectively removed. In this step, an etching process is performed using a chemical dry etching (CDE) device or the like that can selectively remove the Si layers 17, 18, and 19. Alternatively, wet etching may be performed using an etching solution that can selectively remove the Si layers 17, 18, and 19. When wet etching is performed, for example, the following (1) and (2) can be applied. (1) Ammonia, H ２ O ２ , and APM mixed with pure water (4:1:400, 4:1:20, 4:1:100, etc.) 40C. (2) 5% NH ４ TMAH such as OH60C, 2.38% TMAH 60°C, or 5% TMAH60C is used. By this process, as shown in Figures 18 and 19, parts of the Si layers 17, 18, and 19 remain between the layers of the inner spacer 207 and in contact with the source / drain region 208, becoming Si layers 201, 202, and 203. In this process, in addition to removing the Si layers 17, 18, and 19, a groove 211 is formed by digging into the surface of the substrate 11, and a step is formed between the opening and the lower parts of the inner spacer 207 and the source / drain region 208.

[0052] In this process, the remaining amount of the Si layers 201, 202, and 203 between the stacked layers of the inner spacer 207 is adjusted by adjusting the etching conditions and time for the Si layers 17, 18, and 19. When all of the Si layers 17, 18, and 19 are removed, the source / drain regions 208 are exposed inside the device. In this case, the source / drain regions 208 are likely to be damaged in subsequent processes, resulting in a deterioration in the characteristics of the semiconductor device. Furthermore, if subsequent manufacturing processes are performed with the source / drain regions 208 exposed, the source / drain regions 208 are likely to be damaged and the characteristics of the semiconductor device are likely to be deteriorated. For this reason, in the selective removal process of the Si layers 17, 18, and 19, it is preferable to leave at least a portion of the Si layers 201, 202, and 203 between the stacked layers of the inner spacer 207 so that the source / drain regions 208 are not exposed. Furthermore, the etching conditions and time for the Si layers 17, 18, and 19 are adjusted to adjust the recession depth of the surface of the substrate 11. In this embodiment, the etching is performed under conditions that reduce the amount of etching on the surface of the substrate 11. For example, when a CDE apparatus is used, CDE processing conditions are applied that provide higher selectivity for the Si layers 17, 18, and 19 than for the substrate 11. In addition, in the case of wet etching, an etching solution is selected, etching conditions are set, and so on. As a result, adjustments are made so that the amount of etching on the Si layers 17, 18, and 19 is relatively large and the amount of recession on the surface of the substrate 11 is reduced.

[0053] Next, after the resist layer 23 is peeled off, an insulating layer 24 is formed on the entire surface of the substrate 11, as shown in Figures 20 and 21. The insulating layer 24 is made of, for example, SiO ２ The insulating layer 24 is formed by, for example, CVD or the like. The insulating layer 24 becomes the gate insulating film 210 in the second semiconductor element 200 shown in FIGS. 4 and 5. For this reason, the insulating layer 24 is formed to a sufficient thickness to withstand the high voltage applied to the second semiconductor element 200.

[0054] Next, after the entire surface of the substrate 11 is filled with a resist layer 25, the resist layer 25 is patterned to open only the region where the first semiconductor element 100 is to be formed, as shown in FIGS. 22 and 23 . The insulating layer 24 of the first semiconductor element 100 is then selectively removed. In this process, the dummy gate 20, hard mask 21, and dummy gate insulating film 22 are also removed. This exposes the top surface of the Si layer 103 of the first semiconductor element 100 and the inner walls of the sidewalls 106. Furthermore, the SiGe layers 14, 15, and 16 of the first semiconductor element 100 are selectively etched. This exposes the spaces between the Si layers 101, 102, and 103 of the first semiconductor element 100, as shown in FIGS. 24 and 25 . The SiGe layers 14, 15, and 16 are selectively etched by dry etching using a mixed gas containing hydrogen fluoride and oxygen, or by wet etching using a mixed solution of hydrogen fluoride and hydrogen peroxide, for example.

[0055] 26 and 27, the resist layer 25 is removed to expose the second semiconductor element 200. Then, as shown in FIGS. 28 and 29, a high-dielectric-constant material layer 26 is formed on the entire surface of the substrate 11. The high-dielectric-constant material layer 26 is made of, for example, hafnium dioxide (HfO ２ The high dielectric constant material layer 26 is formed of, for example, hafnium oxynitride (HfON), etc. The high dielectric constant material layer 26 is formed by, for example, ALD (Atomic Layer Deposition) or the like.

[0056] Next, as shown in FIGS. 30 and 31 , a metal layer 27 is formed on the high-dielectric-constant material layer 26. The metal layer 27 is formed of, for example, tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), niobium (Nb), tungsten (W), or the like. The metal layer 27 is formed, for example, by CVD. Through this process, in the first semiconductor element 100, gate electrodes 112 (see FIG. 2 ) made of the metal layer 104 are formed between the substrate 11 and each of the Si layers 101, 102, and 103, with the high-dielectric-constant material layer 105 interposed therebetween. In the second semiconductor element 200, the metal layer 204 is embedded on the substrate 11 with the high-dielectric-constant material layer 205 and gate insulating film 210 interposed therebetween, to form a gate electrode 212 (see FIG. 2 ).

[0057] Next, as shown in FIGS. 32 and 33 , the insulating layer 24, the high-dielectric-constant material layer 26, and the metal layer 27 above the insulating layer 41 are removed. Furthermore, the surfaces of the insulating layer 41, the insulating layer 24, the high-dielectric-constant material layer 26, and the metal layer 27 are planarized. Removal and planarization of the insulating layer 24, the high-dielectric-constant material layer 26, and the metal layer 27 are performed using, for example, CMP. As a result, a gate electrode 112 made of the high-dielectric-constant material layer 105 and the metal layer 104 is formed in the first semiconductor element 100. Furthermore, a gate electrode 212 made of the high-dielectric-constant material layer 205 and the metal layer 204 is formed in the second semiconductor element 200. Furthermore, in the second semiconductor element 200, the insulating layer 24 with its surface planarized becomes the gate insulating film 210.

[0058] Furthermore, contacts 109, 209 are formed to connect external wiring to the source / drain regions 108, 208. For example, a resist layer is patterned over the entire surface of the substrate 11, with openings only in the areas where the contacts 109, 209 are to be formed. Then, the insulating layer 41 is etched through the openings in the resist layer to form through-holes that expose the upper surfaces of the source / drain regions 108, 208. Next, the through-holes are filled with Cu or W, and the resist layer is removed and the surface is planarized. As a result, the contacts 109, 209 that connect to the source / drain regions 108, 208 are formed, as shown in FIGS. 32 and 33 .

[0059] The above steps allow the manufacture of a semiconductor device 10, as shown in FIGS. 2-5, in which a first semiconductor element 100 and a second semiconductor element 200 are formed on a substrate 11. In the above-described method for manufacturing the semiconductor device 10, epitaxial growth of the Si layer and the SiGe layer can be performed in common for the first semiconductor element 100 and the second semiconductor element 200. This facilitates control of the Si / SiGe stack formation process and the Si / SiGe stack processing process. Furthermore, since there is no significant difference in the thickness of the SiGe layer, the insulating layer can be easily formed on the wall surface when forming the inner spacers 107 and 207. Furthermore, after the formation of the source / drain regions 108 and 208, an oxidation process, which can cause device degradation, is not required. This prevents performance degradation of the semiconductor device.

[0060] 3. Semiconductor Device of Second Embodiment Next, a semiconductor device of a second embodiment will be described. The semiconductor device of the second embodiment described below has the same configuration as the semiconductor device of the first embodiment described above, with some exceptions. Therefore, detailed description of the same configuration as the semiconductor device of the first embodiment described above will be omitted.

[0061] [Semiconductor Device of Second Embodiment] FIGS. 34 to 37 show the configuration of a semiconductor device of the second embodiment. FIG. 34 is a cross-sectional view (cross-sectional view in the gate length direction) of the semiconductor device shown in FIG. 1 taken along line X1. FIG. 35 is a cross-sectional view (cross-sectional view in the gate width direction) of the semiconductor device shown in FIG. 1 taken along line Y1. FIG. 36 is a cross-sectional view (cross-sectional view in the gate length direction) of the semiconductor device shown in FIG. 1 taken along line X2. FIG. 37 is a cross-sectional view (cross-sectional view in the gate width direction) of the semiconductor device shown in FIG. 1 taken along line Y2. In the semiconductor device of the second embodiment, the first semiconductor element 100 shown in FIGS. 34 and 35 has the same configuration as the semiconductor device of the first embodiment. Therefore, only the configuration of the second semiconductor element 200A shown in FIGS. 36 and 37 will be described below.

[0062] (Second Semiconductor Element) In the cross-sectional view in the gate length direction shown in FIG. 36 , the second semiconductor element 200A has a gate electrode 212 on a substrate 11, with a gate insulating film 210 and a high-dielectric-constant material layer 215 interposed therebetween. In the second semiconductor element 200A, the substrate 11 has a groove 211A in the region where the gate insulating film 210, the high-dielectric-constant material layer 205, and the gate electrode 212 are formed, which is dug deeper than the surrounding region. The groove 211A of the second semiconductor element 200A of the second embodiment is dug deeper in the lateral direction of the substrate 11 than the groove 211 of the second semiconductor element 200 of the first embodiment described above. Furthermore, the groove 211A of the second semiconductor element 200A of the second embodiment has a wider dug region than the groove 211 of the second semiconductor element 200 of the first embodiment. That is, the area where the groove 211A is adjacent to the substrate 11 is larger than the area of ​​the opening 217 at the top of the element. In the groove 211 of the second semiconductor element 200 of the first embodiment, the lower part of the inner spacer 207 is not dug at all. In contrast, in the groove 211A of the second semiconductor element 200A of the second embodiment, the substrate 11 is dug down to the lower part of the inner spacer 207.

[0063] The gate insulating film 210 is formed so as to cover the surface of the groove 211A. Since the groove 211A is formed down to the bottom of the inner spacer 207, the gate insulating film 210 is formed down to the bottom of the inner spacer 207. Furthermore, a high-dielectric-constant material layer 215 is formed so as to cover the inner surface of the gate insulating film 210, and the interiors of the gate insulating film 210 and the high-dielectric-constant material layer 215 are filled with a metal layer 214 constituting the gate electrode 212. That is, in the second semiconductor element 200 of the first embodiment described above, the metal layer 204 constituting the gate electrode 212 is formed only above the groove 211, whereas in the second semiconductor element 200A of the second embodiment, the metal layer 214 constituting the gate electrode 212 is formed continuously down to the inside of the groove 211A. Furthermore, since the groove 211A is expanded laterally beyond the opening 217 at the top of the element, the area of ​​the metal layer 214 adjacent to the substrate 11 is larger than that of the opening 217 at the top of the element. The second semiconductor element 200A also has an impurity diffusion region in the substrate 11 around the groove 211A in which the gate insulating film 210 and the gate electrode 212 are formed. Therefore, in the second semiconductor element 200A, the impurity diffusion region in the substrate 11 becomes a region (channel region) in which a channel is formed when the second semiconductor element 200 is driven.

[0064] In the cross-sectional view in the gate width direction shown in FIG. 37 , the second semiconductor element 200A has a gate insulating film 210 and a high-dielectric-constant material layer 215 formed on the substrate 11 and the STI 42. The second semiconductor element 200A has a metal layer 214 constituting a gate electrode 212 on the high-dielectric-constant material layer 215. In the cross-sectional view in the gate width direction shown in FIG. 37 , the second semiconductor element 200A has a groove 211A in which the substrate 11 is dug to a lower position. The gate insulating film 210 is formed to cover the inside of the groove 211A. Therefore, the gate insulating film 210 is formed in contact with the surface of the substrate 11, the side surface of the groove 211A, and the top surface of the groove 211A. The metal layer 214 is embedded in the gate insulating film 210 and the high-dielectric-constant material layer 215 within the groove 211A.

[0065] In the semiconductor device of the second embodiment described above, the second semiconductor element 200A has the same configuration as the second semiconductor element 200 of the first embodiment described above, except for the groove 211A, gate insulating film 210, high-dielectric-constant material layer 215, and metal layer 214 formed in the substrate 11. Therefore, in the second semiconductor element 200A, a channel is formed in the substrate 11 when a gate voltage is applied to the gate electrode 212. Furthermore, in the second semiconductor element 200A, the groove 211A is expanded in the depth direction and lateral direction on the substrate 11, so the area in which the gate electrode 212 is formed is larger. Therefore, the second semiconductor element 200A of the second embodiment has a longer channel length, indicated by the arrow in FIG. 36 , than the second semiconductor element 200 of the first embodiment. As a result, the second semiconductor element 200A has improved device stability.

[0066] 4. Manufacturing Method of Semiconductor Device of Second Embodiment Next, a manufacturing method of the semiconductor device of the second embodiment shown in FIGS. 34-37 will be described. FIGS. 38-41 show manufacturing process diagrams of the semiconductor device of the second embodiment. In the manufacturing process of the semiconductor device shown in FIGS. 38 and 40, the left side of the drawing shows a cross-sectional view (cross-sectional view in the gate length direction) of the first semiconductor element 100 of the semiconductor device 10 shown in FIG. 1 along line X1, and the right side of the drawing shows a cross-sectional view (cross-sectional view in the gate length direction) of the second semiconductor element 200A along line X2. Also, in the manufacturing process of the semiconductor device shown in FIGS. 39 and 41, the left side of the drawing shows a cross-sectional view (cross-sectional view in the gate width direction) of the first semiconductor element 100 of the semiconductor device 10 shown in FIG. 1 along line Y1, and the right side of the drawing shows a cross-sectional view (cross-sectional view in the gate width direction) of the second semiconductor element 200A along line Y2.

[0067] First, the steps shown in FIGS. 6 to 17 in the manufacturing method of the semiconductor device according to the first embodiment are performed. Then, the Si layers 17, 18, and 19 of the second semiconductor element 200A are selectively removed. In this step, CDE processing or wet etching using an etching solution, which can selectively remove the Si layers 17, 18, and 19, is performed. As a result of this step, as shown in FIGS. 38 and 39 , portions of the Si layers 17, 18, and 19 remain between the stacked layers of the inner spacer 207 and in contact with the source / drain region 208, forming Si layers 201, 202, and 203. In this step, the surface of the substrate 11 is dug in addition to removing the Si layers 17, 18, and 19, forming steps between the openings and the lower portions of the inner spacer 207 and the source / drain region 208, forming trenches 211A. In the second semiconductor element 200A, the amount of recession of the surface of the substrate 11 is made larger than that of the second semiconductor element 200 of the first embodiment by adjusting the conditions of the CDE process, the type of etching solution used, the etching conditions and time, etc. Also, after the formation of the groove 211A, a process of implanting impurities for channel formation into the bottom of the groove 211A may be added. Similar to the process shown in FIGS. 8 and 9 above, the first semiconductor element 100 is protected by patterning a resist layer, and this process is performed separately for the PMOS and NMOS.

[0068] 20 to 33 in the method for manufacturing the semiconductor device of the first embodiment described above, the semiconductor device of the second embodiment shown in Figures 40 and 41 can be manufactured. Also, the method for manufacturing the semiconductor device of the second embodiment can obtain the same effects as the method for manufacturing the semiconductor device of the first embodiment described above.

[0069] 5. Semiconductor Device of Third Embodiment Next, a semiconductor device of a third embodiment will be described. The semiconductor device of the third embodiment described below has the same configuration as the semiconductor device of the first embodiment described above, with some exceptions. Therefore, detailed description of the same configuration as the semiconductor device of the first embodiment described above will be omitted.

[0070] [Semiconductor Device of Third Embodiment] Figures 42 to 45 show the configuration of a semiconductor device of the third embodiment. Figure 42 is a cross-sectional view (cross-sectional view in the gate length direction) of the semiconductor device shown in Figure 1 taken along line X1. Figure 43 is a cross-sectional view (cross-sectional view in the gate width direction) of the semiconductor device shown in Figure 1 taken along line Y1. Figure 44 is a cross-sectional view (cross-sectional view in the gate length direction) of the semiconductor device shown in Figure 1 taken along line X2. Figure 45 is a cross-sectional view (cross-sectional view in the gate width direction) of the semiconductor device shown in Figure 1 taken along line Y2. Note that in the semiconductor device of the third embodiment, the first semiconductor element 100 shown in Figures 42 and 43 has the same configuration as the semiconductor device of the first embodiment. Therefore, only the configuration of the second semiconductor element 200B shown in Figures 44 and 45 will be described below.

[0071] (Second Semiconductor Element) In the cross-sectional view in the gate length direction shown in FIG. 44 , the second semiconductor element 200B has source / drain regions 218 on the inner surface of the substrate 11. The second semiconductor element 200B has the same configuration as the second semiconductor element 200 of the first embodiment described above, except for the configuration of the source / drain regions 218 and the contacts 219. Therefore, like the second semiconductor element 200 of the first embodiment described above, the substrate 11 has a groove 211 in a region where the gate insulating film 210, the high-dielectric-constant material layer 205, and the gate electrode 212 are formed, which is dug deeper than the surrounding area of ​​this region. Furthermore, a metal layer 204 constituting the gate insulating film 210, the high-dielectric-constant material layer 205, and the gate electrode 212 is formed on the inner wall side of the Si layers 201, 202, and 203 and the inner spacer 207, including the groove 211.

[0072] The source / drain regions 218 are formed on the surface of the substrate 11 outside the gate insulating film 210, from the bottom of the lowermost inner spacer 207 to the edge of the position where the insulating layer 41 is embedded as the STI 42. The source / drain regions 218 are formed by diffusing impurities into the surface of the substrate 11. The source / drain regions 218 are diffused with impurities at a higher concentration than the diffusion region on the surface of the substrate 11 below the gate electrode 212 that serves as the channel. Furthermore, the source / drain regions 218 are diffused with impurities of a different conductivity type than the region below the gate electrode 212 that serves as the channel.

[0073] Contacts 219 for connection to external wiring are connected to the source / drain regions 218. The contacts 219 are formed of a metal material embedded in through holes that penetrate from the top of the insulating layer 41 of the second semiconductor element 200B to the source / drain regions 218.

[0074] In addition, in the cross-sectional view in the gate width direction shown in FIG. 45, the second semiconductor element 200B has a configuration similar to the cross-sectional view in the gate width direction of the second semiconductor device of the first embodiment shown in FIG. 5 described above.

[0075] In the semiconductor device of the third embodiment described above, the second semiconductor element 200B has source / drain regions 218 formed in the substrate 11. In this configuration, the source / drain regions 218 can be formed by ion implantation, which makes it easy to adjust the characteristics of the second semiconductor element 200B.

[0076] 6. Manufacturing Method of Semiconductor Device of Third Embodiment Next, a manufacturing method of the semiconductor device of the third embodiment shown in FIGS. 42-45 will be described. FIGS. 46-61 show manufacturing process diagrams of the semiconductor device of the third embodiment. In the manufacturing process of the semiconductor device shown in FIGS. 46, 48, 50, 52, 54, 56, 58, and 60, the left side of the drawing shows a cross-sectional view (cross-sectional view in the gate length direction) of the first semiconductor element 100 of the semiconductor device 10 shown in FIG. 1 along line X1, and the right side of the drawing shows a cross-sectional view (cross-sectional view in the gate length direction) of the second semiconductor element 200B. Also, in the manufacturing process of the semiconductor device 10 shown in FIGS. 47, 49, 51, 53, 55, 57, 59, and 61, the left side of the drawing shows a cross-sectional view (cross-sectional view in the gate width direction) of the first semiconductor element 100 of the semiconductor device 10 shown in FIG. 1 along line Y1, and the right side of the drawing shows a cross-sectional view (cross-sectional view in the gate width direction) of the second semiconductor element 200A along line Y2.

[0077] 6 to 9 in the manufacturing method of the semiconductor device of the first embodiment described above are performed. Then, a Si / SiGe stacked body, a dummy gate insulating film 22, a dummy gate 20, and a hard mask 21 are formed, and these stacked bodies are separated into individual elements. Furthermore, an STI 42 is formed in the substrate 11, and sidewalls 106 and 206 are formed, thereby fabricating the structures of the first semiconductor element 100 and the second semiconductor element 200B shown in FIGS. 46 and 47.

[0078] Next, a resist layer 28 is formed on the entire surface of the substrate 11, and then, as shown in FIGS. 48 and 49 , the resist layer 28 is patterned to open only the formation region of the second semiconductor element 200B. Then, as shown in FIGS. 50 and 51 , impurity ions are implanted into the formation region of the second semiconductor element 200B through the openings in the resist layer 28, followed by annealing treatment or the like to form source / drain regions 218 inside the substrate 11. During the impurity ion implantation, the sidewalls 206 serve as a mask, so the impurities are implanted only into the region of the substrate 11 outside the Si / SiGe stack. Then, annealing treatment or the like diffuses the impurities to the bottom of the Si / SiGe stack. As a result, a continuous source / drain region 218 is formed on the surface of the substrate 11, from the end on the STI 42 side to the bottom of the Si / SiGe stack. Furthermore, impurity ion implantation into the substrate 11 in the formation region of the second semiconductor element 200B is performed for both NMOS and PMOS. Specifically, in patterning the resist layer 28, only the second semiconductor element 200B that will become the NMOS is opened, and impurity ions such as phosphorus are implanted. Furthermore, the resist layer 28 is patterned to open only the second semiconductor element 200B that will become the PMOS, and impurity ions such as boron are implanted. Through this process, impurity ions of different conductivity types are implanted into the second semiconductor element 200B that will become the NMOS or PMOS.

[0079] 52 and 53, the resist layer 28 is removed. Then, inner spacers 107 and 207 are formed on the first semiconductor element 100 and the second semiconductor element 200B.

[0080] Next, as shown in FIGS. 54 and 55 , the AlO (aluminum oxide) layer 29 is patterned to open only the region where the first semiconductor element 100 will be formed. Then, as shown in FIGS. 56 and 57 , source / drain regions 108 are formed in the first semiconductor element 100. The source / drain regions 108 are formed in the first semiconductor element 100 for both the NMOS and PMOS. Specifically, in patterning the AlO layer 29, only the first semiconductor element 100 that will become the NMOS is opened, and n-type source / drain regions 108 are formed by epitaxial growth with the addition of impurity ions such as phosphorus. Furthermore, the AlO layer 29 is patterned to open only the first semiconductor element 100 that will become the PMOS, and p-type source / drain regions 108 are formed by epitaxial growth with the addition of impurity ions such as boron. Through this process, source / drain regions 108 of different conductivity types are formed in the first semiconductor element 100 that will become the NMOS or PMOS.

[0081] 58 and 59, the AlO layer 29 is peeled off. Then, by appropriately applying the steps shown in FIGS. 10 to 33 in the method for manufacturing the semiconductor device of the first embodiment described above, the semiconductor device of the third embodiment shown in FIGS. 60 and 61 can be manufactured. Also, the method for manufacturing the semiconductor device of the third embodiment can obtain the same effects as the method for manufacturing the semiconductor device of the first embodiment described above.

[0082] 7. Semiconductor Device of Fourth Embodiment Next, a semiconductor device of a fourth embodiment will be described. The semiconductor device of the fourth embodiment described below has a configuration similar to that of the semiconductor device of the first embodiment described above. Therefore, a description of the configuration similar to that of the semiconductor device of the first embodiment described above will be omitted.

[0083] 62 and 63 show the configuration of a semiconductor device according to the second embodiment. FIG. 62 is a cross-sectional view (cross-sectional view in the gate length direction) of the semiconductor device shown in FIG. 1 taken along line X1. FIG. 63 corresponds to a cross-sectional view (cross-sectional view in the gate length direction) of the semiconductor device shown in FIG. 1 taken along line X2. In the description of the fourth embodiment, the cross-sectional view (cross-sectional view in the gate width direction) and the cross-sectional view (cross-sectional view in the gate width direction) of the semiconductor device shown in FIG. 1 taken along line Y1 and line Y2 are omitted. The cross-sectional view in the gate width direction also has a configuration in which the first semiconductor element 100 and the second semiconductor element 200 shown in FIG. 3 or 5 are stacked, similar to FIGS. 62 and 63.

[0084] In the semiconductor device of the fourth embodiment, a first semiconductor element 100C shown in FIG. 62 and a second semiconductor element 200C shown in FIG. 63 are formed on a common substrate 11. The first semiconductor element 100C shown in FIG. 62 has a third semiconductor element 100D and a fourth semiconductor element 100E, each having a configuration similar to that of the first semiconductor element 100 shown in FIG. 2 , stacked on the substrate 11. The first semiconductor element 100C has the fourth semiconductor element 100E formed on the third semiconductor element 100D. In the first semiconductor element 100C, the source / drain region 108a of the third semiconductor element 100D is formed as a p-type PMOS, and the source / drain region 108b of the fourth semiconductor element 100E is formed as an n-type NMOS.

[0085] 63 has a fifth semiconductor element 200D and a sixth semiconductor element 200E stacked on a substrate 11. The fifth semiconductor element 200D and the sixth semiconductor element 200E have the same configuration as the second semiconductor element 200 shown in FIG. 4. The second semiconductor element 200C has the sixth semiconductor element 200E formed on the fifth semiconductor element 200D. In the second semiconductor element 200C, the source / drain region 208a of the fifth semiconductor element 200D is formed as a p-type PMOS, and the source / drain region 208b of the sixth semiconductor element 200E is formed as an n-type NMOS.

[0086] The semiconductor device of the fourth embodiment can be manufactured, for example, by the following steps. As with the semiconductor device of the first embodiment described above, a third PMOS semiconductor element 100D and a fifth PMOS semiconductor element 200D are formed on a substrate 11. Then, another substrate 11 is bonded to the upper surface side of the substrate 11 on which the third semiconductor element 100D and the fifth semiconductor element 200D are formed. Then, as with the semiconductor device of the first embodiment described above, a fourth NMOS semiconductor element 100D and a sixth NMOS semiconductor element 200D are formed on the substrate 11. By these steps, the semiconductor device of the fourth embodiment shown in FIGS. 62 and 63 can be manufactured.

[0087] In the semiconductor device of the fourth embodiment, the third semiconductor element 100D and the fourth semiconductor element 100E of the first semiconductor element 100C may be any combination of PMOS and NMOS, PMOS and PMOS, or NMOS and NMOS. Similarly, the fifth semiconductor element 200D and the sixth semiconductor element 200E of the second semiconductor element 200C may be any combination of PMOS and NMOS, PMOS and PMOS, or NMOS and NMOS. Furthermore, in the semiconductor device of the fourth embodiment, the fifth semiconductor element 200D and the sixth semiconductor element 200E of the second semiconductor element 200C may have a configuration similar to that of the second semiconductor element 200 shown in FIG. 4 described above, or may be any combination of the second semiconductor element 200A of the second embodiment shown in FIG. 36 or the second semiconductor element 200B of the third embodiment shown in FIG. 44.

[0088] The present invention is not limited to the configurations described in the above-described embodiments, and various modifications and changes are possible without departing from the scope of the present invention.

[0089] 10 semiconductor device, 11 substrate, 12, 13, 23, 25, 28 resist layer, 14, 15, 16 SiGe layer, 17, 18, 19 Si layer, 20 dummy gate, 21 hard mask, 22 dummy gate insulating film, 24, 41 insulating layer, 26, 105, 205, 215 high dielectric constant material layer, 29 AlO layer, 42 STI, 100, 100C first semiconductor element, 100D third semiconductor element, 100E fourth semiconductor element, 101, 102, 103 Si layer, 104, 204, 214, 27 metal layer, 106, 206, 216 sidewall, 107, 207 inner spacer, 108, 108a, 108b, 208, 208a, 208b, 218 Source / drain regions, 109, 209, 219 Contacts, 112, 212 Gate electrodes, 200, 200A, 200B, 200C Second semiconductor element, 200D Fifth semiconductor element, 200E Sixth semiconductor element, 201, 202, 203 Si layer, 210 Gate insulating film, 211, 211A Groove portion, 217 Opening

Claims

1. A semiconductor device including a first semiconductor element and a second semiconductor element on a substrate, wherein the first semiconductor element includes a first laminate including a channel layer and a first gate electrode that covers the periphery of the channel layer in a cross-section in the gate width direction of the first semiconductor element, and a first gate insulating film interposed between the channel layer and the first gate electrode, and the second semiconductor element includes a second gate electrode formed on the substrate with a second gate insulating film interposed therebetween, and a channel region formed in the substrate below the second gate electrode.

2. The semiconductor device according to claim 1, wherein the second semiconductor element includes an Si layer and a second insulating layer on a side surface of the second gate electrode, and the second gate insulating film is interposed between the second gate electrode and the Si layer and the second insulating layer.

3. The semiconductor device according to claim 2, wherein the second semiconductor element has a second source / drain region formed on a side surface of the stacked Si layer and the second insulating layer on the substrate.

4. The semiconductor device according to claim 1, wherein the substrate has a second source / drain region therein.

5. The semiconductor device according to claim 1, wherein the first semiconductor element includes a first source / drain region formed on a side surface in the gate length direction of the first laminate, a first gate electrode disposed between layers of the channel layer, and a first insulating layer formed between a side surface of the first source / drain region.

6. The semiconductor device according to claim 1, wherein in the second semiconductor element, the substrate has a groove portion recessed more than the periphery below the second gate electrode below the second gate electrode.

7. The semiconductor device according to claim 6, wherein the second gate electrode is disposed above the groove portion.

8. The semiconductor device according to claim 6, wherein the second gate electrode is formed inside the groove portion.

9. A method of manufacturing a semiconductor device including a first semiconductor element and a second semiconductor element on a substrate, the method including: forming a channel region by implanting impurity ions into the substrate in a formation region of the second semiconductor element; forming a Si / SiGe laminate by laminating a Si layer and a SiGe layer in a formation region of the first semiconductor element and a formation region of the second semiconductor element; removing the SiGe layer in the formation region of the first semiconductor element; forming a first gate insulating film in the formation region of the first semiconductor element; removing the SiGe layer in the formation region of the second semiconductor element; removing the Si layer in the formation region of the second semiconductor element; forming a second gate insulating film thicker than the first gate insulating film in the formation region of the second semiconductor element; and forming a metal layer in the formation region of the first semiconductor element and the formation region of the second semiconductor element to form a first gate electrode and a second gate electrode.

10. The method of manufacturing a semiconductor device according to claim 9, further including: forming a second source / drain region at a position facing through the channel region in the formation region of the second semiconductor element.

11. The method of manufacturing a semiconductor device according to claim 10, further including: forming the second source / drain region on the substrate in the formation region of the second semiconductor element.

12. The method of manufacturing a semiconductor device according to claim 10, further including: forming the second source / drain region in the substrate in the formation region of the second semiconductor element.

13. The method of manufacturing a semiconductor device according to claim 9, further including: forming an insulating layer on sidewalls of the SiGe layer in the formation region of the first semiconductor element and the formation region of the second semiconductor element.

14. The method of manufacturing a semiconductor device according to claim 13, further including: removing the Si layer so as to remain only between the insulating layers in the formation region of the second semiconductor element.

15. The method of manufacturing a semiconductor device according to claim 14, wherein in the step of removing the Si layer, a groove is formed in the substrate.

16. The method of manufacturing a semiconductor device according to claim 15, wherein the metal layer is embedded in the groove portion and the second gate electrode is formed in the groove portion.

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