Imaging device and camera system

Abstract

This imaging device comprises: a plurality of pixels arranged in a row direction and a column direction; first wiring for directly connecting a first pixel and a second pixel located in the same row to each other among the plurality of pixels; a voltage supply circuit for supplying a reset voltage to the first pixel and the second pixel via the first wiring; and a first switch connected between the first wiring and the voltage supply circuit.

Description

Imaging device and camera system

[0001] The present disclosure relates to an imaging device and a camera system.

[0002] 2. Description of the Related Art Image capture devices using a charge coupled device (CCD) image sensor and a complementary metal oxide semiconductor (CMOS) image sensor are widely used in digital cameras and the like.

[0003] There is a growing demand for low power consumption in imaging devices. Therefore, in order to realize simple recognition for autonomous power optimization with low power consumption, imaging devices capable of using an imaging mode for generating low-resolution images in addition to a normal imaging mode that consumes a large amount of power are being developed. In the imaging mode for generating low-resolution images, for example, the imaging device combines signals from two or more pixels.

[0004] For example, Patent Document 1 discloses an imaging device that includes floating wiring that connects floating diffusion nodes (FDs) set on a shared pixel basis, and a switch that switches between connection and disconnection between the FD and the floating wiring.

[0005] International Publication No. 2018 / 012316

[0006] However, in the imaging device disclosed in Patent Document 1, in order to combine signals from two or more pixels, it is necessary to provide a switch for each pixel, which makes the pixel circuitry complicated. Also, when combining signals output from pixels by simultaneously outputting signals from two or more pixels to a signal line, the influence of the signal from a pixel that outputs a larger signal becomes large, making it impossible to obtain an evenly combined signal.

[0007] Therefore, the present disclosure provides an imaging device or the like that can combine signals from two or more pixels with a simple circuit configuration.

[0008] An imaging device according to one aspect of the present disclosure includes a first pixel and a second pixel, a first wiring connected to the first pixel and the second pixel, a voltage supply circuit that supplies a reset voltage to the first pixel and the second pixel via the first wiring, and a first switch connected between the first wiring and the voltage supply circuit.

[0009] A camera system according to one aspect of the present disclosure includes the imaging device described above.

[0010] According to the present disclosure, signals from two or more pixels can be synthesized with a simple circuit configuration.

[0011] FIG. 1 is a diagram showing an exemplary configuration of an imaging device according to Embodiment 1. FIG. 2 is a schematic diagram showing an exemplary circuit configuration of an imaging device according to Embodiment 1. FIG. 3 is a timing chart for explaining an example of the operation of the imaging device according to Embodiment 1. FIG. 4 is a timing chart for explaining another example of the operation of the imaging device according to Embodiment 1. FIG. 5 is a schematic diagram showing an exemplary circuit configuration of an imaging device according to Modification 1 of Embodiment 1. FIG. 6 is a timing chart for explaining an example of the operation of the imaging device according to Modification 1 of Embodiment 1. FIG. 7 is a schematic diagram showing an exemplary circuit configuration of an imaging device according to Modification 2 of Embodiment 1. FIG. 8 is a schematic diagram showing an exemplary circuit configuration of an imaging device according to Modification 3 of Embodiment 1. FIG. 9 is a schematic diagram showing an exemplary circuit configuration of an imaging device according to Modification 4 of Embodiment 1. FIG. 10 is a block diagram showing an example of the configuration of a camera system according to Embodiment 2.

[0012] (Summary of the Present Disclosure) As an overview of the present disclosure, examples of an imaging device and a camera system according to the present disclosure are described below.

[0013] For example, an imaging device according to a first aspect of the present disclosure includes a first pixel and a second pixel, a first wiring connected to the first pixel and the second pixel, a voltage supply circuit that supplies a reset voltage to the first pixel and the second pixel via the first wiring, and a first switch connected between the first wiring and the voltage supply circuit.

[0014] This makes it possible to insulate the first wiring from the voltage supply circuit using the first switch, and therefore the first wiring for supplying a reset voltage to the first pixel and the second pixel can be used to combine signals from the first pixel and the second pixel. Therefore, there is no need to form separate transistors and wiring for combining signals in the first pixel and the second pixel, and signals from the first pixel and the second pixel can be combined with a simple circuit configuration.

[0015] Also, for example, an imaging device according to a second aspect of the present disclosure is the imaging device according to the first aspect, wherein each of the first pixel and the second pixel includes a photoelectric conversion unit that converts light into signal charge, a charge accumulation unit that accumulates the signal charge, and a transistor having one of a source and a drain connected to the charge accumulation unit, and the first wiring is connected to the other of the source and the drain of the transistor.

[0016] This allows the signal charges stored in the charge storage sections of the first pixel and the second pixel via the transistors to be mixed in the first wiring, thereby combining the signals of the first pixel and the second pixel.

[0017] Also, for example, an imaging device according to a third aspect of the present disclosure is the imaging device according to the second aspect, in which, after the transistors of the first pixel and the second pixel are turned on when the first switch is turned off, the first pixel outputs a pixel signal corresponding to the signal charge stored in the charge storage section of the first pixel and the second pixel.

[0018] This allows the first pixel itself to output a pixel signal that is a combination of the signals from the first pixel and the second pixel, thereby simplifying the circuit configuration.

[0019] Also, for example, an imaging device according to a fourth aspect of the present disclosure is the imaging device according to the second aspect, further comprising a third pixel connected to the first wiring and not generating the signal charge, wherein after the transistors of the first pixel and the second pixel are turned on when the first switch is turned off, the third pixel outputs a pixel signal corresponding to the signal charge accumulated in the charge accumulation section of the first pixel and the second pixel.

[0020] As a result, the pixel signal is output by an ineffective third pixel that does not generate signal charge and is separate from the first and second pixels, making it possible to fix the pixel that outputs the pixel signal.

[0021] Also, for example, an imaging device according to a fifth aspect of the present disclosure is the imaging device according to any one of the first to fourth aspects, wherein the first pixel and the second pixel are located in the same column.

[0022] This allows signals from pixels located in the same column to be combined.

[0023] Also, for example, an imaging device according to a sixth aspect of the present disclosure is the imaging device according to any one of the first to fifth aspects, wherein the first pixel and the second pixel have color filters of the same color.

[0024] This allows pixel signals to be combined while maintaining color information.

[0025] Also, for example, an imaging device according to a seventh aspect of the present disclosure is an imaging device according to any one of the first to sixth aspects, further comprising: a third pixel located in a different column from the first pixel and the second pixel; a fourth pixel located in the same column as the third pixel; a second wiring connected to the third pixel and the fourth pixel; and a second switch connected between the first wiring and the second wiring.

[0026] This allows the second switch to connect the first wiring and the second wiring connected to pixels in different columns, making it possible to combine signals from pixels in the same column as well as pixels in different columns.

[0027] Also, for example, an imaging device according to an eighth aspect of the present disclosure is the imaging device according to the seventh aspect, wherein the first pixel, the second pixel, the third pixel, and the fourth pixel have color filters of the same color.

[0028] This allows pixel signals to be combined while maintaining color information.

[0029] Also, for example, an imaging device according to a ninth aspect of the present disclosure is the imaging device according to the fifth aspect, further comprising a third pixel and a fourth pixel located in the same column as the first pixel and the second pixel, a second wiring connected to the third pixel and the fourth pixel, and a second switch connected between the second wiring and the voltage supply circuit.

[0030] This allows the wiring for combining signals to be divided into first and second wirings for the first and second pixels and third and fourth pixels, thereby shortening the first and second wirings. Although the capacitance of the wiring for combining signals reduces the signal gain and decreases sensitivity, shortening the first and second wirings can suppress the decrease in sensitivity.

[0031] Also, for example, an imaging device according to a tenth aspect of the present disclosure is the imaging device according to the ninth aspect, further comprising a first substrate and a second substrate stacked on the first substrate, wherein the voltage supply circuit is arranged on the first substrate, and the first wiring and the second wiring are arranged on the second substrate.

[0032] This allows the first and second wiring and the voltage supply circuit to be arranged on separate substrates, making the wiring layout easier.

[0033] Also, for example, an imaging device according to an eleventh aspect of the present disclosure is an imaging device according to any one of the first to fourth aspects, wherein the first pixel and the second pixel are located in the same row, and the imaging device further includes a second wiring extending in the column direction and connected between the first wiring and the first switch.

[0034] This allows signals from pixels located in the same row to be combined, and also allows the first and second pixels, which are located in the same row and therefore in different columns, to share the second wiring extending in the column direction, thereby reducing the number of wirings extending in the column direction.

[0035] Also, for example, a camera system according to a twelfth aspect of the present disclosure includes the imaging device according to any one of the first to eleventh aspects.

[0036] As a result, the camera system according to this aspect includes the imaging device described above, and therefore can combine the signals of the first pixel and the second pixel with a simple circuit configuration.

[0037] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component arrangements and connection forms, steps, and step orders shown in the following embodiments are merely examples and are not intended to limit the present disclosure. The various aspects described in this specification can be combined with each other as long as no contradiction occurs. Furthermore, among the components in the following embodiments, components not recited in independent claims will be described as optional components. In the following description, components having substantially the same functions will be designated by common reference symbols, and their description may be omitted. Furthermore, to avoid overly complicated drawings, illustration of some elements may be omitted.

[0038] Furthermore, the drawings are schematic diagrams and are not necessarily drawn to scale.

[0039] Furthermore, in this specification, terms indicating relationships between elements, such as "equal," terms indicating the shapes of elements, such as "square" or "circle," and numerical ranges are not expressions that express only the strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0040] Furthermore, in this specification, the terms "upper" and "lower" do not refer to the upper direction (vertically upper) and lower direction (vertically lower) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in the stacked structure. Specifically, the light-receiving side of the imaging device is referred to as "upper," and the side opposite the light-receiving side is referred to as "lower." Note that terms such as "upper" and "lower" are used solely to specify the relative arrangement of components and are not intended to limit the orientation of the imaging device during use. Furthermore, the terms "upper" and "lower" are used not only when two components are spaced apart and another component is present between the two components, but also when two components are closely arranged and in contact with each other. Furthermore, in this specification, "plan view" refers to a view perpendicular to the main surface of the semiconductor substrate, in other words, when viewed from the thickness direction of the semiconductor substrate.

[0041] Furthermore, in the description of the circuit configuration in this specification, "connected" includes not only a direct connection via a conductor but also an electrical connection via another circuit element. Furthermore, "C is connected between A and B" means that a part of C (e.g., one end) is connected to A and another part of C (e.g., the other end) is connected to B, meaning that C is arranged in series in the path connecting A and B. "A path connecting A and B" means a path made up of a conductor electrically connecting A to B.

[0042] First Embodiment An imaging device according to a first embodiment will be described below.

[0043] [Overall Configuration] First, the overall configuration of the imaging device according to this embodiment will be described.

[0044] Fig. 1 is a diagram showing an exemplary configuration of an imaging device 100 according to embodiment 1. As shown in Fig. 1, the imaging device 100 has a plurality of pixels 10 and a peripheral circuit 40 formed on a semiconductor substrate 60.

[0045] Each pixel 10 includes a photoelectric conversion unit 12. The photoelectric conversion unit 12 generates positive and negative charges, typically hole-electron pairs, in response to incident light. The charges generated in the photoelectric conversion unit 12 are used as signal charges. In other words, the photoelectric conversion unit 12 converts light into signal charges. The photoelectric conversion unit 12 is, for example, a photoelectric conversion structure including a photoelectric conversion layer disposed above a semiconductor substrate 60. Note that, in FIG. 1 , the photoelectric conversion units 12 of each pixel 10 are illustrated as being spatially separated from one another, but this is merely for convenience of explanation, and the photoelectric conversion units 12 of multiple pixels 10 may be disposed continuously above the semiconductor substrate 60 without any gaps between them.

[0046] In the example shown in FIG. 1 , pixels 10 are arranged in a plurality of n rows and m columns in a planar view. Here, m and n independently represent integers of 1 or greater. The pixels 10 are arranged, for example, from the 0th row to the n-1th row and from the 0th column to the m-1th column. For example, the 0th row to the n-1th row are arranged in the column direction from top to bottom on the page, and the 0th column to the m-1th column are arranged in the row direction from left to right on the page. The pixels 10 are arranged, for example, two-dimensionally on the semiconductor substrate 60 to form an imaging region R1. For example, if each pixel 10 has a photoelectric conversion unit 12 arranged above the semiconductor substrate 60, the imaging region R1 can be defined as the region of the semiconductor substrate 60 that is covered by the photoelectric conversion unit 12.

[0047] The number and arrangement of the pixels 10 are not limited to the example shown in the figure. In the example shown in FIG. 1 , the center of each pixel 10 is located on a lattice point of a square lattice, but for example, multiple pixels 10 may be arranged so that the center of each pixel 10 is located on a lattice point of a triangular lattice, a hexagonal lattice, or the like. Therefore, the column direction and the row direction do not need to be orthogonal as long as they intersect. Furthermore, for example, the pixels 10 may be arranged one-dimensionally, in which case the imaging device 100 can be used as a line sensor.

[0048] 1, each pixel 10 has a color filter CF. The color filter CF is disposed on the light incident side of the photoelectric conversion unit 12. Note that when the imaging device 100 captures a black and white image, each pixel 10 does not need to have a color filter CF.

[0049] In the example shown in FIG. 1 , the peripheral circuit 40 includes a vertical scanning circuit 42, a horizontal signal readout circuit 44, and a voltage supply circuit 46. Also, as shown in FIG. 1 , the peripheral circuit 40 may additionally include a control circuit 48. The peripheral circuit 40 may further include a signal processing circuit, an output circuit, and a voltage supply circuit other than the voltage supply circuit 46. The peripheral circuit 40 is disposed in, for example, a peripheral region R2. The peripheral region R2 is a region on the semiconductor substrate 60 surrounding the imaging region R1. Note that at least a portion of the peripheral circuit 40 may be disposed on one or more semiconductor substrates other than the semiconductor substrate 60 on which the pixels 10 are formed. In other words, at least a portion of the peripheral circuit 40 does not have to be disposed in the peripheral region R2. In this case, the one or more other semiconductor substrates may be stacked on the semiconductor substrate 60. Furthermore, a portion of the components included in the pixels 10 may also be disposed on one or more other semiconductor substrates.

[0050] The vertical scanning circuit 42, also called a row scanning circuit, is connected to row control lines SL provided corresponding to each row of the plurality of pixels 10. For ease of viewing, only one row control line SL is shown per row in FIG. 1 , but as will be described later, the row control line SL may include two or more control lines per row. The vertical scanning circuit 42 applies a predetermined voltage to the row control line SL to select the pixels 10 row by row and cause the pixels 10 to output signals, perform reset operations, and the like.

[0051] The horizontal signal readout circuit 44 is also called a column scanning circuit, and is connected to vertical signal lines 35 provided corresponding to each column of the plurality of pixels 10 via column circuits 43 described below. The columns of the plurality of pixels 10 and the vertical signal lines 35 correspond, for example, one-to-one. The horizontal signal readout circuit 44 sequentially reads out signals from the column circuits 43 to a subsequent circuit (not shown).

[0052] The row control lines SL and the vertical signal lines 35 are formed in, for example, a wiring layer on the semiconductor substrate 60 .

[0053] The voltage supply circuit 46 supplies a reset voltage to each pixel 10. The voltage supply circuit 46 will be described in detail later.

[0054] The control circuit 48 receives command data, a clock, and the like provided, for example, from outside the imaging device 100, and controls the entire imaging device 100. The control circuit 48 has, for example, a timing generator and supplies drive signals to the vertical scanning circuit 42, the horizontal signal readout circuit 44, and the like. The control circuit 48 can be realized, for example, by a microcontroller including one or more processors. The functions of the control circuit 48 may be realized by a combination of a general-purpose processing circuit and software, or by hardware specialized for such processing.

[0055] [Circuit Configuration] Next, the circuit configuration of the imaging device 100 will be described.

[0056] FIG. 2 is a schematic diagram illustrating an exemplary circuit configuration of an imaging device 100 according to the present embodiment. For ease of viewing, FIG. 2 illustrates only the pixels 10 in row 0 and row 1 of column 0 among the pixels 10 arranged in rows 0 to n-1 and columns 0 to m-1. For columns other than column 0, the circuit configuration corresponding to column 0, excluding the voltage supply circuit 46, is repeated. In this embodiment, the pixel 10 in row 0 of column 0 is an example of a first pixel, and the pixel 10 in row 1 of column 0 is an example of a second pixel located in the same column as the first pixel. For ease of viewing, FIG. 2 illustrates only the wiring and circuits necessary for explanation, and the circuit configuration of the imaging device 100 may include wiring, circuits, and the like not illustrated in FIG. 2.

[0057] 2, the imaging device 100 includes an OB (Optical Black) pixel 10OB, a reset voltage line 31, a switch SWa, a current source 39, and a column circuit 43 in addition to the configuration shown in FIG. 1. The switch SWa, the current source 39, and the column circuit 43 may be part of the peripheral circuit 40 described above. The OB pixel 10OB, the reset voltage line 31, the switch SWa, the current source 39, and the column circuit 43 are provided corresponding to each column of the multiple pixels 10. In other words, the imaging device 100 includes multiple OB pixels 10OB, reset voltage lines 31, switches SWa, current sources 39, and column circuits 43.

[0058] As shown in FIG. 2 , the pixel 10 and the OB pixel 10B each include a photoelectric conversion unit 12, a reset transistor 22, an amplification transistor 23, a selection transistor 24, and a charge accumulation unit FD. The pixel 10 and the OB pixel 10OB have, for example, the same circuit configuration. The OB pixel 10OB has a light-shielding layer on the light incident side of the photoelectric conversion unit 12, which is not provided in the pixel 10. Therefore, the OB pixel 10OB is an ineffective pixel that does not generate signal charge even when receiving incident light. For example, the OB pixel 10OB is additionally arranged in a column of multiple pixels 10 in a planar view. In other words, the OB pixel 10OB is arranged at the end of the column in which the pixel 10 and the OB pixel 10OB are arranged. At least one OB pixel 10OB is provided corresponding to each column of multiple pixels 10. In this embodiment, the OB pixel 10OB in the 0th column is an example of a third pixel. Note that, when the imaging device 100 does not perform an operation of outputting pixel signals from the OB pixels 10OB, as in the operation shown in FIG. 4 described later, the imaging device 100 does not need to include the OB pixels 10OB.

[0059] The charge storage unit FD is connected to the photoelectric conversion unit 12 and stores signal charges generated by the photoelectric conversion unit 12. The charge storage unit FD stores signal charges corresponding to light incident on the pixel 10. The charge storage unit FD is also called a "floating diffusion node."

[0060] The photoelectric conversion unit 12 includes a pixel electrode 12a, a counter electrode 12c, and a photoelectric conversion layer 12b disposed between the pixel electrode 12a and the counter electrode 12c. The pixel electrode 12a, the photoelectric conversion layer 12b, and the counter electrode 12c are stacked in this order on a semiconductor substrate 60, for example. The photoelectric conversion unit 12 may further include other elements such as an electron blocking layer and a hole blocking layer.

[0061] The counter electrode 12c and the photoelectric conversion layer 12b are formed, for example, across a plurality of pixels 10 and OB pixels 10OB corresponding to each column of the plurality of pixels 10. A pixel electrode 12a is provided for each pixel 10 and each OB pixel 10OB. The pixel electrode 12a is electrically isolated from the pixel electrodes 12a of other pixels 10. Note that at least one of the counter electrode 12c and the photoelectric conversion layer 12b may be provided separately for one or more pixels 10.

[0062] The pixel electrode 12a is electrically connected to the photoelectric conversion layer 12b and serves to collect signal charges generated in the photoelectric conversion layer 12b. The pixel electrode 12a is connected to a charge accumulation unit FD. The pixel electrode 12a is formed using a conductive material. The signal charges collected by the pixel electrode 12a are accumulated in the charge accumulation unit FD.

[0063] The counter electrode 12c is, for example, a transparent electrode formed from a transparent conductive material. The counter electrode 12c is disposed on the side of the photoelectric conversion layer 12b where light is incident. A bias voltage VITO is supplied to the counter electrode 12c. By controlling the bias voltage VITO, either the holes or the electrons of the hole-electron pairs generated in the photoelectric conversion layer 12b by photoelectric conversion can be collected by the pixel electrode 12a as signal charges. For example, when holes are used as signal charges, a bias voltage VITO that makes the counter electrode 12c higher in potential than the pixel electrode 12a is applied to the counter electrode 12c, thereby allowing the pixel electrode 12a to selectively collect the holes. Note that it is also possible to selectively collect electrons by the pixel electrode 12a by making the counter electrode 12c lower in potential than the pixel electrode 12a. Furthermore, when the imaging device 100 is driven using the global shutter method, for example, signal reading is performed during a period when a bias voltage VITO, which does not substantially cause movement from the photoelectric conversion layer 12b to the pixel electrode 12a, is applied to the opposing electrode 12c.

[0064] The photoelectric conversion layer 12b is a layer that absorbs photons and generates photocharges that become signal charges. Specifically, the photoelectric conversion layer 12b receives incident light and generates hole-electron pairs. In other words, the signal charges are either holes or electrons. For example, when holes are used as signal charges, the holes are collected by the pixel electrode 12a. Electrons, which are charges of the opposite polarity to the signal charges, are collected by the counter electrode 12c. The photoelectric conversion layer 12b is made of a photoelectric conversion material, and is formed, for example, from an organic semiconductor material. The photoelectric conversion layer 12b may also be formed from an inorganic semiconductor material.

[0065] The reset transistor 22, the amplification transistor 23, and the selection transistor 24 are, for example, field effect transistors (FETs) formed on a semiconductor substrate 60 that supports the photoelectric conversion unit 12. For each of the reset transistor 22, the amplification transistor 23, and the selection transistor 24, for example, an N-channel MOSFET (Metal Oxide Semiconductor FET) is used.

[0066] The reset transistor 22 is an example of a transistor in which one of the source and drain is connected to the charge storage unit FD. The other of the source and drain of the reset transistor 22 is connected to a reset voltage line 31. A reset voltage is supplied to the other of the source and drain of the reset transistor 22 from a voltage supply circuit 46 via the reset voltage line 31 and a switch SWa. The gate of the reset transistor 22 is connected to a reset control signal line (not shown in FIG. 2 ) included in the row control line SL. A reset signal RST is supplied to the gate of the reset transistor 22 from the vertical scanning circuit 42 via the reset control signal line. In FIG. 2 and the figures described below, a number ranging from 0 to n-1 (such as 0, 1, ...) affixed to the reference symbol of the reset signal RST supplied to each pixel 10 (only RST0 and RST1 are shown in FIG. 2 ) indicates the row of the pixel 10. For example, the reset signal RST0 indicates the reset signal RST supplied to the pixel 10 in the 0th row. The reset signal RSTA indicates the reset signal RST supplied to the OB pixel 10OB. The reset transistor 22 is turned on when the reset signal RST is at a high level, for example. When the reset transistor 22 and the switch SWa are turned on, the potential of the charge storage unit FD is reset to the reset voltage. When the reset signal RST is at a low level, the reset transistor 22 is turned off, insulating the charge storage unit FD from the reset voltage line 31. Note that the on and off states of the transistor correspond to the conduction and non-conduction of the transistor, respectively.

[0067] The reset voltage lines 31 are provided corresponding to each column of the pixels 10. For example, there is a one-to-one correspondence between the columns of the pixels 10 and the reset voltage lines 31. The reset voltage lines 31 extend in the column direction and are connected to the pixels 10 and the OB pixels 10OB in the corresponding columns. In the present embodiment, the reset voltage lines 31 are an example of first wiring. The reset voltage lines 31 are formed, for example, in a wiring layer on the semiconductor substrate 60.

[0068] The switch SWa is an example of a first switch connected between the reset voltage line 31 and the voltage supply circuit 46. The switch SWa switches between conduction and non-conduction between the reset voltage line 31 and the voltage supply circuit 46. The switch SWa is provided for each column of multiple pixels 10 in correspondence with the reset voltage line 31. The switch SWa and the reset voltage line 31 correspond, for example, to one-to-one correspondence.

[0069] The switch SWa is, for example, an FET formed on the semiconductor substrate 60, and its operation is controlled by a switch control signal φRST applied to its gate. The switch control signal φRST is supplied, for example, from the control circuit 48. The switch SWa is turned on when the switch control signal φRST is high, thereby connecting the reset voltage line 31 and the voltage supply circuit 46. This allows a reset voltage to be supplied to the reset voltage line 31. The switch SWa is turned off when the switch control signal φRST is low, thereby isolating the reset voltage line 31 from the voltage supply circuit 46. For example, the same switch control signal φRST is supplied to each switch SWa connected to the reset voltage line 31 corresponding to each column of multiple pixels 10, and the same control is performed. In the imaging device 100, the switch SWa can isolate the reset voltage line 31 from the voltage supply circuit 46, so that signals based on the signal charges accumulated in the charge accumulation units FD of two or more pixels 10 can be combined via the reset voltage line 31.

[0070] The voltage supply circuit 46 supplies a reset voltage to each pixel 10 via the reset voltage line 31. For example, one voltage supply circuit 46 is connected to a switch SWa connected to the reset voltage line 31 corresponding to each column of the pixels 10. That is, a reset voltage is supplied from one voltage supply circuit 46 to the reset voltage line 31 corresponding to each column of the pixels 10 via the switch SWa connected to the reset voltage line 31. Note that a voltage supply circuit 46 may be provided corresponding to each column of the pixels 10.

[0071] A power supply voltage VDD is supplied to one of the source and drain of the amplification transistor 23. The other of the source and drain of the amplification transistor 23 is connected to one of the source and drain of the selection transistor 24. The gate of the amplification transistor 23 is connected to the charge storage unit FD. As a result, the amplification transistor 23 forms a source follower circuit together with the current source 39 when the selection transistor 24 is in an on state. At this time, the other of the source and drain of the amplification transistor 23 outputs a signal corresponding to the potential of the charge storage unit FD to the vertical signal line 35 via the selection transistor 24. The potential of the charge storage unit FD after exposure of the pixel 10 corresponds to the amount of signal charge stored in the charge storage unit FD by exposure.

[0072] One of the source and drain of the selection transistor 24 is connected to the other of the source and drain of the amplification transistor 23. The other of the source and drain of the selection transistor 24 is connected to a vertical signal line 35. The gate of the selection transistor 24 is connected to a selection control signal line (not shown in FIG. 2 ) included in the row control line SL. The gate of the selection transistor 24 is supplied with a selection signal SEL from the vertical scanning circuit 42 via the selection control signal line. In FIG. 2 and the figures described below, a number ranging from 0 to n-1, such as 0, 1, ..., suffixed to the reference symbol of the selection signal SEL supplied to each pixel 10 (only SEL0 and SEL1 are shown in FIG. 2 ) indicates the row of the pixel 10. For example, the selection signal SEL0 indicates the selection signal SEL supplied to the pixel 10 in the 0th row. The selection signal SELA indicates the selection signal SEL supplied to the OB pixel 10OB. When the selection signal SEL is high, the selection transistor 24 is turned on and outputs a signal from the amplification transistor 23 to the vertical signal line 35. Furthermore, when the selection signal SEL is at a low level, the selection transistor 24 is turned off, and isolates the amplification transistor 23 from the vertical signal line 35 .

[0073] The signals output from the pixels 10 and the OB pixels 10OB and output to the vertical signal lines 35 via the selection transistors 24 are input to corresponding column circuits 43 among a plurality of column circuits 43 provided for each column of a plurality of pixels 10 corresponding to the vertical signal lines 35. The columns of the pixels 10 and the column circuits 43 correspond, for example, to one-to-one correspondence. The column circuits 43 perform noise suppression signal processing, typified by correlated double sampling (CDS), analog-to-digital conversion (AD conversion), and the like. The signals from the column circuits 43 are sequentially read out by the horizontal signal readout circuit 44 described above.

[0074] As described above, the imaging device 100 according to the present embodiment includes a plurality of pixels 10, a reset voltage line 31 connected to pixels 10 in the same column among the plurality of pixels 10, a voltage supply circuit 46 that supplies a reset voltage to the pixels 10 in that column via the reset voltage line 31, and a switch SWa connected between the reset voltage line 31 and the voltage supply circuit 46. This makes it possible to insulate the reset voltage line 31 from the voltage supply circuit 46 by the switch SWa, so that the reset voltage line 31 for supplying a reset voltage to each pixel 10 can be used to combine signals from two or more pixels 10. Therefore, there is no need to form separate transistors, wiring, and the like for combining signals in each pixel 10, and signals from two or more pixels can be combined with a simple circuit configuration.

[0075] [Operation of Imaging Device] Next, the operation (driving method) of the imaging device 100 according to this embodiment will be described. Below, a signal readout sequence when combining signals from two or more pixels 10 to generate a low-resolution image will be described. The circuits of the multiple pixels 10 and the OB pixels 10OB corresponding to each column of the multiple pixels 10 are driven under the control of the control circuit 48. The imaging device 100 may be driven using a global shutter system or a rolling shutter system. When the imaging device 100 generates an image with normal resolution, for example, the switch SWa is always on during imaging operation, allowing a known imaging device driving method to be used.

[0076] FIG. 3 is a timing chart for explaining an example of the operation of the imaging device 100 according to the present embodiment. FIG. 3 shows a timing chart of the operation when combining signals from two pixels 10. FIG. 3 also shows a timing chart of the operation when reading out a signal after exposure of the pixel 10 is completed. FIG. 3 shows the voltage levels of the switch control signal φRST, the selection signals SELA and SEL0 to SELn-1, and the reset signals RSTA and RST0 to RST5. In FIG. 3, "H" indicates a high level and "L" indicates a low level. Note that in the example of operation shown in FIG. 3, the timing charts of the voltage levels of the selection signals SEL0 to SELn-1 are the same, and therefore are shown together.

[0077] As shown in Figure 3, first, at time t1, the selection signal SELA and the reset signal RSTA go high. This turns on the reset transistor 22 of the OB pixel 10OB, establishing electrical continuity between the charge storage unit FD of the OB pixel 10OB and the reset voltage line 31. The selection transistor 24 of the OB pixel 10OB also turns on, causing a signal corresponding to the potential of the charge storage unit FD of the OB pixel 10OB to be output from the amplification transistor 23 of the OB pixel 10OB to the vertical signal line 35. During the operation shown in Figure 3, the selection signals SEL0 to SELn-1 are always low, and no signal from each pixel 10 is output to the vertical signal line 35.

[0078] At time t1, the reset signals RST0 and RST1 also go high. This turns on the reset transistors 22 of the pixels 10 in the 0th and 1st rows, thereby connecting the charge storage units FD of the pixels 10 in the 0th and 1st rows to the reset voltage line 31. Since the exposure of the pixels 10 in the 0th and 1st rows has been completed by time t1, signal charges corresponding to the exposure amount have been accumulated in the charge storage units FD of the pixels 10 in the 0th and 1st rows. At time t1, the switch control signal φRST is low, so the switch SWa is off and the reset voltage from the voltage supply circuit 46 is not supplied to the reset voltage line 31. Therefore, the signal charges accumulated in the charge storage units FD of the pixels 10 in the 0th and 1st rows are mixed by the reset voltage line 31. This combines the signals of the pixels 10 in the 0th and 1st rows and outputs them to the vertical signal line 35 from the amplification transistor 23 of the OB pixel 10OB. In this way, in the imaging device 100, under the control of the control circuit 48, when the switch SWa is turned off, the reset transistors 22 of the pixels 10 in the 0th and 1st rows are turned on, and then the OB pixels 10OB output pixel signals corresponding to the signal charges accumulated in the charge accumulation sections FD of the pixels 10 in the 0th and 1st rows.

[0079] 3 , the selection signal SELA and reset signal RSTA are always high, so the pixel that outputs the signal charge is fixed to the OB pixel 10OB. Therefore, the OB pixel 10OB also outputs pixel signals corresponding to the signal charges accumulated in the charge storage units FD of the pixels 10 in the second row and beyond. This allows the positional relationship between the OB pixel 10OB, which outputs the pixel signal, and the current source 39 to be fixed, enabling stable signal output independent of the position of the readout row. Furthermore, by arranging the OB pixel 10OB closer to the current source 39 than the multiple pixels 10, signal output can be even more stable.

[0080] When the signal charges accumulated in the charge accumulation units FD of the two pixels 10 are mixed by the reset voltage line 31, the capacitance Cvrst of the reset voltage line 31 also functions as a capacitance for accumulating the signal charges. Note that in Figure 2 and other figures, the capacitance Cvrst of the reset voltage line 31 is shown by a dashed line, but this is shown imaginarily for ease of understanding and does not mean that an element of the capacitance Cvrst is connected to the reset voltage line 31.

[0081] Next, at time t2, the switch control signal φRST goes high, turning on the switch SWa and supplying the reset voltage from the voltage supply circuit 46 to the pixels 10 in the 0th and 1st rows and the OB pixel 10OB via the switch SWa and the reset voltage line 31. That is, (i) the potentials of the charge storage units FD of the pixels 10 in the 0th and 1st rows and the OB pixel 10OB, and (ii) the potential of the reset voltage line 31 are reset to the reset voltage.

[0082] Next, at time t3, the switch control signal φRST goes low, turning off the switch SWa and rendering the reset voltage line 31 and the voltage supply circuit 46 non-conductive. The column circuit 43, which outputs a reset signal to the vertical signal line 35 when the potentials of the charge storage units FD of the pixels 10 in the 0th and 1st rows and the OB pixel 10OB are at the reset voltage, performs CDS using the pixel signal and the reset signal, and AD converts the signal after CDS. The switch control signal φRST may also go high when the reset signal is output. In this case, the switch control signal φRST goes low before time t4, which will be described later.

[0083] Next, at time t4, the reset signals RST0 and RST1 go low, turning off the reset transistors 22 of the pixels 10 in the 0th and 1st rows, and causing the charge storage units FD of the pixels 10 in the 0th and 1st rows to become non-conductive with the reset voltage line 31.

[0084] Furthermore, at time t4, the reset signals RST2 and RST3 go high. After time t4, the operations performed on the pixels 10 in the 0th row and the 1st row from time t1 to time t4 are repeated sequentially for every two rows of pixels 10. While the operations of the pixels 10 in the first five rows are shown in FIG. 3, the operations of the pixels 10 in the sixth row and beyond are similar. As a result, a low-resolution image is generated in which the signals of the two pixels 10 are combined.

[0085] In the example shown in FIG. 3 , the pixel signal is output from the OB pixel 10OB, but this is not limiting. The pixel signal may be output from the pixel 10 whose signals are to be combined. FIG. 4 is a timing chart illustrating another example of the operation of the imaging device 100 according to this embodiment. FIG. 4 shows a timing chart illustrating the operation when combining signals from two pixels 10. FIG. 4 also shows a timing chart illustrating the operation when reading out signals after exposure of the pixel 10 is completed. FIG. 4 illustrates the voltage levels of the switch control signal φRST, reset signals RST0 to RST5, and selection signals SEL0 to SEL5. In FIG. 4 , "H" indicates a high level, and "L" indicates a low level. In the following description of FIG. 4 , explanations of points common to the description of FIG. 3 may be omitted or simplified.

[0086] As shown in FIG. 4 , first, at time t1, the reset signals RST0 and RST1 go high. This turns on the reset transistors 22 of the pixels 10 in the 0th and 1st rows, thereby establishing electrical continuity between the charge storage units FD of the pixels 10 in the 0th and 1st rows and the reset voltage line 31. Also, at time t1, the switch control signal φRST is low, so the switch SWa is off and the reset voltage from the voltage supply circuit 46 is not supplied to the reset voltage line 31. Therefore, the signal charges stored in the charge storage units FD of the pixels 10 in the 0th and 1st rows are mixed by the reset voltage line 31. In other words, the signals of the pixels 10 in the 0th and 1st rows are combined by the reset voltage line 31.

[0087] Also, at time t1, the selection signal SEL0 goes high. This turns on the selection transistors 24 of the pixels 10 in the 0th row. This causes the combined signal to be output from the amplification transistors 23 of the pixels 10 in the 0th row to the vertical signal line 35. In this way, in the imaging device 100, under the control of the control circuit 48, with the switches SWa turned off, the reset transistors 22 of the pixels 10 in the 0th row and the 1st row are turned on, and then the pixels 10 in the 0th row output pixel signals corresponding to the signal charges accumulated in the charge accumulation units FD of the pixels 10 in the 0th row and the 1st row.

[0088] At time t1, the selection signal SEL1 may go high instead of or in addition to the selection signal SEL0. This causes a pixel signal to be output from the amplification transistor 23 of at least one of the pixels 10 in the 0th row and the 1st row to the vertical signal line 35. That is, at least one pixel 10 among the pixels 10 whose reset transistor 22 is turned on outputs a pixel signal to the vertical signal line 35.

[0089] Next, at time t2, the switch control signal φRST goes high, turning on the switch SWa, and the reset voltage is supplied from the voltage supply circuit 46 to the pixels 10 in the 0th and 1st rows via the switch SWa and the reset voltage line 31.

[0090] Next, at time t3, the switch control signal φRST goes low, turning off the switch SWa and causing the reset voltage line 31 and the voltage supply circuit 46 to become non-conductive. Then, the pixel 10 in the 0th row outputs a reset signal to the vertical signal line 35, corresponding to the case where the potentials of the charge storage units FD of the pixels 10 in the 0th and 1st rows are the reset voltage. As with the pixel signal, it is sufficient that at least one pixel 10 among the pixels 10 whose reset transistors 22 are turned on outputs a reset signal to the vertical signal line 35.

[0091] Next, at time t4, the reset signals RST0 and RST1 go low, turning off the reset transistors 22 of the pixels 10 in the 0th and 1st rows, and causing the charge storage units FD of the pixels 10 in the 0th and 1st rows to become non-conductive with the reset voltage line 31.

[0092] At time t4, the reset signals RST2 and RST3 and the selection signal SEL2 go high. After time t4, the operations performed on the pixels 10 in the 0th and 1st rows from time t1 to time t4 are repeated sequentially for every two rows of pixels 10. While the operations of the pixels 10 in the first to fifth rows are shown in FIG. 4, the operations of the pixels 10 in the sixth and subsequent rows are similar.

[0093] In the example shown in FIGS. 3 and 4 , the reset transistors 22 of two rows of pixels 10 are turned on simultaneously to combine the signals of the two pixels 10, but this is not limited thereto. The reset transistors 22 of three or more rows of pixels 10 may be turned on simultaneously to combine the signals of three or more pixels 10. Furthermore, the two or more pixels 10 whose signals are combined may have color filters CF of the same color. In the example shown in FIGS. 3 and 4 , the signals of two adjacent pixels 10 in the column direction are combined, but this is not limited thereto. The pixels 10 whose reset transistors 22 are turned on simultaneously do not have to be adjacent to each other, and may be sandwiched between rows of pixels 10 whose reset transistors 22 are not turned on. For example, the pixels 10 whose reset transistors 22 are turned on simultaneously may be two or more pixels 10 that are closest to each other among the pixels 10 in the same column and having color filters CF of the same color.

[0094] [Modification 1] Next, a description will be given of Modification 1 of Embodiment 1. The following description will focus on the differences from Embodiment 1, and the description of the commonalities will be omitted or simplified.

[0095] FIG. 5 is a schematic diagram illustrating an exemplary circuit configuration of an imaging device 110 according to this modification. For ease of viewing, FIG. 5 illustrates only the pixels 10A in row 0 and row 1 of column 0 among the pixels 10A arranged in rows 0 to n-1 and columns 0 to m-1. For columns other than column 0, the circuit configuration corresponding to column 0, excluding the voltage supply circuit 46, is repeated. In this modification, the pixel 10A in row 0 of column 0 is an example of a first pixel, and the pixel 10A in row 1 of column 0 is an example of a second pixel located in the same column as the first pixel. For ease of viewing, FIG. 5 illustrates only the wiring and circuits necessary for explanation, and the circuit configuration of the imaging device 110 may include wiring, circuits, and the like not illustrated in FIG. 5.

[0096] As shown in Figure 5, the imaging device 110 of this modified example differs from the imaging device 100 of embodiment 1 mainly in that it has pixel 10A and OB pixel 10AOB instead of pixel 10 and OB pixel 10OB.

[0097] The pixel 10A and the OB pixel 10AOB have a configuration in which they include a photoelectric conversion unit 13 instead of the photoelectric conversion unit 12 of the pixel 10 and the OB pixel 10OB, and further include a transfer transistor 25. That is, the pixel 10A and the OB pixel 10AOB each include a photoelectric conversion unit 13, a reset transistor 22, an amplification transistor 23, a selection transistor 24, a transfer transistor 25, and a charge storage unit FD. The pixel 10A and the OB pixel 10AOB have, for example, the same circuit configuration, and the OB pixel 10AOB has a light-shielding layer on the light incident side of the photoelectric conversion unit 13 that is not provided in the pixel 10A. Therefore, the OB pixel 10AOB is an ineffective pixel that does not generate signal charge even when receiving incident light. In a plan view, the OB pixel 10AOB is arranged in addition to a column of multiple pixels 10A. At least one OB pixel 10AOB is provided corresponding to each column of multiple pixels 10A. In this modification, the OB pixel 10AOB in the 0th column is an example of the third pixel.

[0098] The photoelectric conversion unit 13 is, for example, a photodiode formed on the semiconductor substrate 60. The photoelectric conversion unit 13 converts light into signal charges. The signal charges generated by the photoelectric conversion unit 13 are transferred to the charge accumulation unit FD by the transfer transistor 25.

[0099] In the pixel 10A, the charge storage unit FD is connected to the photoelectric conversion unit 13 via the transfer transistor 25 and stores the signal charge generated by the photoelectric conversion unit 13 .

[0100] The transfer transistor 25 is, for example, a FET formed on the semiconductor substrate 60. The transfer transistor 25 is, for example, an N-channel MOSFET.

[0101] One of the source and drain of the transfer transistor 25 is connected to the photoelectric conversion unit 13. The other of the source and drain of the transfer transistor 25 is connected to the charge storage unit FD. The gate of the transfer transistor 25 is connected to a transfer control signal line (not shown in FIG. 5 ) included in the row control line SL. A transfer signal TX is supplied to the gate of the transfer transistor 25 from the vertical scanning circuit 42 via the transfer control signal line. In FIG. 5 and the figures described below, a number ranging from 0 to n-1 (such as 0, 1, ...) affixed to the reference symbol of the transfer signal TX supplied to each pixel 10A indicates the row of the pixel 10A (only TX0 and TX1 are shown in FIG. 5 ). For example, the transfer signal TX0 indicates the transfer signal TX supplied to the pixel 10A in the 0th row. The transfer signal TXA indicates the transfer signal TX supplied to the OB pixel 10AOB. The transfer transistor 25 is turned on, for example, when the transfer signal TX is at a high level. When the transfer transistor 25 is turned on, signal charges are transferred from the photoelectric conversion unit 13 to the charge accumulation unit FD. When the transfer signal TX is at a low level, the transfer transistor 25 is turned off, thereby insulating the photoelectric conversion unit 13 from the charge accumulation unit FD.

[0102] Next, the operation (driving method) of the imaging device 110 according to this modification will be described. Below, a signal readout sequence will be described when combining signals from two or more pixels 10A to generate a low-resolution image. The circuits of the multiple pixels 10A and the OB pixels 10AOB corresponding to each column of the multiple pixels 10A are driven under the control of the control circuit 48.

[0103] FIG. 6 is a timing chart for explaining an example of the operation of the imaging device 110 according to this modified example. FIG. 6 shows a timing chart of the operation when combining signals from two pixels 10A. FIG. 6 also shows a timing chart of the signal readout after exposure of the pixel 10A is completed. FIG. 6 shows the voltage levels of the switch control signal φRST, the selection signals SELA and SEL0 to SELn-1, the reset signals RSTA and RST0 to RST5, and the transfer signals TX0 to TX5. In FIG. 6, "H" indicates a high level and "L" indicates a low level. Note that in the example of operation shown in FIG. 6, the timing charts of the voltage levels of the selection signals SEL0 to SELn-1 are the same, and therefore are shown together.

[0104] 6 , first, at time t1, the selection signal SELA and the reset signal RSTA go high. This turns on the reset transistor 22 of the OB pixel 10AOB, establishing electrical continuity between the charge storage unit FD of the OB pixel 10AOB and the reset voltage line 31. Furthermore, the selection transistor 24 of the OB pixel 10AOB turns on, causing a signal corresponding to the potential of the charge storage unit FD of the OB pixel 10AOB to be output from the amplification transistor 23 of the OB pixel 10AOB to the vertical signal line 35.

[0105] Also, at time t1, the reset signals RST0 and RST1 also go high. This turns on the reset transistors 22 of the pixels 10 in the 0th and 1st rows, thereby connecting the charge storage units FD of the pixels 10 in the 0th and 1st rows to the reset voltage line 31. Also, at time t1, the transfer signals TX0 and TX2 are low, so the transfer transistors 25 are off and signal charges from the photoelectric conversion unit 13 are not transferred to the charge storage unit FD. Note that, although not shown, during the operation shown in FIG. 6, the transfer signal TXA is, for example, always low, and the photoelectric conversion unit 13 and the charge storage unit FD are insulated from each other in the OB pixel 10AOB.

[0106] At time t1, the switch control signal φRST also goes high, turning on the switch SWa and supplying a reset voltage from the voltage supply circuit 46 to the pixels 10A in the 0th and 1st rows and the OB pixel 10AOB via the switch SWa and the reset voltage line 31. That is, (i) the potentials of the charge storage units FD of the pixels 10A in the 0th and 1st rows and the OB pixel 10AOB, and (ii) the potential of the reset voltage line 31 are reset to the reset voltage.

[0107] Next, at time t2, the switch control signal φRST goes low, turning off the switch SWa and preventing conduction between the reset voltage line 31 and the voltage supply circuit 46. Then, the OB pixel 10AOB outputs to the vertical signal line 35 a reset signal corresponding to the case where the potentials of the charge storage units FD of the pixels 10A in the 0th and 1st rows and the OB pixel 10AOB are at the reset voltage.

[0108] Next, at time t3, the transfer signals TX0 and TX1 go high. This turns on the transfer transistors 25 in the pixels 10A in the 0th and 1st rows, and the signal charges generated in the photoelectric conversion units 13 are transferred to the charge accumulation units FD. Then, at time t4, the transfer signals TX0 and TX1 go low, which turns off the transfer transistors 25 in the pixels 10A in the 0th and 1st rows, and the transfer of the signal charges ends.

[0109] Furthermore, because the reset transistors 22 of the pixels 10A in the 0th and 1st rows are turned on, the signal charges transferred to the charge storage units FD of the pixels 10A in the 0th and 1st rows are mixed by the reset voltage line 31. As a result, the signals of the pixels 10A in the 0th and 1st rows are combined and output from the amplification transistor 23 of the OB pixel 10AOB to the vertical signal line 35. In this way, in the imaging device 110, under the control of the control circuit 48, with the switch SWa in an off state, the reset transistors 22 of the pixels 10A in the 0th and 1st rows are turned on, and then the OB pixel 10AOB outputs a pixel signal corresponding to the signal charges accumulated in the charge storage units FD of the pixels 10A in the 0th and 1st rows. The column circuit 43 performs CDS using, for example, the pixel signal and the reset signal, and performs AD conversion on the signal after CDS.

[0110] Next, at time t5, the reset signals RST0 and RST1 go low, turning off the reset transistors 22 of the pixels 10A in the 0th and 1st rows, and causing the charge storage units FD of the pixels 10A in the 0th and 1st rows to become non-conductive with the reset voltage line 31.

[0111] At time t5, the switch control signal φRST and the reset signals RST2 and RST3 go high. After time t5, the operations performed on the pixels 10A in the 0th and 1st rows from time t1 to time t5 are repeated sequentially for every two rows of pixels 10A. While FIG. 6 shows the operations of the pixels 10A up to the 5th row, the operations of the pixels 10A in the 6th row and beyond are similar.

[0112] In the example shown in FIG. 6 , the reset transistors 22 of the pixels 10A in two rows are turned on simultaneously to combine the signals of the two pixels 10A, but this is not limited to this. The reset transistors 22 of the pixels 10A in three or more rows may be turned on simultaneously to combine the signals of three or more pixels 10A. Furthermore, the two or more pixels 10A whose signals are combined may have color filters CF of the same color. Furthermore, as in the example shown in FIG. 4 , a pixel signal may be output to the vertical signal line 35 from at least one pixel 10A among the pixels 10A whose reset transistors 22 are turned on.

[0113] [Modification 2] Next, a description will be given of Modification 2 of Embodiment 1. The following description will focus on the differences between Embodiment 1 and Modification 1 of Embodiment 1, and description of commonalities will be omitted or simplified.

[0114] FIG. 7 is a schematic diagram illustrating an exemplary circuit configuration of an imaging device 120 according to this modification. For clarity, FIG. 7 focuses on the connection between the pixels 10 and the voltage supply circuit 46, and omits the vertical signal line 35, current source 39, column circuit 43, and the like shown in FIG. 2 and other figures. FIG. 7 also omits the circuit configuration within the pixels 10. Of the pixels 10 arranged in rows 0 to n-1 and columns 0 to m-1, FIG. 7 illustrates the pixels 10 in rows 0 to 5 in columns 0 and 1. For columns other than columns 0 and 1, the circuit configuration corresponding to columns 0 and 1, excluding the voltage supply circuit 46, is repeated. In this modification, the pixel 10 in row 0 of column 0 is an example of a first pixel, and the pixel 10 in row 0 of column 1 is an example of a second pixel located in the same row as the first pixel.

[0115] 7 , the imaging device 120 according to this modification is different from the imaging device 100 according to the first embodiment mainly in that two adjacent columns of the pixels 10 are connected to one reset voltage line 31 via a reset voltage line 32. In this modification, the reset voltage line 31 is an example of a second wiring, and the reset voltage line 32 is an example of a first wiring.

[0116] 7, the imaging device 120 does not include the OB pixel 10OB, but may include the OB pixel 10OB. In this case, the OB pixel 10OB is connected to the reset voltage line 32 via the reset voltage line 31.

[0117] In the imaging device 120, one reset voltage line 31 is provided for every two columns of pixels 10. The reset voltage line 31 is connected to each of the pixels 10 in the corresponding two columns and is shared by each of the pixels 10 in the corresponding two columns. The reset voltage line 31 is also connected between a reset voltage line 32 and a switch SWa. The switch SWa is provided corresponding to the reset voltage line 31, and therefore, in the imaging device 120, one switch SWa is provided for every two columns of pixels 10.

[0118] The reset voltage line 32 extends in the row direction and is connected to pixels 10 located in the same row in two adjacent columns of pixels 10. Specifically, the reset voltage line 32 is connected to the other of the source and drain of the reset transistor 22 of the pixel 10. A reset voltage line 32 is provided for each row of pixels 10, for every two columns of pixels 10. In other words, each reset voltage line 32 is connected to two pixels 10 adjacent in the row direction. The rows of pixels 10 and the reset voltage lines 32 connected to one reset voltage line 31 have a one-to-one correspondence, for example.

[0119] The reset voltage line 32 may be connected to pixels 10 located in the same row in three or more columns of the pixels 10. In this case, the reset voltage line 31 and the switch SWa are also provided for each of three or more columns of the pixels 10. Furthermore, as long as the reset voltage line 32 is connected to two or more pixels 10 in the same row, two of the two or more pixels 10 do not need to be adjacent to each other.

[0120] In the imaging device 120, signal charges of pixels 10 connected to at least the same reset voltage line 32 are mixed by the reset voltage line 31. In the imaging device 120, a pixel signal obtained by mixing signal charges of two or more pixels 10 is output from the pixels 10 in at least one column among the pixels 10 in a column sharing the reset voltage line 31 to the vertical signal line 35 of the column corresponding to the pixel 10. Furthermore, a column control signal (enable signal) may determine the column circuit 43 from which the signal is read. This reduces the number of column circuits 43 to be driven and reduces power consumption. The column control signal is output from, for example, the control circuit 48. Furthermore, in mixing the signal charges of the pixels 10, as described with reference to FIGS. 3 and 4 , by controlling the driving of the pixels 10, signal charges of pixels 10 in two or more rows in the same column may be mixed by the reset voltage line 31 to combine the signals. Furthermore, the pixels 10 whose signals are combined may have color filters CF of the same color.

[0121] When signal charges from two or more pixels 10 are mixed using the reset voltage line 31, the capacitance Cvrst of the reset voltage line 31 also functions as a capacitance for storing signal charges, resulting in a decrease in the signal sensitivity of the charge storage unit FD compared to before the mixing. In other words, when signal charges from two or more pixels 10 are mixed using the reset voltage line 31, the sensitivity decreases. Here, assuming that the capacitance of the charge storage unit FD is Cfd and the number of pixels 10 whose signal charges are mixed is N, the sensitivity is roughly expressed as Cfd × N / (Cfd × N + Cvrst). In the imaging device 120, two pixels 10 in the same row are connected to one reset voltage line 31. Therefore, even when signal charges from pixels 10 in different columns are mixed, the number N of pixels 10 whose signal charges are mixed increases without an increase in capacitance Cvrst. Therefore, in the imaging device 120, a decrease in sensitivity can be suppressed even when signals from two or more pixels 10 in different columns are mixed.

[0122] [Modification 3] Next, a description will be given of Modification 3 of Embodiment 1. The following description will focus on the differences from Embodiment 1 and Modifications 1 and 2 of Embodiment 1, and description of commonalities will be omitted or simplified.

[0123] FIG. 8 is a schematic diagram illustrating an exemplary circuit configuration of an imaging device 130 according to this modification. For clarity, FIG. 8 focuses on the connection between the pixels 10 and the voltage supply circuit 46, and omits the vertical signal line 35, current source 39, column circuit 43, and the like shown in FIG. 2 and other figures. FIG. 8 also omits the circuit configuration within the pixels 10. Of the pixels 10 arranged in rows 0 to n-1 and columns 0 to m-1, FIG. 8 illustrates only the pixels 10 in rows 0 to 5 of the 0th column. For columns other than the 0th column, the circuit configuration corresponding to the 0th column, excluding the voltage supply circuit 46, is repeated. In this modification, the pixel 10 in row 0 of column 0 is an example of a first pixel, and the pixel 10 in row 1 of column 0 is an example of a second pixel located in the same column as the first pixel. In this modification, the pixels 10 in the second and third rows of the 0th column are examples of the third and fourth pixels located in the same columns as the first and second pixels, respectively.

[0124] 8 , the imaging device 130 according to this modification is different from the imaging device 100 according to embodiment 1 mainly in that the reset voltage line 31 corresponding to each column of the plurality of pixels 10 is divided into multiple lines. In this modification, the reset voltage line 31 connected to the pixels 10 in the 0th row and the 1st row of the 0th column is an example of a first wiring, and the reset voltage line 31 connected to the pixels 10 in the 2nd row and the 3rd row of the 0th column is an example of a second wiring. Note that the imaging device 130 may include a pixel 10A instead of the pixel 10.

[0125] In the imaging device 130, the reset voltage line 31 provided corresponding to each column of the pixels 10 is divided into multiple lines. That is, multiple reset voltage lines 31 are provided for each column of the pixels 10, aligned along the column direction. In the example shown in FIG. 8 , each reset voltage line 31 is connected to two pixels 10 adjacent to each other in the column direction. Each reset voltage line 31 may also be connected to three or more pixels 10 adjacent to each other in the column direction. Furthermore, in the imaging device 130, similar to the imaging device 120, the pixels 10 may be connected to the reset voltage line 31 via reset voltage lines 32 connecting the pixels 10 in the same row, so that the reset voltage line 31 is shared by the pixels 10 in two or more rows.

[0126] The switch SWa is provided corresponding to the reset voltage line 31, and therefore, in the imaging device 130, a plurality of switches SWa are provided for each column of a plurality of pixels 10. Each switch SWa is connected between the corresponding reset voltage line 31 and the voltage supply circuit 46. In the imaging device 130, the switch control signal φRST applied to each switch SWa does not need to be the same. For example, only the switch control signal φRST applied to the switch SWa corresponding to the row of pixels 10 selected for resetting may be at a high level. In this modification, the switch SWa connected between the reset voltage line 31 connected to the pixels 10 in the 0th row and the 1st row of the 0th column and the voltage supply circuit 46 is an example of a first switch. In addition, in this modification, the switch SWa connected between the reset voltage line 31 connected to the pixels 10 in the 2nd row and the 3rd row of the 0th column and the voltage supply circuit 46 is an example of a second switch.

[0127] In the imaging device 130, the signal charges of the pixels 10 connected to the same reset voltage line 31 are mixed by the reset voltage line 31. In the imaging device 130, when the signal charges of two or more pixels 10 are mixed, a pixel signal is output from at least one of the pixels 10 whose signal charges are mixed, as in the example described with reference to FIG. 4 , for example. The signal charges of all the pixels 10 connected to the same reset voltage line 31 may be mixed by the reset voltage line 31, or depending on the number of pixels 10 connected to the same reset voltage line 31, the signal charges of two or more pixels 10 may be mixed by the reset voltage line 31. Furthermore, the pixels 10 whose signals are mixed may have color filters CF of the same color.

[0128] As described in the second modification of the first embodiment, the sensitivity when signal charges of two or more pixels 10 are mixed in the reset voltage line 31 is roughly expressed as Cfd×N / (Cfd×N+Cvrst). In the imaging device 130, the reset voltage lines 31 provided corresponding to each column of the multiple pixels 10 are divided, so that the reset voltage lines 31 are shorter and the capacitance Cvrst of the reset voltage lines 31 is smaller. Therefore, in the imaging device 130, even when signals of two or more pixels 10 are combined, it is possible to suppress a decrease in sensitivity.

[0129] 8, the imaging device 130 includes a first substrate 61 and a second substrate 62 stacked on the first substrate 61. Each of the first substrate 61 and the second substrate 62 includes a semiconductor substrate and a wiring layer on the semiconductor substrate. The first substrate 61 and the second substrate 62 are connected by, for example, a Cu-Cu connection.

[0130] In the example shown in FIG. 8 , the voltage supply circuit 46 and multiple switches SWa are arranged on the first substrate 61. Furthermore, multiple pixels 10 and wiring connected to the multiple pixels 10, such as the reset voltage line 31, are arranged on the second substrate 62. In this way, the reset voltage line 31 and the voltage supply circuit 46 are arranged on separate substrates, making the wiring layout easier. The arrangement of each component in the imaging device 130 is not limited to the example shown in FIG. 8 . For example, the multiple switches SWa may be arranged on the second substrate 62. Furthermore, for example, some of the components in the pixels 10 may be arranged on the first substrate 61. Furthermore, the imaging device 130 may not include the second substrate 62, and all of the components may be arranged on the first substrate 61.

[0131] [Modification 4] Next, a description will be given of Modification 4 of Embodiment 1. The following description will focus on the differences from Embodiment 1 and Modifications 1 to 3 of Embodiment 1, and description of commonalities will be omitted or simplified.

[0132] FIG. 9 is a schematic diagram illustrating an exemplary circuit configuration of an imaging device 140 according to this modification. For clarity, FIG. 9 focuses on the connection between the pixels 10 and the voltage supply circuit 46, and omits the vertical signal line 35, current source 39, column circuit 43, and the like shown in FIG. 2 and other figures. FIG. 9 also omits the circuit configuration within the pixels 10. Of the pixels 10 arranged in rows 0 to n-1 and columns 0 to m-1, FIG. 9 illustrates the pixels 10 in rows 0 to 3 of columns 0 to 5. For columns other than columns 0 to 5, the circuit configuration corresponding to columns 0 to 5, excluding the voltage supply circuit 46, is repeated. In this modification, the pixel 10 in row 0 of column 0 is an example of a first pixel, and the pixel 10 in row 1 of column 0 is an example of a second pixel located in the same column as the first pixel. In addition, in this modified example, pixel 10 in row 0 of the first column is an example of a third pixel located in a different column from the first and second pixels, and pixel 10 in row 1 of the first column is an example of a fourth pixel located in the same column as the third pixel.

[0133] As shown in FIG. 9 , the imaging device 140 according to this modification is different from the imaging device 100 according to embodiment 1 mainly in that it further includes switches SWb and SWc connected between the pixels 10 in the 0th column and the reset voltage lines 31 corresponding to different columns. In this modification, the reset voltage line 31 connected to the pixels 10 in the 0th column is an example of a first wiring, and the reset voltage line 31 connected to the pixels 10 in the 1st column is an example of a second wiring. Note that the imaging device 140 may include a pixel 10A instead of the pixel 10. Furthermore, although the imaging device 140 does not include an OB pixel 10OB in the example shown in FIG. 9 , it may include an OB pixel 10OB.

[0134] Each of the switches SWb and SWc is connected between two reset voltage lines 31 corresponding to different columns of the pixels 10. In the example shown in Fig. 9, each of the switches SWb and SWc is connected between two reset voltage lines 31 corresponding to two adjacent columns. For example, each of the switches SWb and SWc is connected between the reset voltage line 31 connected to the pixels 10 in the 0th column and the reset voltage line 31 connected to the pixels 10 in the 1st column. Note that the columns of the pixels 10 corresponding to the two reset voltage lines 31 connected to the switches SWb and SWc do not have to be adjacent to each other.

[0135] The switches SWb and SWc are, for example, FETs formed on the semiconductor substrate 60, and their operations are controlled by mixed column control signals φMIXb and φMIXc applied to their gates. The mixed column control signals φMIXb and φMIXc are supplied from, for example, the control circuit 48. The switches SWb and SWc may be formed on a semiconductor substrate other than the semiconductor substrate 60, and the other semiconductor substrate may be stacked on the semiconductor substrate 60.

[0136] One switch SWb is provided for each pair of reset voltage lines 31 corresponding to different columns of pixels 10, to enable mutual conduction between the two reset voltage lines 31. In this modification, the switch SWb is an example of a second switch. The switch SWb is turned on when the mixed column control signal φMIXb is at a high level, thereby connecting the two corresponding reset voltage lines 31. This allows the signal charges of the pixels 10 in two different columns to be mixed by the reset voltage line 31. Furthermore, the switch SWb is turned off when the mixed column control signal φMIXb is at a low level, thereby insulating the two corresponding reset voltage lines 31. This makes it possible to control whether or not to mix the signals of the pixels 10 in two different columns. For example, the same mixed column control signal φMIXb is supplied to each switch SWb, and the same control is performed.

[0137] Two switches SWc are provided for each of three reset voltage lines 31 so that three reset voltage lines 31 corresponding to different columns of pixels 10 can be mutually connected. When the mixed column control signal φMIXc is at a high level, the switches SWc are turned on, connecting the corresponding three reset voltage lines 31 to each other. This allows the signal charges of the pixels 10 in three different columns to be mixed by the reset voltage lines 31. When the mixed column control signal φMIXc is at a low level, the switches SWc are turned off, insulating the corresponding three reset voltage lines 31. This makes it possible to control whether or not to mix the signals of the pixels 10 in three different columns. For example, the same mixed column control signal φMIXc is supplied to each switch SWc, and the same control is performed.

[0138] Furthermore, the imaging device 140 includes switches SWb and SWc with different numbers of reset voltage lines 31 that can be connected to each other. This allows the number of reset voltage lines 31 to be connected to each other to be switched, thereby adjusting the image resolution when combining signals from pixels 10. For example, during operation of the imaging device 140, only one of the switches SWb and SWc is controlled to be in an on state. In the imaging device 140, for example, when only one of the switches SWb and SWc is turned on, the same operation as that described with reference to FIG. 3 or 4 is performed. Furthermore, the pixels 10 whose signals are combined may have color filters CF of the same color. In the imaging device 140, a pixel signal obtained by combining signal charges from two or more pixels 10 is output, for example, from the pixels 10 in at least one column among the pixels 10 connected to two or more reset voltage lines 31 that are connected to each other to the vertical signal line 35 of the column corresponding to the pixel 10. Alternatively, a pixel signal may be output from an OB pixel 10OB in the column of the pixel 10 instead of the pixel 10. In the imaging device 140, the column circuit 43 from which the signal is read out may be determined by a column control signal (enable signal). This reduces the number of column circuits 43 to be driven, thereby reducing power consumption.

[0139] 9, the switch SWa is provided for each column of pixels 10 corresponding to the reset voltage line 31, but this is not limiting. For example, of the two reset voltage lines 31 connected to the switch SWb, the switch SWa provided corresponding to one of the reset voltage lines 31 may not be provided, and the position corresponding to the switch SWa may be non-conductive. Even in this case, it is possible to supply a reset voltage from the voltage supply circuit 46 to the one reset voltage line 31 via the other reset voltage line 31 and the switch SWb, for example.

[0140] In addition, the imaging device 140 may be provided with, in addition to the switches SWb and SWc, or instead of at least one of the switches SWb and SWc, a switch for enabling electrical connection between four or more reset voltage lines 31 corresponding to multiple columns of different pixels 10.

[0141] (Embodiment 2) Next, a description will be given of embodiment 2. In embodiment 2, a camera system including an imaging device according to the present disclosure will be described.

[0142] FIG. 10 is a block diagram showing an example of the configuration of a camera system 400 according to this embodiment.

[0143] 10, camera system 400 according to this embodiment includes lens optical system 601, imaging device 602, system controller 603, and camera signal processing circuit 604. Camera system 400 may be, for example, a smartphone, a digital camera, a video camera, or an in-vehicle camera.

[0144] The lens optical system 601 focuses light onto an imaging surface of the imaging device 602. The lens optical system 601 may include, for example, a lens group including an autofocus lens and a zoom lens, and an aperture. As the imaging device 602, for example, the imaging device according to any one of the above-described first embodiment and modifications 1 to 4 of the first embodiment may be used.

[0145] The system controller 603 controls the entire camera system 400. The system controller 603 is, for example, a semiconductor integrated circuit, and a specific example is a CPU (Central Processing Unit).

[0146] The camera signal processing circuit 604 has a function of processing an output signal from the image capture device 602. The camera signal processing circuit 604 receives output data from the image capture device 602 and performs processes such as gamma correction, color interpolation, spatial interpolation, and auto white balance. The camera signal processing circuit 604 is, for example, a DSP (Digital Signal Processor). The image capture device 602 and the camera signal processing circuit 604 may be implemented as a single semiconductor device. The semiconductor device may be, for example, a so-called SoC (System on a Chip). This configuration allows for further miniaturization of electronic devices that include the image capture device 602 as a part thereof.

[0147] In the camera system 400 according to the present embodiment, for example, the system controller 603 has two control modes for causing the imaging device 602 to capture an image: a control mode for causing the imaging device 602 to capture a normal image and a control mode for causing the imaging device 602 to capture a low-resolution image by combining signals from two or more pixels 10 or 10A. For example, when the system controller 603 is controlling the imaging device 602 in the control mode for capturing a low-resolution image, the system controller 603 determines whether to switch to the control mode for capturing a normal image based on the low-resolution image captured by the imaging device 602. This reduces the power consumption of the imaging device 602. For example, the system controller 603 switches to the control mode for capturing a normal image when the luminance value or change in luminance value in the low-resolution image is greater than or equal to a predetermined value. The system controller 603 may switch to the control mode for capturing a normal image when it detects movement of a subject in the low-resolution image.

[0148] While the imaging device and camera system according to the present disclosure have been described above based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the embodiments, as well as other forms constructed by combining some of the components of the embodiments, are also included within the scope of the present disclosure.

[0149] 3 and 6, the pixel that outputs the pixel signal may be a pixel other than the OB pixel 10OB or 10AOB, as long as it is an inactive pixel that does not generate signal charge in response to incident light. In the example of the operation shown in Fig. 3 and 6, the pixel that outputs the pixel signal may be, for example, a pixel in which the photoelectric conversion unit 12 or 13 is insulated from the charge storage unit FD, or a pixel that does not include the photoelectric conversion unit 12 or 13.

[0150] In the above-described embodiment, the processing performed by a specific processing unit may be performed by another processing unit. The order of multiple processing operations may be changed, or multiple processing operations may be performed in parallel.

[0151] In the above-described embodiments, each component may be realized by executing a software program suitable for that component, or by a program execution unit such as a CPU or processor reading and executing a software program recorded on a recording medium such as a hard disk or semiconductor memory.

[0152] Furthermore, each component may be realized by hardware. Each component may be a circuit (or integrated circuit). These circuits may form a single circuit as a whole, or each may be a separate circuit. Furthermore, each of these circuits may be a general-purpose circuit or a dedicated circuit.

[0153] Furthermore, the general or specific aspects of the present disclosure may be realized as a system, an apparatus, a method, an integrated circuit, a computer program, or a computer-readable recording medium such as a CD-ROM, or as any combination of a system, an apparatus, a method, an integrated circuit, a computer program, and a recording medium.

[0154] For example, the present disclosure may be realized as an imaging device according to the above-described embodiment, as a control device that controls an imaging device, as a program for causing a computer to execute a method for driving an imaging device performed by a processing unit such as a control circuit, or as a computer-readable non-transitory recording medium on which such a program is recorded.

[0155] Furthermore, the above-described embodiments can be modified, substituted, added, omitted, and the like in various ways within the scope of the claims or their equivalents.

[0156] The imaging device according to the present disclosure is useful, for example, in image sensors, digital cameras, etc. The imaging device according to the present disclosure can be used in medical cameras, robot cameras, security cameras, cameras mounted on vehicles, etc.

[0157] 10, 10A Pixel 10OB, 10AOB OB pixel 12, 13 Photoelectric conversion unit 12a Pixel electrode 12b Photoelectric conversion layer 12c Counter electrode 22 Reset transistor 23 Amplifying transistor 24 Select transistor 31, 32 Reset voltage line 35 Vertical signal line 39 Current source 40 Peripheral circuit 42 Vertical scanning circuit 43 Column circuit 44 Horizontal signal readout circuit 46 Voltage supply circuit 48 Control circuit 60 Semiconductor substrate 61 First substrate 62 Second substrate 100, 110, 120, 130, 140, 602 Imaging device 400 Camera system 601 Lens optical system 603 System controller 604 Camera signal processing circuit CF Color filter SL Row control line SWa, SWb, SWc Switch

Claims

1. An imaging device comprising: a plurality of pixels arranged in a row direction and a column direction; a first wiring that directly connects a first pixel and a second pixel located in the same row among the plurality of pixels; a voltage supply circuit that supplies a reset voltage to the first pixel and the second pixel via the first wiring; and a first switch connected between the first wiring and the voltage supply circuit.

2. The imaging device according to claim 1, further comprising a second wiring connected between the first wiring and the first switch and extending in a column direction.

3. The imaging device according to claim 2, wherein the plurality of pixels includes a third pixel located in the same column as the first pixel, and the third pixel is connected to the second wiring.

4. Each of the plurality of pixels includes: a photoelectric conversion unit that converts light into signal charges; a charge storage unit that stores the signal charges; and a transistor having one of a source and a drain connected to the charge storage unit. The first wiring is connected to the other of the source and the drain of the transistor of the first pixel and the other of the source and the drain of the transistor of the second pixel. The imaging device according to any one of claims 1 to 3.

5. After each transistor of the first pixel and the second pixel is turned on in a state where the first switch is off, the first pixel outputs a pixel signal corresponding to the potential of the charge storage unit. The imaging device according to claim 4.

6. The imaging device according to claim 4, further comprising an invalid pixel that does not generate signal charges upon incidence of light. The invalid pixel includes a charge storage unit electrically connected to the first wiring. After each transistor of the first pixel and the second pixel is turned on in a state where the first switch is off, the invalid pixel outputs a pixel signal corresponding to the potential of the charge storage unit.

7. The imaging device according to claim 1, wherein the first pixel and the second pixel have color filters of the same color.

8. A camera system comprising the imaging device according to any one of claims 1 to 7.

9. A first pixel and a second pixel, an invalid pixel that does not generate signal charges by the incidence of light, a first wiring connected to the first pixel, the second pixel, and the invalid pixel, a voltage supply circuit that supplies a reset voltage to the first pixel and the second pixel via the first wiring, and a first switch connected between the first wiring and the voltage supply circuit. An imaging device comprising:

10. Each of the first pixel, the second pixel, and the invalid pixel includes a charge storage unit that stores charges and a transistor having one of a source and a drain connected to the charge storage unit. The first wiring is connected to the other of the source and the drain of the transistor of the first pixel, the other of the source and the drain of the transistor of the second pixel, and the other of the source and the drain of the transistor of the invalid pixel. The imaging device according to claim 9.

11. After each of the transistors of the first pixel, the second pixel, and the invalid pixel is turned on in a state where the first switch is off, the invalid pixel outputs a pixel signal corresponding to the potential of the charge storage unit. The imaging device according to claim 4.

Images