Semiconductor device and method for manufacturing semiconductor device

Abstract

[Problem] To further improve yield when a semiconductor chip is mounted on a wiring board. [Solution] A semiconductor device according to the present comprises: a wiring board having a bump electrode on a main surface; a semiconductor chip provided on the main surface of the wiring board and having, on a first surface facing the main surface of the wiring board, a first electrode electrically connected to the bump electrode; a wall part protruding from the main surface of the wiring board and provided so as to surround the entire periphery of the semiconductor chip; a buffer material layer filled between the semiconductor chip and the wall part and extending up to a side surface of the semiconductor chip; and an electrode wiring electrically connected to a second electrode provided on a second surface, of the semiconductor chip, on a side opposite the first surface.

Description

Semiconductor device and method for manufacturing the same

[0001] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

[0002] In recent years, in order to improve the yield of semiconductor devices, studies have been made on suppressing misalignment of semiconductor chips when mounting the semiconductor chips on a wiring substrate. For example, in a micro LED display device in which a plurality of light-emitting diode (LED) chips are arranged on a wiring substrate as pixels, studies have been made on suppressing misalignment of the LED chips when they are mounted in order to suppress poor connections between the electrodes of the LED chips and the electrodes of the wiring substrate.

[0003] Such misalignment of the semiconductor chip is thought to occur when a relative sliding or rotational misalignment occurs between the semiconductor chip and the wiring board when the semiconductor chip is mounted on the wiring board.

[0004] Japanese Patent Application Laid-Open No. 2006-129998 discloses mounting an electronic component having an electrode portion with a recessed portion on its surface on a wiring board having a protruding bump electrode such that the recessed portion of the electrode portion and the bump electrode are face-to-face bonded. The technology disclosed in Japanese Patent Application Laid-Open No. 2006-129998 can suppress sliding or rotational misalignment between the electronic component and the wiring board by fitting the electrode portion with a recessed portion provided on the electronic component and the protruding bump electrode provided on the wiring board.

[0005] Japanese Patent Application Laid-Open No. 2021-19037

[0006] However, with the technology disclosed in Patent Document 1, if the pressing position itself is misaligned when mounting the semiconductor chip on the wiring board, it is difficult to correct the misalignment. Therefore, the technology disclosed in Patent Document 1 has only a limited effect on improving the yield when mounting semiconductor devices.

[0007] Therefore, the present invention has been made in consideration of the above problems, and an object of the present invention is to provide a new and improved semiconductor device and a method for manufacturing the semiconductor device that can further improve the yield when mounting semiconductor chips on a wiring board.

[0008] In order to solve the above problem, according to one aspect of the present invention, there is provided a semiconductor device comprising: a wiring board having a bump electrode on a main surface; a semiconductor chip provided on the main surface of the wiring board, the semiconductor chip having a first electrode electrically connected to the bump electrode on a first surface opposite the main surface of the wiring board; a wall portion protruding from the main surface of the wiring board and provided so as to surround the entire periphery of the semiconductor chip; a buffer material layer filled between the semiconductor chip and the wall portion and extending to a side surface of the semiconductor chip; and electrode wiring electrically connected to a second electrode provided on a second surface of the semiconductor chip opposite the first surface.

[0009] In addition, in order to solve the above-mentioned problem, according to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, including the steps of: preparing a wiring substrate having, on its main surface, a bump electrode and a wall portion surrounding the entire periphery of the area in which the bump electrode is provided; filling the area surrounded by the wall portion with adhesive to form a buffer layer; pressing the semiconductor chip into the buffer layer so that a first electrode provided on a first surface of the semiconductor chip faces the bump electrode; extending the buffer layer pressed out by pressing the semiconductor chip onto a side surface of the semiconductor chip; and forming electrode wiring electrically connected to a second electrode provided on a second surface opposite the first surface of the semiconductor chip.

[0010] As described above, according to the present invention, it is possible to further improve the yield when mounting semiconductor chips on wiring boards.

[0011] FIG. 1 is a longitudinal sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a longitudinal sectional view showing a process for manufacturing a semiconductor device according to the same embodiment. FIG. 3 is a longitudinal sectional view showing a process for manufacturing a semiconductor device according to the same embodiment. FIG. 4 is a longitudinal sectional view showing a process for manufacturing a semiconductor device according to the same embodiment. FIG. 5 is a longitudinal sectional view showing a process for manufacturing a semiconductor device according to the same embodiment. FIG. 6 is a longitudinal sectional view showing a process for manufacturing a semiconductor device according to a first modified example. FIG. 7 is a longitudinal sectional view showing a process for manufacturing a semiconductor device according to the first modified example. FIG. 8 is a longitudinal sectional view showing a process for manufacturing a semiconductor device according to the first modified example. FIG. 9 is a longitudinal sectional view showing a process for manufacturing a semiconductor device according to the second modified example. FIG. 10 is a perspective view showing a configuration of a semiconductor device according to a second embodiment of the present invention. FIG. 11 is a longitudinal sectional view showing a configuration of a semiconductor device according to the same embodiment. FIG. 12 is a top view showing a configuration of a semiconductor device according to the same embodiment.

[0012] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant explanations will be omitted.

[0013] 1. First Embodiment <<1.1. Configuration Example>> First, a configuration example of a semiconductor device according to a first embodiment of the present invention will be described with reference to Fig. 1. Fig. 1 is a vertical cross-sectional view showing the configuration of a semiconductor device 1 according to this embodiment.

[0014] 1, the semiconductor device 1 includes, for example, a wiring substrate 100, a semiconductor chip 110, a wall portion 120, a buffer material layer 130, and a bump electrode 140. The semiconductor device 1 may be a micro LED display device.

[0015] The wiring substrate 100 is a substrate provided with wiring (not shown) that electrically connects to each of the semiconductor chips 110 to be mounted. The wiring substrate 100 may be, for example, a glass substrate, a glass epoxy substrate, an epoxy substrate, a polyimide substrate, or a (meth)acrylic substrate, or may be a flexible substrate made of polyester, polyethersulfone, or the like. The wiring substrate 100 may be, for example, a pixel array substrate of a micro LED display device.

[0016] The bump electrodes 140 are provided in a convex shape on the main surface of the wiring substrate 100, and are electrodes that electrically connect the wiring (not shown) on the main surface of the wiring substrate 100 to the semiconductor chip 110. A bump electrode 140 is provided for each semiconductor chip 110 that is mounted on the wiring substrate 100. The shape of the bump electrodes 140 may be a convex shape such as a truncated cone shape, a column shape, a hemisphere shape, or a flattened sphere shape.

[0017] 1, the bump electrode 140 may be a resin core electrode in which the surface of a resin core 141 made of organic resin is covered with a metal film 142. However, the structure of the bump electrode 140 is not limited to the above. The bump electrode 140 may be made of a single metal or multiple metals, and may be, for example, a metal electrode formed by plating or vapor deposition, a solder paste, or a solder ball.

[0018] An adhesive layer using a metal such as titanium, copper, molybdenum, palladium, or nickel as a base metal may be provided between the resin core 141 and the metal film 142. The adhesive layer can physically bond the resin core 141 and the metal film 142 together.

[0019] The semiconductor chip 110 is an electronic component made of a semiconductor. The semiconductor chip 110 is mounted on the main surface of the wiring substrate 100 via bump electrodes 140. The semiconductor chip 110 may be made of silicon, a single element, or a compound semiconductor such as gallium nitride, gallium arsenide, or silicon carbide. The semiconductor chip 110 may also be formed by stacking layers made of the above semiconductors on a non-semiconductor substrate such as a sapphire substrate, a glass substrate, or a quartz substrate. The semiconductor chip 110 may be an integrated circuit (IC) chip having a computing function or an LED chip having a light-emitting function. For example, the semiconductor chip 110 may be an LED chip that functions as a pixel of a micro LED display device or a control IC chip of the micro LED display device.

[0020] Chip electrodes 111 are provided on the surface of the semiconductor chip 110 facing the main surface of the wiring substrate 100 (i.e., the bottom surface). The chip electrodes 111 are electrodes that electrically connect the semiconductor chip 110 to the wiring of the wiring substrate 100. The chip electrodes 111 are electrically connected to the bump electrodes 140, thereby electrically connecting the semiconductor chip 110 to the wiring of the wiring substrate 100. The chip electrodes 111 may be made of a metal such as gold, silver, copper, or aluminum.

[0021] The wall portion 120 is provided to protrude from the main surface of the wiring substrate 100 so as to surround the entire periphery of the semiconductor chip 110. The wall portion 120 is provided to hold the buffer material layer 130, which physically bonds the semiconductor chip 110 and the wiring substrate 100, around the periphery of the semiconductor chip 110. The wall portion 120 may be made of, for example, a patterned organic resin.

[0022] The wall portion 120 may be provided higher than the bump electrode 140 electrically connected to the chip electrode 111. In this way, the wall portion 120 can hold the buffer material layer 130 up to the height of the side surface of the semiconductor chip 110. Furthermore, the wall portion 120 may be provided lower than the height of the top surface of the semiconductor chip 110 mounted on the wiring substrate 100 to avoid interference with other components.

[0023] The buffer material layer 130 is formed by filling a buffer material in the area surrounded by the wall portion 120. Specifically, the buffer material layer 130 may be formed of an adhesive buffer material and may physically bond the semiconductor chip 110 and the wiring substrate 100 together. For example, the buffer material layer 130 may physically bond the semiconductor chip 110 and the wiring substrate 100 together by filling the space surrounded by the semiconductor chip 110, the wiring substrate 100, and the wall portion 120. Furthermore, if the buffer material layer 130 extends to the side surfaces of the semiconductor chip 110, the buffer material layer 130 can bond the semiconductor chip 110 and the wiring substrate 100 over a wider area, thereby further increasing the adhesive strength between the semiconductor chip 110 and the wiring substrate 100.

[0024] The buffer layer 130 may be configured to include, for example, a thermosetting adhesive as a buffer material. In such a case, the buffer layer 130 can be irreversibly cured by heat, thereby more firmly bonding the semiconductor chip 110 and the wiring substrate 100. For example, the buffer layer 130 may be configured to include a phenol-based adhesive, an epoxy-based adhesive, or an acrylic-based adhesive.

[0025] The buffer material constituting the buffer material layer 130 does not have to have adhesive properties. For example, the buffer material constituting the buffer material layer 130 may be a fluid substance such as solder flux. In such a case, the semiconductor device 1 may, as one example, bond the semiconductor chip 110 and the wiring substrate 100 by bonding the chip electrodes 111 to the bump electrodes 140. As another example, the semiconductor device 1 may bond the semiconductor chip 110 and the wiring substrate 100 by bonding the metals of the chip electrodes 111 to the above-mentioned adhesive layer instead of the bump electrodes 140.

[0026] According to the above configuration, the semiconductor device 1 can further increase the adhesive strength between the semiconductor chip 110 and the wiring substrate 100, thereby further increasing the yield when mounting the semiconductor chip 110. In particular, the semiconductor device 1 can bond the underside and side surfaces of the semiconductor chip 110 facing in different directions with the buffer layer 130, so it can exert a strong adhesive strength against external forces from various directions.

[0027] 2A to 2D, a method for manufacturing the semiconductor device 1 according to this embodiment will be described. 2A to 2D are vertical cross-sectional views showing the steps for manufacturing the semiconductor device 1 according to this embodiment.

[0028] 2A , first, a wiring substrate 100 is prepared, the main surface of which is provided with a bump electrode 140, a wall portion 120, and a buffer material layer 130. Specifically, first, an organic resin layer formed on the main surface of the wiring substrate 100 is patterned using photolithography to form a resin core 141 that becomes the core of the bump electrode 140 and a wall portion 120 that surrounds the entire periphery of the area including the resin core 141.

[0029] The wall portion 120 may be provided so as to be symmetrical with respect to the center line of the semiconductor chip 110 mounted on the bump electrode 140. Specifically, the wall portion 120 may be provided at a position where the distance between the semiconductor chip 110 mounted on the bump electrode 140 and the wall portion 120 is the same on both opposing sides. This is because, when the semiconductor chip 110 is mounted in a subsequent stage, the buffer material layer 130 pushed out by the semiconductor chip 110 applies a force to the semiconductor chip 110 so as to equalize the distance between the wall portion 120 on both sides and the semiconductor chip 110. In this way, the wall portion 120 can self-align the position of the semiconductor chip 110 to a position where the distance from the wall portion 120 on both sides is the same.

[0030] The bump electrode 140, which is made up of the resin core 141 and the metal film 142, can be more stably connected to the chip electrode 111 by being crushed by the chip electrode 111 when the semiconductor chip 110 is mounted in the subsequent stage. In such a case, the resin core 141 may be formed at the same time as the wall portion 120 and at approximately the same height as the wall portion 120 when the organic resin layer is patterned.

[0031] Next, a metal film 142 is formed on the surface of the resin core 141 to form the bump electrode 140. Furthermore, a thermosetting adhesive is filled into the area surrounded by the wall portion 120 to form the buffer material layer 130. The buffer material layer 130 may be provided at a height approximately the same as that of the wall portion 120, for example, so that the buffer material layer 130 pushed out when the semiconductor chip 110 is mounted in the subsequent stage rises up along the side surface of the semiconductor chip 110.

[0032] 2B , alignment is performed between the semiconductor chip 110 and the wiring substrate 100. Specifically, alignment of the semiconductor chip 110 with respect to the wiring substrate 100 is performed so that the chip electrodes 111 of the semiconductor chip 110 and the bump electrodes 140 of the wiring substrate 100 face each other.

[0033] 2C, the semiconductor chip 110 is pressed into the buffer material layer 130. At this time, the wall portion 120 can further function as a stopper that prevents the pressed-in semiconductor chip 110 from shifting sideways.

[0034] As a result, the resin core 141 of the bump electrode 140 is crushed by the chip electrode 111, and the metal film 142 is electrically connected to the chip electrode 111. In addition, the buffer material layer 130 is extruded by the semiconductor chip 110, and the extruded buffer material layer 130 rises up along the side surface of the semiconductor chip 110.

[0035] The extruded buffer material layer 130 applies pressure to the semiconductor chip 110 according to the distance between the wall portion 120 and the semiconductor chip 110. Specifically, the smaller the distance between the wall portion 120 and the semiconductor chip 110, the narrower the space through which the buffer material layer 130 is extruded. Therefore, the smaller the distance between the wall portion 120 and the semiconductor chip 110, the higher the pressure at which the buffer material layer 130 is extruded, and the extruded pressure is applied to the semiconductor chip 110. Therefore, as pressure from the buffer material layer 130 acts on both sides of the semiconductor chip 110, a force corresponding to the pressure difference from both sides is applied to the semiconductor chip 110. In other words, a force is applied to the semiconductor chip 110 so that the distance between the wall portion 120 and the semiconductor chip 110 is equal on both sides. As a result, the semiconductor chip 110 is self-aligned to a position where the distance from the wall portion 120 on both sides is equal.

[0036] For example, in FIG. 2C , the semiconductor chip 110 is mounted offset to the left of the center line between the wall portions 120 on both sides when viewed from the front of the figure. Therefore, the extruded buffer layer 130 applies a higher pressure to the semiconductor chip 110 from the left side than from the right side. As a result, the semiconductor chip 110 moves to the right side due to the applied pressure until the left and right pressures are balanced. This causes the semiconductor chip 110 to self-align to a position where it is equidistant from the wall portions 120 on both sides.

[0037] 2D , after the semiconductor chip 110 is sufficiently pressed into the wiring substrate 100, the buffer material layer 130 is heated and hardened, thereby bonding the semiconductor chip 110 to the wiring substrate 100. In this way, the semiconductor chip 110 is mounted on the wiring substrate 100, and the semiconductor device 1 is formed.

[0038] According to the above manufacturing method, the semiconductor device 1 can mount the semiconductor chip 110 on the wiring substrate 100 by self-alignment based on the position of the wall portion 120. Because the wall portion 120 is patterned with high precision by photolithography, the semiconductor device 1 can mount the semiconductor chip 110 on the wiring substrate 100 with higher positional precision.

[0039] <<1.3. Modifications>> (1.3.1. First Modification) Next, a first modification of the present embodiment will be described with reference to Figures 3A to 3C. Figures 3A to 3C are vertical cross-sectional views showing steps in manufacturing the semiconductor device 1 according to the first modification.

[0040] In the first modification, an opening 130H is formed in the buffer material layer 130. In this case, the pushing resistance of the semiconductor chip 110 to the buffer material layer 130 changes before and after the buffer material layer 130, which has flowed due to the pushing of the semiconductor chip 110, fills the opening 130H. In the first modification, this change in the pushing resistance of the semiconductor chip 110 can be used to determine the end point of the pushing of the semiconductor chip 110.

[0041] The semiconductor chip 110 may be, for example, a control IC chip having a relatively large area of ​​100 μm square. When a semiconductor chip 110 having a relatively large area is mounted on the wiring substrate 100, the buffer material layer 130 near the center of the semiconductor chip 110 is less likely to flow, making it difficult for the semiconductor chip 110 to be pressed into the buffer material layer 130. Therefore, in the first modification, by forming an opening 130H through which the buffer material layer 130 can easily flow, the semiconductor chip 110 can be more easily pressed into the buffer material layer 130. Furthermore, after the buffer material layer 130 flows into the opening 130H and fills the opening 130H, the resistance when pressing the semiconductor chip 110 into the buffer material layer 130 becomes higher. Therefore, in the first modification, the end point of pressing the semiconductor chip 110 into the buffer material layer 130 can be determined by using the change in the pressing resistance of the semiconductor chip 110 against the buffer material layer 130.

[0042] Specifically, first, as shown in FIG. 3A, a wiring substrate 100 is prepared, which has a bump electrode 140, a wall portion 120, and a buffer material layer 130 provided on its main surface.

[0043] An opening 130H is further formed in the buffer material layer 130 provided on the wiring substrate 100 by patterning using photolithography. The opening 130H may be provided in a position of the buffer material layer 130 corresponding to the outer edge of the semiconductor chip 110. In such a case, the opening 130H is provided so as to extend to an area that is not pressed into the semiconductor chip 110, thereby making it possible to easily form an escape route for the air in the opening 130H to escape when the buffer material layer 130 flows.

[0044] 3B , the semiconductor chip 110 is pressed into the buffer layer 130. As a result, the resin core 141 of the bump electrode 140 is crushed by the chip electrode 111, and the metal film 142 is electrically connected to the chip electrode 111. The buffer layer 130 pressed into the semiconductor chip 110 flows into the opening 130H. At this time, the pressed buffer layer 130 flows in the in-plane direction of the wiring substrate 100, so the pressing resistance of the semiconductor chip 110 into the buffer layer 130 is relatively low.

[0045] 3C , when the semiconductor chip 110 is further pressed into the buffer material layer 130, the pressed buffer material layer 130 fills the opening 130H, then rises from between the wall portion 120 and the semiconductor chip 110, and rises along the side of the semiconductor chip 110. At this time, the pressed buffer material layer 130 flows from the space between the wall portion 120 and the semiconductor chip 110 toward the top of the wiring substrate 100, so the pressing resistance of the semiconductor chip 110 against the buffer material layer 130 becomes higher. Therefore, by detecting the change in the pressing resistance of the semiconductor chip 110 against the buffer material layer 130, the end point of the pressing of the semiconductor chip 110 against the buffer material layer 130 can be determined.

[0046] Furthermore, a bonding surface 131 where different layers are bonded together is formed at the location where the opening 130H is filled with the buffer material layer 130. Specifically, the bonding surface 131 is a surface where the buffer material layers 130 on both sides of the opening 130H are bonded together when the opening 130H is filled. The bonded buffer material layers 130 do not mix with each other, and are therefore observed as a bonding surface where different layers are bonded together.

[0047] As described above, in the first modification, by providing the opening 130H in the buffer material layer 130, the change in resistance when the semiconductor chip 110 is pressed into the buffer material layer 130 can be used to determine the end point of the pressing. Therefore, according to the first modification, it is possible to prevent the semiconductor chip 110 from being pressed excessively into the buffer material layer 130, thereby suppressing the occurrence of defects. Therefore, the semiconductor device 1 according to the first modification can improve yield.

[0048] (1.3.2. Second Modification) A second modification of the present embodiment will be described with reference to Figures 4A and 4B, which are vertical cross-sectional views showing steps in manufacturing a semiconductor device 1 according to the second modification.

[0049] In the second modification, a flat jig 200 is used to press the semiconductor chip 110. In this case, the buffer material layer 130 that flows when the semiconductor chip 110 is pressed flows from between the wall portion 120 and the semiconductor chip 110 to between the wall portion 120 and the jig 200. In the second modification, the change in the pressing resistance of the semiconductor chip 110 due to the space into which the buffer material layer 130 has flowed can be used to determine the end point of pressing the semiconductor chip 110.

[0050] The semiconductor chip 110 may be, for example, an LED chip with a relatively small area of ​​10 μm square. When a semiconductor chip 110 with a relatively small area is mounted on the wiring substrate 100, a pressing jig 200 larger than the semiconductor chip 110 is used to press the semiconductor chip 110 more uniformly. Therefore, in the second modification, the buffer material layer 130 pushed out by the semiconductor chip 110 flows into the space between the wall 120 and the semiconductor chip 110 and the space between the wall 120 and the jig 200. At this time, the space between the wall 120 and the jig 200 is narrower than the space between the wall 120 and the semiconductor chip 110, resulting in higher resistance when the semiconductor chip 110 is pressed into the buffer material layer 130. Therefore, in the second modification, the end point of pressing the semiconductor chip 110 into the buffer material layer 130 can be determined by using the change in the pressing resistance of the semiconductor chip 110 against the buffer material layer 130.

[0051] 4A, a wiring substrate 100 is first prepared, the main surface of which is provided with bump electrodes 140, wall portions 120, and a buffer layer 130. The semiconductor chip 110 may be attached to a rigid jig 200, for example, and pressed into the buffer layer 130 together with the jig 200. The jig 200 may be, for example, a sapphire substrate having a flat plate shape that is larger than the semiconductor chip 110.

[0052] 4B , the semiconductor chip 110 is pressed into the buffer layer 130. As a result, the resin core 141 of the bump electrode 140 is crushed by the chip electrode 111, and the metal film 142 is electrically connected to the chip electrode 111. The buffer layer 130 is also pushed out by the semiconductor chip 110, and the pushed-out buffer layer 130 rises up along the side surface of the semiconductor chip 110. At this time, the flowing buffer layer 130 flows into the space between the wall portion 120 and the semiconductor chip 110, which is relatively wide apart, so that the pressing resistance of the semiconductor chip 110 into the buffer layer 130 is relatively low.

[0053] When the semiconductor chip 110 is pressed further into the buffer material layer 130, the pressed buffer material layer 130 flows from the side surface of the semiconductor chip 110 into the space between the wall portion 120 and the jig 200. At this time, the flowed buffer material layer 130 flows into the space between the wall portion 120 and the jig 200, which is narrower than the space between the wall portion 120 and the semiconductor chip 110, and therefore the pressing resistance of the semiconductor chip 110 into the buffer material layer 130 becomes higher. Therefore, by detecting the change in the pressing resistance of the semiconductor chip 110 into the buffer material layer 130, the end point of pressing the semiconductor chip 110 into the buffer material layer 130 can be determined.

[0054] After the mounting of the semiconductor chip 110 on the wiring substrate 100 is completed, the jig 200 is removed from the semiconductor chip 110. At this time, the upper surface of the semiconductor chip 110 and the upper surface of the buffer material layer 130 that has flowed up to the top of the wall portion 120 are in contact with the lower surface of the jig 200 and therefore are flush with each other.

[0055] As described above, in the second modification, by using the jig 200 when pressing the semiconductor chip 110 into the buffer material layer 130, the change in resistance when pressing the semiconductor chip 110 into the buffer material layer 130 can be used to determine the end point of pressing. Therefore, according to the second modification, it is possible to prevent the semiconductor chip 110 from being pressed excessively into the buffer material layer 130, thereby suppressing the occurrence of defects. Therefore, the semiconductor device 1 according to the second modification can improve yield.

[0056] 2. Second Embodiment A configuration example of a semiconductor device according to a second embodiment of the present invention will be described with reference to Fig. 5 to Fig. 7. Fig. 5 is a perspective view showing the configuration of a semiconductor device 2 according to the second embodiment of the present invention. Fig. 6 is a vertical cross-sectional view showing the configuration of the semiconductor device 2 according to this embodiment. Fig. 7 is a top view showing the configuration of the semiconductor device 2 according to this embodiment.

[0057] As shown in FIGS. 5 to 7, the semiconductor device 2 includes a wiring substrate 100, a semiconductor chip 110, a wall portion 120, a buffer material layer 130, bump electrodes 140, and electrode wiring 150.

[0058] The wiring substrate 100 is a substrate provided with wiring (not shown) that is electrically connected to a semiconductor chip 110 mounted on the wiring substrate 100. The wiring substrate 100 may be, for example, a pixel array substrate of a micro LED display device.

[0059] The bump electrode 140 is provided in a convex shape on the main surface of the wiring substrate 100 and is an electrode that electrically connects the wiring (not shown) on the main surface of the wiring substrate 100 to the semiconductor chip 110. The bump electrode 140 may have a convex shape such as a truncated cone shape, a column shape, a hemisphere shape, or a flattened sphere shape. The bump electrode 140 may be a resin core electrode in which the surface of a resin core is covered with a metal film, or may be a metal electrode, a solder paste, or a solder ball.

[0060] The semiconductor chip 110 is an electronic component made of a semiconductor. The semiconductor chip 110 is mounted on the main surface of the wiring substrate 100 via bump electrodes 140. The semiconductor chip 110 may be an LED chip made of a compound semiconductor such as gallium nitride, gallium arsenide, or silicon carbide.

[0061] A first electrode 112A is provided on a first surface S1 (i.e., the bottom surface) of the semiconductor chip 110, which faces the main surface of the wiring substrate 100. The first electrode 112A is an anode of the semiconductor chip 110 (LED chip) and is electrically connected to a bump electrode 140 provided on the main surface of the wiring substrate 100. Meanwhile, a second electrode 112B is provided on a second surface S2 (i.e., the top surface) of the semiconductor chip 110 opposite the first surface S1. The second electrode 112B is a cathode of the semiconductor chip 110 (LED chip) and is electrically connected to electrode wiring 150 provided along the outer contours of the semiconductor chip 110, the buffer material layer 130, and the wall portion 120. The first electrode 112A and the second electrode 112B may be formed using one or more metals, such as gold, silver, copper, aluminum, or titanium.

[0062] The semiconductor chip 110 is electrically connected to the wiring of the wiring substrate 100 via the first electrode 112A and the second electrode 112B. This allows the semiconductor chip 110 to pass a current between the first electrode 112A and the second electrode 112B that are spaced apart in a direction perpendicular to the main surface of the wiring substrate 100. Such a semiconductor chip 110 is also referred to as, for example, a vertical chip.

[0063] The wall portion 120 is provided to protrude from the main surface of the wiring substrate 100 so as to surround the entire periphery of the semiconductor chip 110. The wall portion 120 is provided to hold the buffer material layer 130, which physically bonds the semiconductor chip 110 to the wiring substrate 100, around the periphery of the semiconductor chip 110. The wall portion 120 may be provided higher than the height of the bump electrodes 140 so as to hold the buffer material layer 130 up to the height of the side surfaces of the semiconductor chip 110. The wall portion 120 may be made of, for example, a patterned organic resin.

[0064] The buffer layer 130 is formed by filling an area surrounded by the wall portion 120 with an adhesive buffer material. The buffer layer 130 can physically bond the semiconductor chip 110 and the wiring substrate 100 together by the buffer material filled in the space surrounded by the semiconductor chip 110, the wiring substrate 100, and the wall portion 120. Furthermore, if the buffer layer 130 extends to the side surfaces of the semiconductor chip 110 by pressing the semiconductor chip 110 into the buffer layer 130, the buffer layer 130 can bond the semiconductor chip 110 and the wiring substrate 100 over a wider area. The buffer layer 130 may contain, for example, a thermosetting adhesive as a buffer material. In such a case, the buffer layer 130 irreversibly hardens due to heat, thereby more firmly bonding the semiconductor chip 110 and the wiring substrate 100 together. For example, the buffer layer 130 may contain a phenolic adhesive, an epoxy adhesive, or an acrylic adhesive.

[0065] The electrode wiring 150 is wiring that is electrically connected to the second electrodes 112B provided on the second surface S2 (i.e., the upper surface) of the semiconductor chip 110. Specifically, the electrode wiring 150 is provided along the outer shapes of the semiconductor chip 110, the buffer material layer 130, and the wall portion 120, thereby enabling electrical connection to the second electrodes 112B provided on the second surface S2 of the semiconductor chip 110. As shown in FIG. 7 , the electrode wiring 150 may be provided so as to form a straight line when the second surface S2 is viewed from above. The electrode wiring 150 may be formed using one or more metals, such as gold, silver, copper, aluminum, or titanium.

[0066] The electrode wiring 150 is formed after the semiconductor chip 110 is mounted on the wiring substrate 100. For example, the electrode wiring 150 may be formed by forming a metal film by sputtering or the like on the mounted semiconductor chip 110, the buffer material layer 130, and the wall portion 120, and then patterning the formed metal film using photolithography and etching. In such a case, the electrode wiring 150 can be formed with higher positional accuracy by patterning using the buffer material layer 130 and the wall portion 120 as guides.

[0067] As described above, in this embodiment, the first electrode 112A, which is an anode, is provided on the first surface S1 of the semiconductor chip 110, and the second electrode 112B, which is a cathode, is provided on the second surface S2. Therefore, the size of the semiconductor chip 110 in a plane parallel to the main surface of the wiring substrate 100 can be made smaller than when both the anode and the cathode are provided on the first surface S1. However, in this case, the aspect ratio of the vertical cross section of the semiconductor chip 110 shown in FIG. 6 becomes higher (for example, the aspect ratio exceeds 1), which increases the possibility of the semiconductor chip 110 tipping over or becoming misaligned when mounted on the wiring substrate 100.

[0068] In regard to the above points, in the semiconductor device 2 according to this embodiment, the semiconductor chip 110 is mounted inside an area surrounded by the wall portion 120, and therefore it is possible to prevent the semiconductor chip 110 from falling over or being misaligned by the wall portion 120. Furthermore, in the semiconductor device 2, the electrode wiring 150 that is electrically connected to the second electrode 112B is formed after the semiconductor chip 110 is mounted on the wiring substrate 100, and therefore it is possible to connect the second electrode 112B and the electrode wiring 150 with higher reliability.

[0069] Although the preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings, the present invention is not limited to these examples. It is clear that a person skilled in the art to which the present invention pertains can conceive of various modifications and alterations within the scope of the technical ideas set forth in the claims, and it is understood that these also naturally fall within the technical scope of the present invention.

[0070] REFERENCE SIGNS LIST 1, 2... semiconductor device, 100... wiring substrate, 110... semiconductor chip, 111... chip electrode, 112A... first electrode, 112B... second electrode, 120... wall portion, 130... buffer material layer, 130H... opening, 140... bump electrode, 141... resin core, 142... metal film, 150... electrode wiring, 200... jig, S1... first surface, S2... second surface

Claims

1. A semiconductor device comprising: a wiring board having bump electrodes on a main surface; a semiconductor chip provided on the main surface of the wiring board and having a first electrode electrically connected to the bump electrodes on a first surface facing the main surface of the wiring board; a wall portion protruding from the main surface of the wiring board and provided so as to surround the entire circumference of the semiconductor chip; a buffer material layer filled between the semiconductor chip and the wall portion and extending to the side surface of the semiconductor chip; and an electrode wiring electrically connected to a second electrode provided on a second surface opposite to the first surface of the semiconductor chip.

2. The semiconductor device according to claim 1, wherein the electrode wiring is provided from the second surface of the semiconductor chip to the main surface of the wiring board along the outer shapes of the buffer material layer and the wall portion.

3. The semiconductor device according to claim 1, wherein the bump electrodes are resin core electrodes having an organic resin as a core and a surface covered with a metal film.

4. The semiconductor device according to claim 1, wherein the buffer material layer contains a thermosetting adhesive.

5. The semiconductor device according to claim 1, wherein the height of the wall portion is lower than the height of the upper surface of the semiconductor chip.

6. The semiconductor device according to claim 5, wherein a bonding surface where different layers are joined is formed in the buffer material layer below the semiconductor chip.

7. The semiconductor device according to any one of claims 1 to 5, wherein the upper surface of the buffer material layer is flush with the upper surface of the semiconductor chip.

8. The semiconductor device according to claim 1, wherein the semiconductor chip is an LED chip.

9. A method for manufacturing a semiconductor device, comprising: preparing a wiring board having bump electrodes and a wall portion surrounding the entire circumference of the region where the bump electrodes are provided on a main surface; filling the region surrounded by the wall portion with an adhesive to form a buffer material layer; pushing the semiconductor chip into the buffer material layer so that a first electrode provided on a first surface of the semiconductor chip faces the bump electrodes; a step in which the buffer material layer extruded by the pushing of the semiconductor chip extends to the side surface of the semiconductor chip; and forming an electrode wiring electrically connected to a second electrode provided on a second surface opposite to the first surface of the semiconductor chip.

10. The method for manufacturing a semiconductor device according to claim 9, wherein the electrode wiring is formed from the second surface of the semiconductor chip to the main surface of the wiring board along the outer shapes of the buffer material layer and the wall portion.

11. The bump electrode is a resin core electrode having an organic resin as a core and a surface covered with a metal film. When the semiconductor chip is pushed in, the bump electrode is crushed by the first electrode. The method of manufacturing a semiconductor according to claim 9.

12. The method of manufacturing a semiconductor device according to any one of claims 9 to 11, further including a step of forming an opening in the formed buffer material layer, and the buffer material layer flows in the in-plane direction of the wiring substrate so as to fill the opening by pushing the semiconductor chip into the buffer material layer.

13. The method of manufacturing a semiconductor device according to any one of claims 9 to 11, wherein the semiconductor chip is pushed into the buffer material layer by pressing the upper surface with a flat jig larger than the semiconductor chip.

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