Semiconductor integrated circuit device

Abstract

An inverter cell (C1) having a logical function is provided with an active region (2P1), an active region (2N1) formed above the active region (2P1), and power supply wiring (11) formed in a back surface wiring layer. A filler cell (C3) having no logical function is provided with an active region (2P3) and an active region (2N3) formed above the active region (2P3). In the second direction, an end on the first side and an end on the second side of the active region (2P1) are disposed between an end on the first side and an end on the second side of the active region (2P3).

Description

semiconductor integrated circuit device

[0001] The present disclosure relates to a semiconductor integrated circuit device including standard cells (hereinafter, also simply referred to as cells, as appropriate) that include CFETs (Complementary FETs).

[0002] The standard cell method is known as a method for forming a semiconductor integrated circuit on a semiconductor substrate. In this method, basic units (e.g., inverters, latches, flip-flops, full adders, etc.) having specific logic functions are prepared in advance as standard cells, and multiple standard cells are arranged on the semiconductor substrate and connected with wiring to design an LSI chip.

[0003] Furthermore, transistors, which are fundamental components of LSIs, have achieved improved integration density, reduced operating voltages, and improved operating speeds through the reduction of gate length (scaling). However, in recent years, excessive scaling has led to problems with off-state current and the resulting significant increase in power consumption. To solve this problem, three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional type, have been actively researched. Nanosheet FETs are one type of three-dimensional transistor that has attracted attention.

[0004] Standard cells include cells with logic functions such as NAND gates and NOR gates (hereinafter referred to as logic cells, as appropriate), as well as cells without logic functions. An example of a cell without logic functions is a "filler cell." A "filler cell" is a cell that does not have a logic function, does not contribute to the logic function of a circuit block, and is placed between logic cells.

[0005] Patent Document 1 discloses a filler cell that uses a CFET (Complementary FET) in which a P-type nanosheet transistor and an N-type nanosheet transistor are stacked on a substrate in order to reduce the area of ​​a semiconductor integrated circuit device.

[0006] Patent Document 2 discloses a standard cell using a CFET. In Patent Document 2, wiring is provided on the back surface immediately below the transistor, and the source and drain of the transistor are connected to this wiring.

[0007] International Publication No. 2020 / 137660 U.S. Patent Application Publication No. 2022 / 0123023

[0008] However, regarding filler cells using CFETs, no specific study has yet been made on the layout structure of filler cells in which wiring is provided on the back surface immediately below the transistor.

[0009] The present disclosure aims to provide a layout for a semiconductor integrated circuit device including a filler cell using a CFET, in which wiring is provided on the back side of the transistor.

[0010] In an aspect of the present disclosure, there is provided a semiconductor integrated circuit device comprising: a first standard cell having a logic function; and a second standard cell arranged adjacent to the first standard cell and not having a logic function, wherein the first standard cell comprises: a first active region constituting a channel, a source, and a drain of a first transistor of a first conductivity type, the channel including a first nanosheet extending in a first direction; a second active region formed above the first active region in a depth direction and overlapping with the first active region in a plan view, the second active region constituting a channel, a source, and a drain of a second transistor of a second conductivity type different from the first conductivity type, the channel including a second nanosheet extending in the first direction; a first power supply wiring formed on a back side of the first transistor, extending in the first direction, and supplying a first power supply voltage; a second power supply wiring extending in the first direction, and supplying a second power supply voltage different from the first power supply voltage; and a region of the first active region where the first power supply wiring overlaps with a region of the first transistor that serves as a source of the first transistor. the second power supply wiring is connected to the source of the second transistor in the second active region; the second standard cell comprises: a third active region formed in the same layer as the first active region in the depth direction, constituting a channel, a source, and a drain of a first dummy transistor of the first conductivity type, the channel including a third nanosheet extending in the first direction; and a fourth active region formed in the same layer as the second active region in the depth direction, constituting a channel, a source, and a drain of a second dummy transistor of the second conductivity type, the channel including a fourth nanosheet extending in the first direction; and a second active region between a first end of the first active region, which is one side in the second direction perpendicular to the first direction and the depth direction, and a second end of the third active region, which is the other side in the second direction, andThe second end is disposed.

[0011] According to the present disclosure, in the second direction, the first and second ends of the first active region of the first standard cell having a logic function are arranged between the first and second ends of the third active region of the second standard cell not having a logic function. By arranging the second standard cell adjacent to the first standard cell, the third active region of the second standard cell can be arranged along the entire side surface of the first active region of the first standard cell in the first direction. Therefore, the distance from the first active region of the first standard cell to the third active region of the second standard cell is set to a predetermined value. This improves the accuracy of estimating the transistor performance of standard cells having a logic function.

[0012] According to the present disclosure, with respect to filler cells using CFETs, it is possible to improve the accuracy of estimating the transistor performance of standard cells having logic functions in the layout of a semiconductor integrated circuit device including filler cells in which wiring is provided on the back side of the transistor.

[0013] 1 is a plan view showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to the first embodiment. FIG. 2 is a plan view showing an example of the layout structure of an inverter cell according to the first embodiment. FIG. 3 is a circuit diagram of an inverter cell. FIG. 4 is a plan view showing an example of the layout structure of a filler cell according to the first embodiment. FIG. 5 is a cross-sectional view of the filler cell of FIG. 4. FIG. 6 is another example of the configuration of a semiconductor integrated circuit device according to the first embodiment. FIG. 7 is a plan view showing an example of the layout structure of an inverter cell according to a modified example of the first embodiment. FIG. 8 is a plan view showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to a second embodiment. FIG. 9 is a plan view showing an example of the layout structure of an inverter cell according to the second embodiment. FIG. 10 is a plan view showing an example of the layout structure of a filler cell according to the second embodiment.

[0014] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, a semiconductor integrated circuit device includes a plurality of standard cells. At least some of the plurality of standard cells include nanosheet FETs, and further include a CFET structure in which transistors of different conductivity types (in the embodiment, the lower part of the cell is P conductivity type and the upper part of the cell is N conductivity type) are stacked.

[0015] In this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. In this specification, expressions such as "same wiring width" that mean the same width, etc., are considered to include the range of manufacturing variations.

[0016] 1 is a plan view showing an example of the layout of a circuit block provided in a semiconductor integrated circuit device according to the first embodiment. Specifically, Fig. 1(a) shows the lower part of the cell, i.e., the part including the nanosheet transistor formed on the side closer to the substrate, and Fig. 1(b) shows the upper part of the cell, i.e., the part including the nanosheet transistor formed on the side farther from the substrate.

[0017] 1 is configured by arranging standard cells. In this embodiment, power supply wiring is formed in a BM0 (Backside Metal 0) wiring layer, which is a backside wiring layer provided on the backside of a semiconductor chip on which transistors are formed, and in an M0 wiring layer, which is a metal wiring layer above the transistors.

[0018] In the following description, in plan views such as Figure 1, the horizontal direction of the drawing is the X direction (corresponding to the first direction), the vertical direction of the drawing is the Y direction (corresponding to the second direction), and the direction perpendicular to the substrate surface is the Z direction (corresponding to the depth direction). In the following description, the same symbols refer to the same things, and their explanations may be omitted.

[0019] 1 and other plan views, the solid lines surrounding the cells indicate the cell frames (outer edges of the standard cells). The standard cells are arranged so that the cell frames are in contact with the cell frames of adjacent cells in the X or Y direction.

[0020] In the layout of FIG. 1, a plurality of cells arranged in the X direction constitute a cell row CR. The plurality of cells include inverter cells C1 and C2 having a logic function and a filler cell C3. In the layout of FIG. 1, the filler cell C3 is arranged between the inverter cells C1 and C2. Note that a "filler cell" refers to a cell that does not have a logic function, does not contribute to the logic function of the circuit block, and is arranged between logic cells.

[0021] In each cell, power supply wiring is formed in the center in the Y direction in the BM0 wiring layer and the M0 wiring layer. Specifically, power supply wiring (power supply wiring 11 described later) that supplies power supply voltage VDD is formed in the BM0 wiring layer, and power supply wiring (power supply wiring 51 described later) that supplies power supply voltage VSS is formed in the M0 wiring layer. Each cell receives the power supply voltages VDD and VSS from the outside via these power supply wirings. That is, in the block layout of FIG. 1, power supply wiring that is continuous in the X direction is formed in the BM0 wiring layer and the M0 wiring layer of the cell column CR.

[0022] Additionally, the active region 2P3 (2N3) of the filler cell C3 is arranged to the right of the active region 2P1 (2N1) of the inverter cell C1 in the X direction in the drawing. The active region 2P3 (2N3) of the filler cell C3 is arranged to the left of the active region 2P2 (2N2) of the inverter cell C2 in the X direction in the drawing. In other words, the active regions of the filler cells without logic functions are arranged adjacent to the active regions of the standard cells with logic functions in the X direction.

[0023] (Configuration of inverter cell C1) Fig. 2 is a plan view showing an example of the layout structure of inverter cells C1 and C2 according to the first embodiment, and Fig. 3 is a circuit diagram of the inverter cell. Specifically, Fig. 2(a) shows the lower part of inverter cell C1, Fig. 2(b) shows the upper part of inverter cell C1, Fig. 2(c) shows the lower part of inverter cell C2, and Fig. 2(d) shows the upper part of inverter cell C2.

[0024] In the following description, the dashed lines running vertically and horizontally in plan views such as FIG. 2 and the dashed lines running vertically in cross-sectional views such as FIG. 2 indicate grids used for component placement during design. The grids are arranged at equal intervals in the X direction and at equal intervals in the Y direction. Note that the grid spacing may be the same or different in the X and Y directions. The grid spacing may also be different for each layer. Furthermore, each component does not necessarily have to be arranged on a grid.

[0025] As shown in FIG. 3, the inverter cell C1 has transistors P1 and N1, and an inverter circuit with an input A and an output Y is configured.

[0026] 2A, a BM0 wiring layer is formed on the back surface of a semiconductor chip on which transistors are formed. In the BM0 wiring layer, a power supply wiring 11 extending in the X direction is formed at the center of the cell in the Y direction of the drawing. The power supply wiring 11 supplies a power supply voltage VDD.

[0027] An active region that forms the channel, source, and drain of the P-type transistor is formed in the P-type transistor region at the bottom of the cell. Specifically, an active region 2P1 is formed in the P-type transistor region. The active region 2P1 overlaps with the power supply wiring 11 in plan view.

[0028] A P-type transistor P1 is formed in the P-type transistor region. The transistor P1 has a channel made of a three-sheet structure (not shown) that overlaps in a planar view and has a nanosheet 21 extending in the X direction. In the active region 2P1, the portion that serves as the source of the transistor P1 is connected to the power supply wiring 11 via a via 61. The via 61 is formed in a region where the power supply wiring 11 and the active region 2P1 overlap in a planar view.

[0029] As shown in FIG. 2B, an active region that forms the channel, source, and drain of the N-type transistor is formed in the N-type transistor region in the upper part of the cell. Specifically, an active region 2N1 is formed in the N-type transistor region. The active region 2N1 is disposed above the active region 2P1 in the Z direction. The active region 2N1 overlaps with the active region 2P1 in a plan view.

[0030] An N-type transistor N1 is formed in the N-type transistor region. The transistor N1 has a channel made of a nanosheet 22 (not shown) that is made of three overlapping sheets in a plan view and extends in the X direction.

[0031] In the active region, the portions that become the source and drain on both sides of the nanosheet are formed, for example, by epitaxial growth from the nanosheet.

[0032] A gate wiring 31 is formed in the center of the cell in the X direction of the drawing, extending in the Y direction and extending in the Z direction from the top of the cell to the bottom of the cell. The nanosheets 21 and 22 overlap the gate wiring 31 in plan view. The gate wiring 31 corresponds to the gates of transistors P1 and N1.

[0033] Dummy gate wirings 32 and 33 extending in the Y and Z directions are formed on both sides of the cell frame in the X direction. The dummy gate wiring 32 is shared with another cell arranged on the left side of the drawing. The dummy gate wiring 33 is shared with another cell (filler cell C3 in FIG. 1 ) arranged on the right side of the drawing.

[0034] 2A, local interconnects (LI) 41 and 42 extending in the Y direction are formed below the cell. The local interconnect 41 is connected to a portion of the active region 2P1 that serves as the source of the transistor P1. The local interconnect 42 is connected to a portion of the active region 2P1 that serves as the drain of the transistor P1.

[0035] 2B, local wirings 43 and 44 extending in the Y direction are formed above the cell. The local wiring 43 is connected to a portion of the active region 2N1 that will become the source of the transistor N1. The local wiring 44 is connected to a portion of the active region 2N1 that will become the drain of the transistor N1.

[0036] In the M0 wiring layer, which is a metal wiring layer above the active region 2N1, a power supply wiring 51 and wirings 52 and 53 extending in the X direction are formed. The power supply wiring 51 supplies a power supply voltage VSS. The wiring 52 corresponds to the input A, and the wiring 53 corresponds to the output Y.

[0037] The power supply wiring 51 is formed in the center of the cell in the Y direction in the drawing. The power supply wiring 51 overlaps with the active region 2N1 in plan view. The power supply wiring 51 is connected to a portion of the active region 2N1 that serves as the source of the transistor N1 through a via 62 and a local wiring 43. The via 62 is formed in the region where the power supply wiring 51 and the active region 2N1 overlap in plan view.

[0038] The wiring 52 is disposed on the lower side of the cell in the Y direction in the drawing. The wiring 52 is connected to the gate wiring 31 through a via 63. The via 63 is formed in a region where the wiring 52 and the gate wiring 31 overlap in a plan view.

[0039] The wiring 53 is arranged on the upper side of the cell in the Y direction in the drawing. The wiring 53 is connected to the portion that becomes the drain of the transistor P1 and the portion that becomes the drain of the transistor N1 through vias 64 and 65 and local wirings 42 and 44.

[0040] As described above, the inverter cell C1 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C1 is a standard cell having a logic function.

[0041] As shown in FIGS. 2A and 2B, the active regions 2P1 and 2N1 in the inverter cell C1 have a width w1 in the Y direction in plan view.

[0042] (Configuration of Inverter Cell C2) The inverter cell C2 has almost the same configuration as the inverter cell C1. Specifically, the inverter cell C2 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C2 is a standard cell having a logic function.

[0043] As shown in Figures 2(c) and (d), compared to the inverter cell C1 shown in Figures 2(a) and (b), the inverter cell C2 has active regions 2P2 and 2N2, each having a different width in the Y direction, arranged in place of the active regions 2P1 and 2N1.

[0044] Specifically, the active regions 2P2 and 2N2 have a width w2 in the Y direction, which is smaller than w1. That is, the drive capability of the inverter cell C1 is greater than the drive capability of the inverter cell C2.

[0045] 2, the upper end of the active region 2P2 (2N2) in the Y direction on the drawing is located at the same position in the Y direction as the upper end of the active region 2P1 (2N1) in the Y direction on the drawing. That is, the upper end of the active region 2P1 (2N1) in the Y direction on the drawing of the inverter cell C1 and the upper end of the active region 2P2 (2N2) in the Y direction on the drawing of the inverter cell C2 are aligned in the Y direction.

[0046] (Configuration of filler cell C3) Fig. 4 is a plan view showing an example of the layout structure of the filler cell according to the first embodiment, and Fig. 5 is a cross-sectional view showing an example of the layout structure of the filler cell according to the first embodiment. Specifically, Fig. 4(a) shows the lower part of the cell, Fig. 4(b) shows the upper part of the cell, Fig. 5(a) is a cross-section taken along X1-X1' in Fig. 4, Fig. 5(b) is a cross-section taken along Y1-Y1' in Fig. 4, and Fig. 5(c) is a cross-section taken along Y2-Y2' in Fig. 4.

[0047] 4A, the BM0 wiring layer is formed with a power supply wiring 11 extending in the X direction and wirings 111 and 112. The power supply wiring 11 is formed in the center of the cell in the Y direction in the drawing, and supplies a power supply voltage VDD. The wirings 111 and 112 are formed at the top and bottom of the power supply wiring 11 in the Y direction in the drawing, respectively.

[0048] An active region 2P3 is formed in the P-type transistor region below the cell. The active region 2P3 overlaps with the power supply wiring 11 in plan view.

[0049] P-type dummy transistors DP1 to DP3 are formed in the active region 2P3. The dummy transistors PD1 to PD3 each have a channel made of three overlapping sheet structures in a plan view, and have nanosheets 121 to 123 extending in the X direction.

[0050] 4B, an active region 2N3 is formed in the N-type transistor region in the upper part of the cell. The active region 2N3 overlaps with the active region 2P3 in plan view.

[0051] N-type dummy transistors DN1 to DN3 are formed in the active region 2N3. The dummy transistors DN1 to DN3 have nanosheets 124 to 126 as channels, each of which has a three-sheet structure overlapping in a plan view and extends in the X direction.

[0052] Dummy gate wirings 131 to 133 are formed extending in the Y and Z directions. Nanosheets 121 and 124 overlap with dummy gate wiring 131 in a planar view. Nanosheets 122 and 125 overlap with dummy gate wiring 132 in a planar view. Nanosheets 123 and 126 overlap with dummy gate wiring 133 in a planar view. Dummy gate wiring 131 corresponds to the gates of dummy transistors DP1 and DN1. Dummy gate wiring 132 corresponds to the gates of dummy transistors DP2 and DN2. Dummy gate wiring 133 corresponds to the gates of dummy transistors DP3 and DN3.

[0053] Dummy gate wiring 134, 135 extending in the Y and Z directions are formed on both sides of the cell frame in the X direction. The dummy gate wiring 134 is shared with another cell (inverter cell C1 in FIG. 1) located on the left side of the drawing. The dummy gate wiring 135 is shared with another cell (inverter cell C2 in FIG. 1) located on the right side of the drawing.

[0054] As shown in FIG. 4A, local interconnections 141 to 144 extending in the Y direction are formed below the cell. Local interconnection 141 is connected to a portion in active region 2P3 that will become the source of dummy transistor DP1. Local interconnection 142 is connected to a portion in active region 2P3 that will become the drain of dummy transistor DP1 and a portion in active region 2P3 that will become the source of dummy transistor DP2. Local interconnection 143 is connected to a portion in active region 2P3 that will become the drain of dummy transistor DP2 and a portion in active region 2P3 that will become the source of dummy transistor DP3. Local interconnection 144 is connected to a portion in active region 2P3 that will become the drain of dummy transistor DP3.

[0055] As shown in FIG. 4B, local interconnections 145 to 148 extending in the Y direction are formed above the cell. Local interconnection 145 is connected to a portion of active region 2N3 that will become the source of dummy transistor DN1. Local interconnection 146 is connected to a portion of active region 2N3 that will become the drain of dummy transistor DN1 and a portion of active region 2N3 that will become the source of dummy transistor DN2. Local interconnection 147 is connected to a portion of active region 2N3 that will become the drain of dummy transistor DN2 and a portion of active region 2N3 that will become the source of dummy transistor DN3. Local interconnection 148 is connected to a portion of active region 2N3 that will become the drain of dummy transistor DN3.

[0056] The M0 wiring layer is formed with a power supply wiring 51 extending in the X direction and wirings 151 and 152. The power supply wiring 51 is formed in the center of the cell in the Y direction in the drawing, and supplies a power supply voltage VSS. The wirings 151 and 152 are formed at the top and bottom of the power supply wiring 51 in the Y direction in the drawing, respectively.

[0057] 4, unlike the inverter cells C1 and C2, the dummy gate wirings 131 to 135 and the local wirings 141 to 148 are not connected to any other wirings. In other words, the filler cell C3 is a standard cell that does not have a logic function.

[0058] In the block layout of FIG. 1 , the Y-direction width of the active region 2P1 (2N1) of the inverter cell C1 and the Y-direction width of the active region 2P3 (2N3) of the filler cell C3 are w1. The Y-direction width of the active region 2P2 (2N2) of the inverter cell C2 is w2, which is smaller than w1. Furthermore, the Y-direction top ends of the active regions 2P1 (2N1), 2P2 (2N2), and 2P3 (2N3) are aligned in the same Y-direction. That is, the Y-direction top ends of the active region 2P1 (2N1) of the inverter cell C1, the Y-direction top ends of the active region 2P2 (2N2) of the inverter cell C2, and the Y-direction top ends of the active region 2P3 (2N3) of the filler cell C3 are aligned in the Y-direction. By placing the filler cell C3 between the inverter cells C1 and C2, each of which has an active area with a different width in the Y direction, the active area of ​​the filler cell C3 can be positioned along the entire right side of the active area of ​​the inverter cell C1 and the entire left side of the active area of ​​the inverter cell C2. Therefore, the distances from the active area 2P1 (2N1) of the inverter cell C1 and the active area 2P2 (2N2) of the inverter cell C2 to the active area 2P3 (2N3) of the filler cell C3 are set to predetermined values. This improves the accuracy of estimating the transistor performance of the logic cells.

[0059] 1, the gate wiring 31 and dummy gate wirings 32, 33 (134) of the inverter cell C1, the gate wiring 31 and dummy gate wirings 32 (135), 33 of the inverter cell C2, and the dummy gate wirings 131 to 133 of the filler cell C3 are arranged at the same pitch Pg in the X direction. That is, the gate wirings (including the dummy gate wirings) of the inverter cells C1, C2 and the filler cell C3 are arranged regularly. This makes it possible to suppress manufacturing variations in the semiconductor integrated circuit device and improve yields.

[0060] 1A, the local wirings 41 and 42 of inverter cell C1, the local wirings 41 and 42 of inverter cell C2, and the local wirings 141 to 144 of filler cell C3 are arranged at the same pitch P1 in the X direction. As shown in FIG. 1B, the local wirings 43 and 44 of inverter cell C1, the local wirings 43 and 44 of inverter cell C2, and the local wirings 145 to 148 of filler cell C3 are arranged at the same pitch P1 in the X direction. That is, the local wirings of inverter cells C1 and C2 and filler cell C3 are regularly arranged at the top and bottom of the cells, respectively. This allows for suppression of manufacturing variations in semiconductor integrated circuit devices, improving yield.

[0061] In this embodiment, the size of the filler cell C3 in the X direction is set to four grids, but is not limited to this.

[0062] In addition, in this embodiment, the filler cell C3 is provided in the local wirings 141 to 148 and the wirings 111, 112, 151, and 152, but some or all of these may not be provided.

[0063] In this embodiment, the Y-direction widths of the active regions at the top and bottom of the inverter cells C1, C2, and filler cell C3 are equal, but they may be different. In this case, it is sufficient that the Y-direction width of the active region 2P3 of filler cell C3 is the same as the Y-direction width of the active region 2P1 of inverter cell C1 and is larger than the Y-direction width of the active region 2P3 of inverter cell C2. Similarly, it is sufficient that the Y-direction width of the active region 2N3 of filler cell C3 is the same as the Y-direction width of the active region 2N1 of inverter cell C1 and is larger than the Y-direction width of the active region 2N3 of inverter cell C2.

[0064] Although the present embodiment has been described with reference to an example in which two inverter cells with different widths of active regions are arranged in a circuit block, three or more inverter cells with different widths of active regions may be arranged in a circuit block. In this case, the width of the active region of filler cell C3 in the Y direction may be adjusted to the width of the active region with the largest width in the Y direction among the active regions included in the three or more inverter cells.

[0065] In addition, in this embodiment, the power supply wiring 11 formed in the BM0 wiring layer and the power supply wiring 51 formed in the M0 wiring layer are illustrated as having the same wiring width, but the wiring widths of the power supply wiring 11 and 51 may be different.

[0066] (Other Configuration Examples) The power supply wiring formed on the back surface side of the transistor described above may be configured using a semiconductor chip separate from the semiconductor chip on which the transistor is configured.

[0067] Fig. 6(a) shows another example of the configuration of the semiconductor integrated circuit device according to the first embodiment. The semiconductor integrated circuit device 100 shown in Fig. 6(a) is configured by stacking a first semiconductor chip 101 (chip A) and a second semiconductor chip 102 (chip B). Standard cells including the inverter cells described above are arranged on chip A. Power supply wiring is formed in a wiring layer provided on the surface of chip B. Chip B is attached to the back side of chip A using bumps or the like.

[0068] 6B shows a cross section of filler cell C3 of FIG. 5 taken along line Y1-Y1' in this configuration example. As shown in FIG. 6B, power supply wiring 11 for supplying VDD is formed in a wiring layer provided on the surface of chip B. Although not shown, in inverter cell C1 (C2), power supply wiring 11 is connected to active region 2P1 (2P2) of chip A through via 61.

[0069] This configuration example also provides the same effects as those of FIG.

[0070] 7A and 7B are plan views showing an example of the layout structure of inverter cells C1 and C2 according to a modification of the first embodiment. Specifically, Fig. 7A shows the lower part of inverter cell C1, Fig. 7B shows the upper part of inverter cell C1, Fig. 7C shows the lower part of inverter cell C2, and Fig. 7D shows the upper part of inverter cell C2. In Fig. 7, the positions of active regions 2P2 and 2N2 in the Y direction are different from those in Fig. 2.

[0071] 7, the center of the active region 2P2 (2N2) in the Y direction is located at the same position in the Y direction as the center of the active region 2P1 (2N1) in the Y direction. That is, the center of the active region 2P1 (2N1) of the inverter cell C1 in the Y direction and the center of the active region 2P2 (2N2) of the inverter cell C2 in the Y direction are aligned in the Y direction. This provides the same effect as in FIG. 2.

[0072] In addition, if the upper and lower ends of the active region 2P2 (2N2) in the Y direction are positioned between the upper and lower ends of the active region 2P1 (2N1) in the Y direction, the same effect as in Figure 2 can be obtained.

[0073] 8A and 8B are plan views showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to a second embodiment. Specifically, Fig. 8A shows a lower part of a cell, and Fig. 8B shows an upper part of a cell.

[0074] 8 is configured by arranging standard cells. In this embodiment, the power supply wiring is formed in a BM0 wiring layer, which is a backside wiring layer provided on the backside of the semiconductor chip on which the transistors are formed.

[0075] In the layout of Fig. 8, a plurality of cells arranged in the X direction constitute a cell column CR. The plurality of cells include inverter cells C4 and C5 having a logic function and a filler cell C6 having no logic function. In the layout of Fig. 8, the filler cell C6 is disposed between the inverter cells C4 and C5.

[0076] In each cell, power supply wiring is formed at both ends in the Y direction in the BM0 wiring layer. Specifically, a power supply wiring (power supply wiring 11 described later) that supplies a power supply voltage VDD is formed at the upper end in the Y direction of the drawing, and a power supply wiring (power supply wiring 12 described later) that supplies a power supply voltage VSS is formed at the lower end in the Y direction of the drawing. Each cell receives the power supply voltages VDD and VSS from the outside via these power supply wirings. That is, in the block layout of FIG. 8, power supply wiring that is continuous in the X direction is formed in the BM0 wiring layer of the cell column CR.

[0077] As will be described in detail later, the active region 2P6 (2N6) of the filler cell C6 is arranged to the right of the active region 2P4 (2N4) of the inverter cell C4 in the X direction of the drawing. The active region 2P6 (2N6) of the filler cell C6 is arranged to the left of the active region 2P5 (2N5) of the inverter cell C5 in the X direction of the drawing. In other words, the active regions of the filler cells that do not have a logic function are arranged adjacent to the active regions of the standard cells that have a logic function in the X direction.

[0078] (Configuration of inverter cell C4) Figure 9 is a plan view showing an example of the layout structure of inverter cells C4 and C5 according to the second embodiment. Specifically, Figure 9(a) shows the lower part of inverter cell C4, Figure 9(b) shows the upper part of inverter cell C4, Figure 9(c) shows the lower part of inverter cell C5, and Figure 9(d) shows the upper part of inverter cell C5. Note that the inverter circuits shown in Figure 3 are configured in the inverter cells C4 and C5 in Figure 9, respectively.

[0079] 9A, the BM0 wiring layer is formed with power supply wirings 11 and 12 extending in the X direction. The power supply wiring 11 is formed at the upper end of the cell in the Y direction in the drawing, and supplies a power supply voltage VDD. The power supply wiring 12 is formed at the lower end of the cell in the Y direction in the drawing, and supplies a power supply voltage VSS.

[0080] An active region 2P4 is formed in the P-type transistor region at the bottom of the cell. A transistor P1 is formed in the active region 2P4. The transistor P1 has a nanosheet 21. In the active region 2P4, a portion that serves as the source of the transistor P1 is connected to the power supply wiring 11 via a via 61. The via 61 is formed in a region where the power supply wiring 11 and the active region 2P4 overlap in a planar view.

[0081] 9B, an active region 2N4 is formed in the N-type transistor region in the upper part of the cell. The active region 2N4 is arranged higher in the Z direction than the active region 2P4. The active region 2N4 overlaps with the active region 2P4 in plan view.

[0082] The active region 2N4 includes a transistor N1. The transistor N1 includes a nanosheet 22.

[0083] A gate wiring 31 extending in the Y direction is formed in the center of the cell in the X direction in the drawing. The nanosheets 21 and 22 overlap the gate wiring 31 in plan view. The gate wiring 31 corresponds to the gates of the transistors P1 and N1.

[0084] Dummy gate wirings 32 and 33 extending in the Y and Z directions are formed on both sides of the cell frame in the X direction. The dummy gate wiring 32 is shared with another cell arranged on the left side of the drawing. The dummy gate wiring 33 is shared with another cell (filler cell C6 in FIG. 8 ) arranged on the right side of the drawing.

[0085] 9A, local wirings 41 and 42 extending in the Y direction are formed below the cell. The local wiring 41 is connected to a portion of the active region 2P4 that will become the source of the transistor P1. The local wiring 42 is connected to a portion of the active region 2P4 that will become the drain of the transistor P1.

[0086] 9B, local wirings 43 and 44 extending in the Y direction are formed above the cell. The local wiring 43 is connected to a portion of the active region 2N4 that will become the source of the transistor N1. The local wiring 43 is connected to the power supply wiring 12 via a via 62. The via 62 is formed in a region where the power supply wiring 12 and the local wiring 43 overlap in a planar view. That is, the power supply wiring 12 is connected to a portion of the active region 2N4 that will become the source of the transistor N1 via the via 62 and the local wiring 43. The local wiring 44 is connected to a portion of the active region 2N4 that will become the drain of the transistor N1.

[0087] In the M0 wiring layer, wirings 52 and 53 extending in the X direction are formed. The wiring 52 corresponds to the input A, and the wiring 53 corresponds to the output Y.

[0088] The wiring 52 is disposed in the center of the cell in the Y direction in the drawing. The wiring 52 is connected to the gate wiring 31 through a via 63. The via 63 is formed in a region where the wiring 52 and the gate wiring 31 overlap in a plan view.

[0089] The wiring 53 is arranged on the upper side of the cell in the Y direction in the drawing. The wiring 53 is connected to the portion that becomes the drain of the transistor P1 and the portion that becomes the drain of the transistor N1 through vias 64 and 65 and local wirings 42 and 44.

[0090] As described above, the inverter cell C4 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C1 is a standard cell having a logic function.

[0091] As shown in FIGS. 9A and 9B, the active regions 2P4 and 2N4 in the inverter cell C4 have a width w1 in the Y direction in plan view.

[0092] (Configuration of Inverter Cell C5) The inverter cell C5 has a configuration similar to that of the inverter cell C4. Specifically, the inverter cell C5 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C5 is a standard cell having a logic function.

[0093] As shown in Figures 9(c) and (d), compared to the inverter cell C1 shown in Figures 9(a) and (b), the inverter cell C5 has active regions 2P5 and 2N5, each having a different width in the Y direction, instead of the active regions 2P4 and 2N4.

[0094] Specifically, the active regions 2P5 and 2N5 have a width w2 in the Y direction, which is smaller than w1. That is, the drive capability of the inverter cell C4 is greater than the drive capability of the inverter cell C5.

[0095] 9, the upper end of the active region 2P5 (2N5) in the Y direction on the drawing is located at the same position in the Y direction as the upper end of the active region 2P4 (2N4) in the Y direction on the drawing. That is, the upper end of the active region 2P4 (2N4) in the Y direction on the drawing of the inverter cell C4 and the upper end of the active region 2P5 (2N5) in the Y direction on the drawing of the inverter cell C5 are aligned in the Y direction.

[0096] 10A and 10B are plan views showing an example of a layout structure of a filler cell according to the second embodiment. Specifically, Fig. 10A shows the lower part of the cell, and Fig. 10B shows the upper part of the cell.

[0097] 10A, the BM0 wiring layer is formed with power supply wirings 11 and 12 extending in the X direction. The power supply wiring 11 is formed at the upper end of the cell in the Y direction in the drawing, and supplies a power supply voltage VDD. The power supply wiring 12 is formed at the lower end of the cell in the Y direction in the drawing, and supplies a power supply voltage VSS.

[0098] An active region 2P6 is formed in the P-type transistor region below the cell. The active region 2P6 overlaps with the power supply wirings 11 and 12 in plan view.

[0099] Dummy transistors DP1 to DP3 are formed in the active region 2P6. The dummy transistors DP1 to DP3 have nanosheets 121 to 123 extending in the X direction as channels.

[0100] 10B, an active region 2N6 is formed in the N-type transistor region in the upper part of the cell. The active region 2N6 overlaps with the active region 2P6 in plan view.

[0101] Dummy transistors DN1 to DN3 are formed in the active region 2N6. The dummy transistors DN1 to DN3 have nanosheets 124 to 126 extending in the X direction as channels.

[0102] Dummy gate wirings 131 to 133 are formed extending in the Y and Z directions. Nanosheets 121 and 124 overlap with dummy gate wiring 131 in a planar view. Nanosheets 122 and 125 overlap with dummy gate wiring 132 in a planar view. Nanosheets 123 and 126 overlap with dummy gate wiring 133 in a planar view. Dummy gate wiring 131 corresponds to the gates of dummy transistors DP1 and DN1. Dummy gate wiring 132 corresponds to the gates of dummy transistors DP2 and DN2. Dummy gate wiring 133 corresponds to the gates of dummy transistors DP3 and DN3.

[0103] Dummy gate wiring 134, 135 extending in the Y and Z directions are formed on both sides of the cell frame in the X direction. The dummy gate wiring 134 is shared with another cell (inverter cell C4 in FIG. 8) located on the left side of the drawing. The dummy gate wiring 135 is shared with another cell (inverter cell C5 in FIG. 8) located on the right side of the drawing.

[0104] As shown in FIG. 10A, local interconnections 141 to 144 extending in the Y direction are formed below the cell. Local interconnection 141 is connected to a portion in active region 2P6 that will become the source of dummy transistor DP1. Local interconnection 142 is connected to a portion in active region 2P6 that will become the drain of dummy transistor DP1 and a portion in active region 2P6 that will become the source of dummy transistor DP2. Local interconnection 143 is connected to a portion in active region 2P6 that will become the drain of dummy transistor DP2 and a portion in active region 2P6 that will become the source of dummy transistor DP3. Local interconnection 144 is connected to a portion in active region 2P6 that will become the drain of dummy transistor DP3.

[0105] As shown in FIG. 10B, local interconnections 145 to 148 extending in the Y direction are formed above the cell. Local interconnection 145 is connected to a portion of active region 2N6 that will become the source of dummy transistor DN1. Local interconnection 146 is connected to a portion of active region 2N6 that will become the drain of dummy transistor DN1 and a portion of active region 2N6 that will become the source of dummy transistor DN2. Local interconnection 147 is connected to a portion of active region 2N6 that will become the drain of dummy transistor DN2 and a portion of active region 2N6 that will become the source of dummy transistor DN3. Local interconnection 148 is connected to a portion of active region 2N6 that will become the drain of dummy transistor DN3.

[0106] The M0 wiring layer is formed with wirings 153 to 156 extending in the X direction. The wirings 153 to 156 are arranged at the same pitch in the Y direction.

[0107] 10, unlike the inverter cells C4 and C5, the dummy gate wirings 131 to 135 and the local wirings 141 to 148 are not connected to any other wirings. In other words, the filler cell C6 is a standard cell that does not have a logic function.

[0108] In the block layout of Figure 8, the Y-direction width of the active region 2P4 (2N4) of the inverter cell C4 and the Y-direction width of the active region 2P6 (2N6) of the filler cell C6 are w1. The Y-direction width of the active region 2P5 (2N5) of the inverter cell C5 is w2, which is smaller than w1. Furthermore, the Y-direction top ends of the active regions 2P4 (2N4), 2P5 (2N5), and 2P6 (2N6) are arranged at the same position in the Y direction. That is, the Y-direction top ends of the active region 2P4 (2N4) of the inverter cell C4, the Y-direction top ends of the active region 2P5 (2N5) of the inverter cell C5, and the Y-direction top ends of the active region 2P6 (2N6) of the filler cell C6 are aligned in the Y direction. By placing the filler cell C6 between the inverter cells C4 and C5, each of which has an active area with a different width in the Y direction, the active area of ​​the filler cell C6 can be positioned along the entire right side of the active area of ​​the inverter cell C4 and the entire left side of the active area of ​​the inverter cell C5. Therefore, the distances from the active area 2P4 (2N4) of the inverter cell C4 and the active area 2P5 (2N5) of the inverter cell C5 to the active area 2P6 (2N6) of the filler cell C6 are set to predetermined values. This improves the accuracy of estimating the transistor performance of the logic cells.

[0109] Furthermore, power supply wiring 11 that supplies power supply voltage VDD is formed at the upper end of the cell in the Y direction on the drawing. It is located at the same position in the Y direction as the upper end of active region 2P4 in the Y direction on the drawing and the upper end of active region 2P5 in the Y direction on the drawing. This allows the power supply wiring that supplies power supply voltage VDD to be closer to the part of the active region of the inverter cell that serves as the source of transistor P1, thereby reducing the resistance between the power supply wiring and the source of transistor P1 and suppressing a drop in power supply voltage.

[0110] 8, the gate wiring 31 and dummy gate wirings 32, 33 (134) of inverter cell C4, the gate wiring 31 and dummy gate wirings 32 (135), 33 of inverter cell C5, and the dummy gate wirings 131 to 133 of filler cell C6 are arranged at the same pitch Pg in the X direction. That is, the gate wirings (including dummy gate wirings) of inverter cells C4, C5 and filler cell C6 are arranged regularly. This makes it possible to suppress manufacturing variations in semiconductor integrated circuit devices and improve yields.

[0111] 8A, the local wirings 41 and 42 of inverter cell C4, the local wirings 41 and 42 of inverter cell C5, and the local wirings 141 to 144 of filler cell C6 are arranged at the same pitch P1 in the X direction. As shown in FIG. 8B, the local wirings 43 and 44 of inverter cell C4, the local wirings 43 and 44 of inverter cell C5, and the local wirings 145 to 148 of filler cell C6 are arranged at the same pitch P1 in the X direction. That is, the local wirings of inverter cells C4 and C5 and filler cell C6 are regularly arranged at the top and bottom of the cells, respectively. This allows for suppression of manufacturing variations in semiconductor integrated circuit devices, improving yield.

[0112] In this embodiment, the size of the filler cell C6 in the X direction is set to four grids, but is not limited to this.

[0113] In addition, in this embodiment, the filler cell C6 is provided in the local wirings 141 to 148 and wirings 153 to 156, but some or all of these may not be provided.

[0114] In this embodiment, the active regions of the inverter cells C4, C5, and filler cell C6 have the same Y-direction width at the top and bottom of the cells, but this is not limited to this. In this case, it is sufficient that the Y-direction width of the active region 2P6 of filler cell C6 is the same as the Y-direction width of the active region 2P4 of inverter cell C4 and is larger than the Y-direction width of the active region 2P5 of inverter cell C5. Similarly, it is sufficient that the Y-direction width of the active region 2N6 of filler cell C6 is the same as the Y-direction width of the active region 2N4 of inverter cell C4 and is larger than the Y-direction width of the active region 2N5 of inverter cell C5.

[0115] Although the present embodiment has been described with reference to an example in which two inverter cells with different widths of active regions are arranged in a circuit block, three or more inverter cells with different widths of active regions may be arranged in a circuit block. In this case, the width of the active region of filler cell C6 in the Y direction may be adjusted to the width of the active region with the largest width in the Y direction among the active regions included in the three or more inverter cells.

[0116] In addition, in this embodiment, the power supply wirings 11 and 12 formed in the BM0 wiring layer are illustrated as having the same width, but the wiring widths of the power supply wirings 11 and 12 may be different.

[0117] In the above-described embodiments and variants, each transistor has three nanosheets, but some or all of the transistors may have one, two, or four or more nanosheets.

[0118] In addition, in the above-described embodiments and modifications, the cross-sectional shape of the nanosheet is rectangular, but this is not limited to this and may be, for example, square, circular, elliptical, or the like.

[0119] Furthermore, in each of the above-described embodiments and variants, a P-type transistor is formed at the bottom of the cell and an N-type transistor is formed at the top of the cell, but this is not limited to this, and a P-type transistor may be formed at the top of the cell and an N-type transistor may be formed at the bottom of the cell.

[0120] Furthermore, in each of the above-described embodiments and variants, the standard cells having logic functions are described as inverter cells, but the standard cells having logic functions may also be other cells (NAND, NOR, flip-flops, etc.).

[0121] In the present disclosure, with respect to filler cells using CFETs, it is possible to improve the accuracy of estimating the transistor performance of standard cells having logic functions in the layout of a semiconductor integrated circuit device including filler cells in which wiring is provided on the back side of the transistor.

[0122] 11, 12, 51 Power supply wiring 21, 22, 121 to 126 Nanosheet 31 Gate wiring 32, 33, 131 to 135 Dummy gate wiring 111, 112, 151 to 156 Wiring 41 to 44, 141 to 148 Local wiring 61 to 65 Via 2P1 to 2P6, 2N1 to 2N6 Active area P1, N1 Transistor DP1 to DP3, DN1 to DN3 Dummy transistor C1, C2, C4, C5 Inverter cell C3, C6 Filler cell

Claims

1. A semiconductor integrated circuit device comprising a first standard cell having a logic function and a second standard cell arranged adjacent to the first standard cell and having no logic function, wherein the first standard cell constitutes a channel, a source, and a drain of a first transistor of a first conductivity type, and as the channel, a first active region including a first nanosheet extending in a first direction; formed above the first active region in a depth direction, overlapping the first active region in a plan view, and constituting a channel, a source, and a drain of a second transistor of a second conductivity type different from the first conductivity type, and as the channel, a second active region including a second nanosheet extending in the first direction; a first power supply wiring formed on a back side of the first transistor, extending in the first direction, and supplying a first power supply voltage; a second power supply wiring extending in the first direction and supplying a second power supply voltage different from the first power supply voltage; a first via formed in a region where a region serving as a source of the first transistor in the first active region overlaps with the first power supply wiring, and connecting the source of the first transistor in the first active region and the first power supply wiring, wherein the second power supply wiring is connected to a source of the second transistor in the second active region, and the second standard cell is formed in the same layer as the first active region in the depth direction, and constitutes a channel, a source, and a drain of a first dummy transistor of the first conductivity type, and as the channel, a third active region including a third nanosheet extending in the first direction; is formed in the same layer as the second active region in the depth direction, and constitutes a channel, a source, and a drain of a second dummy transistor of the second conductivity type, and as the channel, a fourth active region including a fourth nanosheet extending in the first direction.In a second direction perpendicular to the first direction and the depth direction, between an end portion on a first side, which is one side in the second direction of the third active region, and an end portion on a second side, which is the other side in the second direction, an end portion on the first side and an end portion on the second side of the first active region are arranged. A semiconductor integrated circuit device.

2. The semiconductor integrated circuit device according to claim 1, wherein in the second direction, between the end portion on the first side and the end portion on the second side of the fourth active region, the end portion on the first side and the end portion on the second side of the second active region are arranged. A semiconductor integrated circuit device.

3. The semiconductor integrated circuit device according to claim 1, wherein the first standard cell further includes a gate wiring that extends in the second direction and the depth direction and serves as the gates of the first and second transistors. The second standard cell further includes a first dummy gate wiring that extends in the second direction and the depth direction and serves as the gates of the first and second dummy transistors. At the boundary between the first standard cell and the second standard cell, a second dummy gate wiring that extends in the second direction and the depth direction is provided. The gate wiring, the first dummy gate wiring, and the second dummy gate wiring are arranged at the same pitch in the first direction. A semiconductor integrated circuit device.

4. In the semiconductor integrated circuit device according to claim 1, the first standard cell further includes: a first local wiring extending in the second direction and connected to the source of the first transistor in the first active region; a second local wiring extending in the second direction and connected to the drain of the first transistor in the first active region; a third local wiring extending in the second direction and connected to the source of the second transistor in the second active region; and a fourth local wiring extending in the second direction and connected to the drain of the second transistor in the second active region. The second standard cell further includes: a fifth local wiring extending in the second direction and connected to the source of the first dummy transistor in the third active region; a sixth local wiring extending in the second direction and connected to the drain of the first dummy transistor in the third active region; a seventh local wiring extending in the second direction and connected to the source of the second dummy transistor in the fourth active region; and an eighth local wiring extending in the second direction and connected to the drain of the second dummy transistor in the fourth active region. The first, second, fifth, and sixth local wirings are arranged in the same layer in the depth direction and at the same pitch in the first direction. The third, fourth, seventh, and eighth local wirings are arranged in the same layer in the depth direction and at the same pitch in the first direction. A semiconductor integrated circuit device.

5. In the semiconductor integrated circuit device according to claim 1, the second power supply wiring is formed above the second active region in the depth direction. A semiconductor integrated circuit device.

6. In the semiconductor integrated circuit device according to claim 5, the second standard cell extends in the first direction, is formed in the same layer as the first power supply wiring in the depth direction, and includes a third power supply wiring connected to the first power supply wiring; and a fourth power supply wiring that extends in the first direction, is formed in the same layer as the second power supply wiring in the depth direction, and is connected to the second power supply wiring. A semiconductor integrated circuit device.

7. In the semiconductor integrated circuit device according to claim 1, further comprising a third standard cell having a logic function, the third standard cell being formed in the same layer as the first active region in the depth direction and constituting a channel, a source, and a drain of a third transistor of the first conductivity type, the channel including a fifth active region including a fifth nanosheet extending in the first direction; formed in the same layer as the second active region in the depth direction and constituting a channel, a source, and a drain of a fourth transistor of the second conductivity type, the channel including a sixth active region including a sixth nanosheet extending in the first direction; a fifth power supply wiring that is formed in the same layer as the first power supply wiring in the depth direction, extends in the first direction, and is connected to the first power supply wiring; a sixth power supply wiring that is formed in the same layer as the second power supply wiring in the depth direction, extends in the first direction, and is connected to the second power supply wiring; and a third via that is formed in a region where a region serving as a source of the third transistor in the fifth active region overlaps with the fifth power supply wiring and connects the source of the third transistor in the third active region to the fifth power supply wiring. In a plan view, a width of the fifth active region in the second direction is smaller than a width of the first active region in the second direction. A semiconductor integrated circuit device.

8. In the semiconductor integrated circuit device according to claim 7, in a plan view, an end portion on the first side of the first active region, an end portion on the first side of the third active region, and an end portion on the first side of the fifth active region are arranged at the same position in the second direction. A semiconductor integrated circuit device.

9. The semiconductor integrated circuit device according to claim 7, wherein, in a plan view, the central portions of the first active region and the third active region in the second direction are arranged at the same position in the second direction.

10. The semiconductor integrated circuit device according to claim 1, wherein the first power supply wiring is arranged at the end portion on the first side of the first standard cell, and the second power supply wiring is formed in the same layer as the first power supply wiring in the depth direction and is arranged at the end portion on the second side of the first standard cell.

11. The semiconductor integrated circuit device according to claim 10, wherein the second standard cell further includes a third power supply wiring that extends in the first direction, is formed in the same layer as the first power supply wiring in the depth direction, is arranged at the end portion on the first side of the second standard cell, and is connected to the first power supply wiring, and a fourth power supply wiring that extends in the first direction, is formed in the same layer as the second power supply wiring in the depth direction, is arranged at the end portion on the first side of the second standard cell, and is connected to the second power supply wiring.

12. In the semiconductor integrated circuit device according to claim 10, further comprising a third standard cell having a logic function, wherein the third standard cell is formed in the same layer as the first active region in the depth direction, and constitutes a channel, a source, and a drain of a third transistor of the first conductivity type. As the channel, a fifth active region including a fifth nanosheet extending in the first direction, formed in the same layer as the second active region in the depth direction, and constituting a channel, a source, and a drain of a fourth transistor of the second conductivity type. As the channel, a sixth active region including a sixth nanosheet extending in the first direction, formed in the same layer as the first power supply wiring in the depth direction, extending in the first direction, and a fifth power supply wiring connected to the first power supply wiring, formed in the same layer as the second power supply wiring in the depth direction, extending in the first direction, and a sixth power supply wiring connected to the second power supply wiring, formed in a region where a region serving as a source of the third transistor in the fifth active region overlaps with the fifth power supply wiring, and a third via connecting the source of the third transistor in the third active region and the fifth power supply wiring. In a plan view, a semiconductor integrated circuit device in which a width of the fifth active region in the second direction is smaller than a width of the first active region in the second direction.

13. In the semiconductor integrated circuit device according to claim 12, in a plan view, an end portion on the first side of the first active region, an end portion on the first side of the third active region, and an end portion on the first side of the fifth active region are arranged at the same position in the second direction. A semiconductor integrated circuit device.

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