Electronic device and method for manufacturing electronic device

Abstract

This invention improves reliability of an electrode formed in an opening part.　This electronic device is provided with: an opening part in which the inner surface is insulated; and an electrode formed on the inner surface of the opening part. The electrode is provided with a metal lamination part in which metals with differing compositions or structures are laminated on the bottom surface of the opening part. The metal lamination part in which the metals are laminated may include a sputtering layer, an electroless plating layer laminated on the sputtering layer, and an electrolytic plating layer laminated on the electroless plating layer. The metal lamination part in which the metals are laminated may be positioned on the bottom surface of the opening part and on the side surface of the opening part.

Description

Electronic device and method for manufacturing the same

[0001] The present technology relates to an electronic device and a method for manufacturing the electronic device. More specifically, the present technology relates to an electronic device in which an electrode is formed in an opening and a method for manufacturing the electronic device.

[0002] Through electrodes are sometimes used to connect wiring in electronic devices. For example, a semiconductor package has been proposed in which conductor posts are formed in openings in a molding resin using a plating layer (see, for example, Patent Document 1).

[0003] JP 2017-103426 A

[0004] However, in the above-mentioned conventional technology, depending on the depth and shape of the opening, a step may occur in the seed layer used to form the plating layer, which may cause problems in forming the electrode using the plating layer.

[0005] This technology was developed in light of these circumstances, and aims to improve the reliability of the electrodes formed in the openings.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is an electronic device including an opening having an insulated inner surface and an electrode formed on the inner surface of the opening, the electrode including a metal laminate portion in which metals having different compositions or structures are laminated on the bottom surface of the opening, thereby improving coverage of the bottom surface of the opening.

[0007] In the first aspect, the metal laminated portion in which the metal is laminated may be located on the bottom surface of the opening and on the side surface of the opening, thereby improving coverage of the side surface of the opening.

[0008] In the first aspect, the texture may be a grain size, which provides the effect of laminating an electrolytic plated layer on an electroless plated layer.

[0009] In the first aspect, the metal laminate portion may include a sputtered layer, an electroless plated layer laminated on the sputtered layer, and an electrolytic plated layer laminated on the electroless plated layer, thereby providing an effect that the electrolytic plated layer is formed based on the sputtered layer and the electroless plated layer that are disconnected within the opening.

[0010] In the first aspect, the electroless plating layer may be selectively formed on the bottom surface of the opening via the sputtered layer, thereby preventing the electroless plating layer from being formed on the entire surface of the sputtered layer.

[0011] In the first aspect, the electroless plating layer may be selectively formed on the bottom surface and the side surface of the opening via the sputtered layer, thereby preventing the electroless plating layer from being formed on the entire surface of the sputtered layer.

[0012] In addition, in the first aspect, the sputtered layer on the bottom surface of the opening and the sputtered layer on the side surface of the opening may be separated from each other, and the electroless plated layer may be connected to the sputtered layer on the side surface of the opening via the electrolytic plated layer, thereby providing the effect of forming an electrolytic plated layer while filling in any discontinuities in the sputtered layer within the opening with the electroless plated layer.

[0013] In the first aspect, the semiconductor device may further include a wiring drawn out from the opening and connected to the electrode, the wiring including the sputtered layer and an electrolytic plating layer laminated on the sputtered layer, thereby providing an effect that the wiring connected to the electrode in the opening is configured without using an electroless plating layer.

[0014] In the first aspect, a diameter of the bottom surface of the opening may be larger than a diameter of the opening surface of the opening. This brings about an effect that the shape of the opening is determined based on the notching of the bottom surface of the opening.

[0015] In addition, in the first aspect, the semiconductor device may further include a first semiconductor chip having a first wiring layer formed on a first semiconductor substrate, a second semiconductor chip having a second wiring layer formed on a second semiconductor substrate and stacked on the first semiconductor chip so that the second wiring layer faces the first wiring layer, and through electrodes having the electrodes formed thereon and penetrating the first semiconductor chip to be connected to the second wiring layer, thereby providing an effect of reducing connection defects of through electrodes that penetrate the semiconductor chip and are connected to the wiring layer while dealing with an increase in the depth of the through holes.

[0016] In addition, in the first aspect, the semiconductor device may further include a first semiconductor chip having a first wiring layer formed on a first semiconductor substrate, a second semiconductor chip having a second wiring layer formed on a second semiconductor substrate and stacked on the first semiconductor chip so that the second wiring layer faces the first wiring layer, and through electrodes having the electrodes formed thereon and penetrating the first semiconductor substrate to be connected to the first wiring layer, thereby providing an effect of reducing connection defects of through electrodes that penetrate the semiconductor substrate and are connected to the wiring layer while accommodating an increase in the depth of the through holes.

[0017] In addition, in a first aspect, the semiconductor device may further include a first semiconductor chip having a first wiring layer formed on a first semiconductor substrate, a second semiconductor chip having a second wiring layer formed on a second semiconductor substrate and stacked on the first semiconductor chip so that the second wiring layer faces the first wiring layer, a buried layer formed on the first semiconductor chip so that the second semiconductor chip is buried, a third semiconductor chip having a third wiring layer formed on a third semiconductor substrate and stacked on the buried layer, and through electrodes formed on the third semiconductor chip and the second semiconductor chip and connected to the first wiring layer. This provides the effect of reducing connection defects of through electrodes that penetrate multiple semiconductor chips and are connected to the wiring layer while accommodating an increase in the depth of the through holes.

[0018] In addition, in a first aspect, the semiconductor device may further include a first semiconductor chip having a first wiring layer formed on a first semiconductor substrate, a second semiconductor chip having a second wiring layer formed on a second semiconductor substrate and stacked on the first semiconductor chip so that the second wiring layer faces the first wiring layer, a buried layer formed on the first semiconductor chip so that the second semiconductor chip is buried, a third semiconductor chip having a third wiring layer formed on a third semiconductor substrate and stacked on the buried layer, and through electrodes formed on the third semiconductor chip and penetrating the third semiconductor chip and the buried layer to be connected to the first wiring layer. This provides the effect of reducing connection defects of through electrodes that penetrate the semiconductor chip and the buried layer to be connected to the wiring layer while accommodating an increase in the depth of the through holes.

[0019] In addition, in the first aspect, a capacitor may be provided that is located within the opening and formed on the electrode, thereby improving coverage of the bottom surface of the opening and forming a capacitor within the opening.

[0020] In the first aspect, the capacitor may include a first capacitor electrode formed on the electrode and a second capacitor electrode formed on the first capacitor electrode with a dielectric layer interposed therebetween, thereby providing an effect of forming a capacitor within the opening while ensuring selectivity of the material of the capacitor electrode.

[0021] In the first aspect, the capacitor may include a first capacitor electrode that also serves as the electrode, and a second capacitor electrode formed on the first capacitor electrode via a dielectric layer, thereby simplifying the formation of the capacitor electrode and forming a capacitor within the opening.

[0022] In the first aspect, an insulating layer may be formed on the capacitor through a cavity in the opening, thereby protecting the capacitor formed in the opening without filling the opening.

[0023] In the first aspect, a buried layer may be formed on the capacitor so as to be embedded in the opening, thereby providing an effect that the capacitor formed in the opening is covered with the buried layer.

[0024] A second aspect of the present invention is a method for manufacturing an electronic device, comprising the steps of forming a sputtered layer on an inner surface of an opening, forming an insulating layer on the sputtered layer, removing the insulating layer from the sputtered layer on the bottom surface of the opening, forming an electroless plating layer on the sputtered layer on the bottom surface of the opening, removing the insulating layer in the opening after forming the electroless plating layer, and forming an electrolytic plating layer on the sputtered layer and the electroless plating layer, thereby forming a three-layer structure including the sputtered layer, the electroless plating layer, and the electrolytic plating layer on the bottom surface of the opening.

[0025] In a second aspect, the sputtered layer on the side surface of the opening may be separated from the sputtered layer and the electroless plated layer on the bottom surface of the opening, and the electroless plated layer may be connected to the sputtered layer on the side surface of the opening via the electrolytic plated layer, thereby providing the effect of forming an electrolytic plated layer while filling in any discontinuities in the sputtered layer within the opening with the electroless plated layer.

[0026] 10 is a cross-sectional view showing a configuration example of an electronic device according to a first embodiment. FIG. 11 is a cross-sectional view showing another example of the configuration of an electronic device according to the first embodiment. FIG. 12 is a cross-sectional view showing yet another example of the configuration of an electronic device according to the first embodiment. FIG. 13 is a cross-sectional view showing yet another example of the configuration of an electronic device according to the first embodiment. FIG. 14 is a cross-sectional view showing an example of a method for manufacturing an electronic device according to the first embodiment. FIG. 15 is a cross-sectional view showing an example of a method for manufacturing an electronic device according to the first embodiment. FIG. 16 is a cross-sectional view showing an example of a method for manufacturing an electronic device according to the first embodiment. FIG. 17 is a cross-sectional view showing an example of a configuration example of an electronic device according to a second embodiment. FIG. 18 is a cross-sectional view showing yet another example of the configuration of an electronic device according to the second embodiment. FIG. 19 is a cross-sectional view showing an example of a configuration example of an electronic device according to a third embodiment. FIG. 19 is a cross-sectional view showing yet another example of the configuration of an electronic device according to the ... 13A and 13B are cross-sectional views showing a configuration example of an electronic device according to an eighth embodiment; FIG. 14A is a cross-sectional view showing a configuration example of an electronic device according to a ninth embodiment; FIG. 15A is a cross-sectional view showing a configuration example of an electronic device according to a tenth embodiment; FIG. 16B is a cross-sectional view showing a configuration example of an electronic device according to an eleventh embodiment; FIG. 17A is a cross-sectional view showing a configuration example of an electronic device according to a twelfth embodiment; FIG. 18A is a cross-sectional view showing a configuration example of an electronic device according to a thirteenth embodiment; FIG. 19A is a cross-sectional view showing a configuration example of an electronic device according to a fourteenth embodiment; FIG. 19B is a cross-sectional view showing a configuration example of an electronic device according to a fifteenth embodiment; FIG. 20A is a cross-sectional view showing a configuration example of an electronic device according to a sixteenth embodiment; FIG. 21B is a cross-sectional view showing an example of a configuration of an electronic device according to a seventeenth embodiment; and FIG. 21C is a cross-sectional view showing an example of a method for manufacturing an electronic device according to the seventeenth embodiment.18. A cross-sectional view showing a configuration example of an electronic device according to an eighteenth embodiment. 19. A cross-sectional view showing another example of the configuration of an electronic device according to an eighteenth embodiment. 20. A cross-sectional view showing an example of a method for manufacturing an electronic device according to an eighteenth embodiment. 21. A cross-sectional view showing an example of a method for manufacturing an electronic device according to an eighteenth embodiment. 22. A cross-sectional view showing another example of the configuration of an electronic device according to an nineteenth embodiment. 23. A cross-sectional view showing an example of a configuration of an electronic device according to an twentieth embodiment. 24. A cross-sectional view showing an example of a method for manufacturing an electronic device according to an eighteenth embodiment. 25. A cross-sectional view showing an example of a configuration of an electronic device according to an nineteenth embodiment. 26. A cross-sectional view showing another example of the configuration of an electronic device according to an twentieth embodiment. 27. A cross-sectional view showing an example of a configuration of an electronic device according to an twenty-first embodiment. 28. A cross-sectional view showing another example of the configuration of an electronic device according to an twenty-first embodiment. 29. A cross-sectional view showing an example of a configuration of an electronic device according to an twenty-second embodiment. 29. A cross-sectional view showing an example of a method for manufacturing an electronic device according to an twenty-second embodiment. 20. A cross-sectional view showing an example of a method for manufacturing an electronic device according to an twenty-second embodiment. 21. A cross-sectional view showing an example of a method for manufacturing an electronic device according to an twenty-third embodiment. 22. A cross-sectional view showing an example of a configuration of an electronic device according to an twenty-fourth embodiment. 23. A cross-sectional view showing an example of a configuration of an electronic device according to an twenty-fourth embodiment. 24. A cross-sectional view showing an example of a method for manufacturing an electronic device according to an twenty-fourth embodiment. 25. A cross-sectional view showing an example 25. A cross-sectional view showing an example of a method for manufacturing an electronic device according to a 25th embodiment. A cross-sectional view showing an example of a configuration of an electronic device according to a 26th embodiment. A cross-sectional view showing an example of a method for manufacturing an electronic device according to a 26th embodiment. A cross-sectional view showing an example of a method for manufacturing an electronic device according to a 26th embodiment. A cross-sectional view showing an example of a configuration of an electronic device according to a 27th embodiment. A cross-sectional view showing an example of a method for manufacturing ... configuration of an electronic device according to a 28th embodiment. A diagram showing an example of a method for manufacturing an electronic device according to a 28th embodiment. A diagram showing an example of a method for manufacturing an electronic device according to a 28th embodiment. A diagram showing an example of a method for manufacturing an electronic device according to a 28th embodiment.28. A diagram showing an example of a manufacturing method for an electronic device according to a 28th embodiment. A diagram showing an example of a manufacturing method for an electronic device according to a 28th embodiment. A diagram showing an example of a manufacturing method for an electronic device according to a 28th embodiment. A cross-sectional view showing an example of a configuration of an electronic device according to a 29th embodiment. A diagram showing an example of a manufacturing method for an electronic device according to a 29th embodiment. A diagram showing an example of a manufacturing method for an electronic device according to a 29th embodiment. A diagram showing an example of a manufacturing method for an electronic device according to a 29th embodiment. A diagram showing an example of a manufacturing method for an electronic device according to a 29th embodiment. A diagram showing an example of a manufacturing method for an electronic device according to a 29th embodiment. A cross-sectional view showing an example of a configuration of an electronic device according to a 30th embodiment. A cross-sectional view showing an example of a configuration of an electronic device according to a 31st embodiment. A cross-sectional view showing an example of a configuration of an electronic device according to a 32nd embodiment. A cross-sectional view showing an example of a configuration of an electronic device according to a 33rd embodiment. A cross-sectional view showing an example of a configuration of an electronic device according to a 34th embodiment. A cross-sectional view showing an example of a configuration of an electronic device according to a 35th embodiment. A cross-sectional view showing an example of a configuration of an electronic device according to a 36th embodiment. A block diagram showing an example of a schematic configuration of a vehicle control system. An explanatory diagram showing an example of installation positions of an outside vehicle information detection unit and an imaging unit.

[0027] Modes for carrying out the present technology (hereinafter referred to as embodiments) will be described below. The descriptions will be given in the following order: 1. First embodiment (an example in which a metal laminate portion having a sputtered layer, an electroless plated layer, and an electrolytic plated layer stacked in sequence is provided on the bottom surface of an opening); 2. Second embodiment (an example in which a metal laminate portion having a sputtered layer, an electroless plated layer, and an electrolytic plated layer stacked in sequence is provided on the bottom surface of an opening via a barrier metal film); 3. Third embodiment (an example in which a metal laminate portion having a sputtered layer, an electroless plated layer, and an electrolytic plated layer stacked in sequence is provided on the bottom surface of an opening, and the cross section of the electroless plated layer is convex); 4. Fourth embodiment (an example in which a metal laminate portion having a sputtered layer, an electroless plated layer, and an electrolytic plated layer stacked in sequence is provided on the bottom surface of an opening, and a part of the sputtered layer is exposed when the electroless plated layer is formed); 5. Fifth embodiment (an example in which a metal laminate portion having a sputtered layer, an electroless plated layer, and an electrolytic plated layer stacked in sequence is provided on the bottom surface and side surfaces of an opening); 6. 6. Sixth embodiment (an example in which a metal laminate portion having a sputtered layer, an electroless plated layer, and an electrolytic plated layer laminated in sequence is provided on the bottom surface of an opening, and the entire opening is filled with an electrolytic plated layer) 7. Seventh embodiment (an example in which a metal laminate portion having a sputtered layer, an electroless plated layer, and an electrolytic plated layer laminated in sequence connects a through electrode provided on the bottom surface of an opening to a lower chip through an upper chip) 8. Eighth embodiment (an example in which a metal laminate portion having a sputtered layer, an electroless plated layer, and an electrolytic plated layer laminated in sequence connects a through electrode provided on the bottom surface of an opening to a lower chip through an upper chip, and the upper chip and the lower chip are joined based on hybrid bonding) 9. Ninth embodiment (an example in which a metal laminate portion having a sputtered layer, an electroless plated layer, and an electrolytic plated layer laminated in sequence connects a through electrode provided on the bottom surface of an opening to a lower chip through an upper chip, and the upper chip and the lower chip are joined via an adhesive layer) 10. Tenth embodiment (an example in which a metal laminated portion, in which a sputtered layer, an electroless plated layer, and an electrolytic plated layer are sequentially laminated, connects a through electrode provided on the bottom surface of an opening to a lower chip through an upper chip, and the upper chip is laminated on a lower chip based on CoW (Chip on Wafer))11. Eleventh embodiment (an example in which a metal laminate portion in which a sputtered layer, an electroless plated layer, and an electrolytic plated layer are sequentially stacked connects a through electrode provided on the bottom surface of an opening to a lower chip through an upper chip, the upper chip is stacked on a lower chip based on CoW, and the upper chip and the lower chip are joined based on hybrid bonding) 12. Twelfth embodiment (an example in which a metal laminate portion in which a sputtered layer, an electroless plated layer, and an electrolytic plated layer are sequentially stacked connects a through electrode provided on the bottom surface of an opening to a lower chip through a buried layer around the upper chip, and the upper chip is stacked on a lower chip based on CoW) 13. Thirteenth embodiment (an example in which a metal laminate portion in which a sputtered layer, an electroless plated layer, and an electrolytic plated layer are sequentially stacked connects a through electrode provided on the bottom surface of an opening to a lower chip through a buried layer around the upper chip, and the upper chip is stacked on a lower chip based on CoW, and the upper chip is joined to a lower chip based on hybrid bonding) 14. 14th embodiment (an example in which a metal laminate portion having a sputtered layer, an electroless plated layer, and an electrolytic plated layer laminated in sequence leads out wiring via a through electrode provided on the bottom surface of an opening) 15. 15th embodiment (an example in which a metal laminate portion having a sputtered layer, an electroless plated layer, and an electrolytic plated layer laminated in sequence connects a through electrode provided on the bottom surface of an opening to a lower chip through an upper chip and an intermediate chip) 16. 16th embodiment (an example in which a metal laminate portion having a sputtered layer, an electroless plated layer, and an electrolytic plated layer laminated in sequence connects a through electrode provided on the bottom surface of an opening to a lower chip through a buried layer in which the upper chip and the intermediate chip are buried) 17. 17th embodiment (an example in which a metal laminate portion having a sputtered layer, an electroless plated layer, and an electrolytic plated layer laminated in sequence leads out wiring from a semiconductor chip on a sensor chip via a through electrode provided on the bottom surface of an opening) 18. 18. Eighteenth embodiment (an example in which a capacitor is provided on a metal laminate portion in which a sputtered layer, an electroless plated layer, and an electrolytic plated layer are sequentially laminated in an opening) 19. Nineteenth embodiment (an example in which a capacitor is provided on a metal laminate portion in which a sputtered layer, an electroless plated layer, and an electrolytic plated layer are sequentially laminated in an opening, and an insulating layer is formed along the surface of the capacitor)20. Twentieth embodiment (an example in which a capacitor is provided on a metal laminate portion in which a sputtered layer, an electroless plated layer, and an electrolytic plated layer are sequentially laminated in an opening, and a buried layer is formed on the capacitor so as to be buried in the opening) 21. Twenty-first embodiment (an example in which a capacitor is provided on a metal laminate portion in which a sputtered layer, an electroless plated layer, and an electrolytic plated layer are sequentially laminated in an opening, and a through electrode also serves as a first capacitor electrode) 22. Twenty-second embodiment (an example in which a metal laminate portion in which a sputtered layer, an electroless plated layer, and an electrolytic plated layer are sequentially laminated is provided on the bottom surface of an opening, and a photosensitive insulating film is buried in the skirting portion of the bottom surface of the opening) 23. Twenty-third embodiment (an example in which a metal laminate portion in which a sputtered layer, an electroless plated layer, and an electrolytic plated layer are sequentially laminated is provided on the bottom surface of an opening, and a barrier metal layer configured to include an ALD (Atomic Layer Deposition) film is provided below the sputtered layer) 24. 24th embodiment (an example in which a metal laminate portion having a sputtered layer, an electroless plated layer, and an electrolytic plated layer laminated in that order is provided on the bottom surface of an opening, and electroless plating is added around the periphery of the electroless plated layer) 25. 25th embodiment (an example in which a metal laminate portion having a sputtered layer, an electroless plated layer, and an electrolytic plated layer laminated in that order is provided on the bottom surface of an opening in which a plurality of footing portions are formed at different depth positions) 26. 26th embodiment (an example in which a metal laminate portion having a sputtered layer, an electroless plated layer, and an electrolytic plated layer laminated in that order is provided on the bottom surface of an opening, and a SIMOX (Separation by Implanted Oxygen) layer is provided over the entire substrate at a midpoint in the depth direction of the opening so as to surround the periphery of the opening) 27. 27. 27th embodiment (an example in which a metal laminate portion in which a sputtered layer, an electroless plated layer, and an electrolytic plated layer are sequentially laminated is provided on the bottom surface of an opening, and a SIMOX layer is provided in a part of the substrate at a midpoint in the depth direction of the opening so as to surround the periphery of the opening) 28. 28th embodiment (an example in which a metal laminate portion in which an electroless plated layer, a sputtered layer, and an electrolytic plated layer are sequentially laminated is provided on the bottom surface of an opening, the electroless plated layer is embedded in a wiring layer provided below the opening, and no wiring exists below the electroless plated layer)29. Twenty-ninth embodiment (an example in which a metal laminate portion having an electroless plated layer, a sputtered layer, and an electrolytic plated layer sequentially laminated thereon is provided on the bottom surface of an opening, the electroless plated layer is embedded in a wiring layer provided below the opening, and wiring exists below the electroless plated layer) 30. Thirtieth embodiment (an example in which a metal laminate portion having an electroless plated layer, a sputtered layer, and an electrolytic plated layer sequentially laminated thereon is provided on the bottom surface of an opening, and the electroless plated layer is embedded in a wiring layer provided below an opening that expands in the depth direction) 31. Thirty-first embodiment (an example in which a metal laminate portion having an electroless plated layer and an electrolytic plated layer sequentially laminated thereon is provided on the bottom surface of an opening, and a via embedded in a semiconductor substrate is formed below the electroless plated layer, and the via is composed of a sputtered film) 32. Thirty-second embodiment (an example in which a metal laminate portion having an electroless plated layer and an electrolytic plated layer sequentially laminated thereon is provided on the bottom surface of an opening, and a via embedded in a semiconductor substrate is formed below the electroless plated layer, and the via is composed of a plated film and a sputtered film thereon) 33. 33rd embodiment (an example in which a metal laminate portion in which an electroless plated layer and an electrolytic plated layer are sequentially laminated is provided on the bottom surface of an opening, and wiring embedded in a semiconductor substrate is formed below the electroless plated layer) 34. 34th embodiment (an example in which a metal laminate portion in which an electroless plated layer, a sputtered layer, and an electrolytic plated layer are sequentially laminated is provided on the bottom surface of an opening, and the electroless plated layer is embedded in a wiring layer provided below the opening, and the electroless plated layer protrudes from the wiring layer, and no wiring exists below the electroless plated layer) 35. 35th embodiment (an example in which a metal laminate portion in which an electroless plated layer, a sputtered layer, and an electrolytic plated layer are sequentially laminated is provided on the bottom surface of an opening, and the electroless plated layer is embedded in a wiring layer provided below the opening, and the electroless plated layer protrudes from the wiring layer, and wiring exists below the electroless plated layer) 36. 36th embodiment (an example in which a metal laminated portion in which an electroless plated layer, a sputtered layer, and an electrolytic plated layer are laminated in this order is provided on the bottom surface of an opening, the electroless plated layer is embedded in a wiring layer provided below the opening that widens in the depth direction, the electroless plated layer protrudes from the wiring layer, and wiring exists below the electroless plated layer) 37. Application example to a moving body

[0028] 1 is a cross-sectional view showing an example of the configuration of an electronic device according to a first embodiment. Note that the drawings used in the following description may differ in scale and shape from the actual structure in order to make each component easier to understand.

[0029] In the figure, the electronic device is provided with a through-electrode TV1. The through-electrode TV1 may be formed on a semiconductor substrate, an insulating substrate, a mounting substrate, or a wiring layer. The electronic device may include a semiconductor device, an optical device, a MEMS (Micro Electro Mechanical Systems), a display device, or an antenna element.

[0030] The semiconductor device may include a memory, a processor, a signal processing circuit, a data processing circuit, or an interface circuit. The semiconductor device may include a hardware circuit such as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). The semiconductor material used for the semiconductor device may be Si, GaAs, SiC, GaN, InGaAsP, or the like.

[0031] The optical device may be an image sensor such as a CCD (Charged Coupled Device) sensor, a CMOS (Complementary Metal-Oxide Semiconductor) sensor, or a SPAD (Single Photon Avalanche Diode) sensor. The light received by the image sensor may be visible light, near infrared light (NIR: Near Infrared), short wavelength infrared light (SWIR: Short Wavelength Infrared), ultraviolet light, or X-rays. The optical device may be a light receiving element such as a PD (Photo Diode), or a light emitting element such as an LD (Laser Diode), an LED (Light Emitting Diode), or a VCSEL (Vertical Cavity Surface Emitting Laser). The optical material used in the optical device may be a semiconductor such as Si, GaAs, or InGaAs, or LiNbO ３ , or may be a dielectric material such as glass or transparent resin.

[0032] The MEMS may be an optical switch, an optical scanner, a DMD (Digital Micromirror Device), a pressure sensor, a flow sensor, or a gyroscope.

[0033] The display device may be a liquid crystal display, an organic electroluminescence (EL) display, or a micro LED display.

[0034] A wiring layer 112 is formed on the semiconductor substrate 111. The through-electrodes TV1 penetrate the semiconductor substrate 111 and are connected to the wiring layer 112. In the wiring layer 112, wiring 113 embedded in an insulating layer is formed.

[0035] An opening 114 is also formed in the semiconductor substrate 111. The opening 114 can penetrate the semiconductor substrate 111 and reach the wiring layer 112. The opening 114 may be cylindrical in shape. The through electrode TV1 can be formed along the inner surface of the opening 114. The through electrode TV1 includes a metal stack portion MT1 located on the bottom surface of the opening 114. The metal stack portion MT1 is formed by stacking metals having different compositions or structures. The structure is, for example, grain size. The through electrode TV1 is an example of an electrode as defined in the claims.

[0036] The inner surface of the opening 114 is insulated to insulate the through electrode TV1 from the semiconductor substrate 111. At this time, an insulating layer 115 can be formed on the inner surface of the opening 114. The insulating layer 115 may be formed continuously from the side surface of the opening 114 to the rear surface of the semiconductor substrate 111.

[0037] The sputtered layer 116 can be formed on the bottom surface of the opening 114, and can also be formed on the side surface of the opening 114 and the rear surface of the semiconductor substrate 111 via the insulating layer 115. This sputtered layer 116 can be used as a seed layer for forming the electrolytic plating layer 119. A barrier metal layer may be present below the seed layer. The sputtered layer 116 on the bottom surface of the opening 114 may be separated from the sputtered layer 116 on the side surface of the opening 114.

[0038] An electroless plated layer 118 is formed on the sputtered layer 116 on the bottom surface of the opening 114. An insulating layer 117 is formed on the side surface of the electroless plated layer 118. The insulating layer 117 can be used to selectively form the electroless plated layer 118 on the sputtered layer 116 on the bottom surface of the opening 114. The insulating layer 117 can be formed on the side surface of the opening 114 before the formation of the electroless plated layer 118. After the formation of the electroless plated layer 118, the insulating layer 117 on the side surface of the opening 114 can be removed before the formation of the electrolytic plated layer 119. In this case, the insulating layer 117 can remain only on the side surface of the electroless plated layer 118.

[0039] An electrolytic plated layer 119 is formed on electroless plated layer 118 and insulating layer 117. At this time, electrolytic plated layer 119 can be continuously formed from electroless plated layer 118 and insulating layer 117, through sputtered layer 116, onto the side surface of opening 114 and onto the rear surface of semiconductor substrate 111.

[0040] The insulating layers 115 and 117 are made of, for example, SiO ２ Alternatively, an inorganic material such as SiN or SiCN may be used, or an organic material such as polyimide may be used.

[0041] In this case, the metal laminate unit MT1 on the bottom surface of the opening 114 can have a three-layer structure consisting of a sputtered layer 116, an electroless plated layer 118, and an electrolytic plated layer 119. The sputtered layer 116, the electroless plated layer 118, and the electrolytic plated layer 119 can be composed of Cu, Ni, Sn, Ag, An, or a combination thereof. The sputtered layer 116, the electroless plated layer 118, and the electrolytic plated layer 119 can also be composed of a single metal such as Cu. In this case, the grain sizes of the sputtered layer 116, the electroless plated layer 118, and the electrolytic plated layer 119 can be made different from one another.

[0042] The material of the electroless plated layer 118 may be Co (cobalt). By using cobalt as the material of the electroless plated layer 118, it is possible to improve electromigration resistance. In addition, it is possible to improve the efficiency of electrolytic plating and suppress compatibility with Cu.

[0043] Here, electroless plating layer 118 is formed on sputtered layer 116 on the bottom surface of opening 114, and then electrolytic plating layer 119 is formed. As a result, even if a step is generated in sputtered layer 116 as the aspect ratio of opening 114 increases, the conductivity of through electrode TV1 on the bottom surface of opening 114 can be ensured, and open defects can be reduced.

[0044] FIG. 2 is a cross-sectional view showing another example of the configuration of the electronic device according to the first embodiment.

[0045] In the figure, this electronic device has a through electrode TV2 and an insulating layer 125 instead of the through electrode TV1 and insulating layer 115 in Fig. 1. Other configurations of this electronic device are the same as those of the electronic device in Fig. 1.

[0046] At this time, an opening 124 is formed in the semiconductor substrate 111. The opening 124 can penetrate the semiconductor substrate 111 and reach the wiring layer 112. The shape of the opening 124 may widen toward the bottom surface. In this case, the diameter of the bottom surface of the opening 124 can be larger than the diameter of the opening surface of the opening 124. For example, the bottom of the opening 124 may be notched. The through electrode TV2 can be formed along the inner surface of the opening 124. The through electrode TV2 includes a metal stack portion MT2 located on the bottom surface of the opening 124. The metal stack portion MT2 is formed by stacking metals having different compositions or structures.

[0047] An insulating layer 125 is formed on the inner surface of the opening 124. The insulating layer 125 may be formed continuously from the side surface of the opening 124 to the rear surface of the semiconductor substrate 111.

[0048] The sputtered layer 126 can be formed on the bottom surface of the opening 124, and can also be formed on the side surface of the opening 124 and the rear surface of the semiconductor substrate 111 via the insulating layer 125. Here, the sputtered layer 126 may be separated between the bottom surface and the side surface of the opening 124. This sputtered layer 126 can be used as a seed layer for forming the electrolytic plating layer 129.

[0049] An electroless plated layer 128 is formed on the sputtered layer 126 on the bottom surface of the opening 124. The side surface of the electroless plated layer 128 may be warped. The electroless plated layer 128 can penetrate into the separated portion of the sputtered layer 126 between the bottom surface and the side surface of the opening 124. In this case, the electroless plated layer 128 may be separated from the sputtered layer 126 on the side surface of the opening 124.

[0050] An electrolytic plating layer 129 is formed on the electroless plating layer 128. The electrolytic plating layer 129 can be continuously formed from the electroless plating layer 128, via the sputtered layer 126, onto the side surface of the opening 124, and onto the back surface of the semiconductor substrate 111. Even if the electroless plating layer 128 and the sputtered layer 126 on the side surface of the opening 124 are separated, the electrolytic plating layer 129 can be formed on the sputtered layer 126 on the side surface of the opening 124 using the sputtered layer 126 as a seed layer. As the electrolytic plating layer 129 grows, it thickens, allowing the electrolytic plating layer 129 to come into contact with the electroless plating layer 128. This allows electrical conduction between the sputtered layer 126 on the bottom surface and the electrolytic plating layer 129 via the electroless plating layer 128. At this time, the metal laminated portion MT2 on the bottom surface of the opening 124 can use a three-layer structure of a sputtered layer 126, an electroless plated layer 128, and an electrolytic plated layer 129.

[0051] Here, electroless plating layer 128 is formed on sputtered layer 126 on the bottom surface of opening 124, and then electrolytic plating layer 129 is formed. This ensures the conductivity of through electrode TV2 on the bottom surface of opening 124 even when a step occurs in sputtered layer 126 due to notching at the bottom of opening 124, thereby reducing open defects.

[0052] FIG. 3 is a cross-sectional view showing still another example of the configuration of the electronic device according to the first embodiment.

[0053] In the figure, this electronic device has a through electrode TV3, an opening 134, and an insulating layer 135 instead of the through electrode TV1, the opening 114, and the insulating layer 115 in Figure 1. Other configurations of this electronic device are the same as those of the electronic device in Figure 1.

[0054] The through electrode TV3 is embedded in the opening 134. The diameter of the opening 134 decreases toward the bottom. At this time, the side surfaces of the opening 134 may be inclined. For example, the three-dimensional shape of the opening 134 may be a shot glass shape or a flowerpot shape. The through electrode TV3 includes an insulating layer 137, a sputtered layer 136, an electroless plated layer 138, and an electrolytic plated layer 139 instead of the insulating layer 117, the sputtered layer 116, the electroless plated layer 118, and the electrolytic plated layer 119 in FIG. 1 .

[0055] The insulating layer 135 can be formed continuously from the side surface of the opening 134 to the rear surface of the semiconductor substrate 111. The insulating layer 137 is formed on the side surface of the electroless plated layer 138.

[0056] The sputtered layer 136 can be formed on the bottom surface of the opening 134 and can also be continuously formed on the side surface of the opening 134 and the rear surface of the semiconductor substrate 111 via the insulating layer 135 .

[0057] The electroless plating layer 138 is formed on the sputtered layer 136 on the bottom surface of the opening 134. The three-dimensional shape of the electroless plating layer 138 may be, for example, an inverted truncated cone.

[0058] Electrolytic plated layer 139 is formed continuously from electrolessly plated layer 138 and insulating layer 137 through sputtered layer 136 onto the side surface of opening 134 and the rear surface of semiconductor substrate 111 .

[0059] FIG. 4 is a cross-sectional view showing still another example of the configuration of the electronic device according to the first embodiment.

[0060] In the figure, this electronic device has a through electrode TV4 instead of the through electrode TV2 in Fig. 2. Other configurations of this electronic device are the same as those of the electronic device in Fig. 2.

[0061] The through electrode TV4 includes a sputtered layer 146, an electroless plated layer 148, and an electrolytic plated layer 149 instead of the sputtered layer 126, the electroless plated layer 128, and the electrolytic plated layer 129 in Fig. 2. Furthermore, the through electrode TV4 has an insulating layer 147 added to the electronic device in Fig. 2. Other configurations of the through electrode TV4 are the same as those of the through electrode TV2 in Fig. 2.

[0062] The sputtered layer 146 can be formed on the bottom surface of the opening 124 and can also be continuously formed on the side surface of the opening 124 and the rear surface of the semiconductor substrate 111 via the insulating layer 125 .

[0063] The electroless plated layer 148 is formed on the sputtered layer 146 on the bottom surface of the opening 124. The insulating layer 147 is formed on the side surface of the electroless plated layer 148.

[0064] Electrolytic plated layer 149 is formed on the bottom surface of opening 124, on electroless plated layer 148 and insulating layer 147. At this time, electrolytic plated layer 149 can be continuously formed from electroless plated layer 148 and insulating layer 147, via sputtered layer 146, onto the side surface of opening 124 and the rear surface of semiconductor substrate 111.

[0065] 5 to 7 are cross-sectional views showing an example of a method for manufacturing an electronic device according to the first embodiment. Note that, although Fig. 5 to Fig. 7 show an example of a method for manufacturing the electronic device shown in Fig. 2, the method may also be applied to a method for manufacturing the electronic device shown in Fig. 1, Fig. 3, or Fig. 4.

[0066] 5A, a wiring layer 112 is formed on a semiconductor substrate 111. Note that transistors, diodes, resistors, capacitors, etc. may also be formed on the semiconductor substrate 111. Then, a resist pattern PA is formed on the back surface of the semiconductor substrate 111 based on lithography technology. An opening KA is formed in the resist pattern PA at a position where the opening 124 is to be formed.

[0067] 5B, the semiconductor substrate 111 is etched using the resist pattern PA as an etching mask, thereby forming an opening 124 in the semiconductor substrate 111. At this time, a notch may be formed at the bottom of the opening 124. The etching of the semiconductor substrate 111 can be performed by dry etching such as RIE (Reactive Ion Etching).

[0068] Next, as shown in FIG. 5c, an insulating layer 125 is formed on the bottom and side surfaces of the opening 124 and on the rear surface of the semiconductor substrate 111 by a method such as CVD (Chemical Vapor Deposition).

[0069] Next, as shown in FIG. 6A, the bottom surface of the opening 124 is selectively etched through the opening 124 to remove the insulating layer 125 on the wiring layer 112 in the opening 124.

[0070] 6B, a sputtered layer 126 is formed by sputtering on the bottom and side surfaces of the opening 124 and on the rear surface of the semiconductor substrate 111. At this time, the sputtered layer 126 may be separated between the bottom surface and the side surface of the opening 124.

[0071] 6c, an insulating layer 127 is formed on the sputtered layer 126 by a method such as CVD. The insulating layer 127 can also be formed on the insulating layer 125 exposed from the sputtered layer 126 between the bottom and side surfaces of the opening 124.

[0072] Next, as shown in FIG. 7A, the bottom surface of the opening 124 is selectively etched through the opening 124 to remove the insulating layer 127 on the sputtered layer 126 on the bottom surface of the opening 124.

[0073] Next, as shown in FIG. 7B, an electroless plating layer 128 is selectively formed on the sputtered layer 126 on the bottom surface of the opening 124 by electroless plating. The electroless plating layer 128 may extend beyond the sputtered layer 126 on the bottom surface of the opening 124. In this case, the electroless plating layer 128 may penetrate into the separated portion of the sputtered layer 126 between the bottom surface and the side surface of the opening 124. The electroless plating layer 128 may be separated from the sputtered layer 126 on the side surface of the opening 124. In this case, the entire sputtered layer 126 on the side surface of the opening 124 may be covered with an insulating layer 127.

[0074] Next, as shown in FIG. 7c, the insulating layer 127 on the sputtered layer 126 is removed by a method such as plasma etching.

[0075] 2 , electrolytic plating layer 129 is continuously formed from above electrolytic plating layer 128 onto the side surfaces of opening 124 and the rear surface of semiconductor substrate 111 by electrolytic plating using sputtered layer 126 as a seed layer. As electrolytic plating layer 129 grows, it becomes thicker, allowing it to come into contact with electroless plating layer 128.

[0076] In this way, in the first embodiment described above, for example, electroless plated layer 128 is formed between sputtered layer 126 and electrolytic plated layer 129 on the bottom surface of opening 124. This ensures the conductivity of through electrode TV2 on the bottom surface of opening 124 even when a step is generated in sputtered layer 126 at the bottom of opening 124, and makes it possible to reduce open defects while accommodating miniaturization of through electrode TV2.

[0077] 2. Second Embodiment In the above-described first embodiment, electroless plated layer 128 is formed between sputtered layer 126 and electrolytic plated layer 129 on the bottom surface of opening 124. In this second embodiment, electroless plated layer 128 is formed between sputtered layer 126 and electrolytic plated layer 129 on the bottom surface of opening 124, and a barrier metal film is formed below sputtered layer 126.

[0078] FIG. 8 is a cross-sectional view illustrating a configuration example of an electronic device according to the second embodiment.

[0079] In the figure, this electronic device has a through silicon via TV5 instead of the through silicon via TV1 in Fig. 1. Other configurations of this electronic device are the same as those of the electronic device in Fig. 1.

[0080] The through silicon via TV5 is obtained by adding a barrier metal film 120 to the through silicon via TV1 in Fig. 1. The other configurations of the through silicon via TV5 are the same as those of the through silicon via TV1 in Fig. 1.

[0081] The barrier metal film 120 is formed under the sputtered layer 116. At this time, the barrier metal film 120 is located on the insulating layer 115 and on the wiring layer 112 in the opening 114. The material of the barrier metal film 120 may be, for example, Ti, TiN, Ta, TaN, Ru, or RuN.

[0082] FIG. 9 is a cross-sectional view showing another example of the configuration of the electronic device according to the second embodiment.

[0083] In the figure, this electronic device has a through electrode TV6 instead of the through electrode TV2 in Fig. 2. Other configurations of this electronic device are the same as those of the electronic device in Fig. 2.

[0084] The through silicon via TV6 is obtained by adding a barrier metal film 130 to the through silicon via TV2 in Fig. 2. The other configurations of the through silicon via TV6 are the same as those of the through silicon via TV2 in Fig. 2.

[0085] The barrier metal film 130 is formed under the sputtered layer 126. At this time, the barrier metal film 130 is located on the insulating layer 125 and on the wiring layer 112 in the opening 124. The barrier metal film 130 may be separated between the bottom surface and the side surface of the opening 124.

[0086] As described above, in the second embodiment, for example, electroless plated layer 128 is formed between sputtered layer 126 and electrolytic plated layer 129 on the bottom surface of opening 124, and a barrier metal film is formed below sputtered layer 126. This makes it possible to reduce open defects while responding to miniaturization of through electrodes TV5, and also makes it possible to suppress diffusion of metal contained in sputtered layer 126 into insulating layer 125 and wiring layer 112.

[0087] 3. Third Embodiment In the first embodiment described above, electroless plated layer 128 is formed between sputtered layer 126 and electrolytic plated layer 129 on the bottom surface of opening 124. In this third embodiment, the cross-sectional shape of the electroless plated layer formed between sputtered layer 126 and the electrolytic plated layer on the bottom surface of opening 124 is made convex.

[0088] FIG. 10 is a cross-sectional view illustrating a configuration example of an electronic device according to the third embodiment.

[0089] In the figure, this electronic device has a through silicon via TV7 instead of the through silicon via TV1 in Fig. 1. Other configurations of this electronic device are the same as those of the electronic device in Fig. 1.

[0090] The through electrode TV7 includes an electroless plated layer 158 and an electrolytic plated layer 159 instead of the electroless plated layer 118 and the electrolytic plated layer 119 in Fig. 1. The other configurations of the through electrode TV7 are the same as those of the through electrode TV1 in Fig. 1.

[0091] The electroless plating layer 158 is formed on the sputtered layer 116 on the bottom surface of the opening 114. The cross-sectional shape of the electroless plating layer 158 may be convex. In this case, the top surface of the electroless plating layer 158 may be a convex curved surface. For example, the three-dimensional shape of the electroless plating layer 158 may be cap-shaped, cup-shaped, or bowl-shaped.

[0092] Electrolytic plated layer 159 is formed on the bottom surface of opening 114, on electroless plated layer 158 and insulating layer 117. At this time, electrolytic plated layer 159 is continuously formed from electroless plated layer 158 and insulating layer 117, via sputtered layer 116, onto the side surface of opening 114 and the rear surface of semiconductor substrate 111. Electrolytic plated layer 159 is curved on electroless plated layer 158 to correspond to the shape of the upper surface of electroless plated layer 158.

[0093] FIG. 11 is a cross-sectional view showing another example of the configuration of the electronic device according to the third embodiment.

[0094] In the figure, this electronic device has a through electrode TV8 instead of the through electrode TV2 in Fig. 2. Other configurations of this electronic device are the same as those of the electronic device in Fig. 2.

[0095] The through electrode TV8 includes an electroless plated layer 168 and an electrolytic plated layer 169 instead of the electroless plated layer 128 and the electrolytic plated layer 129 in Fig. 2. The other configurations of the through electrode TV8 are the same as those of the through electrode TV2 in Fig. 2.

[0096] The electroless plating layer 168 is formed on the bottom surface of the opening 124 and on the sputtered layer 126. The cross-sectional shape of the electroless plating layer 168 may be convex.

[0097] Electrolytic plated layer 169 is formed on electroless plated layer 168 on the bottom surface of opening 124. At this time, electrolytic plated layer 169 is continuously formed from on electroless plated layer 168, via sputtered layer 126, onto the side surface of opening 124 and the rear surface of semiconductor substrate 111. Electrolytic plated layer 169 is curved on electroless plated layer 168 to correspond to the shape of the upper surface of electroless plated layer 168.

[0098] FIG. 12 is a cross-sectional view showing still another example of the configuration of the electronic device according to the third embodiment.

[0099] In the figure, this electronic device has a through electrode TV9 instead of the through electrode TV4 in Fig. 4. Other configurations of this electronic device are the same as those of the electronic device in Fig. 4.

[0100] The through electrode TV9 includes an electroless plated layer 178 and an electrolytic plated layer 179 instead of the electroless plated layer 148 and the electrolytic plated layer 149 in Fig. 4. The other configurations of the through electrode TV9 are the same as those of the through electrode TV4 in Fig. 4.

[0101] The electroless plated layer 178 is formed on the sputtered layer 146 on the bottom surface of the opening 124. The cross-sectional shape of the electroless plated layer 178 may be convex. The insulating layer 147 is formed on the side surface of the electroless plated layer 178.

[0102] Electrolytic plated layer 179 is formed on electroless plated layer 178 and insulating layer 147. At this time, electrolytic plated layer 179 can be continuously formed from electroless plated layer 178 and insulating layer 147, via sputtered layer 146, onto the side surface of opening 124 and the rear surface of semiconductor substrate 111. Electrolytic plated layer 179 is curved on electroless plated layer 178 to correspond to the shape of the upper surface of electroless plated layer 178.

[0103] FIG. 13 is a cross-sectional view showing still another example of the configuration of the electronic device according to the third embodiment.

[0104] In the figure, this electronic device has a through silicon via TV10 instead of the through silicon via TV3 in Fig. 3. Other configurations of this electronic device are the same as those of the electronic device in Fig. 3.

[0105] The through-hole electrode TV 10 includes an electroless plated layer 188 and an electrolytic plated layer 189 instead of the electroless plated layer 138 and the electrolytic plated layer 139 in Fig. 3. The rest of the configuration of the through-hole electrode TV 10 is the same as the configuration of the through-hole electrode TV 10 in Fig. 3.

[0106] The electroless plated layer 188 is formed on the sputtered layer 136 on the bottom surface of the opening 134. The cross-sectional shape of the electroless plated layer 188 may be convex. The insulating layer 137 is formed on the side surface of the electroless plated layer 188.

[0107] Electrolytic plated layer 189 is formed on electroless plated layer 188 and insulating layer 137. At this time, electrolytic plated layer 189 can be continuously formed from electroless plated layer 188 and insulating layer 137, via sputtered layer 136, onto the side surface of opening 134 and the rear surface of semiconductor substrate 111. Electrolytic plated layer 189 is curved on electroless plated layer 188 to correspond to the shape of the upper surface of electroless plated layer 188.

[0108] In this way, in the third embodiment described above, for example, the cross-sectional shape of electroless plated layer 168 formed between sputtered layer 126 and electrolytic plated layer 169 on the bottom surface of opening 124 is made convex. This allows electroless plated layer 168 to be selectively formed on sputtered layer 126 while corresponding to the diameter and shape of opening 124.

[0109] 4. Fourth Embodiment In the first embodiment described above, electroless plating layer 128 is selectively formed on sputtered layer 126 on the bottom surface of opening 124, with sputtered layer 126 on the side surface of opening 124 entirely covered with insulating layer 127. In this fourth embodiment, electroless plating layer is selectively formed on sputtered layer 126 on the bottom surface of opening 124, with part of the sputtered layer on the side surface of opening 124 exposed from the insulating layer.

[0110] Fig. 14 is a cross-sectional view showing a configuration example of an electronic device according to a fourth embodiment. Note that, in this figure, an example in which an electroless plating layer is selectively formed in a state in which a part of the sputtered layer is exposed from the insulating layer is shown, which is applied to the electronic device of Fig. 2, but the present invention may be applied to other electronic devices.

[0111] In the figure, this electronic device has a through silicon via TV11 instead of the through silicon via TV2 in Fig. 2. Other configurations of this electronic device are the same as those of the electronic device in Fig. 2.

[0112] The through electrode TV11 includes an electroless plated layer 198 and an electrolytic plated layer 199 instead of the electroless plated layer 128 and the electrolytic plated layer 129 in Fig. 2. The other configurations of the through electrode TV11 are the same as those of the through electrode TV2 in Fig. 2.

[0113] On the side surface of opening 124, the tip of sputtered layer 126 comes into contact with electroless plated layer 198. Here, in order to bring the tip of sputtered layer 126 into contact with electroless plated layer 198, the tip of sputtered layer 126 on the side surface of opening 124 can be exposed from insulating layer 127 in step b of FIG.

[0114] The electroless plated layer 198 is formed on the sputtered layer 126 on the bottom surface of the opening 124. The electroless plated layer 198 is also formed on the tip of the sputtered layer 126 on the side surface of the opening 124. At this time, the peripheral portion of the electroless plated layer 198 can rise higher than the central portion.

[0115] Electrolytic plated layer 199 is formed on electroless plated layer 198 on the bottom surface of opening 124. At this time, electrolytic plated layer 199 can be formed continuously from electroless plated layer 198, via sputtered layer 126, onto the side surface of opening 124 and onto the rear surface of semiconductor substrate 111.

[0116] In this way, in the fourth embodiment described above, for example, the electroless plated layer 198 is selectively formed in a state in which a portion of the sputtered layer 126 on the side surface of the opening 124 is exposed from the insulating layer. This makes it possible to ensure the conductivity of the through electrode TV11 on the bottom surface of the opening 124 while accommodating a reduction in the thickness of the electroless plated layer 198, and to reduce open defects while accommodating a reduction in the size of the through electrode TV11.

[0117] 5. Fifth Embodiment In the first embodiment described above, electroless plated layer 128 is formed between sputtered layer 126 and electrolytic plated layer 129 on the bottom surface of opening 124. In this fifth embodiment, electroless plated layer 128 is formed on sputtered layer 126 on the bottom surface of opening 124, and an electroless plated layer is also formed on sputtered layer 126 on the side surface of opening 124.

[0118] 15 is a cross-sectional view showing an example of a method for manufacturing an electronic device according to the fifth embodiment. Note that, in this figure, an example in which an electroless plating layer 128' is formed on the sputtered layer 126 on the side surface of the opening 124 is applied to the electronic device of FIG. 2, but the method may be applied to other electronic devices.

[0119] In the diagram b, this electronic device has a through silicon via TV12 instead of the through silicon via TV2 in Fig. 2. Other configurations of this electronic device are the same as those of the electronic device in Fig. 2.

[0120] The through electrode TV12 includes an electrolytic plated layer 1009 instead of the electrolytic plated layer 129 in Fig. 2. Furthermore, the through electrode TV12 includes an electroless plated layer 128' in addition to the through electrode TV2 in Fig. 2. The other configurations of the through electrode TV12 are the same as those of the through electrode TV2 in Fig. 2.

[0121] The electroless plated layer 128' is formed on the sputtered layer 126 on the side surface of the opening 124. The electroless plated layer 128' can be selectively formed together with the electroless plated layer 128.

[0122] At this time, as shown in a in the figure, before performing electroless plating, a resist pattern PB is formed by lithography on the sputtered layer 126 on the back surface of the semiconductor substrate 111. An opening KB is formed in the resist pattern PB at a position where the side surface of the sputtered layer 126 is exposed.

[0123] Then, electroless plating is performed through the resist pattern PB to form an electroless plating layer 128 on the sputtered layer 126 on the bottom surface of the opening 124, and an electroless plating layer 128' is formed on the sputtered layer 126 on the side surface of the opening 124.

[0124] As shown in Fig. 1B, electrolytic plated layer 1009 is formed on electroless plated layers 128, 128'. At this time, electrolytic plated layer 1009 can be continuously formed from each of electroless plated layers 128, 128' onto the rear surface of semiconductor substrate 111 via sputtered layer 126.

[0125] In this way, in the above-described fifth embodiment, electroless plating layer 128 is formed on sputtered layer 126 on the bottom surface of opening 124, and electroless plating layer 128' is formed on sputtered layer 126 on the side surface of opening 124. As a result, even if a step occurs in sputtered layer 126 at the bottom of opening 124, the conductivity of through electrode TV12 at the bottom surface of opening 124 can be ensured, and open defects can be reduced.

[0126] 6. Sixth Embodiment In the first embodiment described above, electroless plated layer 128 is formed between sputtered layer 126 and electrolytic plated layer 129 on the bottom surface of opening 124. In this sixth embodiment, electroless plated layer 128 fills opening 124 formed on the bottom surface with sputtered layer 126 interposed therebetween.

[0127] FIG. 16 is a cross-sectional view illustrating a configuration example of an electronic device according to the sixth embodiment.

[0128] In the figure, this electronic device has a through silicon via TV12 instead of the through silicon via TV1 in Fig. 1. Other configurations of this electronic device are the same as those of the electronic device in Fig. 1.

[0129] The through silicon via TV12 has an electrolytic plated layer 1019 instead of the electrolytic plated layer 119 in Fig. 1. The other configurations of the through silicon via TV12 are the same as those of the through silicon via TV1 in Fig. 1 .

[0130] Electrolytic plated layer 1019 is embedded in opening 114 on electroless plated layer 118 and insulating layer 117. At this time, electrolytic plated layer 1019 is formed continuously from within opening 114 onto the rear surface of semiconductor substrate 111.

[0131] FIG. 17 is a cross-sectional view showing another example of the configuration of the electronic device according to the sixth embodiment.

[0132] In the figure, this electronic device has a through electrode TV13 instead of the through electrode TV2 in Fig. 2. Other configurations of this electronic device are the same as those of the electronic device in Fig. 2.

[0133] The through electrode TV13 includes an electrolytic plated layer 1029 instead of the electrolytic plated layer 129 in Fig. 2. The other configurations of the through electrode TV13 are the same as those of the through electrode TV2 in Fig. 2.

[0134] The electrolytic plated layer 1029 is embedded in the opening 124 on the electroless plated layer 128. At this time, the electrolytic plated layer 1029 is formed continuously from within the opening 124 onto the rear surface of the semiconductor substrate 111.

[0135] In this manner, in the sixth embodiment described above, for example, electrolytic plating layer 1029 is embedded in opening 124 formed on the bottom surface of electroless plating layer 128 via sputtered layer 126. This makes it possible to ensure the conductivity of through electrode TV13 at the bottom surface of opening 124 even when a step in sputtered layer 126 occurs at the bottom of opening 124, and also makes it possible to adjust the stress acting on through electrode TV13.

[0136] 2 will be described below. A stacked chip in which a plurality of chips are stacked will be described. Any of the through electrodes TV1, TV3 to TV13 other than the through electrode TV2 may be applied to the stacked chip in which a plurality of chips are stacked.

[0137] 7. Seventh Embodiment In the first embodiment described above, through-hole electrodes TV2, in which sputtered layer 126, electroless plated layer 128, and electrolytic plated layer 129 are sequentially stacked on the bottom surface of opening 124, are connected to wiring layer 112 by penetrating semiconductor substrate 111. In this seventh embodiment, through-hole electrodes TV2, in which sputtered layer 126, electroless plated layer 128, and electrolytic plated layer 129 are sequentially stacked on the bottom surface of opening 124, are connected to a lower-layer chip through an upper-layer chip.

[0138] FIG. 18 is a cross-sectional view illustrating a configuration example of an electronic device according to the seventh embodiment.

[0139] In the figure, the electronic device includes chips P21 and P22. The chip P22 is stacked on the chip P21. The chip P21 is directly bonded onto the chip P22.

[0140] The direct bonding of the chips P21 and P22 can be achieved by compression bonding of oxides. This compression bonding can be performed, for example, at a temperature of 250° C. or less after plasma activation of the bonding surfaces. In this case, oxides may be formed on the bonding surfaces of the chips P21 and P22.

[0141] For example, SiO ２ In plasma activation using this method, oxygen plasma or nitrogen plasma is irradiated onto the bonding surfaces to hydrophilize them. The bonding surfaces can then be bonded together based on hydrogen bonds between OH groups formed on the bonding surfaces by adsorption of moisture from the air. Heat treatment then decomposes the OH groups, diffusing the resulting hydrogen into the interface layer, achieving direct bonding based on Si-O-Si bonds mediated by oxygen. Plasma activation of the bonding surfaces prior to heat treatment improves the moisture adsorption properties of the bonding surfaces, and even heat treatment at temperatures below 250°C can achieve the bonding strength required to ensure the reliability of electronic devices.

[0142] Each of the chips P21 and P22 may have a semiconductor element, an optical element, or a MEMS formed thereon. The substrate used for each of the chips P21 and P22 may be a semiconductor substrate, a dielectric substrate, or an organic substrate.

[0143] The chip P21 includes a semiconductor substrate 211 and a wiring layer 261. The wiring layer 261 is formed on the front surface side of the semiconductor substrate 211. The wiring layer 261 is provided with wiring 271 embedded in an insulating layer and land electrodes 291. The wiring layer 261 is also provided with vias 281 used for interlayer connection. The land electrodes 291 can be used for connecting the through electrodes TV2.

[0144] Furthermore, a gate electrode 241 embedded in an insulating layer is formed on the surface side of the semiconductor substrate 211 via a gate insulating film 231. At this time, a channel region located below the gate electrode 241 and impurity diffusion layers located on both sides of the channel region may be formed in the semiconductor substrate 211. Sidewalls 251 may be formed on both sides of the gate electrode 241. Furthermore, an impurity diffusion layer 221 connected to a wiring 271 is formed in the semiconductor substrate 211.

[0145] The chip P22 includes a semiconductor substrate 212 and a wiring layer 262. The wiring layer 262 is formed on the front surface side of the semiconductor substrate 212. The wiring layer 262 is provided with wiring 272 embedded in an insulating layer. The wiring layer 262 is also provided with vias 282 used for interlayer connection.

[0146] Furthermore, through electrodes TV2 are formed in the semiconductor substrate 212 and the wiring layer 262, penetrating the semiconductor substrate 212 and the wiring layer 262 in the depth direction. The through electrodes TV2 penetrate the chip P22 to reach the chip P21 and are connected to the land electrodes 291. On the back surface side of the semiconductor substrate 212, back surface wiring 214 is formed via an insulating layer 125. The back surface wiring 214 is connected to the through electrodes TV2. Here, the back surface wiring 214 can be composed of the sputtered layer 126 and the electrolytic plated layer 129. This prevents the electroless plated layer 128 from being included in the back surface wiring 214, thereby preventing the back surface wiring 214 from becoming thicker and more resistive.

[0147] Furthermore, a gate electrode 242 embedded in an insulating layer is formed on the surface side of the semiconductor substrate 212 via a gate insulating film 232. At this time, a channel region located below the gate electrode 242 and impurity diffusion layers located on both sides of the channel region may be formed in the semiconductor substrate 212. Sidewalls 252 may be formed on both sides of the gate electrode 242. Furthermore, an impurity diffusion layer 222 connected to an interconnect 272 is formed in the semiconductor substrate 212.

[0148] The stacked structure of the chips P21 and P22 may form a wafer-level chip size package (WLCSP). In the WLCSP, the planar size and shape of the chip P22 can be made equal to those of the chip P21. In this case, the position of the horizontal end of the chip P21 can be aligned with the position of the horizontal end of the chip P22.

[0149] The insulating layers used in the wiring layers 261 and 262, the gate insulating films 231 and 232, and the sidewalls 251 and 252 are made of, for example, SiO ２ , SiN, or SiCN can be used. The wirings 271, 272, the back surface wiring 214, the vias 281, 282, and the land electrode 291 can be made of a metal such as Al, Cu, AlCu, AlSiCu, or Co. The gate electrodes 241, 242 can be made of a material such as polycrystalline silicon.

[0150] In this way, in the seventh embodiment described above, the through electrode TV2, in which the sputtered layer 126, the electroless plated layer 128, and the electrolytic plated layer 129 are sequentially stacked on the bottom surface of the opening 124, is provided in the chip P22 and connected to the chip P21. This makes it possible to extend wiring from the chip P21 to the outside while stacking the chip P22 on the chip P21, and also reduces open defects in the stacked structure of the chips P21 and P22.

[0151] 8. Eighth Embodiment In the seventh embodiment described above, the through silicon via TV2 is provided in the stacked structure of the chips P21 and P22 that are stacked based on direct oxide bonding. In this eighth embodiment, the through silicon via TV2 is provided in the stacked structure of the chips that are bonded based on hybrid bonding.

[0152] FIG. 19 is a cross-sectional view illustrating a configuration example of an electronic device according to the eighth embodiment.

[0153] In the figure, this electronic device includes chips P31 and P32 instead of the chips P21 and P22 of the seventh embodiment.

[0154] The chip P31 is obtained by adding a bonding electrode 311 to the chip P21 of the seventh embodiment. The chip P32 is obtained by adding a bonding electrode 312 to the chip P22 of the seventh embodiment. The other configurations of the chips P31 and P32 of the eighth embodiment are the same as the configurations of the chips P31 and P32 of the seventh embodiment.

[0155] The bonding electrode 311 is formed on the wiring layer 261. The bonding electrode 312 is formed on the wiring layer 262. The bonding electrodes 311 and 312 can be used for direct bonding between the chips P31 and P32. Hybrid bonding can be used for direct bonding between the chips P31 and P32. In this case, the bonding electrodes 311 and 312 are arranged in opposing positions. Then, the bonding electrodes 311 and 312 can be bonded to each other based on metal bonding such as Cu-Cu bonding.

[0156] In this way, in the above-described eighth embodiment, the through electrodes TV2 are provided in the stacked structure of the chips P31 and P32 bonded based on hybrid bonding. This makes it possible to connect the chips P31 and P32 while stacking the chip P32 on the chip P31, and also makes it possible to draw wiring from the chip P31 to the outside while reducing open defects in the stacked structure of the chips P31 and P32.

[0157] 9. Ninth Embodiment In the seventh embodiment, the through electrodes TV2 are provided in the stacked structure of the chips P21 and P22 that are stacked based on direct oxide bonding. In this ninth embodiment, the through electrodes TV2 are provided in the stacked structure of the chips P21 and P22 that are bonded via an adhesive layer.

[0158] FIG. 20 is a cross-sectional view illustrating a configuration example of an electronic device according to the ninth embodiment.

[0159] In the figure, this electronic device is the same as the electronic device of the seventh embodiment described above, except that an adhesive layer 321 is added. The other configurations of the electronic device of the ninth embodiment are the same as those of the electronic device of the seventh embodiment described above.

[0160] The adhesive layer 321 is located between the chips P21 and P22 and bonds the chips P21 and P22 together. At this time, the through-electrodes TV2 penetrate the chip P21 and the adhesive layer 321 and are connected to the chip P22. The adhesive layer 321 can be made of a resin such as epoxy, for example.

[0161] In this way, in the above-described ninth embodiment, the through electrode TV2 is provided in the stacked structure of the chips P21 and P22 bonded via the adhesive layer 321. This makes it possible to draw wiring from the chip P11 to the outside while stacking the chip P12 on the chip P11, and also reduces open defects in the stacked structure of the chips P11 and P12.

[0162] 10. Tenth Embodiment In the seventh embodiment, the through silicon via TV2 is provided in the stacked structure of the chips P21 and P22 that are stacked based on direct oxide bonding. In this tenth embodiment, the through silicon via TV2 is provided in the stacked structure of the chips that are stacked based on CoW.

[0163] FIG. 21 is a cross-sectional view illustrating a configuration example of an electronic device according to the tenth embodiment.

[0164] In the figure, this electronic device includes a chip P42 instead of the chip P22 of the seventh embodiment. A buried layer 411 is formed around the chip P42. The chip P42 is stacked on the chip P21 together with the buried layer 411 based on CoW. The chip P42 is directly bonded to the chip P21. Compression bonding between oxides can be used for direct bonding between the chips P21 and P42. The other configurations of the electronic device of the tenth embodiment are the same as those of the electronic device of the seventh embodiment.

[0165] The chip P42 includes a semiconductor substrate 412 and a wiring layer 462. The wiring layer 462 is formed on the front surface side of the semiconductor substrate 412. The wiring layer 462 is provided with wiring 472 embedded in an insulating layer. The wiring layer 462 is also provided with vias 482 used for interlayer connection.

[0166] Furthermore, a through electrode TV2 is formed in the semiconductor substrate 412 and the wiring layer 462, penetrating the semiconductor substrate 412 and the wiring layer 462 in the depth direction. The through electrode TV2 penetrates the chip P42 to reach the chip P21 and is connected to the land electrode 291. A back surface wiring 214 is formed on the back surface side of the semiconductor substrate 412 via an insulating layer 125. The back surface wiring 214 is connected to the through electrode TV2.

[0167] Furthermore, a gate electrode 442 embedded in an insulating layer is formed on the surface side of the semiconductor substrate 412 via a gate insulating film 432. At this time, a channel region located below the gate electrode 442 and impurity diffusion layers located on both sides of the channel region may be formed in the semiconductor substrate 412. Sidewalls 452 may be formed on both sides of the gate electrode 442. Furthermore, an impurity diffusion layer 422 connected to a wiring 472 is formed in the semiconductor substrate 412.

[0168] The structure in which the chip P42, around which the buried layer 411 is formed, is stacked on the chip P21 may constitute a wafer-level packaged WLCSP. In the WLCSP, the planar size and planar shape of the chip P22 can be made equal to the outer size and outer shape of the buried layer 411 formed around the chip P42. In this case, the position of the horizontal end of the chip P21 can be made to coincide with the position of the horizontal end of the buried layer 411. The height of the buried layer 411 can be made equal to the height of the chip P42. The material of the buried layer 411 may be a mold resin or SiO ２ After the chip P42 is buried in the buried layer 411, the buried layer 411 may be planarized by a method such as CMP (Chemical Mechanical Polishing) or back grinding.

[0169] In this way, in the above-described tenth embodiment, the through silicon vias TV2 are provided in the stacked structure of the chips P21 and P42 stacked based on CoW, which makes it possible to lead wiring from the chip P21 to the outside while stacking the chips P21 and P42 of different sizes, and also reduces open defects in the stacked structure of the chips P21 and P42.

[0170] 11. Eleventh Embodiment In the above-described tenth embodiment, the through silicon via TV2 is provided in the stacked structure of the chips P21 and P42 stacked based on CoW. In this eleventh embodiment, the through silicon via TV2 is provided in the stacked structure of the chips joined based on hybrid bonding.

[0171] FIG. 22 is a cross-sectional view illustrating a configuration example of an electronic device according to the eleventh embodiment.

[0172] In the figure, this electronic device includes chips P31 and P52 instead of the chips P21 and P42 of the tenth embodiment.

[0173] The chip P52 is obtained by adding a bonding electrode 312 to the chip P42 of the above-described tenth embodiment. A buried layer 411 is formed around the chip P52. The chip P52 is stacked on the chip P31 together with the buried layer 411 based on CoW. The chip P52 is directly bonded to the chip P31. The other configurations of the chip P52 of the eleventh embodiment are the same as the configuration of the chip P42 of the above-described tenth embodiment.

[0174] The bonding electrodes 312 are formed on the wiring layer 462. The bonding electrodes 311 and 312 can be used for direct bonding between the chips P31 and P52. Hybrid bonding can be used for direct bonding between the chips P31 and P52. The bonding electrodes 311 and 312 can be bonded to each other based on metal bonding such as Cu-Cu bonding.

[0175] In this way, in the eleventh embodiment described above, the through electrodes TV2 are provided in the stacked structure of the chips P31 and P52 bonded based on hybrid bonding. This makes it possible to connect the chips P31 and P52 while stacking the chips P31 and P52, which are different in size, and also makes it possible to draw wiring from the chip P31 to the outside while reducing open defects in the stacked structure of the chips P31 and P52.

[0176] The electronic device according to the above-described tenth or eleventh embodiment may be configured as a FOWLP (Fan Out Wafer Level Package).

[0177] 12. Twelfth Embodiment In the above-described tenth embodiment, the through electrodes TV2 that penetrate the chip P42 stacked on the chip P21 based on CoW are connected to the chip P21. In this twelfth embodiment, the through electrodes TV2 that penetrate the buried layer 411 around the chip P42 stacked on the chip P21 based on CoW are connected to the chip P21.

[0178] FIG. 23 is a cross-sectional view illustrating a configuration example of an electronic device according to the twelfth embodiment.

[0179] In the figure, in this electronic device, the through silicon via TV2 penetrates the buried layer 411 and is connected to the chip P21. Other configurations of this electronic device are the same as those of the electronic device of the above-described tenth embodiment.

[0180] As described above, in the twelfth embodiment, the through silicon vias TV2 that penetrate the buried layer 411 around the chip P42 stacked on the chip P21 based on CoW are connected to the chip P21. This makes it possible to extend wiring from the chip P21 to the outside while stacking the chips P21 and P42, which are different in size, and also reduces open defects in the stacked structure of the chips P21 and P42. In this case, the through silicon vias TV2 formed in the chip P42 can be eliminated, and the size of the chip P42 can be reduced.

[0181] 13. Thirteenth Embodiment In the above-described eleventh embodiment, the through electrodes TV2 that penetrate the chip P52 bonded onto the chip P31 based on hybrid bonding are connected to the chip P21. In this thirteenth embodiment, the through electrodes TV2 that penetrate the buried layer 411 around the chip P52 bonded onto the chip P31 based on hybrid bonding are connected to the chip P31.

[0182] FIG. 24 is a cross-sectional view illustrating a configuration example of an electronic device according to the thirteenth embodiment.

[0183] In the figure, in this electronic device, the through silicon via TV2 penetrates the buried layer 411 and is connected to the chip P31. Other configurations of this electronic device are the same as those of the electronic device of the above-described eleventh embodiment.

[0184] As described above, in the thirteenth embodiment, the through electrodes TV2 that penetrate the buried layer 411 around the chip P52 bonded onto the chip P31 based on hybrid bonding are connected to the chip P31. This makes it possible to extend wiring from the chip P31 to the outside while stacking the chips P31 and P52 that are different in size, and also reduces open defects in the stacked structure of the chips P31 and P52. In this case, the through electrodes TV2 formed in the chip P52 can be eliminated, and the size of the chip P52 can be reduced.

[0185] 14. Fourteenth Embodiment In the first embodiment described above, the through electrodes TV2 penetrating the chip P22 are connected to the chip P21. In this fourteenth embodiment, the through electrodes TV2 penetrating a semiconductor substrate are connected to a wiring layer on the semiconductor substrate.

[0186] FIG. 25 is a cross-sectional view illustrating a configuration example of an electronic device according to the fourteenth embodiment.

[0187] In the figure, this electronic device includes a chip P72 instead of the chip P22 of the seventh embodiment. The other configurations of the electronic device of the fourteenth embodiment are the same as those of the electronic device of the seventh embodiment.

[0188] The chip P72 is obtained by adding a land electrode 292 to the chip P22 of the seventh embodiment described above. The land electrode 292 is formed in the wiring layer 262. A through-electrode TV2 is connected to the land electrode 292. At this time, the through-electrode TV2 can penetrate the semiconductor substrate 212 and reach the wiring layer 262. Other configurations of the chip P72 of the fourteenth embodiment are similar to the configuration of the chip P22 of the seventh embodiment described above.

[0189] In this way, in the above-described fourteenth embodiment, the through electrodes TV2 that penetrate the semiconductor substrate 212 are connected to the wiring layer 262 on the semiconductor substrate 212. This makes it possible to extend wiring from the chip P72 to the outside while stacking the chip P72 on the chip P21, and also reduces open defects in the stacked structure of the chips P21 and P72.

[0190] 15. Fifteenth Embodiment In the seventh embodiment described above, the through electrodes TV2 are provided in the stacked structure of the chips P21 and P22 that are stacked based on direct oxide bonding. In this fifteenth embodiment, the through electrodes TV2 that penetrate the upper chip and the middle chip are connected to the lower chip.

[0191] FIG. 26 is a cross-sectional view illustrating a configuration example of an electronic device according to the fifteenth embodiment.

[0192] In the figure, this electronic device is obtained by adding a chip P22 to the electronic device of the above-described eleventh embodiment. The chip P22 is stacked on the back surface side of the chip P52 embedded in the embedding layer 411. At this time, the embedding layer 411 can cover the back surface side of the chip P52. Furthermore, in this electronic device, the through-electrode TV2 passes through the chips P22 and P52 in order and is connected to the chip P31. Other configurations of this electronic device are the same as those of the electronic device of the above-described eleventh embodiment.

[0193] In this way, in the above-described fifteenth embodiment, the through electrode TV2 that passes through the chips P22 and P52 in sequence is connected to the chip P31. This makes it possible to extend wiring from the chip P31 to the outside while stacking the chip P22 on the stacked structure of the chips P31 and P52 that are different in size, and also reduces open defects in the stacked structure of the chips P22, P31, and P52.

[0194] 16. Sixteenth Embodiment In the fifteenth embodiment described above, the through silicon via TV2 that passes through the chips P22 and P52 in sequence is connected to the chip P31. In this sixteenth embodiment, the through silicon via TV2 that passes through the buried layer 411 around the chips P22 and P52 in sequence is connected to the chip P31.

[0195] FIG. 27 is a cross-sectional view illustrating a configuration example of an electronic device according to the sixteenth embodiment.

[0196] In the figure, in this electronic device, the through silicon via TV2 passes through the buried layer 411 around the chip P22 and the chip P52 in this order, and is connected to the chip P31. The other configurations of this electronic device are the same as those of the electronic device of the above-described fifteenth embodiment.

[0197] As described above, in the sixteenth embodiment, the through electrodes TV2 that sequentially penetrate the buried layers 411 around the chips P22 and P52 are connected to the chip P31. This makes it possible to stack the chip P22 on the stacked structure of the chips P31 and P52, which are different in size, and to draw wiring from the chip P31 to the outside, while reducing open defects in the stacked structure of the chips P22, P31, and P52. In this case, the through electrodes TV2 formed in the chip P52 can be eliminated, and the size of the chip P52 can be reduced.

[0198] 17. Seventeenth Embodiment In the above-described fourteenth embodiment, the through electrodes TV2 penetrating the semiconductor substrate 212 are connected to the wiring layer 262 on the semiconductor substrate 212. In this seventeenth embodiment, the through electrodes TV2 penetrating the semiconductor substrate of a semiconductor chip stacked on a sensor chip are connected to the wiring layer on the semiconductor substrate.

[0199] 28 is a cross-sectional view showing an example of the configuration of an electronic device according to the seventeenth embodiment, in which an electronic device 600 cut out from the laminated wafer STW is shown.

[0200] In the figure, the electronic device 600 includes a sensor chip P61 and a semiconductor chip P62. The semiconductor chip P62 is stacked on the sensor chip P61. The sensor chip P61 is directly bonded onto the semiconductor chip P62. Hybrid bonding can be used for directly bonding the sensor chip P61 and the semiconductor chip P62.

[0201] A back-illuminated image sensor is formed in the sensor chip P61. The sensor chip P61 includes a semiconductor substrate 611 and a wiring layer 661. The wiring layer 661 is formed on the front surface side of the semiconductor substrate 611. The wiring layer 661 is provided with wiring embedded in an insulating layer. The wiring layer is also provided with vias used for interlayer connection.

[0202] An interlayer insulating layer 621 is formed between the semiconductor substrate 611 and the wiring layer 661. At this time, a gate electrode embedded in the interlayer insulating layer 621 is formed on the surface side of the semiconductor substrate 611. A channel region located under the gate electrode and impurity diffusion layers located on both sides of the channel region may be formed in the semiconductor substrate 611. Sidewalls may be formed on both sides of the gate electrode.

[0203] A light receiving area RA is provided on the back surface side of the semiconductor substrate 611. The light receiving area RA detects light incident thereon. In the light receiving area RA, pixels and pixel transistors are arranged in a matrix along the row and column directions.

[0204] A pixel isolation layer 631 that isolates pixels is formed in the light receiving area RA. The pixel isolation layer 631 can be formed on the back surface side of the semiconductor substrate 611 so as to be embedded in the semiconductor substrate 611 at the boundaries of the pixels. Also, a photodiode 641 is formed for each pixel in the light receiving area RA.

[0205] In addition, a light-shielding film 651 is formed on the back surface side of the semiconductor substrate 611. The light-shielding film 651 can suppress color mixing of light incident on the photodiode 641 via the color filter 681. The material of the light-shielding film 651 may be a black resin or a metal such as Cr. A planarizing film 671 is formed on the light-shielding film 651. The material of the planarizing film 671 may be, for example, SiO ２ or SiN can be used.

[0206] A color filter 681 is formed for each pixel on the planarization film 671. A stress mitigation layer 691 is formed on the color filter 681. An opening KS for adjusting stress is formed in the stress mitigation layer 691 in the depth direction. The opening KS may penetrate the stress mitigation layer 691 and reach the semiconductor substrate 611. The material of the stress mitigation layer 691 is, for example, SiO ２ or SiN can be used.

[0207] On the stress relaxation layer 691, on-chip lenses 632 and 633 are formed for each pixel. In this case, the on-chip lenses 632 and 633 may have a two-layer structure. The material of the color filter 681 and the on-chip lenses 632 and 633 may be, for example, SiO ２An insulating film such as SiN or SiCN, or a transparent resin such as acrylic or polycarbonate can be used. In this case, the materials of the on-chip lenses 632 and 633 may have different compositions or structures. For example, the materials of the on-chip lenses 632 and 633 can be selected to optimize optical characteristics and suppress deterioration over time due to moisture absorption, etc. The color filter 681 may contain a pigment. The color filter 681 may, for example, form a Bayer array or a quad-Bayer array. The color filter 681 may include an RGB filter, a complementary color filter, or a white filter. A lens, a color splitter, or a deflector formed of a metasurface may be formed on the light receiving area RA.

[0208] A planarization film 634 is formed on the on-chip lens 633. The planarization film 634 is made of, for example, SiO ２ or SiN can be used.

[0209] A logic circuit is formed on the semiconductor chip P62. The semiconductor chip P62 includes a semiconductor substrate 612 and a wiring layer 662. The wiring layer 662 is formed on the front side of the semiconductor substrate 612. The wiring layer 662 is provided with wiring embedded in an insulating layer. The wiring layer 662 is also provided with vias used for interlayer connections. Furthermore, the wiring layer 662 is provided with test pads KPD. The test pads KPD can be used for testing the semiconductor chip P62. At this time, the semiconductor chip P62 can be tested by applying a probe to the test pads KPD before the transparent resin layer 602 is embedded in the openings KD.

[0210] An interlayer insulating layer 622 is formed between the semiconductor substrate 612 and the wiring layer 662. At this time, a gate electrode embedded in the interlayer insulating layer 622 is formed on the surface side of the semiconductor substrate 612. A channel region located under the gate electrode and impurity diffusion layers located on both sides of the channel region can be formed in the semiconductor substrate 612. Sidewalls may be formed on both sides of the gate electrode. In addition, a land electrode 692 embedded in the interlayer insulating layer 622 is formed on the surface side of the semiconductor substrate 612. The land electrode 692 can be used to connect the through-electrode TV2.

[0211] Furthermore, a through electrode TV2 is formed in the semiconductor substrate 612, penetrating the semiconductor substrate 612 in the depth direction. The through electrode TV2 penetrates the semiconductor substrate 612 and is connected to the land electrode 692. A back surface wiring 214 is formed on the back surface side of the semiconductor substrate 612 via an insulating layer 125. The back surface wiring 214 is connected to the through electrode TV2.

[0212] Openings KD are formed in the sensor chip P61 and the semiconductor chip P62. The openings KD are arranged at positions where the test pads KPD are exposed. At this time, the openings KD penetrate the sensor chip P61 and reach the surfaces of the test pads KPD.

[0213] Furthermore, openings KB are formed in the sensor chip P61 and the semiconductor chip P62. The openings KB are arranged along the scribe lines. At this time, the openings KB can penetrate the sensor chip P61 and the wiring layer 662.

[0214] A transparent substrate 601 is bonded to the rear surface side of the sensor chip P61 via a transparent resin layer 602. At this time, the transparent resin layer 602 is embedded in the openings KB and KD.

[0215] The stacked structure of the sensor chip P61 and the semiconductor chip P62 may form a wafer-level packaged WLCSP. In the WLCSP, the planar size and shape of the sensor chip P61 can be made equal to those of the semiconductor chip P62. Furthermore, the planar size and shape of the sensor chip P61 can be made equal to those of the transparent substrate 601. In this case, the positions of the horizontal ends of the sensor chip P61 can be aligned with the positions of the horizontal ends of the semiconductor chip P62. Furthermore, the positions of the horizontal ends of the sensor chip P61 can be aligned with the positions of the horizontal ends of the transparent substrate 601.

[0216] The transparent substrate 601 may be a glass substrate, a quartz substrate, or a transparent resin substrate such as an acrylic or polycarbonate substrate. The transparent substrate 601 is made of Al ２ O ３ , CaF ２ , MgF ２ Alternatively, LiF or the like may be used.

[0217] The transparent resin layer 602 may be a thermosetting resin or an ultraviolet-curable resin. For example, the material of the transparent resin layer 602 may be a transparent resin such as a siloxane-based resin, an acrylic-based resin, or an epoxy-based resin. In this case, the material of the transparent resin layer 602 may be selected so as to ensure a refractive index difference between the transparent resin layer 602 and the on-chip lenses 632, 633. The transparent resin layer 602 may contain a filler such as glass fiber to improve reliability. A resin material may be selected for the transparent resin layer 602 whose optical properties (refractive index, extinction coefficient, etc.) are adjusted so that light can be received well in the pixel region RA.

[0218] 29A to 29C are cross-sectional views illustrating an example of a method for manufacturing an electronic device according to the seventeenth embodiment.

[0219] In the figure, a division region RE is provided in the laminated wafer STW. The laminated wafer STW is formed by stacking a transparent substrate wafer 601W and semiconductor wafers 612W and 622W. Transparent substrates 601 are cut out for each division region RE from the transparent substrate wafer 601W. Semiconductor substrates 612 are cut out for each division region RE from the semiconductor wafer 612W. Semiconductor substrates 622 are cut out for each division region RE from the semiconductor wafer 622W. The division regions RE are divided along scribe lines SBL. The scribe lines SBL are formed at the positions of the openings KB. Electronic devices 600 are cut out from each division region RE. At this time, the laminated wafer STW can be separated into individual electronic devices 600 by cutting along the scribe lines SBL.

[0220] As described above, in the seventeenth embodiment, the through electrodes TV2 that penetrate the semiconductor substrate 612 of the semiconductor chip P62 stacked on the sensor chip P61 are connected to the wiring layer 662. This makes it possible to draw wiring from the semiconductor chip P62 to the outside while stacking the semiconductor chip P62 on the sensor chip P61, and also reduces open defects in the electronic device 600.

[0221] In the above-described seventeenth embodiment, an example has been shown in which the semiconductor chip P62 is stacked on the sensor chip P61. In addition to this, the sensor chip P61 may be used for the chip P21 in the seventh, ninth, tenth, twelfth, or fourteenth embodiment, or the sensor chip P61 may be used for the chip P31 in the eighth, eleventh, thirteenth, fifteenth, or sixteenth embodiment.

[0222] 18. Eighteenth Embodiment In the first embodiment described above, a metal laminate portion in which a sputtered layer, an electroless plated layer, and an electrolytic plated layer are sequentially stacked is provided on the bottom surface of the opening. In this eighteenth embodiment, a capacitor is provided on the metal laminate portion in which a sputtered layer, an electroless plated layer, and an electrolytic plated layer are sequentially stacked inside the opening.

[0223] FIG. 30 is a cross-sectional view showing a configuration example of an electronic device according to the eighteenth embodiment.

[0224] In the figure, this electronic device has a capacitor CA1 provided on the through silicon via TV1 in Fig. 1. Other configurations of this electronic device are the same as those of the electronic device in Fig. 1.

[0225] The capacitor CA1 includes capacitor electrodes CD11 and CD12 and a dielectric layer ED1. The capacitor electrodes CD11 and CD12 are disposed opposite each other with the dielectric layer ED1 interposed therebetween. The capacitor CA1 is located within the opening 114. In this case, the capacitor CA1 can be formed continuously from above the metal stack portion MT1 to the side surface of the opening 114 and the rear surface of the semiconductor substrate 111.

[0226] The capacitance electrode CD11 is formed on the through electrode TV1, the dielectric layer ED1 is formed on the capacitance electrode CD11, and the capacitance electrode CD12 is formed on the dielectric layer ED1. An insulating layer Z1 is formed on the capacitance CA1 so as to cover the opening 114. At this time, a cavity CAV1 can be formed in the opening 114 below the insulating layer Z1.

[0227] On the back surface of the semiconductor substrate 111, a portion of the capacitive electrode CD11 is exposed from the dielectric layer ED1, the capacitive electrode CD12, and the insulating layer Z1. The external electrode D1 is connected to the capacitive electrode CD11 via the insulating layer Z1. On the back surface of the semiconductor substrate 111, a portion of the capacitive electrode CD12 is exposed from the insulating layer Z1. The external electrode D2 is connected to the capacitive electrode CD12 via the insulating layer Z1.

[0228] The capacitive electrodes CD11 and CD12 may be made of, for example, Cu, Ti, Ta, Al, W, Ni, Ru, Co, TiN, TaN, or WN, or may have a laminated structure of multiple materials.

[0229] The material of the dielectric layer ED1 is, for example, SiO ２ , SiON, Si ３ N ４ , hafnium oxide (HfO ２ ), aluminum oxide (Al ２ O ３ ), zirconium oxide (ZrO), tantalum oxide (Ta ２ O ５ ), titanium oxide (TiO ２ ), lanthanum oxide (LaO３ ), yttrium oxide (Y ２ O ３ , aluminum nitride (AlN), hafnium oxynitride (HfON), aluminum oxynitride (AlON)) can be used, and a laminate structure of a plurality of materials may also be used.

[0230] The insulating layer Z1 is made of a material such as polyimide, acrylic, silicone, or an organic material having an epoxy group as a skeleton, or SiO ２ , Al ２ O ３ Materials containing fillers such as ZnO, AlN, BN, etc. can be used. The insulating layer Z1 may be a CVD (Chemical Vapor Deposition) film or a coating film.

[0231] FIG. 31 is a cross-sectional view showing another example of the configuration of the electronic device according to the eighteenth embodiment.

[0232] In the figure, in this electronic device, a capacitor CA2 is provided on the through electrode TV2 in Fig. 2. Other configurations of this electronic device are the same as those of the electronic device in Fig. 2.

[0233] The capacitor CA2 includes capacitor electrodes CD21 and CD22 and a dielectric layer ED2. The capacitor electrodes CD21 and CD22 are disposed opposite each other with the dielectric layer ED2 interposed therebetween. The capacitor CA2 is located within the opening 124. In this case, the capacitor CA2 can be formed continuously from above the metal stack portion MT2 to the side surface of the opening 124 and the rear surface of the semiconductor substrate 111.

[0234] The capacitance electrode CD21 is formed on the through-electrode TV2, the dielectric layer ED2 is formed on the capacitance electrode CD21, and the capacitance electrode CD22 is formed on the dielectric layer ED2. An insulating layer Z2 is formed on the capacitance CA2 so as to cover the opening 124. At this time, a cavity CAV2 can be formed in the opening 124 below the insulating layer Z2.

[0235] On the back surface of the semiconductor substrate 111, a portion of the capacitive electrode CD21 is exposed from the dielectric layer ED2, the capacitive electrode CD22, and the insulating layer Z2. The external electrode D1 is connected to the capacitive electrode CD21 via the insulating layer Z2. On the back surface of the semiconductor substrate 111, a portion of the capacitive electrode CD22 is exposed from the insulating layer Z2. The external electrode D2 is connected to the capacitive electrode CD22 via the insulating layer Z2.

[0236] 32 to 34 are cross-sectional views showing an example of a method for manufacturing an electronic device according to the eighteenth embodiment. Note that, although Fig. 32 to 34 take the method for manufacturing the electronic device in Fig. 31 as an example, they may also be applied to the method for manufacturing the electronic device in Fig. 30.

[0237] 32A, the capacitive electrode CD21 is formed on the electrolytic plating layer 129 by a method such as sputtering. At this time, the capacitive electrode CD21 can be formed not only on the rear surface side of the semiconductor substrate 111 but also on the bottom surface and side surfaces of the opening 124.

[0238] 32b, a dielectric layer ED2 is formed on the capacitive electrode CD21 by a method such as sputtering. At this time, the dielectric layer ED2 can be formed not only on the rear surface side of the semiconductor substrate 111 but also on the bottom surface and side surfaces of the opening 124.

[0239] 32c, the capacitive electrode CD22 is formed on the dielectric layer ED2 by a method such as sputtering. At this time, the capacitive electrode CD22 can be formed not only on the rear surface side of the semiconductor substrate 111 but also on the bottom surface and side surfaces of the opening 124.

[0240] 33A, a resist pattern PC is formed on the capacitor electrode CD22 using lithography technology so as to cover the opening 124. At this time, the resist pattern PC can be formed to correspond to the planar shape of the capacitor CA2.

[0241] 33B, the capacitance electrodes CD21, CD22 and the dielectric layer ED2 are etched using the resist pattern PC as an etching mask to form a capacitance CA2. The capacitance electrodes CD21, CD22 and the dielectric layer ED2 can be etched by dry etching such as RIE. The resist pattern PC is then removed by ashing or other methods.

[0242] 33 c, a resist pattern PD is formed on the capacitive electrode CD22 using lithography technology so as to cover the opening 124. At this time, the resist pattern PD can expose a part of the capacitive electrode CD22 on the back surface side of the semiconductor substrate 111.

[0243] 34A, the capacitive electrode CD22 and the dielectric layer ED2 are etched using the resist pattern PD as an etching mask to expose a portion of the capacitive electrode CD21. Dry etching such as RIE can be used to etch the capacitive electrode CD22 and the dielectric layer ED2. Then, the resist pattern PD is removed by ashing or other methods.

[0244] 34b, an insulating layer Z2 is formed on the capacitor CA2 by a method such as sputtering so as to cover the opening 124. At this time, a cavity CAV2 may be formed in the opening 124 below the insulating layer Z2. Then, openings KA1 and KA2 are formed in the insulating layer Z2 corresponding to the positions of the external electrodes D1 and D2.

[0245] Next, as shown in FIG. 31, the external electrode D1 is connected to the capacitive electrode CD21 through the opening KA1, and the external electrode D2 is connected to the capacitive electrode CD22 through the opening KA2.

[0246] In this way, in the above-described 18th embodiment, for example, capacitor CA1 is provided on metal laminate portion MT1 in which sputtered layer 116, electroless plated layer 118, and electrolytic plated layer 119 are sequentially laminated within opening 114. This ensures the conductivity of capacitor electrode CD11 at the bottom of opening 114 even when a step disconnection occurs in sputtered layer 116 at the bottom of opening 114, and reduces open defects while accommodating miniaturization of capacitor CA1.

[0247] 19. Nineteenth Embodiment In the above-described eighteenth embodiment, a capacitor is provided on the bottom surface of an opening, with a metal laminate portion having a sputtered layer, an electroless plated layer, and an electrolytic plated layer laminated in that order, and an insulating layer is formed on the capacitor so as to cover the top of the opening. In this nineteenth embodiment, a capacitor is provided on a metal laminate portion having a sputtered layer, an electroless plated layer, and an electrolytic plated layer laminated in that order within an opening, and an insulating layer is formed along the surface of the capacitor.

[0248] FIG. 35 is a cross-sectional view showing a configuration example of an electronic device according to the nineteenth embodiment.

[0249] In the figure, this electronic device has an insulating layer Z3 instead of the insulating layer Z1 in Fig. 30. Other configurations of this electronic device are the same as those of the electronic device in Fig. 30.

[0250] The insulating layer Z3 is formed along the surface of the capacitor CA1. In this case, the insulating layer Z3 can be disposed on the bottom surface of the opening 114, on the side surfaces of the opening 114, and on the rear surface of the semiconductor substrate 111. On the rear surface side of the semiconductor substrate 111, the external electrode D1 is connected to the capacitive electrode CD11 via the insulating layer Z3. Furthermore, the external electrode D2 is connected to the capacitive electrode CD12 via the insulating layer Z3.

[0251] The material of the insulating layer Z3 is, for example, SiO ２ , SiON, SiOC, Si ３ N ４ Inorganic materials such as SiCO, polyimide, acrylic, silicone, and organic materials having an epoxy group as a skeleton can be used, and a laminate structure of a plurality of materials may also be used.

[0252] FIG. 36 is a cross-sectional view showing another example of the configuration of the electronic device according to the nineteenth embodiment.

[0253] In the figure, this electronic device has an insulating layer Z4 instead of the insulating layer Z2 in Fig. 31. Other configurations of this electronic device are the same as those of the electronic device in Fig. 31.

[0254] The insulating layer Z4 is formed along the surface of the capacitor CA2. In this case, the insulating layer Z4 can be disposed on the bottom surface of the opening 124, on the side surfaces of the opening 124, and on the rear surface of the semiconductor substrate 111. Then, on the rear surface side of the semiconductor substrate 111, the external electrode D1 is connected to the capacitive electrode CD21 via the insulating layer Z4. Furthermore, the external electrode D2 is connected to the capacitive electrode CD22 via the insulating layer Z4.

[0255] In this way, in the above-described 19th embodiment, for example, the capacitor CA1 is provided on the metal laminate portion MT1 in which the sputtered layer 116, the electroless plated layer 118, and the electrolytic plated layer 119 are laminated in this order within the opening 114, and the insulating layer Z3 is formed along the surface of the capacitor CA1. As a result, even if a step is generated in the sputtered layer 116 at the bottom of the opening 114, it is possible to ensure the conductivity of the capacitor electrode CD11 at the bottom of the opening 114 and to protect the capacitor CA1.

[0256] 20. Twentieth Embodiment In the above-described eighteenth embodiment, a capacitor is provided on the bottom surface of an opening, with a metal laminate portion having a sputtered layer, an electroless plated layer, and an electrolytic plated layer laminated in that order, and an insulating layer is formed on the capacitor so as to cover the top of the opening. In this twentieth embodiment, a capacitor is provided on a metal laminate portion having a sputtered layer, an electroless plated layer, and an electrolytic plated layer laminated in that order within an opening, and a buried layer is formed on the capacitor so as to be embedded in the opening.

[0257] FIG. 37 is a cross-sectional view showing a configuration example of an electronic device according to the twentieth embodiment.

[0258] In this figure, this electronic device has a buried layer Z5 instead of the insulating layer Z1 in Fig. 30. Other configurations of this electronic device are the same as those of the electronic device in Fig. 30.

[0259] The buried layer Z5 is formed on the capacitor CA1 so as to be embedded in the opening 114. At this time, the buried layer Z5 can be disposed from the inside of the opening 114 onto the rear surface of the semiconductor substrate 111. Then, on the rear surface side of the semiconductor substrate 111, the external electrode D1 is connected to the capacitive electrode CD11 via the buried layer Z5. Also, the external electrode D2 is connected to the capacitive electrode CD12 via the buried layer Z5.

[0260] The material of the buried layer Z5 is polyimide, acrylic, silicone, organic material with an epoxy group as a skeleton, or SiO ２ , Al ２ O ３ Materials containing fillers such as ZnO, AlN, BN, etc. can be used. The insulating layer Z1 may be a CVD (Chemical Vapor Deposition) film or a coating film.

[0261] FIG. 38 is a cross-sectional view showing another example of the configuration of the electronic device according to the twentieth embodiment.

[0262] In this figure, this electronic device has a buried layer Z6 instead of the insulating layer Z2 of Fig. 31. Other configurations of this electronic device are the same as those of the electronic device of Fig. 31.

[0263] The buried layer Z6 is formed on the capacitor CA2 so as to be embedded in the opening 124. At this time, the buried layer Z6 can be disposed from the inside of the opening 124 onto the rear surface of the semiconductor substrate 111. Then, on the rear surface side of the semiconductor substrate 111, the external electrode D1 is connected to the capacitive electrode CD21 via the buried layer Z6. Also, the external electrode D2 is connected to the capacitive electrode CD22 via the buried layer Z6.

[0264] In this way, in the above-described twentieth embodiment, for example, capacitor CA1 is provided on metal laminate portion MT1 in which sputtered layer 116, electroless plated layer 118, and electrolytic plated layer 119 are sequentially laminated within opening 114, and buried layer Z5 is formed on capacitor CA1 so as to be buried within opening 114. This makes it possible to ensure the conductivity of capacitor electrode CD11 at the bottom of opening 114 and protect capacitor CA1 even if a step in sputtered layer 116 occurs at the bottom of opening 114.

[0265] 21. Twenty-first embodiment In the above-described eighteenth embodiment, a capacitor is provided on the bottom surface of an opening, with a metal laminate portion having a sputtered layer, an electroless plated layer, and an electrolytic plated layer laminated in that order, and an insulating layer is formed on the capacitor so as to cover the top of the opening. In this twenty-first embodiment, a capacitor is provided on the metal laminate portion having a sputtered layer, an electroless plated layer, and an electrolytic plated layer laminated in that order within the opening, and the through electrode also serves as a first capacitor electrode.

[0266] FIG. 39 is a cross-sectional view showing a configuration example of an electronic device according to the twenty-first embodiment.

[0267] In the figure, the capacitive electrode CD11 of Fig. 30 has been removed from this electronic device. In this case, the capacitive electrode CD11 can be substituted with a through silicon via TV1. Other configurations of this electronic device are the same as those of the electronic device of Fig. 30.

[0268] The capacitor CA3 includes a through-electrode TV1, a capacitance electrode CD12, and a dielectric layer ED1. The through-electrode TV1 and the capacitance electrode CD12 are disposed opposite each other with the dielectric layer ED1 interposed therebetween. The capacitor CA3 is located within the opening 114. In this case, the capacitor CA3 can be formed continuously from the bottom surface of the opening 114 to the side surface of the opening 114 and the back surface of the semiconductor substrate 111.

[0269] The dielectric layer ED1 is formed on the through electrode TV1, and the capacitance electrode CD12 is formed on the dielectric layer ED1. An insulating layer Z1 is formed on the capacitance CA3 so as to cover the opening 114.

[0270] On the back surface of the semiconductor substrate 111, a portion of the through-electrode TV1 is exposed from the dielectric layer ED1, the capacitive electrode CD12, and the insulating layer Z1. The external electrode D1 is connected to the through-electrode TV1 via the insulating layer Z1. Also, on the back surface of the semiconductor substrate 111, a portion of the capacitive electrode CD12 is exposed from the insulating layer Z1. The external electrode D2 is connected to the capacitive electrode CD12 via the insulating layer Z1.

[0271] FIG. 40 is a cross-sectional view showing another example of the configuration of the electronic device according to the twenty-first embodiment.

[0272] In the figure, the capacitive electrode CD21 of Fig. 31 has been removed from this electronic device. In this case, the capacitive electrode CD21 can be substituted with a through silicon via TV2. Other configurations of this electronic device are the same as those of the electronic device of Fig. 31.

[0273] The capacitor CA4 includes a through-electrode TV2, a capacitive electrode CD22, and a dielectric layer ED2. The through-electrode TV2 and the capacitive electrode CD22 are disposed opposite each other with the dielectric layer ED2 interposed therebetween. The capacitor CA4 is located within the opening 124. In this case, the capacitor CA4 can be formed continuously from the bottom surface of the opening 124 to the side surface of the opening 124 and the back surface of the semiconductor substrate 111.

[0274] The dielectric layer ED2 is formed on the through electrode TV2, and the capacitance electrode CD22 is formed on the dielectric layer ED2. An insulating layer Z2 is formed on the capacitance CA4 so as to cover the opening 124.

[0275] On the back surface of the semiconductor substrate 111, a portion of the through-electrode TV2 is exposed from the dielectric layer ED2, the capacitive electrode CD22, and the insulating layer Z2. The external electrode D1 is connected to the through-electrode TV2 via the insulating layer Z2. Also, on the back surface of the semiconductor substrate 111, a portion of the capacitive electrode CD22 is exposed from the insulating layer Z2. The external electrode D2 is connected to the capacitive electrode CD22 via the insulating layer Z2.

[0276] As described above, in the twenty-first embodiment, for example, the capacitor CA3 is provided on the metal laminate portion MT1 in which the sputtered layer 116, the electroless plated layer 118, and the electrolytic plated layer 119 are sequentially laminated within the opening 114, and the through electrode TV1 also serves as the capacitor lower electrode. This makes it possible to reduce open defects while suppressing the complexity of the configuration of the capacitor CA3, even when a step disconnection occurs in the sputtered layer 116 at the bottom of the opening 114.

[0277] In the above-described eighteenth to twenty-first embodiments, examples have been shown in which a capacitance is formed on the through electrode TV1 of Fig. 1 or the through electrode TV2 of Fig. 2. In addition to this, a capacitance may be formed on the through electrode TV3 of Fig. 3, the through electrode TV4 of Fig. 4, the through electrode TV5 of Fig. 8, the through electrode TV6 of Fig. 9, the through electrode TV7 of Fig. 10, the through electrode TV8 of Fig. 11, the through electrode TV9 of Fig. 12, the through electrode TV10 of Fig. 13, or the through electrode TV11 of Fig. 14. Furthermore, a capacitance may be formed on a through electrode provided in the electronic device of Figs. 18 to 28.

[0278] 22. Twenty-Second Embodiment In the example of the first embodiment described above, electroless plated layer 128 is selectively formed on sputtered layer 126 on the bottom surface of opening 124, and then electrolytic plated layer 129 is formed. In this twenty-second embodiment, a photosensitive insulating film is embedded in the footing portion of the bottom surface of opening 124, and then sputtered layer 116, electroless plated layer 118, and electrolytic plated layer 119 are formed sequentially on the bottom surface of opening 124.

[0279] FIG. 41 is a cross-sectional view illustrating a configuration example of an electronic device according to the twenty-second embodiment.

[0280] In the figure, this electronic device has a through silicon via TV22 instead of the through silicon via TV2 in Fig. 2. Furthermore, this electronic device has a photosensitive insulating film 2201 added to the electronic device in Fig. 2. Other configurations of this electronic device are the same as those of the electronic device in Fig. 2.

[0281] A skirt portion 2200 is formed at the bottom of the opening 124 due to the notching. The skirt portion 2200 is formed so as to widen toward the bottom of the opening 124.

[0282] The photosensitive insulating film 2201 has positive photosensitivity. An inorganic material can be used as the material for the photosensitive insulating film 2201. At this time, a photosensitive agent may be mixed into the inorganic material to impart photosensitivity to the inorganic material. The photosensitive insulating film 2201 is embedded in the footing portion 2200 of the opening 124 via the insulating layer 125. At this time, the photosensitive insulating film 2201 can planarize the side surface of the opening 124 in the depth direction.

[0283] The through electrode TV22 can be configured in the same manner as the through electrode TV1 in Fig. 1. At this time, the through electrode TV22 has a sputtered layer 116, an electroless plated layer 118, and an electrolytic plated layer 119 formed in this order on the bottom surface of the opening 124.

[0284] FIG. 42 is a cross-sectional view showing an example of a method for manufacturing an electronic device according to the twenty-second embodiment.

[0285] 42A, after the step of FIG. 5C, a photosensitive inorganic solvent is applied onto the insulating layer 125 by a method such as coating. At this time, the photosensitive inorganic solvent can be embedded into the opening 124. Then, the photosensitive inorganic solvent is baked to evaporate the solvent from the photosensitive inorganic solvent, thereby forming a photosensitive insulating film 2201 on the insulating layer 125.

[0286] Next, as shown in FIG. 42 b, the photosensitive insulating film 2201 is exposed to light, causing the exposed region of the photosensitive insulating film 2201 to become soluble. At this time, the photosensitive insulating film 2201 can be exposed in the depth direction of the opening 124, and the photosensitive insulating film 2201 can be made soluble in the vertical direction. Then, the exposed region of the photosensitive insulating film 2201 is removed by developing the photosensitive insulating film 2201 after exposure. At this time, the photosensitive insulating film 2201 is embedded in the footing portion 2200 of the opening 124 via the insulating layer 125.

[0287] 42c, a sputtered layer 116 is formed by sputtering on the bottom surface of the opening 124, the side surfaces of the photosensitive insulating film 2201, and the rear surface of the semiconductor substrate 111. Thereafter, the steps from c onward in FIG.

[0288] As described above, in the above-described 22nd embodiment, after photosensitive insulating film 2201 is embedded in footing portion 2200 on the bottom surface of opening 124, sputtered layer 116, electroless plated layer 118, and electrolytic plated layer 119 are sequentially formed on the bottom surface of opening 124. This ensures the conductivity of through electrode TV22 on the bottom surface of opening 124 even when notching occurs on the bottom surface of opening 124, making it possible to accommodate miniaturization of through electrode TV22 and reduce open defects.

[0289] 23. Twenty-Third Embodiment In the example of the first embodiment described above, electroless plated layer 128 is selectively formed on sputtered layer 126 on the bottom surface of opening 124, and then electrolytic plated layer 129 is formed. In this twenty-third embodiment, the barrier metal layer formed below the seed layer used for electrolytic plating includes an ALD film.

[0290] FIG. 43 is a cross-sectional view illustrating a configuration example of an electronic device according to the twenty-third embodiment.

[0291] In the figure, this electronic device has a through electrode TV23 instead of the through electrode TV2 in Fig. 2. Other configurations of this electronic device are the same as those of the electronic device in Fig. 2.

[0292] The through silicon via TV23 includes a barrier metal layer 126A and a seed layer 126B instead of the sputtered layer 126 in Fig. 2. The other configurations of the through silicon via TV23 are the same as those of the through silicon via TV2 in Fig. 2.

[0293] The barrier metal layer 126A can be formed on the bottom surface of the opening 124, and can also be formed on the side surface of the opening 124 and the rear surface of the semiconductor substrate 111 via the insulating layer 125. The barrier metal layer 126A on the bottom surface of the opening 124 may be separated from the barrier metal layer 126A on the side surface of the opening 124. The material of the barrier metal layer 126A can be, for example, Ti (titanium). In this case, the barrier metal layer 126A can be configured to include an ALD film. In this case, the barrier metal layer 126A may be configured only of an ALD film, or may be configured of an ALD film and a sputtered film.

[0294] The seed layer 126B can be formed on the barrier metal layer 126A. The seed layer 126B can be used to form an electrolytic plated layer 129. The seed layer 126B on the bottom surface of the opening 124 may be separated from the seed layer 126B on the side surface of the opening 124. The material of the seed layer 126B can be, for example, Cu. An electroless plated layer 128 is formed on the seed layer 126B on the bottom surface of the opening 124. An electrolytic plated layer 129 is formed on the electroless plated layer 128 and on the seed layer 126B on the side surface of the opening 124.

[0295] As described above, in the twenty-third embodiment, the barrier metal layer 126A formed below the seed layer 126B used for electrolytic plating includes an ALD film. This makes it possible to improve the coverage of the barrier metal layer 126A on the bottom surface of the opening 124 even when notching occurs at the bottom of the opening 124, thereby enabling the miniaturization of the through silicon via TV23 and reducing open defects.

[0296] 24. Twenty-fourth embodiment In one example of the first embodiment described above, electroless plated layer 128 is selectively formed on sputtered layer 126 on the bottom surface of opening 124, and then electrolytic plated layer 129 is formed. In this twenty-fourth embodiment, after the electroless plated layer is selectively formed on sputtered layer 126 on the bottom surface of opening 124, the insulating layer around the electroless plated layer is removed, electroless plating is added, and then the electrolytic plated layer is formed.

[0297] FIG. 44 is a cross-sectional view illustrating a configuration example of an electronic device according to the twenty-fourth embodiment.

[0298] In the figure, this electronic device has a through electrode TV24 instead of the through electrode TV2 in Fig. 2. Other configurations of this electronic device are the same as those of the electronic device in Fig. 2.

[0299] 2, the through electrode TV24 includes electroless plated layers 128A and 128B and an electrolytic plated layer 2429. The other configurations of the through electrode TV24 are the same as those of the through electrode TV2 in FIG.

[0300] Electroless plated layer 128A is formed on sputtered layer 126 on the bottom surface of opening 124. Here, electroless plated layer 128A may be formed so as to bulge within opening 124. In this case, the outer peripheral surface of electroless plated layer 128A can be spaced apart from sputtered layer 126.

[0301] An electroless plated layer 128B is formed on the electroless plated layer 128A. Here, the electroless plated layer 128B can cover the outer peripheral surface of the electroless plated layer 128A. At this time, the electroless plated layer 128B can penetrate into the gap between the electroless plated layer 128A and the sputtered layer 126 and can be formed from the side surface to the upper surface of the sputtered layer 126.

[0302] An electrolytic plated layer 2429 is formed on electroless plated layer 128B. At this time, electrolytic plated layer 2429 can be formed on electroless plated layer 128A and from the side surfaces to the upper surface of electroless plated layer 128A.

[0303] FIG. 45 is a cross-sectional view showing an example of a method for manufacturing an electronic device according to the twenty-fourth embodiment.

[0304] 45a, after the step of FIG. 7a, an electroless plated layer 128A is selectively formed on the sputtered layer 126 on the bottom surface of the opening 124 by electroless plating.

[0305] 45B, insulating layer 127 on sputtered layer 126 is removed by a method such as plasma etching. At this time, a gap can be formed between sputtered layer 126 and the outer peripheral surface of electroless plated layer 128A.

[0306] Next, as shown in Fig. 45c, electroless plated layer 128B is formed on electroless plated layer 128A. At this time, the gap between sputtered layer 126 and the outer peripheral surface of electroless plated layer 128A can be filled with electroless plated layer 128B. Then, as shown in Fig. 44, electrolytic plated layer 2429 is formed on electroless plated layer 128B based on electroplating using sputtered layer 126 as a seed layer.

[0307] As described above, in the 24th embodiment, electroless plated layer 128A is selectively formed on sputtered layer 126 on the bottom surface of opening 124, and then insulating layer 127 around electroless plated layer 128A is removed to form electroless plated layer 128B, and then electrolytic plated layer 2429 is formed. This makes it possible to improve the film formation efficiency of electrolytic plated layer 2429 and ensure the conductivity of through electrode TV22 on the bottom surface of opening 124, even when notching occurs on the bottom of opening 124.

[0308] 25. Twenty-fifth Embodiment In the example of the first embodiment described above, electroless plated layer 128 is selectively formed on sputtered layer 126 on the bottom surface of opening 124, and then electrolytic plated layer 129 is formed. In this twenty-fifth embodiment, a sputtered layer, an electroless plated layer, and an electrolytic plated layer are sequentially laminated on the bottom surface of an opening having a plurality of footing portions formed at different depth positions.

[0309] FIG. 46 is a cross-sectional view illustrating a configuration example of an electronic device according to the twenty-fifth embodiment.

[0310] In the figure, this electronic device has a through silicon via TV25 instead of the through silicon via TV2 in Fig. 2. Other configurations of this electronic device are the same as those of the electronic device in Fig. 2.

[0311] An opening 2524 is formed in the semiconductor substrate 111. The opening 2524 can penetrate the semiconductor substrate 111 and reach the wiring layer 112. The opening 2524 has footing portions 2501 and 2502 formed at different positions in the depth direction. The footing portion 2501 can be located at the bottom surface of the opening 2524, and the footing portion 2502 can be located in the middle of the opening 2524. At this time, a step corresponding to the footing portion 2502 is formed on the inner surface of the opening 2524. An insulating layer 2525 is formed on the inner surface of the opening 2524. The through electrode TV25 can be formed along the inner surface of the opening 2524 via the insulating layer 2525.

[0312] The sputtered layer 2526 is formed on the bottom surface of the opening 2524, and can also be formed on the side surface of the opening 2524 and the rear surface of the semiconductor substrate 111 via the insulating layer 2525. On the bottom surface of the opening 2524, an electroless plating layer 2528 is formed on the sputtered layer 2526.

[0313] An electrolytic plated layer 2529 is formed on electroless plated layer 2528. At this time, electrolytic plated layer 2529 can be formed continuously from above electroless plated layer 2528, via sputtered layer 2526, onto the side surface of opening 2524 and onto the rear surface of semiconductor substrate 111. The step of opening 2524 is reflected in insulating layer 2525, sputtered layer 2526, and electroless plated layer 2528.

[0314] 47 and 48 are cross-sectional views showing an example of a method for manufacturing an electronic device according to the twenty-fifth embodiment.

[0315] 47A, a resist pattern RS1 is formed on the semiconductor substrate 111 using lithography. An opening KA3 is provided in the resist pattern RS1. The opening KA3 is disposed at the position of the opening 2524.

[0316] Next, as shown in FIG. 47 b, an opening 2524′ is formed in the semiconductor substrate 111 by anisotropic etching using the resist pattern RS1 as an etching mask. The depth of the opening 2524′ can be shallower than the depth of the opening 2524. Here, a footing portion 2502 is formed on the bottom surface of the opening 2524′ by notching. In this case, by making the depth of the opening 2524′ shallower than the depth of the opening 2524, the footing portion 2502 can be made smaller than when the depth of the opening 2524′ is equal to the depth of the opening 2524.

[0317] 47c, resist pattern RS1 is removed by ashing or other methods. Then, using lithography, resist pattern RS2 is formed on semiconductor substrate 111 so as to cover the side surfaces of opening 2524'. Resist pattern RS2 can be removed from the bottom of opening 2524'.

[0318] 48 a, an opening 2524 is formed in the semiconductor substrate 111 by anisotropic etching using the resist pattern RS2 as an etching mask. Here, a footing portion 2501 is formed on the bottom surface of the opening 2524 by notching. At this time, by forming the opening 2524 through the opening 2524′, the footing portion 2501 can be made smaller than when the opening 124 in FIG. 2 is formed without the opening 2524′.

[0319] 48b, the resist pattern RS2 is removed by ashing or other methods, and then the steps from c onward in FIG. 5 are carried out to form the through electrodes TV25.

[0320] In this way, in the above-described twenty-fifth embodiment, sputtered layer 2526, electroless plated layer 2528, and electrolytic plated layer 2529 are sequentially laminated on the bottom surface of opening 2524, in which multiple footing portions 2501, 2502 are formed at different positions in the depth direction. This makes it possible to suppress an increase in the notching shape even when opening 2524 is deep, and reduces open defects while accommodating miniaturization of through silicon via TV25.

[0321] 26. Twenty-Sixth Embodiment In the example of the first embodiment described above, electroless plated layer 128 is selectively formed on sputtered layer 126 on the bottom surface of opening 124, and then electrolytic plated layer 129 is formed. In this twenty-sixth embodiment, a SIMOX layer is provided over the entire substrate at a midpoint in the depth direction of the opening so as to surround the periphery of the opening, and a sputtered layer, an electroless plated layer, and an electrolytic plated layer are sequentially stacked on the bottom surface of the opening.

[0322] FIG. 49 is a cross-sectional view showing a configuration example of an electronic device according to the twenty-sixth embodiment.

[0323] In the figure, this electronic device has a through electrode TV26 instead of the through electrode TV2 in Fig. 2. Other configurations of this electronic device are the same as those of the electronic device in Fig. 2.

[0324] A SIMOX layer 2611 is formed in the semiconductor substrate 111. The SIMOX layer 2611 can be disposed at the center of the semiconductor substrate 111 in the depth direction. An opening 2624 is formed in the semiconductor substrate 111. The opening 2624 can penetrate the semiconductor substrate 111 and the SIMOX layer 2611 and reach the wiring layer 112. The opening 2624 has footing portions 2601 and 2602 formed at different positions in the depth direction. The footing portion 2601 can be located at the bottom surface of the opening 2624, and the footing portion 2602 can be located on the SIMOX layer 2611. An insulating layer 2625 is formed on the inner surface of the opening 2624. The through electrode TV26 can be formed along the inner surface of the opening 2624 via the insulating layer 2625.

[0325] The sputtered layer 2626 is formed on the bottom surface of the opening 2624, and can also be formed via the insulating layer 2625 on the side surface of the opening 2624 and the rear surface of the semiconductor substrate 111. On the bottom surface of the opening 2624, an electroless plating layer 2628 is formed on the sputtered layer 2626.

[0326] An electrolytic plated layer 2629 is formed on the electroless plated layer 2628. At this time, the electrolytic plated layer 2629 can be formed continuously from the electroless plated layer 2628, via the sputtered layer 2626, onto the side surface of the opening 2624 and onto the rear surface of the semiconductor substrate 111.

[0327] 50 and 51 are cross-sectional views showing an example of a method for manufacturing an electronic device according to the twenty-sixth embodiment.

[0328] In FIG. 50A, a wiring layer 112 is formed on a semiconductor substrate 111 .

[0329] As shown in FIG. 50b, oxygen ions are implanted into the semiconductor substrate 111, and then the semiconductor substrate 111 is heat-treated to form a SIMOX layer 2611 in the semiconductor substrate 111.

[0330] 50c, a resist pattern RS4 is formed on the semiconductor substrate 111 using lithography. An opening KA6 is provided in the resist pattern RS4. The opening KA6 is disposed at the position of the opening 2624.

[0331] Next, as shown in FIG. 51 a, an opening 2624′ is formed in the semiconductor substrate 111 by anisotropic etching using the resist pattern RS4 as an etching mask. The depth of the opening 2624′ can be set to a position in the depth direction of the SIMOX layer 2611. Here, a footing portion 2602 is formed on the bottom surface of the opening 2624′ by notching. In this case, by setting the depth of the opening 2624′ to a position in the depth direction of the SIMOX layer 2611, the footing portion 2602 can be made smaller than when the depth of the opening 2624′ is equal to the depth of the opening 2624.

[0332] Next, as shown in Fig. 51b, an opening 2624 is formed by anisotropic etching using resist pattern RS4 as an etching mask. Here, a footing portion 2601 is formed by notching at the bottom surface of opening 2624. In this case, by forming opening 2624 through opening 2624', footing portion 2601 can be made smaller than when opening 124 in Fig. 2 is formed without opening 2624'.

[0333] Next, as shown in Fig. 51c, the resist pattern RS4 is removed by ashing or the like. Then, the steps from Fig. 5c onwards are carried out to form the through electrodes TV26.

[0334] As described above, in the twenty-sixth embodiment, SIMOX layer 2611 is provided over the entire semiconductor substrate 111 at the intermediate position in the depth direction of opening 2624 so as to surround the periphery of opening 2624, and sputtered layer 2626, electroless plated layer 2628, and electrolytic plated layer 2629 are sequentially stacked on the bottom surface of opening 2624. This makes it possible to suppress an increase in the notching shape even when opening 2624 is deep, and to reduce open defects while accommodating miniaturization of through silicon via TV 26.

[0335] 27. Twenty-seventh embodiment In the twenty-sixth embodiment described above, the SIMOX layer 2611 is provided over the entire semiconductor substrate 111 at a midpoint in the depth direction of the opening 2624 so as to surround the periphery of the opening 2624. In this twenty-seventh embodiment, the SIMOX layer is provided in a part of the semiconductor substrate 111 so as to surround the periphery of the opening 2624 so as to be at a midpoint in the depth direction of the opening 2624.

[0336] FIG. 52 is a cross-sectional view showing a configuration example of an electronic device according to the twenty-seventh embodiment.

[0337] In the figure, this electronic device has a through silicon via TV27 instead of the through silicon via TV26 in Fig. 49. Other configurations of this electronic device are the same as those of the electronic device in Fig. 49.

[0338] 49. However, a SIMOX layer 2711 is provided in the semiconductor substrate 111 at the intermediate position in the depth direction of the opening 2624 so as to surround the periphery of the opening 2624. The SIMOX layer 2711 can be disposed only around the periphery of the opening 2624.

[0339] 53 and 54 are cross-sectional views showing an example of a method for manufacturing an electronic device according to the twenty-seventh embodiment.

[0340] 53A, a resist pattern RS5 is formed on the semiconductor substrate 111 by lithography. An opening KA7 is provided in the resist pattern RS5. The opening KA7 is disposed at a position overlapping the SIMOX layer 2711.

[0341] Next, as shown in FIG. 53b, a SIMOX layer 2711 is formed on the semiconductor substrate 111 based on ion implantation using the resist pattern RS5 as a mask.

[0342] 53c, a resist pattern RS4 is formed on the semiconductor substrate 111 using lithography. An opening KA6 is provided in the resist pattern RS4. The opening KA6 is disposed at the position of the opening 2624.

[0343] Next, as shown in FIG. 54, after performing the same steps as those in FIG. 51, steps c and thereafter in FIG. 5 are performed to form the through electrodes TV27.

[0344] As described above, in the above-described 27th embodiment, the SIMOX layer 2711 is provided in a part of the semiconductor substrate 111 at the intermediate position in the depth direction of the opening 2624 so as to surround the periphery of the opening 2624. This makes it possible to suppress an increase in the notching shape even when the depth of the opening 2624 is deep, and to reduce open defects while accommodating miniaturization of the through silicon via TV27.

[0345] Note that the capacitors of any of the above-described 18th to 21st embodiments may be formed on the through silicon vias TV22 to TV27 of the above-described 22nd to 27th embodiments. Furthermore, the through silicon vias TV22 to TV27 of the above-described 22nd to 27th embodiments may be applied to the chips of the above-described 7th to 17th embodiments.

[0346] 28. Twenty-eighth Embodiment In the first embodiment described above, metal laminate portion MT1, in which sputtered layer 116, electroless plated layer 118, and electrolytic plated layer 119 are laminated, is provided within opening 114. In this twenty-eighth embodiment, a metal laminate portion, in which electroless plated layer, sputtered layer, and electrolytic plated layer are laminated, is provided within an opening, the electroless plated layer is embedded in a wiring layer provided below the opening, and no wiring is disposed below the electroless plated layer.

[0347] FIG. 55 is a cross-sectional view showing a configuration example of an electronic device according to the twenty-eighth embodiment.

[0348] 8, this electronic device has a through silicon via TV28 and a wiring layer 2812 instead of the through silicon via TV5 and wiring layer 112 in FIG. 8. Other configurations of this electronic device are the same as those of the electronic device in FIG.

[0349] The wiring layer 2812 is formed on the semiconductor substrate 111. A wiring 2813 embedded in an insulating layer is formed in the wiring layer 2812. Insulating layers 2814 and 2815 are sequentially stacked on the wiring layer 2812. The insulating layer 2814 may be a PMD (Pre-Metal Dielectric). The insulating layer 2815 may be an STI (Shallow Trench Isolation). The insulating layers 2814 and 2815 may be made of an oxide film or a nitride film.

[0350] The wiring layer 2812 also has a recess KA. The recess KA is connected to the opening 114 via insulating layers 2814 and 2815. At this time, the wiring 2813 can be exposed on the side surface of the recess KA. Alternatively, the wiring 2813 can be prevented from being exposed on the bottom surface of the recess KA. A guard ring GR is formed around the recess KA. The guard ring GR can surround the recess KA. The planar shape of the guard ring GR may be ring-shaped or rectangular.

[0351] An insulating layer 115 is formed on the inner surface of the opening 114. The insulating layer 115 may be formed continuously from the side surface of the opening 114 to the rear surface of the semiconductor substrate 111. In this case, the insulating layer 115 may be in contact with the insulating layer 2814 via the insulating layer 2815.

[0352] The through electrode TV28 penetrates the semiconductor substrate 111 and is connected to the wiring layer 2812. The through electrode TV28 includes a metal stack portion MT28. The metal stack portion MT28 is disposed at the tip of the through electrode TV28. The tip of the through electrode TV28 can be located at the bottom of the opening 114. The metal stack portion MT28 can have a stacked structure of an electroless plated layer 2818, a sputtered layer 116, and an electrolytic plated layer 2819. The metal stack portion MT28 may include a barrier metal layer 120 between the electroless plated layer 2818 and the sputtered layer 116.

[0353] The electroless plated layer 2818 is embedded in the recess KA. At this time, the electroless plated layer 2818 can be electrically connected to the guard ring GR. On the electroless plated layer 2818, a barrier metal layer 120, a sputtered layer 116, and an electrolytic plated layer 2819 are sequentially stacked.

[0354] Barrier metal layer 120 may be formed continuously from above electrolessly plated layer 2818, across the side surfaces of insulating layer 115, and onto the upper surface thereof. Sputtered layer 116 may be formed continuously from above the bottom surface of barrier metal layer 120, across the side surfaces, and onto the upper surface thereof. Electrolytically plated layer 2819 may be formed continuously from above the bottom surface of sputtered layer 116, across the side surfaces, and onto the upper surface thereof. Note that a portion of barrier metal layer 120 may be located within recess KA, or portions of barrier metal layer 120 and sputtered layer 116 may be located within recess KA, or portions of barrier metal layer 120, sputtered layer 116, and electrolytically plated layer 2819 may be located within recess KA.

[0355] 56 to 61 are diagrams showing an example of a method for manufacturing an electronic device according to the 28th embodiment. Note that Fig. 56(a) to Fig. 61(a) are cross-sectional views showing an example of a method for manufacturing an electronic device according to the 28th embodiment, and Fig. 56(b) to Fig. 61(b) are plan views showing an example of a method for manufacturing an electronic device according to the 28th embodiment. Fig. 56(b) to Fig. 61(b) show a perspective view of the planar shape of wiring 2813.

[0356] 56 , an insulating layer 2815 is embedded in the semiconductor substrate 111. At this time, the insulating layer 2815 can be disposed around the position where the recess KA of the semiconductor substrate 111 is formed. Then, an insulating layer 2814 is formed on the semiconductor substrate 111 and the insulating layer 2815 by a method such as CVD. Next, a wiring layer 2812 is formed on the insulating layer 2814. A wiring 2813 including a guard ring GR is formed in the wiring layer 2812.

[0357] 57, the semiconductor substrate 111 is selectively etched from the back surface side thereof to form an opening 114 in the semiconductor substrate 111. The semiconductor substrate 111 can be etched by anisotropic etching such as RIE (Reactive Ion Etching), for example.

[0358] 58, an insulating layer 2814 is formed on the semiconductor substrate 111 and the insulating layer 2815 by a method such as CVD. At this time, the back surface of the semiconductor substrate 111 can be covered with the insulating layer 115.

[0359] 59 , the insulating layer 2814 and the wiring layer 2812 are selectively etched through the opening 114 to form a recess KA in the wiring layer 2812. The insulating layer 2814 and the wiring layer 2812 can be etched by anisotropic etching such as RIE. At this time, the recess KA can be disposed in a self-aligned manner with respect to the opening 114. Furthermore, a portion of the wiring 2813 can be exposed at the side surface of the recess KA.

[0360] Next, as shown in FIG. 60, an electroless plated layer 2818 is formed in the recess KA by electroless plating.

[0361] 61, a barrier metal layer 120 and a sputtered layer 116 are formed by sputtering on the electroless plated layer 2818. Then, an electroplated layer 2819 is formed on the sputtered layer 116 by electroplating using the sputtered layer 116 as a seed layer.

[0362] In this way, in the above-described twenty-eighth embodiment, metal laminate portion MT28, in which electroless plated layer 2818, sputtered layer 116, and electrolytic plated layer 2819 are laminated, is provided in opening 114. This ensures the conductivity of through electrode TV28 at the bottom surface of opening 114 even when a step disconnection occurs in sputtered layer 116 at the bottom of opening 114, and enables the miniaturization of through electrode TV28 to be accommodated while reducing open defects.

[0363] Furthermore, the electroless plated layer 2818 is embedded in the wiring layer 2812 provided below the opening 114. At this time, a circuit design can be achieved in which no wiring exists below the electroless plated layer 2818. The through electrode TV28 can ensure conductivity with the wiring layer 2812 via the electroless plated layer 2818, while preventing the wiring 2813 from existing below the opening 114. This makes it possible to prevent etching products generated when etching the insulating layer 115, the insulating layer 2814, and the wiring layer 2812 from remaining on the bottom and side surfaces of the opening 114, thereby improving yield and reliability.

[0364] 29. Twenty-ninth embodiment In the twenty-eighth embodiment described above, an electroless plated layer 2818 is embedded in the wiring layer 2812 provided below the opening 114, and no wiring 2813 is disposed in contact with the electroless plated layer 2818. In this twenty-ninth embodiment, an electroless plated layer 2818 is embedded in the wiring layer 2812 provided below the opening 114, and the wiring 2813 is disposed below the electroless plated layer 2818.

[0365] FIG. 62 is a cross-sectional view showing a configuration example of an electronic device according to the twenty-ninth embodiment.

[0366] In the figure, this electronic device has a wiring layer 2912 instead of the wiring layer 2812 in Fig. 55. Other configurations of this electronic device are the same as those of the electronic device in Fig. 55.

[0367] The wiring layer 2912 is formed on the semiconductor substrate 111. A wiring 2913 embedded in an insulating layer is formed in the wiring layer 2912. Insulating layers 2814 and 2815 are formed between the wiring layer 2912 and the semiconductor substrate 111.

[0368] The wiring layer 2912 also has a recess KA. The recess KA is connected to the opening 114 via the insulating layers 2814 and 2815. At this time, the wiring 2913 can be exposed from the bottom surface of the recess KA.

[0369] The through electrodes TV28 penetrate the semiconductor substrate 111 and are connected to the wiring layer 2912. At this time, the bottom surface of the electroless plating layer 2818 can be brought into contact with the wiring 2913.

[0370] Figures 63 to 68 are diagrams showing an example of a method for manufacturing an electronic device according to the 29th embodiment. Note that Figures 63a to 68a are cross-sectional views showing an example of a method for manufacturing an electronic device according to the 29th embodiment, and Figures 63b to 68b are plan views showing an example of a method for manufacturing an electronic device according to the 29th embodiment. Figures 63b to 68b also show the planar shape of wiring 2813 in a see-through manner.

[0371] 63 to 68 , the method for manufacturing an electronic device according to the twenty-ninth embodiment is similar to the steps shown in FIGS. 56 to 61 , except that the wiring layer 2812 of the twenty-eighth embodiment described above is replaced with a wiring layer 2912. However, in the step shown in FIG. 66 , a recess KA is formed in the wiring layer 2912 by selectively etching the insulating layer 2814 and the wiring layer 2912 through the opening 114. At this time, a portion of the wiring 2913 is exposed at the bottom of the recess KA. Furthermore, in the step shown in FIG. 67 , an electroless plated layer 2818 is embedded in the recess KA, so that the bottom of the electroless plated layer 2818 comes into contact with the wiring 2913.

[0372] As described above, in the twenty-ninth embodiment, the electroless plated layer 2818 is embedded in the wiring layer 2912 provided below the opening 114, and the wiring 2813 is provided below the electroless plated layer 2818. This reduces the contact resistance between the through electrode TV28 and the wiring layer 2912 while ensuring conductivity between the through electrode TV28 and the wiring layer 2912, thereby improving EM (electromigration) resistance.

[0373] 30. Thirty-first embodiment In the twenty-eighth embodiment described above, an electroless plated layer 2818 is embedded in the wiring layer 2812 provided below the opening 114, and no wiring 2813 is disposed below the electroless plated layer 2818. In this thirtieth embodiment, an electroless plated layer 2818 is embedded in the wiring layer 2812 provided below the opening 124 that widens in the depth direction, and no wiring 2813 is present below the electroless plated layer 2818.

[0374] FIG. 69 is a cross-sectional view showing a configuration example of an electronic device according to the 30th embodiment.

[0375] 55. In the figure, this electronic device has a through silicon via TV 30 and an opening 124 instead of the through silicon via TV 28 and the opening 114 in Fig. 55. Other configurations of this electronic device are the same as those of the electronic device in Fig. 55.

[0376] The through silicon via TV30 includes a barrier metal layer 3030, a sputter layer 3026, and an electrolytic plating layer 3029 instead of the barrier metal layer 120, the sputter layer 116, and the electrolytic plating layer 2819 in Fig. 55. The other configurations of the through silicon via TV30 are the same as those of the through silicon via TV28 in Fig. 55.

[0377] Barrier metal layer 3030, sputtered layer 3026, and electrolytic plated layer 3029 are sequentially stacked on electroless plated layer 2818. Barrier metal layer 3030, sputtered layer 3026, and electrolytic plated layer 3029 are formed to conform to the depth-wise shape of opening 124. In this case, barrier metal layer 3030, sputtered layer 3026, and electrolytic plated layer 3029 can have a shape that extends in the depth direction of opening 124. Note that a portion of barrier metal layer 3030 may be located within recess KA, or portions of barrier metal layer 3030 and sputtered layer 3026 may be located within recess KA, or portions of barrier metal layer 3030, sputtered layer 3026, and electrolytic plated layer 3029 may be located within recess KA.

[0378] As described above, in the 30th embodiment, the electroless plated layer 2818 is embedded in the wiring layer 2812 provided below the opening 124 that widens in the depth direction, and the wiring 2813 is not disposed below the electroless plated layer 2818. This prevents etching products generated when the insulating layer 125, the insulating layer 2814, and the wiring layer 2812 are etched from remaining on the bottom and side surfaces of the opening 124, while ensuring conductivity between the through electrode TV30 and the wiring layer 2812.

[0379] In the above-described thirtieth embodiment, the configuration in which the through silicon via TV30 is connected to the wiring layer 2812 has been shown, but the through silicon via TV30 may be connected to the wiring layer 2912 instead.

[0380] 31. Thirty-first embodiment In the thirtieth embodiment described above, an electroless plated layer 2818 is embedded in the wiring layer 2812 provided below the opening 124 that widens in the depth direction, and a structure is adopted in which no wiring 2813 is disposed below the electroless plated layer 2818. In this thirty-first embodiment, an electroless plated layer having an electrolytic plated layer laminated thereon is provided on the bottom surface of the opening, and a via embedded in the semiconductor substrate 111 is formed below the electroless plated layer, and the via is configured with a sputtered film.

[0381] FIG. 70 is a cross-sectional view showing a configuration example of an electronic device according to the thirty-first embodiment.

[0382] In the figure, a recess 3111 is formed in a semiconductor substrate 111. A via 3112 or a wiring 3112 (hereinafter referred to as a via 3112 for simplicity) is buried in the recess 3111. At this time, an insulating layer 3113 is formed between the recess 3111 and the via 3112, thereby insulating the semiconductor substrate 111 from the via 3112. The via 3112 can be made of a sputtered film. The material of the via 3112 can be, for example, Cu.

[0383] A wiring layer 112 is formed on the semiconductor substrate 111. A via 3112 can be located on the wiring layer 112. In this case, the via 3112 can protrude onto the wiring layer 112. The via 3112 can be electrically connected to the wiring 113.

[0384] Furthermore, an opening 3124 is formed in the semiconductor substrate 111. The opening 3124 can be disposed below the recess 3111. The opening 3124 can penetrate the semiconductor substrate 111 and reach the via 3112. The shape of the opening 3124 may widen toward the bottom surface.

[0385] An insulating layer 3125 is formed on the inner surface of the opening 3124. The insulating layer 3125 may be formed continuously from the side surface of the opening 3124 to the rear surface of the semiconductor substrate 111.

[0386] A through electrode TV31 is formed in the opening 3124 via an insulating layer 3125. The through electrode TV31 is disposed on the via 3112. At this time, the through electrode TV31 can be electrically connected to the via 3112. The through electrode TV31 includes an electroless plating layer 3128, a sputtering layer 3126, and an electrolytic plating layer 3129.

[0387] The electroless plated layer 3128 is formed on the via 3112 within the opening 3124. At this time, the electroless plated layer 3128 can be electrically connected to the via 3112.

[0388] The sputtered layer 3126 can be formed on the side surface of the opening 3124 and on the rear surface of the semiconductor substrate 111 via the insulating layer 3125. The sputtered layer 3126 can be used as a seed layer for forming the electroplated layer 3129.

[0389] An electrolytic plating layer 3129 is formed on electroless plating layer 3128 and sputtered layer 3126. Electrolytic plating layer 3129 can be formed continuously from electroless plating layer 3128, via sputtered layer 3126, onto the side surface of opening 3124 and the rear surface of semiconductor substrate 111. Sputtered layer 3126 and electrolytic plating layer 3129 are formed to conform to the shape of opening 3124 in the depth direction. In this case, sputtered layer 3126 and electrolytic plating layer 3129 can have a shape that extends in the depth direction of opening 3124.

[0390] As described above, in the thirty-first embodiment, the electroless plated layer 3128 on which the electrolytic plated layer 3129 is laminated is provided on the bottom surface of the opening 3124, the via 3112 embedded in the semiconductor substrate 111 is formed below the electroless plated layer 3128, and the via 3112 is made of a sputtered film. This allows the depth of the through electrode TV31 to be shallower than the thickness of the semiconductor substrate 111, thereby improving the embeddability of the electrolytic plated layer 3129. This makes it possible to reduce open defects (disconnections) while responding to the miniaturization of the through electrode TV31.

[0391] 32. Thirty-Second Embodiment In the thirty-first embodiment described above, electroless plated layer 3128 having electrolytic plated layer 3129 laminated thereon is provided on the bottom surface of opening 3124, via 3112 embedded in semiconductor substrate 111 is formed below electroless plated layer 3128, and via 3112 is composed of a sputtered film. In this thirty-second embodiment, electroless plated layer 3128 having electrolytic plated layer 3129 laminated thereon is provided on the bottom surface of opening 3124, via 3112 embedded in semiconductor substrate 111 is formed below electroless plated layer 3128, and via 3112 is composed of a plated film and a sputtered film thereon.

[0392] FIG. 71 is a cross-sectional view illustrating a configuration example of an electronic device according to the thirty-second embodiment.

[0393] In the figure, this electronic device has a via 3212 or a wiring 3212 (hereinafter referred to as a via 3212 for the sake of simplicity) instead of the via 3112 in Fig. 70. The other configurations of this electronic device are the same as those of the electronic device in Fig. 70.

[0394] The via 3212 is embedded in the recess 3111. An insulating layer 3113 is formed between the recess 3111 and the via 3112. The via 3212 can be composed of a plating film 3212A and a sputtered film 3212B formed thereon. The plating film 3212A and the sputtered film 3212B can be made of, for example, Cu. By configuring the via 3112 with the plating film 3212A and the sputtered film 3212B, the sputtered film 3212B can be used as a seed layer, and the embedding property in the recess 3111 can be improved.

[0395] The via 3212 can be disposed on the wiring layer 112. In this case, the via 3212 can protrude onto the wiring layer 112. The via 3212 can be electrically connected to the wiring 113.

[0396] As described above, in the thirty-second embodiment, electroless plated layer 3128 on which electrolytic plated layer 3129 is laminated is provided on the bottom surface of opening 3124, via 3212 embedded in semiconductor substrate 111 is formed below electroless plated layer 3128, and via 3212 is formed of plating film 3212A and sputtered film 3212B thereon. This allows the depth of through electrode TV31 to be shallower than the thickness of semiconductor substrate 111, improving the embeddability of electrolytic plated layer 3129. This makes it possible to accommodate miniaturization of through electrode TV31 while reducing open defects.

[0397] 33. Thirty-Third Embodiment In the thirty-first embodiment described above, electroless plated layer 3128 having electrolytic plated layer 3129 laminated thereon is provided on the bottom surface of opening 3124, via 3112 embedded in semiconductor substrate 111 is formed below electroless plated layer 3128, and via 3112 is made of a sputtered film. In this thirty-third embodiment, an electroless plated layer having electrolytic plated layer laminated thereon is provided on the bottom surface of the opening, and wiring embedded in the semiconductor substrate is formed below the electroless plated layer.

[0398] FIG. 72 is a cross-sectional view illustrating a configuration example of an electronic device according to the thirty-third embodiment.

[0399] In the figure, a recess 3311 is formed in the semiconductor substrate 111. Wiring or vias 3312, 3314 (hereinafter referred to as wirings 3312, 3314 for simplicity) are buried in the recess 3311. The wiring 3314 is stacked on the wiring 3312. At this time, the width of the wiring 3314 can be smaller than the width of the wiring 3312. Furthermore, an insulating layer 3313 can be formed between the recess 3311 and the wiring 3314 to insulate the semiconductor substrate 111 from the wiring 3314. The wiring 3312 can be made of a CVD film. The wiring 3314 can be made of a sputtered film. The wiring 3312 can be made of, for example, W. The wiring 3314 can be made of, for example, Cu. The wiring 3312 can also be made of Ru. By using Ru as the material for the wiring 3312, it is possible to improve the embeddability of the wiring 3312, and it is also possible to improve the conductivity by stacking the wiring 3314 made of Cu on the wiring 3312. The wirings 3312 and 3314 may be used, for example, in a backside PDN (Power Delivery Network).

[0400] A wiring layer 112 is formed on a semiconductor substrate 111. Wirings 3312 and 3314 can be disposed on the wiring layer 112. At this time, the wirings 3312 and 3314 can protrude above the wiring layer 112. The wirings 3312 and 3314 can be electrically connected to the wiring 113.

[0401] Furthermore, an opening 3324 is formed in the semiconductor substrate 111. The opening 3324 can be disposed below the recess 3311. The opening 3324 can penetrate the semiconductor substrate 111 and reach the wirings 3312 and 3314. The shape of the opening 3324 may widen toward the bottom surface.

[0402] An insulating layer 3325 is formed on the inner surface of the opening 3324. The insulating layer 3325 may be formed continuously from the side surface of the opening 3324 to the rear surface of the semiconductor substrate 111.

[0403] A through electrode TV33 is formed in the opening 3324 via an insulating layer 3325. The through electrode TV33 is disposed on the wirings 3312 and 3314. At this time, the through electrode TV33 can be electrically connected to the wirings 3312 and 3314. The through electrode TV33 includes an electroless plating layer 3328, a sputtering layer 3326, and an electrolytic plating layer 3329.

[0404] The electroless plated layer 3328 is formed on the wirings 3312 and 3314 within the opening 3324. At this time, the electroless plated layer 3328 can be electrically connected to the wirings 3312 and 3314.

[0405] The sputtered layer 3326 can be formed on the side surface of the opening 3324 and on the rear surface of the semiconductor substrate 111 via the insulating layer 3325. The sputtered layer 3326 can be used as a seed layer for forming the electrolytic plated layer 3329.

[0406] An electrolytic plating layer 3329 is formed on the electroless plating layer 3328 and the sputtered layer 3326. The electrolytic plating layer 3329 can be formed continuously from the electroless plating layer 3328, via the sputtered layer 3326, onto the side surface of the opening 3324 and onto the rear surface of the semiconductor substrate 111. The sputtered layer 3326 and the electrolytic plating layer 3329 are formed to conform to the shape of the depth of the opening 3324. In this case, the sputtered layer 3326 and the electrolytic plating layer 3329 can have a shape that extends in the depth direction of the opening 2124.

[0407] As described above, in the thirty-third embodiment, the electroless plated layer 3328 on which the electrolytic plated layer 3329 is laminated is provided on the bottom surface of the opening 3324, and the wiring 3312, 3314 embedded in the semiconductor substrate 111 are formed below the electroless plated layer 3328. This allows the depth of the through electrode TV 33 to be shallower than the thickness of the semiconductor substrate 111, thereby improving the embeddability of the electrolytic plated layer 3329 and reducing the wiring resistance without increasing the planar size of the wiring layer 112. This makes it possible to reduce open defects while responding to miniaturization of the through electrode TV 33 and stabilize the potential during operation of the electronic device.

[0408] 34. Thirty-fourth embodiment In the twenty-ninth embodiment described above, the structure is such that the electroless plated layer 2818 is embedded in the wiring layer 2812 provided below the opening 114, and the wiring 2813 is not disposed below the electroless plated layer 2818. In this thirty-fourth embodiment, the electroless plated layer 2818 is embedded in the wiring layer 2812 provided below the opening 114, and the electroless plated layer 2818 is made to protrude into the opening 114, and the wiring 2813 in contact with the bottom of the electroless plated layer 2818 is removed.

[0409] FIG. 73 is a cross-sectional view showing a configuration example of an electronic device according to the thirty-fourth embodiment.

[0410] In the figure, this electronic device has a through silicon via TV 34 instead of the through silicon via TV 28 in Fig. 55. Other configurations of this electronic device are the same as those of the electronic device in Fig. 55.

[0411] The through electrode TV 34 includes an electroless plating layer 3418 , a barrier metal layer 3420 , a sputter layer 3416 and an electrolytic plating layer 3419 .

[0412] The electroless plated layer 3418 is embedded in the recess KA. At this time, the electroless plated layer 3418 can be electrically connected to the guard ring GR. The electroless plated layer 3418 protrudes into the opening 114. The lower surface of the electroless plated layer 3418 can be located below the surface of the semiconductor substrate 111. The surface of the semiconductor substrate 111 is the boundary surface between the semiconductor substrate 111 and the insulating layer 2815. The lower surface of the electroless plated layer 3418 can be located below the lower surface of the wiring layer 2812. The lower surface of the wiring layer 2812 is the boundary surface between the wiring layer 281 and the insulating layer 2814.

[0413] The barrier metal layer 3420 is laminated on the electroless plated layer 3418. In this case, the barrier metal layer 3420 may be formed continuously from the electroless plated layer 3418 to the upper surface of the insulating layer 115 via the side surface of the insulating layer 115.

[0414] The sputtered layer 3416 is laminated on the barrier metal layer 3420. At this time, the sputtered layer 3416 can be formed on the side surface of the opening 114 and the rear surface of the semiconductor substrate 111 from above the electroless plated layer 3418 via the barrier metal layer 3420.

[0415] Electrolytic plated layer 3419 is formed on sputtered layer 3416. Electrolytic plated layer 3419 can be formed continuously from electrolessly plated layer 3418, via sputtered layer 3416, onto the side surface of opening 114 and onto the rear surface of semiconductor substrate 111.

[0416] As described above, in the thirty-fourth embodiment, the electroless plated layer 3418 is embedded in the wiring layer 2812 provided below the opening 114, and the electroless plated layer 3418 protrudes into the opening 114, so that the wiring 2813 that contacts the electroless plated layer 3418 is not disposed below the electroless plated layer 3418. This allows the depth of the through electrode TV34 to be shallower than the thickness of the semiconductor substrate 111, thereby improving the embeddability of the electrolytic plated layer 3419. This makes it possible to accommodate the miniaturization of the through electrode TV34, reduce open defects (disconnections), and alleviate stress.

[0417] 56 to 61 can be applied to the manufacturing method of the thirty-fourth embodiment, as in the manufacturing method of the twenty-eighth embodiment. In this case, the electroless plating layer 3418 can be made to protrude into the opening 114 in the step of FIG.

[0418] 35. Thirty-fifth embodiment In the thirty-fourth embodiment described above, an electroless plated layer 3418 is embedded in wiring layer 2812 provided below opening 114, and electroless plated layer 3418 is made to protrude into opening 114, so that wiring 2813 is not disposed in contact with the electroless plated layer 3418 below. In this thirty-fifth embodiment, an electroless plated layer 3418 is embedded in wiring layer 2812 provided below opening 114, and electroless plated layer 3418 is made to protrude into opening 114, so that wiring 2813 is present below electroless plated layer 3418.

[0419] FIG. 74 is a cross-sectional view showing a configuration example of an electronic device according to the thirty-fifth embodiment.

[0420] In the figure, this electronic device includes a wiring layer 2912 instead of the wiring layer 2812 in Fig. 55. Here, the through electrodes TV34 penetrate the semiconductor substrate 111 and are connected to the wiring layer 2912. At this time, the bottom surface of the electroless plating layer 3418 can be brought into contact with the wiring 2913. Other configurations of this electronic device are the same as those of the electronic device in Fig. 55.

[0421] As described above, in the thirty-fifth embodiment, the electroless plated layer 3418 is embedded in the wiring layer 2812 provided below the opening 114, and the electroless plated layer 3418 is protruded into the opening 114, so that the wiring 2813 is present below the electroless plated layer 3418. This allows the depth of the through electrode TV34 to be shallower than the thickness of the semiconductor substrate 111, making it possible to improve the embeddability of the electrolytic plated layer 3419 and reduce the contact resistance between the through electrode TV34 and the wiring layer 2912. This makes it possible to accommodate the miniaturization of the through electrode TV34, reduce open defects, and improve EM resistance while mitigating stress.

[0422] 63 to 68 can be applied to the manufacturing method of the thirty-fifth embodiment, as with the manufacturing method of the twenty-ninth embodiment described above. In this case, the electroless plating layer 3418 can be made to protrude into the opening 114 in the step of FIG.

[0423] 36. Thirty-sixth Embodiment In the thirty-fourth embodiment described above, an electroless plated layer 3418 is embedded in wiring layer 2812 provided below opening 114, and electroless plated layer 3418 is made to protrude into opening 114, with no wiring 2813 in contact with the bottom of electroless plated layer 3418. In this thirty-sixth embodiment, an electroless plated layer is embedded in wiring layer 2812 provided below opening 124 that widens in the depth direction, and the electroless plated layer is made to protrude into opening 124, with no wiring 2813 in contact with the bottom of the electroless plated layer.

[0424] FIG. 75 is a cross-sectional view showing a configuration example of an electronic device according to the thirty-sixth embodiment.

[0425] In the figure, this electronic device has a through silicon via TV 36 instead of the through silicon via TV 30 in Fig. 69. Other configurations of this electronic device are the same as those of the electronic device in Fig. 69.

[0426] The through electrode TV 36 includes an electroless plating layer 3628 , a barrier metal layer 3620 , a sputtered layer 3626 and an electrolytic plating layer 3629 .

[0427] The electroless plated layer 3628 is embedded in the recess KA. At this time, the electroless plated layer 3628 can be electrically connected to the guard ring GR. The electroless plated layer 3628 protrudes into the opening 124. At this time, the lower surface of the electroless plated layer 3628 can be located lower than the surface of the semiconductor substrate 111. Furthermore, the lower surface of the electroless plated layer 3628 can be located lower than the lower surface of the wiring layer 2812.

[0428] The barrier metal layer 3620 is laminated on the electroless plated layer 3628. In this case, the barrier metal layer 3620 may be formed continuously from the electroless plated layer 3628 to the upper surface of the insulating layer 125 via the side surface of the insulating layer 125.

[0429] The sputtered layer 3626 is laminated on the barrier metal layer 3620. At this time, the sputtered layer 3626 can be formed on the side surface of the opening 124 and the rear surface of the semiconductor substrate 111 from above the electroless plated layer 3628 via the barrier metal layer 3620.

[0430] Electrolytic plated layer 3629 is formed on sputtered layer 3626. At this time, electrolytic plated layer 3629 can be formed continuously from above electroless plated layer 3628, via sputtered layer 3626, onto the side surface of opening 124 and onto the rear surface of semiconductor substrate 111.

[0431] As described above, in the thirty-sixth embodiment, the electroless plated layer 3628 is embedded in the wiring layer 2812 provided below the opening 124 that widens in the depth direction, and the electroless plated layer 3628 protrudes into the opening 124, so that the wiring 2813 that contacts the electroless plated layer 3628 is not disposed below the electroless plated layer 3628. This allows the depth of the through electrode TV36 to be shallower than the thickness of the semiconductor substrate 111, thereby improving the embeddability of the electrolytic plated layer 3629. This makes it possible to accommodate the miniaturization of the through electrode TV36, reduce open defects (disconnections), and alleviate stress.

[0432] In the above-mentioned thirty-sixth embodiment, an example was shown in which the electroless plating layer 3628 is embedded in the wiring layer 2812, but the electroless plating layer 3628 may also be embedded in the wiring layer 2912 of the above-mentioned thirty-fifth embodiment.

[0433] 37. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0434] FIG. 76 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology of the present disclosure can be applied.

[0435] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 76, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0436] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0437] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0438] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0439] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0440] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0441] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0442] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0443] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0444] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 76, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0445] FIG. 77 is a diagram showing an example of the installation position of the imaging unit 12031.

[0446] In FIG. 77, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0447] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0448] 77 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0449] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0450] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0451] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0452] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0453] The above describes an example of a vehicle control system to which the technology disclosed herein can be applied. The technology disclosed herein can be applied to the drivetrain control unit 12010, body system control unit 12020, outside-vehicle information detection unit 12030, inside-vehicle information detection unit 12040, integrated control unit 12050, and image capture unit 12031 among the above-described configurations. Specifically, for example, the electronic device according to the above-described embodiment can be applied to the drivetrain control unit 12010, body system control unit 12020, outside-vehicle information detection unit 12030, inside-vehicle information detection unit 12040, integrated control unit 12050, and image capture unit 12031. By applying the technology disclosed herein to the vehicle control system 12000, it is possible to reduce open defects while addressing miniaturization of through-electrodes and capacitances of electronic devices.

[0454] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology with the same title correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist. Furthermore, the effects described in this specification are merely examples and are not limited, and other effects may also be present.

[0455] The present technology may also be configured as follows: (1) An electronic device comprising: an opening having an insulated inner surface; and an electrode formed on the inner surface of the opening, wherein the electrode comprises a metal laminate portion in which metals having different compositions or structures are laminated on a bottom surface of the opening. (2) The electronic device according to (1), wherein the metal laminate portion in which the metals are laminated is located on the bottom surface and on the side surface of the opening. (3) The electronic device according to (1) or (2), wherein the structure is grain-sized. (4) The electronic device according to any one of (1) to (3), wherein the electronic device comprises a wiring layer provided below the opening and on which wiring is formed to electrically connect the electrode. (5) The electronic device according to (4), wherein at least a portion of the metal laminate portion is embedded in the wiring layer. (6) The electronic device according to (5), wherein the metal laminate portion comprises an electroless plating layer embedded in the wiring layer. (7) The electronic device according to any one of (4) to (6), wherein the wiring in the wiring layer does not contact the lower surface of the metal laminate portion. (8) The electronic device according to any one of (4) to (6), wherein the wiring exists in the wiring layer and contacts the lower surface of the metal stack portion. (9) The electronic device according to any one of (4) to (8), wherein a portion of the wiring is used as a guard ring around the metal stack portion. (10) The electronic device according to any one of (4) to (9), wherein the metal stack portion protrudes above the wiring layer. (11) The electronic device according to any one of (1) to (10), wherein the electronic device includes a semiconductor substrate in which the opening is formed. (12) The electronic device according to (11), wherein the bottom surface of the metal stack portion is located below the lower surface of the semiconductor substrate. (13) The electronic device according to (11) or (12), wherein the top surface of the metal stack portion is located above the lower surface of the semiconductor substrate. (14) The electronic device according to any one of (1) to (10), wherein the electronic device includes a via or buried wiring provided below the opening and embedded in the semiconductor substrate.(15) The electronic device according to (14), wherein the via or the embedded wiring comprises: a sputtered film formed below the metal laminate portion; and a plated film or a CVD (Chemical Vapor Deposition) film formed below the sputtered film. (16) The electronic device according to any one of (1) to (15), wherein the metal laminate portion comprises: an electroless plated layer; a sputtered layer laminated on the electroless plated layer; and an electrolytic plated layer laminated on the sputtered layer. (17) The electronic device according to any one of (1) to (15), wherein the metal laminate portion comprises: a sputtered layer; an electroless plated layer laminated on the sputtered layer; and an electrolytic plated layer laminated on the electroless plated layer. (18) The electronic device according to (17), wherein the electroless plated layer is selectively formed on the bottom surface of the opening via the sputtered layer. (19) The electronic device according to (17), wherein the electroless plating layer is selectively formed on the bottom surface of the opening and on the side surface of the opening via the sputtered layer. (20) The electronic device according to any of (17) to (19), wherein the sputtered layer on the bottom surface of the opening and the sputtered layer on the side surface of the opening are separated from each other, and the electroless plating layer is connected to the sputtered layer on the side surface of the opening via the electrolytic plating layer. (21) The electronic device according to any of (17) to (20), further comprising wiring drawn out from the opening and connected to the electrode, the wiring comprising: the sputtered layer; and an electrolytic plating layer laminated on the sputtered layer. (22) The electronic device according to any of (1) to (21), wherein the diameter of the bottom surface of the opening is larger than the diameter of the opening surface of the opening. (23) The electronic device described in any one of (1) to (22) further comprises: a first semiconductor chip having a first wiring layer formed on a first semiconductor substrate; a second semiconductor chip having a second wiring layer formed on a second semiconductor substrate and stacked on the first semiconductor chip so that the second wiring layer faces the first wiring layer; and a through electrode on which the electrode is formed and which penetrates the first semiconductor chip and is connected to the second wiring layer.(24) The electronic device according to any of (1) to (22), further comprising: a first semiconductor chip having a first wiring layer formed on a first semiconductor substrate; a second semiconductor chip having a second wiring layer formed on a second semiconductor substrate and stacked on the first semiconductor chip so that the second wiring layer faces the first wiring layer; and a through electrode on which the electrode is formed, passing through the first semiconductor substrate and connected to the first wiring layer. (25) The electronic device according to any of (1) to (22), further comprising: a first semiconductor chip having a first wiring layer formed on a first semiconductor substrate; a second semiconductor chip having a second wiring layer formed on a second semiconductor substrate and stacked on the first semiconductor chip so that the second wiring layer faces the first wiring layer; a buried layer formed on the first semiconductor chip so that the second semiconductor chip is buried; a third semiconductor chip having a third wiring layer formed on a third semiconductor substrate and stacked on the buried layer; and a through electrode on which the electrode is formed, passing through the third semiconductor chip and the second semiconductor chip and connected to the first wiring layer. (26) The electronic device according to any one of (1) to (22), further comprising: a first semiconductor chip having a first wiring layer formed on a first semiconductor substrate; a second semiconductor chip having a second wiring layer formed on a second semiconductor substrate and stacked on the first semiconductor chip so that the second wiring layer faces the first wiring layer; a buried layer formed on the first semiconductor chip so that the second semiconductor chip is buried; a third semiconductor chip having a third wiring layer formed on a third semiconductor substrate and stacked on the buried layer; and a through electrode formed on the electrode, penetrating the third semiconductor chip and the buried layer to be connected to the first wiring layer. (27) The electronic device according to any one of (1) to (26), further comprising: a capacitor located in the opening and formed on the electrode. (28) The electronic device according to (27), wherein the capacitor comprises: a first capacitor electrode formed on the electrode; and a second capacitor electrode formed on the first capacitor electrode via a dielectric layer.(29) The electronic device according to (27), wherein the capacitor comprises: a first capacitor electrode also serving as the electrode; and a second capacitor electrode formed on the first capacitor electrode via a dielectric layer. (30) The electronic device according to any one of (27) to (29), wherein the capacitor comprises: an insulating layer formed on the capacitor via a cavity in the opening. (31) The electronic device according to any one of (27) to (30), wherein the insulating layer is formed on the capacitor so as to be embedded in the opening. (32) The electronic device according to any one of (1) to (31), wherein the insulating layer is formed on the capacitor so as to be embedded in the opening. (33) The electronic device according to any one of (1) to (32), wherein the electrode comprises a barrier metal layer. (34) The electronic device according to (33), wherein the barrier metal layer includes an atomic layer deposition (ALD) film. (35) The electronic device according to (32) or (33), wherein the barrier metal layer includes at least one of Ti, TiN, Ta, TaN, Ru, and RuN. (36) The electronic device according to any of (1) to (35), wherein the electrode includes an electroless plating layer containing cobalt. (37) The electronic device according to any of (1) to (36), wherein the metal stack portion includes: a seed layer; a first electroless plating layer stacked on the seed layer and spaced from the inner circumferential surface of the opening; a second electroless plating layer formed around the first electroless plating layer; and an electrolytic plating layer formed on the second electroless plating layer. (38) The electronic device according to any of (1) to (37), wherein the opening includes a plurality of footing portions positioned at different depth directions. (39) The electronic device according to any one of (1) to (38), further comprising a SIMOX (Separation by Implanted Oxygen) layer provided at a midpoint in the depth direction of the opening so as to surround the periphery of the opening.(40) A method for manufacturing an electronic device, comprising the steps of: forming a sputtered layer on an inner surface of an opening, forming an insulating layer on the sputtered layer, removing the insulating layer on the sputtered layer on a bottom surface of the opening, forming an electroless plating layer on the sputtered layer on the bottom surface of the opening, removing the insulating layer in the opening after forming the electroless plating layer, and forming an electrolytic plating layer on the sputtered layer and the electroless plating layer. (41) The method for manufacturing an electronic device according to (40), wherein the sputtered layer on the side surface of the opening is separated from the sputtered layer and the electroless plating layer on the bottom surface of the opening, and the electroless plating layer is connected to the sputtered layer on the side surface of the opening via the electrolytic plating layer. (42) The method for manufacturing an electronic device according to (40) or (41), comprising the step of filling a footing portion of the bottom surface of the opening with a photosensitive insulating film before forming the sputtered layer. (43) The method for manufacturing an electronic device according to any one of (40) to (42), comprising the steps of: removing the insulating layer in the opening after forming the electroless plating layer, and then backfilling the area from which the insulating layer has been removed with electroless plating. (44) The method for manufacturing an electronic device according to any one of (40) to (43), wherein the etching to form the opening is divided into multiple steps. (45) The method for manufacturing an electronic device according to any one of (40) to (44), comprising the steps of: forming a SIMOX layer on the substrate where the opening will be formed; and forming the opening in the substrate based on etching divided at the position of the SIMOX layer.

[0456] TV1: Through electrode MT1: Metal laminated portion 111: Semiconductor substrate 112: Wiring layer 113: Wiring 114: Opening 115, 117: Insulating layer 116: Sputtered layer 118: Electroless plating layer 119: Electrolytic plating layer

Claims

1. An electronic device comprising an opening whose inner surface is insulated, and an electrode formed on the inner surface of the opening, wherein the electrode includes a metal laminate in which metals having different compositions or structures are laminated on the bottom surface of the opening.

2. The electronic device according to claim 1, wherein the metal laminate in which the metals are laminated is located on the bottom surface and the side surface of the opening.

3. The electronic device according to claim 1, wherein the structure is a grain size.

4. The electronic device according to claim 1, wherein the metal laminate includes a sputter layer, an electroless plating layer laminated on the sputter layer, and an electroplating layer laminated on the electroless plating layer.

5. The electronic device according to claim 4, wherein the electroless plating layer is selectively formed on the bottom surface of the opening via the sputter layer.

6. The electronic device according to claim 4, wherein the electroless plating layer is selectively formed on the bottom surface and the side surface of the opening via the sputter layer.

7. The sputter layer on the bottom surface of the opening and the sputter layer on the side surface of the opening are separated from each other, and the electroless plating layer is connected to the sputter layer on the side surface of the opening via the electroplating layer. The electronic device according to claim 4.

8. The electronic device according to claim 4, further comprising a wiring drawn from the opening and connected to the electrode, wherein the wiring includes the sputter layer and an electroplating layer laminated on the sputter layer.

9. The electronic device according to claim 1, wherein the diameter of the bottom surface of the opening is larger than the diameter of the opening surface of the opening.

10. A first semiconductor chip having a first wiring layer formed on a first semiconductor substrate, a second semiconductor chip having a second wiring layer formed on a second semiconductor substrate and laminated on the first semiconductor chip so that the second wiring layer faces the first wiring layer, and a through electrode formed with the electrode and connected to the second wiring layer through the first semiconductor chip. The electronic device according to claim 1.

11. The electronic device according to claim 1, further comprising: a first semiconductor chip having a first wiring layer formed on a first semiconductor substrate; a second semiconductor chip having a second wiring layer formed on a second semiconductor substrate and laminated on the first semiconductor chip such that the second wiring layer faces the first wiring layer; and a through electrode having the electrode formed thereon and connected to the first wiring layer through the first semiconductor substrate.

12. The electronic device according to claim 1, further comprising: a first semiconductor chip having a first wiring layer formed on a first semiconductor substrate; a second semiconductor chip having a second wiring layer formed on a second semiconductor substrate and laminated on the first semiconductor chip such that the second wiring layer faces the first wiring layer; an embedding layer formed on the first semiconductor chip so that the second semiconductor chip is embedded therein; a third semiconductor chip having a third wiring layer formed on a third semiconductor substrate and laminated on the embedding layer; and a through electrode having the electrode formed thereon and connected to the first wiring layer through the third semiconductor chip and the second semiconductor chip.

13. The electronic device according to claim 1, further comprising: a first semiconductor chip having a first wiring layer formed on a first semiconductor substrate; a second semiconductor chip having a second wiring layer formed on a second semiconductor substrate and laminated on the first semiconductor chip such that the second wiring layer faces the first wiring layer; an embedding layer formed on the first semiconductor chip so that the second semiconductor chip is embedded therein; a third semiconductor chip having a third wiring layer formed on a third semiconductor substrate and laminated on the embedding layer; and a through electrode having the electrode formed thereon and connected to the first wiring layer through the third semiconductor chip and the embedding layer.

14. The electronic device according to claim 1, further comprising a capacitor located within the opening and formed on the electrode.

15. The electronic device according to claim 14, wherein the capacitor includes: a first capacitor electrode formed on the electrode; and a second capacitor electrode formed on the first capacitor electrode with a dielectric layer therebetween.

16. The electronic device according to claim 14, wherein the capacitor includes: a first capacitor electrode also serving as the electrode; and a second capacitor electrode formed on the first capacitor electrode with a dielectric layer therebetween.

17. The electronic device according to claim 14, comprising an insulating layer formed on the capacitor through a cavity in the opening.

18. The electronic device according to claim 14, comprising an embedded layer formed on the capacitor so as to be embedded in the opening.

19. A method of manufacturing an electronic device, comprising: a step of forming a sputter layer on an inner surface of an opening; a step of forming an insulating layer on the sputter layer; a step of removing the insulating layer on the sputter layer on a bottom surface of the opening; a step of forming an electroless plating layer on the sputter layer on the bottom surface of the opening; a step of removing the insulating layer in the opening after the formation of the electroless plating layer; and a step of forming an electroplating layer on the sputter layer and the electroless plating layer.

20. The method of manufacturing an electronic device according to claim 19, wherein the sputter layer on a side surface of the opening is separated from the sputter layer on a bottom surface of the opening and the electroless plating layer, and the electroless plating layer is connected to the sputter layer on the side surface of the opening via the electroplating layer.

Images