Settling acceleration circuit and image sensor reading circuit including the same

Abstract

To improve performance such as RC time constant reduction and slew rate improvement regarding analog signal settling. A settling acceleration circuit includes a first transistor having an output terminal where a capacitive component exists, a gate electrode being connected to the output terminal; a first capacitor connected to a source terminal of the first transistor; a first constant current source connected to the source terminal of the first transistor; a current mirror circuit that amplifies a current from a drain terminal of the first transistor to output the amplified current to an output node; a second constant current source connected to the output node; and a first switch disposed between the output terminal and the output node. Then, after an end of the settling acceleration period in which the first switch is made conductive to accelerate the settling of the voltage of the output terminal, the first switch is cut off, and the reading circuit connected to the output terminal reads the voltage of the output terminal. The present technology can be applied to, for example, an imaging element such as a CMOS image sensor.

Description

SETTLING ACCELERATION CIRCUIT AND IMAGE SENSOR READING CIRCUIT INCLUDING THE SAME

[0001] The present disclosure relates to a settling acceleration circuit and an image sensor reading circuit including the same, and more particularly to a settling acceleration circuit that is capable of improving performance such as RC time constant reduction and slew rate improvement related to analog signal settling and an image sensor reading circuit including the same.

[0002] <CROSS REFERENCE TO RELATED APPLICATIONS> This application claims the benefit of Japanese Priority Patent Application JP 2024-009507 filed on January 25, 2024, the entire contents of which are incorporated herein by reference.

[0003] In the related art, for example, in a solid-state imaging element such as a complementary metal-oxide-semiconductor (CMOS) image sensor, it is desired to increase the reading speed and definition of a pixel signal. With the progress of higher definition and more pixels, the number of pixels connected to the vertical signal line (VSL) increases, and thus the parasitic capacitance of the vertical signal line increases. This increase in the parasitic capacitance of the vertical signal line prevents a reduction in settling time of the voltage of the vertical signal line. The shortening of the settling time is important for increasing the reading speed of the pixel signal.

[0004] In the related art, in order to shorten the settling time of the voltage of the vertical signal line, an additional current is supplied to the vertical signal line according to the voltage fluctuation amount of the vertical signal line (see, for example, PTL 1 and PTL 2). The RC time constant and the slew rate of the vertical signal line can be improved by flowing the additional current to the vertical signal line according to the voltage fluctuation amount of the vertical signal line, so that the settling time can be shortened.

[0005] In addition, in order to shorten the settling time of the voltage of the vertical signal line, an additional current is supplied to the vertical signal line at the timing of reading the pixel signal in synchronization with a signal (reset control signal or transfer control signal) that changes the voltage of the vertical signal line (see, for example, PTL 3 and NPL 1.). Since the slew rate of the vertical signal line is improved by supplying the additional current to the vertical signal line, the settling time can be shortened.

[0006] JP 2015-139081 AJP 2011-234243 AJP 2017-118373 A

[0007] A 3.7M-pixel l300-fpsCMOS Image Sensor with 5.0G-Pixel / s High-Speed Readout Circuit, The Society of Video Media 2014, https: / / www.jstage.jst.go.jp / aricle / itetr / 38.37 / 0 / 38.37_9 / _pdf / -char / ja

[0008] By using the technique in the related art described in PTL 1 or PTL 2, a negative capacitance can be realized, a large parasitic capacitance added to a vertical signal line can be reduced, and an RC time constant can be shortened. However, in a case where settling after the voltage of the floating diffusion ((FD): charge voltage conversion unit / charge detection unit) node greatly fluctuates due to feedthrough generated with the transition of the voltage of the pixel control line dominates the entire settling time, the effect of shortening the settling time is small. In addition, an element (current source, current mirror circuit, and the like) for realizing the negative capacitance is connected to the VSL even after convergence by VSL settling. At this time, when the next-stage circuit reads the voltage of the VSL, there is a problem that the influence of thermal noise and 1 / f noise mixed in the VSL from the element is large.

[0009] In the case of using the technique in the related art described in PTL 3 or NPL 1, even when the voltage of the vertical signal line settles once, the gate-source voltage Vgs of the amplification transistor constituting the source follower varies with the stop of the supply of the additional current. Then, when the gate-source voltage Vgs changes, it is necessary to wait again for a settling time determined by the formula of the RC delay of the parasitic wiring resistance R and the parasitic capacitance C of the vertical signal line.

[0010] Therefore, the present disclosure has been made in view of such a situation, and an object thereof is to more reliably shorten the settling time of the voltage of the vertical signal line and to increase the reading speed of the pixel signal.

[0011] A settling acceleration circuit according to a first aspect of the present disclosure includes a first transistor having an output terminal where a capacitive component exists, a gate electrode being connected to the output terminal, a first capacitor connected to a source terminal of the first transistor, a first constant current source connected to a source terminal of the first transistor, a current mirror circuit that amplifies a current from a drain terminal of the first transistor to output the amplified current to an output node, a second constant current source connected to the output node, and a first switch disposed between the output terminal and the output node, in which after an end of a settling acceleration period in which the first switch is made conductive to accelerate settling of a voltage of the output terminal, the first switch is cut off, and a reading circuit connected to the output terminal reads a voltage of the output terminal.

[0012] In the first aspect of the present disclosure, the settling acceleration circuit includes a first transistor having an output terminal where a capacitive component exists, a gate electrode being connected to the output terminal, a first capacitor connected to a source terminal of the first transistor, a first constant current source connected to the source terminal of the first transistor, a current mirror circuit that amplifies a current from a drain terminal of the first transistor to output the amplified current to an output node, a second constant current source connected to the output node, and a first switch disposed between the output terminal and the output node. Then, after an end of the settling acceleration period in which the first switch is made conductive to accelerate the settling of the voltage of the output terminal, the first switch is cut off, and the voltage of the output terminal is read by the reading circuit connected to the output terminal.

[0013] A settling acceleration circuit according to a second aspect of the present disclosure includes a first transistor having an output terminal where a capacitive component exists, a gate electrode being connected to the output terminal, a first capacitor connected to a source terminal of the first transistor, a first constant current source connected to a source terminal of the first transistor, a current mirror circuit that amplifies a current from a drain terminal of the first transistor to output the amplified current to the output terminal, a third constant current source that supplies the current to the current mirror circuit, and a fifth switch that connects the third constant current source and the current mirror circuit, in which the fifth switch is made conductive to improve a slew rate of a voltage of the output terminal a slew rate acceleration period.

[0014] In the second aspect of the present disclosure, the settling acceleration circuit includes a first transistor having an output terminal where a capacitive component exists, a gate electrode being connected to the output terminal, a first capacitor connected to a source terminal of the first transistor, a first constant current source connected to a source terminal of the first transistor, a current mirror circuit that amplifies a current from a drain terminal of the first transistor to output the amplified current to the output terminal, a third constant current source that supplies a current to the current mirror circuit, and a fifth switch that connects the third constant current source and the current mirror circuit. Then, the fifth switch is conducted to improve the slew rate of the voltage at the output terminal in the slew rate acceleration period.

[0015] An image sensor reading circuit according to a third aspect of the present disclosure includes a settling acceleration circuit including a first transistor having an output terminal where a capacitive component exists, a gate electrode being connected to the output terminal, a first capacitor connected to a source terminal of the first transistor, a first constant current source connected to a source terminal of the first transistor, a current mirror circuit that amplifies a current from a drain terminal of the first transistor to output the amplified current to an output node, a second constant current source connected to the output node, and a first switch disposed between the output terminal and the output node, in which after an end of a settling acceleration period in which the first switch is made conductive to accelerate settling of a voltage of the output terminal, the first switch is cut off, and a reading circuit connected to the output terminal reads a voltage of the output terminal.

[0016] In the third aspect of the present disclosure, the image sensor reading circuit includes a settling acceleration circuit including a first transistor having an output terminal where a capacitive component exists, a gate electrode being connected to the output terminal, a first capacitor connected to a source terminal of the first transistor, a first constant current source connected to the source terminal of the first transistor, a current mirror circuit that amplifies a current from a drain terminal of the first transistor to output the amplified current to an output node, a second constant current source connected to the output node, and a first switch disposed between the output terminal and the output node. Then, after an end of the settling acceleration period in which the first switch is made conductive to accelerate the settling of the voltage of the output terminal, the first switch is cut off, and the voltage of the output terminal is read by the reading circuit connected to the output terminal.

[0017] An image sensor reading circuit according to a fourth aspect of the present disclosure includes a settling acceleration circuit including a first transistor having an output terminal where a capacitive component exists, a gate electrode being connected to the output terminal, a first capacitor connected to a source terminal of the first transistor, a first constant current source connected to a source terminal of the first transistor, a current mirror circuit that amplifies a current from a drain terminal of the first transistor to output the amplified current to the output terminal, a third constant current source that supplies the current to the current mirror circuit, and a fifth switch that connects the third constant current source and the current mirror circuit, in which the fifth switch is made conductive to improve a slew rate of a voltage of the output terminal in a slew rate acceleration period is used.

[0018] In the fourth aspect of the present disclosure, an image sensor reading circuit includes a first transistor having an output terminal where a capacitive component exists, a gate electrode being connected to the output terminal, a first capacitor connected to a source terminal of the first transistor, a first constant current source connected to a source terminal of the first transistor, a current mirror circuit that amplifies a current from a drain terminal of the first transistor to output the amplified current to the output terminal, a third constant current source that supplies a current to the current mirror circuit, and a fifth switch that connects the third constant current source and the current mirror circuit. Then, the fifth switch is conducted to improve the slew rate of the voltage at the output terminal in the slew rate acceleration period.

[0019] An image sensor reading circuit according to a fifth aspect of the present disclosure includes a pixel source follower circuit having a signal line for outputting a pixel signal from a pixel, and a transistor serving as an acceleration current source, in which the signal line is connected to a gate terminal of the transistor via a capacitor.

[0020] In the fifth aspect of the present disclosure, the image sensor reading circuit includes a pixel source follower circuit having a signal line for outputting a pixel signal from a pixel, and a transistor serving as an acceleration current source. Then, the signal line is connected to the gate terminal of the transistor via the capacitor.

[0021] Fig. 1 is a circuit diagram illustrating a configuration example of the first embodiment of an analog integrated circuit to which the present technology is applied.Fig. 2 is a diagram for describing operation timing and time waveform.Fig. 3 is a circuit diagram illustrating the first modification of the analog integrated circuit of Fig. 1.Fig. 4 is a circuit diagram illustrating the second modification of the analog integrated circuit of Fig. 1.Fig. 5 is a circuit diagram illustrating the third modification of the analog integrated circuit of Fig. 1.Fig. 6 is a circuit diagram illustrating a configuration example of the second embodiment of an analog integrated circuit to which the present technology is applied.Fig. 7 is a diagram for describing operation timing and time waveform.Fig. 8 is a circuit diagram illustrating a configuration example of the third embodiment of an analog integrated circuit to which the present technology is applied.Fig. 9 is a diagram for describing operation timing and time waveform.Fig. 10 is a circuit diagram illustrating the first modification of the analog integrated circuit in Fig. 8.Fig. 11 is a diagram for describing operation timing and time waveform.Fig. 12 is a circuit diagram illustrating the second modification of the analog integrated circuit in Fig. 8.Fig. 13 is a diagram for describing operation timing and time waveform.Fig. 14 is a circuit diagram illustrating a configuration example of the fourth embodiment of an analog integrated circuit (imaging element) to which the present technology is applied.Fig. 15 is a diagram for describing operation timing and time waveform.Fig. 16 is a circuit diagram illustrating a configuration example of the fifth embodiment of an analog integrated circuit (imaging element) to which the present technology is applied.Fig. 17 is a diagram for describing driving of the analog integrated circuit (imaging element) of Fig. 16.Fig. 18 is a block diagram illustrating a configuration example of an imaging device.Fig. 19 is a diagram illustrating a use example in which an image sensor is used.

[0022] Hereinafter, specific embodiments according to the present technology will be described in detail with reference to the drawings.

[0023] <First configuration example of analog integrated circuit> Fig. 1 is a circuit diagram illustrating a configuration example of a first embodiment of an analog integrated circuit to which the present technology is applied.

[0024] As illustrated in Fig. 1, an analog integrated circuit 11 includes a buffer unit 12 and a settling acceleration circuit 13, an input terminal VIN is connected to the buffer unit 12, and an output terminal VOUT is connected to the buffer unit 12 through the settling acceleration circuit 13.

[0025] Since a parasitic resistance or a parasitic capacitance is generated in the output terminal VOUT due to the wiring or the like, the output terminal VOUT is affected by an RC delay when the voltage of the output terminal VOUT is settling. When the voltage of the input terminal VIN is indirectly read through the output terminal VOUT, a settling time is necessary until the voltage of the output terminal VOUT is stable (static). The purpose of the settling acceleration circuit 13 is to accelerate and increase the speed of the settling of the voltage at the output terminal VOUT and to shorten the settling time.

[0026] The buffer unit 12 includes a voltage buffer 21, a resistor 22, and a capacitor 23. The settling acceleration circuit 13 includes a P-type metal-oxide-semiconductor (MOS) transistor 31, a constant current source 32, a capacitor 33, an N-type MOS transistor 34, an N-type MOS transistor 35, a constant current source 36, and a connection cutoff switch 37. Here, the voltage buffer 21 means a voltage follower including a source follower and an operational amplifier.

[0027] When the impedance of the input terminal VIN is high, it is difficult to directly read the voltage. For example, in a case where the voltage of the FD node is read, a buffer circuit having a high input impedance such as a source follower is necessary. An input terminal of the buffer circuit can be connected to the FD node to indirectly read the voltage. By using a buffer circuit having a low output impedance, a voltage change of the FD node can be transmitted to the VSL to which a large parasitic capacitance and a large parasitic wiring resistance are added, and settling can be performed in a short period of time. The settling acceleration circuit 13 is a circuit that assists speeding up the settling and shortening the settling time.

[0028] The input terminal VIN is connected to the input terminal of the voltage buffer 21, the output terminal of the voltage buffer 21 is connected to one terminal of the resistor 22, and the other terminal of the resistor 22 is connected to the output terminal VOUT and to a ground terminal VSS via the capacitor 23. The resistor 22 and the capacitor 23 simulate a resistance component and a capacitive component due to a parasitic element or a parasitic effect. For example, the resistor 22 means a wiring resistance of a vertical signal line, and the capacitor 23 means a wiring capacitance of a vertical signal line. In a case where the parasitic effect is small and the resistance value is small, the resistor 22 may not be present, and the output terminal of the voltage buffer 21 may be directly connected to the capacitor 23.

[0029] A connection point between the resistor 22 and the capacitor 23 is the output terminal VOUT, and is connected to a gate terminal of the P-type MOS transistor 31.

[0030] A source terminal of the P-type MOS transistor 31 is connected to a power supply terminal VDD via the constant current source 32 and the capacitor 33 connected in parallel. A drain terminal of the P-type MOS transistor 31 is connected to the ground terminal VSS via the N-type MOS transistor 34.

[0031] The N-type MOS transistor 34 and the N-type MOS transistor 35 constitute a current mirror circuit, and gate terminals thereof are connected to each other, and the N-type MOS transistor 34 has a diode connection configuration in which a gate terminal and a drain terminal thereof are connected in common. The drain terminal of the P-type MOS transistor 31 is connected to this connection point, the current from the drain terminal of the P-type MOS transistor 31 is multiplied by M, and the multiplied current is output to a node VOUT_BST to which the drain terminal of the N-type MOS transistor 35 is connected.

[0032] The drain terminal of the N-type MOS transistor 35 is connected to the power supply terminal VDD via the constant current source 36. A source terminal of the N-type MOS transistor 35 is connected to the ground terminal VSS.

[0033] The connection cutoff switch 37 has one terminal connected to the output terminal VOUT, and the other terminal connected to the node VOUT_BST between the N-type MOS transistor 35 and the constant current source 36. The node VOUT_BST is an output node of the settling acceleration circuit 13. The connection cutoff switch 37 disconnects or conducts the output terminal VOUT and the node VOUT_BST according to a digital control signal DIN_FB.

[0034] (Description of operation timing and time waveform) Fig. 2 illustrates voltage waveforms of the input terminal VIN and the output terminal VOUT and a time waveform of the digital control signal DIN_FB indicating the settling acceleration period. When the voltage of the input terminal VIN is constant or small in change, settling acceleration of the voltage of the output terminal VOUT is unnecessary, and thus the digital control signal DIN_FB is set to the LOW level. Since the output terminal VOUT is cut off from the settling acceleration circuit 13, the voltage of the output terminal VOUT indicates settling characteristics determined by the characteristics of the voltage buffer 21, the resistance value of the resistor 22, and the capacitance value of the capacitor 23.

[0035] On the other hand, immediately before or at the moment when the voltage of the input terminal VIN decreases, the digital control signal DIN_FB is caused to transition from the LOW level to the HIGH level, and the connection cutoff switch 37 is made conductive. At this time, the node VOUT_BST and the output terminal VOUT are short-circuited, the settling acceleration circuit 13 accelerates the settling of the output terminal VOUT, and the voltage of the output terminal VOUT can be quickly converged to the expected value in a shorter time. In the settling acceleration period in which the digital control signal DIN_FB is at the HIGH level, the voltage of the output terminal VOUT converges to a voltage V1-VERRclose to an expected value V1. Thereafter, the digital control signal DIN_FB is returned to the LOW level. The read WAIT period is waited until the voltage of the output terminal VOUT is stabilized at the expected value V1. Thereafter, the next-stage circuit connected to the output terminal VOUT reads the voltage of the output terminal VOUT according to the timing indicated by a digital control signal DIN_SAMP.

[0036] A voltage waveform of the output terminal VOUT in a case of settling is performed with a time constant determined by the voltage buffer circuit, the resistor, and the capacitor without using the settling acceleration circuit 13 is indicated by a dotted line in Fig. 2. In a case where the settling acceleration circuit 13 is not used, it takes time from when the voltage of the input terminal VIN starts to decrease to when the voltage of the output terminal VOUT settles and stabilizes. By using the settling acceleration circuit 13, settling of the output terminal VOUT can be accelerated, the voltage can be converged to an expected value in a short period of time, and a period from when the voltage of the input terminal VIN changes to when the voltage of the output terminal VOUT is read can be shortened.

[0037] (Improvement of settling parameters (RC time constant, slew rate)) The fact that the settling acceleration circuit 13 can improve the voltage settling characteristic of the output terminal VOUT will be described using an RC time constant τ1and a slew rate SR1of the output terminal VOUT. Since the connection cutoff switch 37 is cut off when the digital control signal DIN_FB is LOW, the RC time constant τ1and the slew rate SR1of the output terminal VOUT are determined only from the characteristics of respective elements of the buffer unit 12, and are expressed by the following Expression (1).

[0038]

[0039] In Expression (1), RVSLis a resistance value of the resistor 22, and CVSLis a capacitance value of the capacitor 23. RBUFFis an output impedance of the voltage buffer 21, and the range of the output current of the voltage buffer 21 was set to within ±IMAXBUFF.

[0040] In addition, settling characteristics in a case where the voltage of a VOUT terminal decreases as illustrated in Fig. 2 will be considered. Since the connection cutoff switch 37 is conducted when the digital control signal DIN_FB is HIGH, an RC time constant τ2and a slew rate SR2of the output terminal VOUT are determined from the characteristics of respective elements of the buffer unit 12 and the settling acceleration circuit 13, and are expressed by the following Expression (2).

[0041]

[0042] where, the current of the constant current source 36 is M times the current of the constant current source 32, and CBSTis a capacitance value of the capacitor 33. As is clear from the RC time constant τ1of the above Expression (1) and the RC time constant τ2of the above Expression (2), the RC time constant τ2is smaller than the RC time constant τ1. Specifically, it can be seen that the RC time constant τ2can be greatly shortened by increasing M, which is the ratio of the current mirror circuit and the settling characteristic can be improved.

[0043] Similarly, as is clear from the slew rate SR1of the above Expression (1) and the slew rate SR2of the above Expression (2), the absolute value |SR2| of the slew rate SR2is larger than the absolute value |SR1| of the slew rate SR1(the magnitude and the absolute value of the slew rate are important for settling. For example, |SR| means an absolute value of SR. Specifically, it can be seen that the absolute value |SR2| of the slew rate SR2can be significantly increased by increasing M, which is the ratio of the current mirror circuit, and the settling characteristic can be improved. In the above Expression (2), as represented by the term of CVSL-M・CBST, it can be seen that the settling acceleration circuit can reduce the capacitance added to the output terminal VOUT, that is, can realize the negative capacitance (-M・CBST).

[0044] (Noise (thermal noise, 1 / f noise) of settling acceleration circuit and read WAIT period) In the transistor constituting the settling acceleration circuit 13, thermal noise or 1 / f noise current is generated between the source terminal and the drain terminal. Since the constant current source also includes a transistor, the noise is generated. In the settling acceleration circuit 13, in particular, noise from the constant current source 32, the N-type MOS transistor 34, the N-type MOS transistor 35, and the constant current source 36 is mixed into the output terminal VOUT via the node VOUT_BST and the connection cutoff switch 37. During the settling acceleration period in which the connection cutoff switch 37 conducts as illustrated in Fig. 2, the noise is mixed into the output terminal VOUT, and thus the voltage of the output terminal VOUT randomly varies with time depending on the noise.

[0045] Further, characteristics of respective elements of the transistors constituting the settling acceleration circuit 13 varies. For example, the current values of the constant current source 32 and the constant current source 36 and M, which is the ratio of the current mirror circuit, are difficult to be constant, and have variations for each circuit. Due to this variation, an error occurs in the voltage of the output terminal VOUT immediately before the end of the settling acceleration period.

[0046] VERRrepresents the influence of the offset voltage and the noise generated by the element variation of the settling acceleration circuit 13 (VERRis preferably close to 0). In order to alleviate the influence of VERR, the read WAIT period in which the connection cutoff switch 37 is cut off before the voltage reading of the output terminal VOUT is necessary. In this WAIT period, the influence of VERRis alleviated, and the voltage of the output terminal VOUT converges to the expected value V1.

[0047] The settling acceleration circuit 13 exemplified in the present embodiment has a configuration capable of performing settling acceleration in a case where the voltage of the output terminal VOUT drops. In a case where settling acceleration is performed in a case where the voltage of the output terminal VOUT increases, the P-type MOS transistor is replaced with an N-type MOS transistor, the N-type MOS transistor is replaced with a P-type MOS transistor, and the circuit configuration is complementarily changed with respect to the power supply terminal VDD and the ground terminal VSS in the settling acceleration circuit 13 illustrated in the example, so that the settling acceleration circuit can be similarly realized.

[0048] The constant current source 32 and the constant current source 36 described in the present embodiment include transistors. Since the CMOS process can be easily configured, description of the configuration and the like is omitted. The connection cutoff switch 37 and a current cutoff switch 38 described in the present embodiment are analog switches including transistors, and assume an operation of short-circuiting and conducting (ON state) between two nodes when a digital control signal for controlling the state of the switch is HIGH, and cutting off (OFF state) between the two nodes when the digital control signal is LOW.

[0049] As described above, the analog integrated circuit 11 can significantly improve the voltage settling characteristic of the output terminal VOUT while reducing the influence of the thermal noise of the settling acceleration circuit 13. That is, it is possible to shorten the RC time constant of the output terminal VOUT and improve the slew rate of the output terminal VOUT.

[0050] Fig. 3 is a circuit diagram illustrating the first modification of the analog integrated circuit 11. In an analog integrated circuit 11-a illustrated in Fig. 3, components common to those of the analog integrated circuit 11 in Fig. 1 are denoted by the same reference numerals, and a detailed description thereof is omitted.

[0051] In the analog integrated circuit 11-a illustrated in Fig. 3, the buffer unit 12 has a circuit configuration similar to that of the buffer unit 12 in Fig. 1. A settling acceleration circuit 13-a includes the P-type MOS transistor 31, the constant current source 32, the capacitor 33, the N-type MOS transistor 34, the N-type MOS transistor 35, the constant current source 36, and the connection cutoff switch 37, which have a circuit configuration similar to that of the settling acceleration circuit 13 of Fig. 1.

[0052] Then, the settling acceleration circuit 13-a has a configuration different from that of the settling acceleration circuit 13 in Fig. 1 in that it includes the current cutoff switch 38.

[0053] The current cutoff switch 38 has one terminal connected to the constant current source 36, and the other terminal connected to the node VOUT_BST to which the N-type MOS transistor 35 and the connection cutoff switch 37 are connected. Then, the current cutoff switch 38 turns on / off the output of the current from the constant current source 36 according to the digital control signal DIN_FB.

[0054] Therefore, the analog integrated circuit 11-a can cut off the current flowing from the constant current source 36 to the N-type MOS transistor 35 by controlling the digital control signal DIN_FB to the LOW level in a period other than the settling acceleration period to turn off the connection cutoff switch 37 and turning off the current cutoff switch 38. That is, since the settling acceleration circuit 13-a does not need to operate in a period in which the node VOUT_BST is not connected to the output terminal VOUT, it is possible to achieve low current consumption by cutting off the current flowing from the constant current source 36 to the N-type MOS transistor 35.

[0055] As described above, the analog integrated circuit 11-a can further reduce current consumption in addition to improvement in performance by the analog integrated circuit 11.

[0056] Fig. 4 is a circuit diagram illustrating the second modification of the analog integrated circuit 11. In an analog integrated circuit 11-b illustrated in Fig. 4, components common to those of the analog integrated circuit 11 in Fig. 1 are denoted by the same reference numerals, and a detailed description thereof is omitted.

[0057] In the analog integrated circuit 11-b illustrated in Fig. 4, the buffer unit 12 has a circuit configuration similar to that of the buffer unit 12 in Fig. 1. A settling acceleration circuit 13-b includes the P-type MOS transistor 31, the constant current source 32, the capacitor 33, the N-type MOS transistor 34, the N-type MOS transistor 35, the constant current source 36, and the connection cutoff switch 37, which have a circuit configuration similar to that of the settling acceleration circuit 13 of Fig. 1.

[0058] Then, the settling acceleration circuit 13-b has a configuration different from that of the settling acceleration circuit 13 of Fig. 1 in that it includes a current cutoff switch 39 and an inverter 40. The inverter 40 is a circuit that inverts and outputs the logic of the digital control signal DIN_FB and can be easily realized in the CMOS process, and thus details thereof are omitted.

[0059] The current cutoff switch 39 has one terminal connected to a connection point between the gate terminals of the N-type MOS transistor 34 and the N-type MOS transistor 35 constituting the current mirror circuit, and the other terminal connected to the ground terminal VSS to which the source terminal of the N-type MOS transistor 34 is connected. Then, the current cutoff switch 39 turns on / off the connection between the gate terminals of the N-type MOS transistor 34 and the N-type MOS transistor 35 and the ground terminal VSS according to the digital control signal DIN_FB inversely input via the inverter 40.

[0060] Therefore, when the analog integrated circuit 11-b controls the digital control signal DIN_FB to the LOW level and turns off the connection cutoff switch 37 in a period other than the acceleration period, the HIGH level obtained by inverting the digital control signal DIN_FB is supplied to the current cutoff switch 39. As a result, the current cutoff switch 39 is turned on, the gate terminals of the N-type MOS transistor 34 and the N-type MOS transistor 35 are connected to the ground terminal VSS, a voltage Vgs between the gate terminal and the source terminal of the N-type MOS transistor 35 is 0, and the current between the drain terminal and the source terminal of the N-type MOS transistor 35 is cut off. Therefore, the current flowing from the constant current source 36 to the N-type MOS transistor 35 can be cut off. That is, since the settling acceleration circuit 13-b does not need to operate in a period in which the node VOUT_BST is not connected to the output terminal VOUT, it is possible to achieve low current consumption by cutting off the current flowing from the constant current source 36 to the N-type MOS transistor 35.

[0061] As described above, the analog integrated circuit 11-b can further reduce current consumption in addition to improvement in performance by the analog integrated circuit 11.

[0062] Fig. 5 is a circuit diagram illustrating the third modification of the analog integrated circuit 11. In an analog integrated circuit 11-c illustrated in Fig. 5, components common to those of the analog integrated circuit 11 in Fig. 1 are denoted by the same reference numerals, and a detailed description thereof is omitted.

[0063] In the analog integrated circuit 11-c illustrated in Fig. 5, the buffer unit 12 has a circuit configuration similar to that of the buffer unit 12 in Fig. 1. A settling acceleration circuit 13-c includes the P-type MOS transistor 31, the constant current source 32, the capacitor 33, an N-type MOS transistor 34, the N-type MOS transistor 35, the constant current source 36, and the connection cutoff switch 37, which have a circuit configuration similar to that of the settling acceleration circuit 13 of Fig. 1.

[0064] Then, the settling acceleration circuit 13-c has a configuration different from that of the settling acceleration circuit 13 of Fig. 1 in that it includes a current cutoff switch 41 and a comparator 42. The comparator 42 has a non-inverting input terminal, an inverting input terminal, and a digital output terminal to output the HIGH level as a digital output in a case where a voltage or a current of the non-inverting input terminal is larger than a voltage or a current of the inverting input terminal, or to output the LOW level in a case where the voltage or the current of the non-inverting input terminal is smaller than the voltage or the current of the inverting input terminal.

[0065] The current cutoff switch 41 has one terminal connected to a connection point between the gate terminals of the N-type MOS transistor 34 and the N-type MOS transistor 35 constituting the current mirror circuit, and the other terminal connected to the ground terminal VSS to which the source terminal of the N-type MOS transistor 34 is connected. Then, the current cutoff switch 41 turns on / off the connection of the gate terminals of the N-type MOS transistor 34 and the N-type MOS transistor 35 to the ground terminal VSS according to the output of the comparator 42.

[0066] In the comparator 42, the inverting input terminal is connected to a connection point between gate terminals of the N-type MOS transistor 34 and the N-type MOS transistor 35 constituting the current mirror circuit, and a comparison voltage VBN_VGS set from the outside is input to the non-inverting input terminal. While the voltage of the input terminal VIN decreases and the voltage of the output terminal VOUT is settling, the voltage at the connection point between the gate terminals increases and reaches a voltage level higher than the comparison voltage VBN_VGS. As the settling is stabilized, the voltage at the connection point between the gate terminals decreases and is lower than the comparison voltage VBN_VGS. At this time, the comparator 42 detects a voltage (a voltage at a connection point between the gate terminals) in the settling acceleration circuit 13-c, outputs the HIGH level, and turns on the current cutoff switch 41. Here, the fact that the voltage inside the settling acceleration circuit 13-c is lower than the comparison voltage VBN_VGS means a state in which the voltage of the output terminal VOUT converges and settling is being completed. The voltage at the connection point between the gate terminals indicates a settling state of the voltage of the output terminal VOUT.

[0067] As a result, when the settling of the settling acceleration circuit 13-c converges and the voltage of the output terminal VOUT is stabilized, the gate terminals of the N-type MOS transistor 34 and the N-type MOS transistor 35 are connected to the ground terminal VSS, the voltage Vgs between the gate terminal and the source terminal of the N-type MOS transistor 35 is 0, and the current between the drain terminal and the source terminal of the N-type MOS transistor 35 is cut off. Therefore, the current flowing from the constant current source 36 to the N-type MOS transistor 35 can be cut off. That is, the settling acceleration circuit 13-c monitors the voltage of the internal node, detects the settling state, in particular, convergence of the settling, and automatically cuts off the current flowing from the constant current source 36 to the N-type MOS transistor 35, so that low current consumption can be achieved.

[0068] As described above, the analog integrated circuit 11-c can further reduce current consumption in addition to improvement in performance by the analog integrated circuit 11.

[0069] <Second configuration example of analog integrated circuit> Fig. 6 is a block diagram illustrating a configuration example of the second embodiment of an analog integrated circuit to which the present technology is applied. In an analog integrated circuit 11A illustrated in Fig. 6, components common to those of the analog integrated circuit 11 in Fig. 1 are denoted by the same reference numerals, and a detailed description thereof is omitted.

[0070] In the analog integrated circuit 11A illustrated in Fig. 6, the buffer unit 12 has a circuit configuration similar to that of the buffer unit 12 in Fig. 1. A settling acceleration circuit 13A includes the P-type MOS transistor 31, the constant current source 32, the capacitor 33, the N-type MOS transistor 34, the N-type MOS transistor 35, and the connection cutoff switch 37, which have a circuit configuration similar to that of the settling acceleration circuit 13 of Fig. 1.

[0071] Then, the settling acceleration circuit 13A has a configuration different from that of the settling acceleration circuit 13 of Fig. 1 in that it includes a P-type MOS transistor 43, a capacitor 44, and an auto-zero switch 45. That is, in the settling acceleration circuit 13A, the constant current source 36 in Fig. 1 includes an auto-zero circuit including the P-type MOS transistor 43, the capacitor 44, and the auto-zero switch 45.

[0072] In the P-type MOS transistor 43, a source terminal is connected to the power supply terminal VDD, and a drain terminal thereof is connected to the node VOUT_BST. The capacitor 44 has one terminal connected to the power supply terminal VDD, and the other terminal connected to the gate terminal of the P-type MOS transistor 43.

[0073] The auto-zero switch 45 has one terminal of is connected to a connection point between the capacitor 44 and the gate terminal of the P-type MOS transistor 43, and the other terminal connected to the node VOUT_BST. Then, the auto-zero switch 45 turns on / off the connection between the gate terminal and the drain terminal of the P-type MOS transistor 43 according to a digital control signal DIN_AZ.

[0074] (Description of operation timing and time waveform) Fig. 7 illustrates voltage waveforms of the input terminal VIN and the output terminal VOUT, the digital control signal DIN_FB indicating a settling acceleration period, and a time waveform of the digital control signal DIN_AZ indicating an auto-zero period. Only matters different from Fig. 2 showing the operation of the settling acceleration circuit 13 will be described below.

[0075] When the voltage of the input terminal VIN is held at a constant value, the digital control signal DIN_FB is set to the LOW level. That is, since the connection cutoff switch 37 is cut off, the current flowing from the drain terminal of the N-type MOS transistor 35 flows to the drain terminal of the P-type MOS transistor 43. In this period, an auto-zero period for setting the digital control signal DIN_AZ to the HIGH level is provided. The auto-zero switch 45 is conducted, and the gate terminal and the drain terminal of the P-type MOS transistor 43 are short-circuited and diode-connected.

[0076] The voltage at the gate terminal of the P-type MOS transistor 43 converges to a certain value such that the current between the source terminal and the drain terminal of the P-type MOS transistor 43 is equal to the current flowing from the drain terminal of the N-type MOS transistor 35. When the auto-zero period ends, the voltage of the gate terminal of the P-type MOS transistor 43 is held in the capacitor 44. Since the current between the source terminal and the drain terminal of the P-type MOS transistor 43 can be made equal to the current flowing through the drain terminal of the N-type MOS transistor 35 (the current of the auto-zero circuit stores the current of the current mirror circuit output to the node VOUT_BST), the offset voltage VERRgenerated in the voltage of the output terminal VOUT immediately before the settling acceleration period ends can be reduced.

[0077] On the other hand, in the settling acceleration circuit 13 illustrated in Fig. 1, since element parameters such as the current values of the constant current source 32 and the constant current source 36 and the mirror ratio of the current mirror circuit vary, it is difficult to match the current flowing through the drain terminal of the N-type MOS transistor 35 with the current of the constant current source 36. When the current with this difference flows to the output terminal VOUT through the connection cutoff switch 37, a large offset voltage VERRis generated in the voltage of the output terminal VOUT immediately before the end of the settling acceleration period, leading to deterioration of settling characteristics.

[0078] Therefore, the analog integrated circuit 11A can accurately match the drain current of the P-type MOS transistor 43 with the drain current of the N-type MOS transistor 35 by the auto zero function. The offset current, which is the difference between the drain current of the P-type MOS transistor 43 and the drain current of the N-type MOS transistor 35, can be made 0. When the settling of the output terminal VOUT converges and the voltage thereof is stabilized in the settling acceleration period, the offset current flowing from the settling acceleration circuit 13A to the output terminal VOUT can be reduced, the voltage fluctuation of the output terminal VOUT can be suppressed in the read WAIT period, the read WAIT period can be shortened, or the voltage error at the time of voltage reading of the output terminal VOUT can be reduced.

[0079] As described above, in addition to improvement in performance by the analog integrated circuit 11, the analog integrated circuit 11A can further improve the performance by reducing the element variation by the auto zero function.

[0080] <Third configuration example of analog integrated circuit> Fig. 8 is a block diagram illustrating a configuration example of a third embodiment of an analog integrated circuit to which the present technology is applied. In an analog integrated circuit 11B illustrated in Fig. 8, components common to those of the analog integrated circuit 11 in Fig. 1 are denoted by the same reference numerals, and a detailed description thereof is omitted.

[0081] In the analog integrated circuit 11B illustrated in Fig. 8, the buffer unit 12 has a circuit configuration similar to that of the buffer unit 12 in Fig. 1. A settling acceleration circuit 13B includes the P-type MOS transistor 31, the constant current source 32, the capacitor 33, the N-type MOS transistor 34, and the N-type MOS transistor 35, which have a circuit configuration similar to that of the settling acceleration circuit 13 in Fig. 1.

[0082] Then, the settling acceleration circuit 13B has a configuration different from that of the settling acceleration circuit 13 in Fig. 1 in that it includes a constant current source 49 and a current connection switch 50. In the settling acceleration circuit 13B, the constant current source 36 and the connection cutoff switch 37 in Fig. 1 are preferably disposed, but are not necessarily disposed. The settling acceleration circuit 13B does not include the constant current source 36 and the connection cutoff switch 37, and the drain terminal of the N-type MOS transistor 35 is directly connected to the output terminal VOUT.

[0083] The current connection switch 50 has one terminal connected to the constant current source 49, and the other terminal connected to a connection point between the P-type MOS transistor 31 and the N-type MOS transistor 34. Then, the current connection switch 50 turns on / off the connection of the constant current source 49 according to a digital control signal DIN_SI.

[0084] Therefore, the analog integrated circuit 11B having such a circuit configuration can improve the slew rate of the output terminal VOUT by controlling the digital control signal DIN_SI to the HIGH level and turning on the current connection switch 50 to connect the constant current source 49 to the N-type MOS transistor 34 in a period in which the voltage value of the output terminal VOUT decreases.

[0085] (Description of operation timing and time waveform) Fig. 9 illustrates voltage waveforms of the input terminal VIN and the output terminal VOUT and a time waveform of the digital control signal DIN_SI indicating the slew rate acceleration period (SR acceleration period).

[0086] When the voltage of the input terminal VIN is constant or small in change, settling acceleration of the voltage of the output terminal VOUT is unnecessary, and thus the digital control signal DIN_SI is set to the LOW level. Since a connection cutoff switch is not provided between the settling acceleration circuit 13B and the output terminal VOUT, the voltage of the output terminal VOUT constantly exhibits a settling characteristic determined by the characteristic of the settling acceleration circuit 13B in addition to the characteristic of the voltage buffer 21, the resistance value of the resistor 22, and the capacitance value of the capacitor 23. Immediately before or at the moment when the voltage of the input terminal VIN decreases, the digital control signal DIN_SI is caused to transition from the LOW level to the HIGH level, and the current connection switch 50 is made conductive (SR acceleration period).

[0087] In the SR acceleration period, the DC current of the constant current source 49 is input to the drain terminal of the N-type MOS transistor 34, and the current amplified according to the current mirror ratio is output from the drain terminal of the N-type MOS transistor 35 and flows to the output terminal VOUT. The settling acceleration circuit 13B accelerates the settling of the output terminal VOUT, and the voltage of the output terminal VOUT can be quickly converged to the expected value in a shorter time.

[0088] In the SR acceleration period, the voltage of the output terminal VOUT drops to a voltage close to the expected value V2. Thereafter, the digital control signal DIN_SI is returned to the LOW level. Wait until the voltage of the output terminal VOUT is stabilized at the expected value V2. Thereafter, a next-stage circuit connected to the output terminal VOUT reads the voltage at the output terminal VOUT.

[0089] A voltage waveform of the output terminal VOUT in a case of settling is performed with a time constant determined by the voltage buffer circuit, the resistor, and the capacitor without using the settling acceleration circuit 13B is indicated by a dotted line in Fig. 9. In a case where the settling acceleration circuit 13B is not used, it takes time from when the voltage of the input terminal VIN starts to decrease to when the voltage of the output terminal VOUT settles and stabilizes. By using the settling acceleration circuit 13B, settling of the output terminal VOUT can be accelerated, the voltage can be converged to an expected value in a short period of time, and a period from when the voltage of the input terminal VIN changes to when the voltage of the output terminal VOUT is read can be shortened.

[0090] When the SR acceleration period ends and the digital control signal DIN_SI is set to the LOW level, the voltage of the output terminal VOUT converges to V2lower than V1. Here, V1illustrated in Figs. 2 and 9 is an expected value, a convergence value, determined by the configuration of the buffer unit 12 to which the settling acceleration circuit is not connected. In the settling acceleration circuit 13B, since the connection cutoff switch 37 and the constant current source 36 are not provided, the output current from the drain terminal of the N-type MOS transistor 35 flows to the output terminal VOUT, and thus converges to V2lower than V1(offset voltage V2-V1is generated). Further, when the SR acceleration period ends and the digital control signal DIN_SI is set to the LOW level, since the settling acceleration circuit 13B is directly connected to the output terminal VOUT, the thermal noise and the 1 / f noise from the elements constituting the settling acceleration circuit 13B are directly superimposed on the output terminal VOUT. Note that in a case where the offset voltage, the thermal noise, and the like are not tolerated, it is preferable to provide the constant current source 36 and the connection cutoff switch 37 as in the settling acceleration circuit 13 of Fig. 1.

[0091] (Improvement of settling parameter (slew rate)) The slew rate SR3of the output terminal VOUT in the SR acceleration period is determined by the characteristics of respective elements of the buffer unit 12 and the settling acceleration circuit 13B, and is expressed by the following Expression (3).

[0092]

[0093] where IBSTand ISIare the DC currents of the constant current source 32 and the constant current source 49, respectively. When comparing the slew rate SR1of the above Expression (1), the slew rate SR2of the above Expression (2), and the slew rate SR3of the above Expression (3), it is apparent that the absolute value |SR3| of the slew rate SR3is larger than the absolute value |SR1| of the slew rate SR1and the absolute value |SR2| of the slew rate SR2. Specifically, the absolute value |SR3| of the slew rate SR3can be significantly increased by increasing M, which is the ratio of the current mirror circuit, or increasing the DC current ISIof the constant current source 49, and it can be seen that the settling characteristic can be improved.

[0094] As described above, the analog integrated circuit 11B can further improve the slew rate of the output terminal VOUT in addition to improvement in performance by the analog integrated circuit 11.

[0095] Fig. 10 is a circuit diagram illustrating the first modification of the analog integrated circuit 11B. In an analog integrated circuit 11B-a illustrated in Fig. 10, components common to those of the analog integrated circuit 11B in Fig. 8 are denoted by the same reference numerals, and a detailed description thereof is omitted.

[0096] In the analog integrated circuit 11B-a illustrated in Fig. 10, the buffer unit 12 has a circuit configuration similar to that of the buffer unit 12 in Fig. 8. A settling acceleration circuit 13B-a includes the P-type MOS transistor 31, the constant current source 32, the capacitor 33, the N-type MOS transistor 34, the N-type MOS transistor 35, the constant current source 49, and the current connection switch 50, which have a circuit configuration similar to that of the settling acceleration circuit 13B in Fig. 8.

[0097] Then, the settling acceleration circuit 13B-a has a configuration different from that of the settling acceleration circuit 13B of Fig. 8 in that it includes the constant current source 36, a current cutoff switch 51, and an inverter 52.

[0098] The current cutoff switch 51 has one terminal connected to the constant current source 36 and the other terminal connected to the output terminal VOUT. Then, the current cutoff switch 51 receives the inverted signal of the digital control signal DIN_SI via the inverter 52, and turns on / off the connection between the constant current source 36 and the output terminal VOUT.

[0099] The analog integrated circuit 11B-a having such a circuit configuration can improve the slew rate of the output terminal VOUT by controlling the digital control signal DIN_SI to the HIGH level and turning on the current connection switch 50 to connect the constant current source 49 to the N-type MOS transistor 34 in a period in which the voltage value of the output terminal VOUT decreases.

[0100] (Description of operation timing and time waveform) Fig. 11 illustrates voltage waveforms of the input terminal VIN and the output terminal VOUT and a time waveform of the digital control signal DIN_SI indicating the slew rate acceleration period (SR acceleration period). Only points different from Fig. 9 will be described below.

[0101] In the SR acceleration period, the voltage of the output terminal VOUT drops to a voltage close to the expected value V'1. Thereafter, the digital control signal DIN_SI is returned to the LOW level. When the SR acceleration period ends and the digital control signal DIN_SI is set to the LOW level, the voltage of the output terminal VOUT converges to V'1. Thereafter, a next-stage circuit connected to the output terminal VOUT reads the voltage at the output terminal VOUT.

[0102] In the settling acceleration circuit 13B-a, the current of the constant current source 36 is M×IBST. When the settling of the voltage at the output terminal VOUT converges and is stable, the output current M×IBSTfrom the drain terminal of the N-type MOS transistor 35 does not flow to the output terminal VOUT but flows to the constant current source 36. Therefore, the convergence value V'1of the voltage of the output terminal VOUT can be set to a value close to the convergence value V1determined only by the configuration of the buffer unit 12. That is, the offset voltage V'1-V1by the settling acceleration circuit 13B-a can be reduced.

[0103] (Improvement of settling parameter (slew rate)) During the SR acceleration period, since the constant current source 36 is cut off from the output terminal VOUT, the slew rate of the output terminal VOUT is not affected. Therefore, the slew rate of the output terminal VOUT in the SR acceleration period is represented by the slew rate SR3of the above Expression (3) as in the analog integrated circuit 11B, and it can be seen that the settling characteristic can be improved as described above.

[0104] As described above, the analog integrated circuit 11B-a can further improve the slew rate of the output terminal VOUT in addition to improvement in performance by the analog integrated circuit 11. In addition, as compared with the analog integrated circuit 11B, the analog integrated circuit 11B-a can reduce the offset of the voltage of the output terminal VOUT to the convergence value by the settling acceleration circuit 13B-a.

[0105] Fig. 12 is a circuit diagram illustrating the second modification of the analog integrated circuit 11B. In an analog integrated circuit 11B-b illustrated in Fig. 12, components common to those of the analog integrated circuit 11B in Fig. 8 are denoted by the same reference numerals, and a detailed description thereof is omitted.

[0106] In the analog integrated circuit 11B-b illustrated in Fig. 12, the buffer unit 12 has a circuit configuration similar to that of the buffer unit 12 in Fig. 8. A settling acceleration circuit 13B-b includes the P-type MOS transistor 31, the constant current source 32, the capacitor 33, the N-type MOS transistor 34, and the N-type MOS transistor 35, which have a circuit configuration similar to that of the settling acceleration circuit 13B in Fig. 8.

[0107] Then, the settling acceleration circuit 13B-b has a configuration different from that of the settling acceleration circuit 13B in Fig. 8 in that it includes a capacitor 53.

[0108] The capacitor 53 has one terminal connected to a connection point between the P-type MOS transistor 31 and the constant current source 32, and the other terminal to which a digital control signal DIN_SC is input.

[0109] The analog integrated circuit 11B-b having such a circuit configuration can improve the slew rate of the output terminal VOUT by shifting the digital control signal DIN_SC from the LOW level to the HIGH level and supplying the charge accumulated in the capacitor 53 to the connection point of the constant current source 32 in a period in which the voltage value of the output terminal VOUT decreases.

[0110] (Description of operation timing and time waveform) The operation of the settling acceleration circuit 13B-b is basically the same as that of the settling acceleration circuit 13B. Only different points will be described.

[0111] Fig. 13 illustrates voltage waveforms of the input terminal VIN and the output terminal VOUT and a time waveform of the digital control signal DIN_SC. When the voltage of the input terminal VIN is constant or small in change, settling acceleration of the voltage of the output terminal VOUT is unnecessary, and thus the digital control signal DIN_SC is set to the LOW level. The digital control signal DIN_SC is caused to transition from the LOW level to the HIGH level immediately before or at the moment when the voltage of the input terminal VIN decreases. This transition period is a slew rate acceleration period (SR acceleration period). Here, in order to describe the slew rate improving effect in an easily understandable manner, a period in which the digital control signal DIN_SC is changed from the LOW level to the HIGH level is provided, but the digital control signal DIN_SC may be instantaneously shifted from the LOW level to the HIGH level.

[0112] When the digital control signal DIN_SC changes from the LOW level to the HIGH level at the slew rate SRSCin the SR acceleration period, a current of ISC=SRSC×CSCis generated in the capacitor 53, and flows to the drain terminal of the N-type MOS transistor 34 via the source terminal and the drain terminal of the P-type MOS transistor 31. The current M×ISCamplified according to the current mirror ratio is output from the drain terminal of the N-type MOS transistor 35 and flows to the output terminal VOUT. The settling acceleration circuit 13B-b accelerates the settling of the output terminal VOUT, and the voltage of the output terminal VOUT can be quickly converged to the expected value in a shorter time. Hereinafter, since it is similar to the settling acceleration circuit 13B, the description thereof will be omitted.

[0113] (Improvement of settling parameter (slew rate)) The slew rate SR4of the output terminal VOUT in the SR acceleration period is determined by the characteristics of respective elements of the buffer unit 12 and the settling acceleration circuit 13B-b, and is expressed by the following Expression (4).

[0114]

[0115] When comparing the slew rate SR1of the above Expression (1), the slew rate SR2of the above Expression (2), and the slew rate SR4of the above Expression (4), it is apparent that the absolute value |SR4| of the slew rate SR4is larger than the absolute value |SR1| of the slew rate SR1and the absolute value |SR2| of the slew rate SR2. Specifically, the absolute value |SR4| of the slew rate SR4can be significantly increased by increasing M, which is the ratio of the current mirror circuit, or increasing the capacitance value CSCof the capacitor 53 to increase the DC current ISC, and it can be seen that the settling characteristic can be improved. Here, an example in which one terminal of the capacitor 53 is connected to the source terminal of the P-type MOS transistor 31 is described, but a similar effect can be obtained even if the one terminal is connected to the connection point between the gate terminal and the drain terminal of the N-type MOS transistor 34.

[0116] As described above, the analog integrated circuit 11B-b can further improve the slew rate of the output terminal VOUT in addition to improvement in performance by the analog integrated circuit 11.

[0117] As described above, the analog integrated circuit 11 of each of the above-described embodiments and modifications can be used for an image sensor reading circuit including an imaging element.

[0118] <Fourth configuration example of analog integrated circuit> Fig. 14 is a block diagram illustrating a configuration example of the fourth embodiment of an analog integrated circuit to which the present technology is applied. In an analog integrated circuit 11C illustrated in Fig. 14, components common to the analog integrated circuit 11 in Fig. 1 and the analog integrated circuit 11B-a in Fig. 10 are denoted by the same reference numerals, and a detailed description thereof is omitted.

[0119] The analog integrated circuit 11C illustrated in Fig. 14 is an image sensor reading circuit including an imaging element, and includes a buffer unit 14 including a pixel signal reading unit 67, a constant current source 69, the capacitor 23, and the resistor 22, and a settling acceleration circuit 13C.

[0120] The pixel signal reading unit 67 includes a photodiode 61, a transfer transistor 62, an FD node 63, an amplification transistor 64, a selection transistor 65, and a reset transistor 66. The output terminal of the pixel signal reading unit 67 is connected to a vertical signal line 68 via the resistor 22. The vertical signal line 68 is connected to the ground terminal VSS via the constant current source 69 and the capacitor 23 connected in parallel. Then, the vertical signal line 68 is connected to the gate terminal of the P-type MOS transistor 31 of the settling acceleration circuit 13C. Here, the resistor 22 and the capacitor 23 represent a parasitic wiring resistance and a parasitic capacitance of the vertical signal line 68, respectively. The amplification transistor 64 and the constant current source 69 constitute a source follower circuit to transmit the voltage of the FD node 63 to the vertical signal line 68. This is the same as the voltage buffer 21 described above, and the FD node 63 corresponds to the input terminal VIN and the output terminal VOUT corresponds to the vertical signal line 68.

[0121] As in the settling acceleration circuit 13B-a of Fig. 10, the settling acceleration circuit 13C includes the P-type MOS transistor 31, the constant current source 32, the capacitor 33, the N-type MOS transistor 34, the N-type MOS transistor 35, the constant current source 36, the constant current source 49, the current connection switch 50, the current cutoff switch 51, and the inverter 52. Further, as in the settling acceleration circuit 13 of Fig. 1, the connection cutoff switch 37 is provided.

[0122] (Description of operation timing and time waveform) Fig. 15 illustrates voltage waveforms of RST, TRG, DIN_SI, DIN_FB, and DIN_SAMP which are digital control signals, a voltage waveform of the FD node 63 which is an analog signal of an internal node, and a voltage waveform of the vertical signal line 68 (VSL). The settling acceleration period is when the digital control signal DIN_FB is at the HIGH level, and the slew rate acceleration period is when the digital control signal DIN_SI is at the HIGH level. A pixel selection signal SEL is set to the HIGH level.

[0123] In the FD node reset period of the P-phase period, the FD node 63 is connected to the power supply terminal VDD, and the FD node 63 is reset. When a digital control signal RST transitions from the HIGH level to the LOW level, the voltage of the FD node 63 decreases under the influence of the feedthrough from the reset transistor 66, and the voltage of the vertical signal line 68 decreases following the change of the FD node 63. A next-stage circuit (not illustrated) connected to the vertical signal line 68 waits for the voltage of the vertical signal line 68 to be stabilized, and reads the voltage V1Pof the vertical signal line 68 at the P-phase VSL voltage read timing.

[0124] In the pixel charge transfer period of the D-phase period, the charge accumulated in the photodiode 61 is transferred to the FD node 63. At this time, the voltage of the FD node 63 increases under the influence of the feedthrough of the transfer transistor 62. When a digital control signal TRG transitions from the HIGH level to the LOW level, the voltage of the FD node 63 greatly decreases under the influence of the feedthrough of the transfer transistor 62. A next-stage circuit (not illustrated) connected to the vertical signal line 68 waits for the voltage of the vertical signal line 68 to be stabilized, and reads the voltage V1Dof the vertical signal line 68 at the D-phase VSL voltage read timing.

[0125] In the P-phase period and the D-phase period, the digital control signal DIN_FB is caused to transition from the LOW level to the HIGH level immediately before or at the moment when the voltage of the vertical signal line 68 decreases, and the connection cutoff switch 37 is made conductive. At this time, the node VOUT_BST and the vertical signal line 68 are short-circuited, the settling acceleration circuit 13C accelerates the settling of the vertical signal line 68, and the voltage of the vertical signal line 68 can be converged to the expected value in a shorter time. Furthermore, in the D-phase period, the digital control signal DIN_SI is caused to transition from the LOW level to the HIGH level, and holds the HIGH level for a certain period (slew rate acceleration period). Although the voltage of the vertical signal line 68 drops in the slew rate acceleration period, by cutting off the current supplied from the constant current source 36 to the node VOUT_BST, the speed at which the voltage of the vertical signal line 68 drops in this period can be further increased.

[0126] The voltage of the vertical signal line 68 immediately after the end of the P-phase settling acceleration period is V1P-VERR, and the voltage of the vertical signal line 68 immediately after the end of the D-phase settling acceleration period is V1D-VERR. VERRis an error voltage generated by element variation or noise of the settling acceleration circuit 13C (VERRis preferably close to 0).

[0127] The error of the VSL voltage immediately after the end of the P-phase settling acceleration period from the expected value is VERR. The error of the VSL voltage immediately after the end of the D-phase settling acceleration period from the expected value is also the same VERR. The voltage of the vertical signal line 68 after the end of the P-phase and D-phase settling acceleration periods is settled by a time constant determined only from the characteristics of respective elements of the buffer unit 14, the influence of the VERRis reduced, and converges to expected values V1Pand V1D. In the CDS output V1D-V1P, the settling error voltage caused by the VERRis canceled out, and the influence can be reduced.

[0128] It is preferable to set the P-phase read WAIT period and the D-phase read WAIT period to the same value. At this time, the influence of the offset error VERRcaused by DAMP in the CDS output can be alleviated.

[0129] Therefore, as in the analog integrated circuit 11 of Fig. 1, the analog integrated circuit 11C having such a circuit configuration can significantly improve the settling characteristic of the vertical signal line (shortening of the time constant of the vertical signal line and improvement of the slew rate of the vertical signal line) while reducing the influence of the thermal noise of the settling acceleration circuit. Furthermore, as in the analog integrated circuit 11B-a in Fig. 10, the slew rate of the vertical signal line can be improved. Therefore, in the image sensor including the imaging element, the readout time of the pixel signal can be shortened and sped up.

[0130] <Fifth configuration example of analog integrated circuit> Fig. 16 is a block diagram illustrating a configuration example of a fifth embodiment of an analog integrated circuit to which the present technology is applied. An analog integrated circuit 11D illustrated in Fig. 16 is an imaging element including a buffer unit 14 serving as a pixel source follower circuit and a settling acceleration circuit 13D, as in the analog integrated circuit 11C in Fig. 14.

[0131] In the analog integrated circuit 11D illustrated in Fig. 16, the buffer unit 14 has a circuit configuration similar to that of the buffer unit 14 in Fig. 14, and the resistor 22 and the capacitor 23 represent a parasitic wiring resistance and a parasitic capacitance of the vertical signal line 68, respectively. The settling acceleration circuit 13D includes an N-type MOS transistor 81, a P-type MOS transistor 82, a capacitor 83, a P-type MOS transistor 84, an N-type MOS transistor 85, an N-type MOS transistor 86, a capacitor 87, and an N-type MOS transistor 88.

[0132] The vertical signal line 68 of the buffer unit 14 is connected to the source terminal of the N-type MOS transistor 81, and the drain terminal of the N-type MOS transistor 81 is connected to the connection point between the P-type MOS transistor 82 and the N-type MOS transistor 85. The N-type MOS transistor 81 is driven in accordance with a drive signal PC_DN3. In addition, the parasitic capacitance 89 of several pF is provided at a connection point between the vertical signal line 68 of the buffer unit 14 and the N-type MOS transistor 81.

[0133] The P-type MOS transistor 82 has a drain terminal of connected to the power supply terminal VDD, and a source terminal connected to a drain terminal of the N-type MOS transistor 85. The capacitor 83 has one terminal connected to the power supply terminal VDD, and the other terminal connected to the gate terminal of the P-type MOS transistor 82. The P-type MOS transistor 84 has one terminal connected to a connection point between the gate terminal of the P-type MOS transistor 82 and the capacitor 83, and the other terminal connected to the connection point between the P-type MOS transistor 82 and the N-type MOS transistor 85, and is driven according to a drive signal XPC_LMSH. That is, the P-type MOS transistor 82, the capacitor 83, and the P-type MOS transistor 84 constitute a second current source having a self-bias function in order to compensate for a current flowing through the N-type MOS transistor 86 serving as an acceleration current source. Furthermore, the self-bias function includes the P-type MOS transistor 82 serving as a switch constituting diode connection, and the sampling / holding capacitor 83.

[0134] The N-type MOS transistor 85 has a drain terminal connected to the P-type MOS transistor 82 and a source terminal connected to the N-type MOS transistor 86, and is driven according to a drive signal PC_DN. The N-type MOS transistor 86 has a drain terminal connected to the N-type MOS transistor 85, a source terminal connected to the ground terminal VSS, and a gate terminal connected to a connection point between the capacitor 87 and the N-type MOS transistor 88.

[0135] The capacitor 87 has one terminal connected to the drain terminal of the N-type MOS transistor 81, and the other terminal connected to the gate terminal of the N-type MOS transistor 86 and the drain terminal of the N-type MOS transistor 88. The N-type MOS transistor 88 is driven in accordance with a drive signal PC_LMSH.

[0136] The settling acceleration circuit 13D is configured in this manner, and the acceleration circuit unit including the N-type MOS transistor 85, the N-type MOS transistor 86, the capacitor 87, and the N-type MOS transistor 88 has a function of sampling and holding the bias voltage by the drive signal PC_LMSH, and is biased so as to flow a certain current IEN. As a result, at the end of the acceleration period, it is possible to prevent the N-type MOS transistor 86 for acceleration from being turned off and the acceleration capability from being rapidly lowered.

[0137] In addition, when the bias voltage is sampled and held, the N-type MOS transistor 81 driven according to the drive signal PC_DN3 is turned off, and the N-type MOS transistor 85 driven according to the drive signal PC_DN is turned on. Then, the gate electrode of the N-type MOS transistor 86 and the vertical signal line 68 are connected via the capacitor 87, and the fluctuation of the vertical signal line 68 is directly input to the N-type MOS transistor 86 as the fluctuation of the gate-source voltage, so that the vertical signal line 68 can be efficiently accelerated.

[0138] In addition, the current compensation unit including the P-type MOS transistor 82, the capacitor 83, and the P-type MOS transistor 84 has a mechanism of sampling and holding the current IEN so that the current does not become 0 in the bias state of the N-type MOS transistor 86 for acceleration. As a result, it is possible to maintain high speed performance by supplying a sufficient current to the N-type MOS transistor 86 even at the time of convergence.

[0139] Then, when the acceleration period ends, the N-type MOS transistor 81 is turned off according to the drive signal PC_DN3, and the acceleration circuit unit and the current compensation unit are disconnected from the vertical signal line 68. At this time, the noise of the acceleration circuit unit and the current compensation unit is stored in the parasitic capacitance 89, but the noise is reduced by the convergence operation of the buffer unit 14 after the acceleration period.

[0140] Furthermore, as illustrated in Fig. 17, in the sampling and holding period from time t0 to time t1, the bias voltage can be held in the capacitor 87 connected between the output terminal of the vertical signal line 68 and the gate terminal of an N-type MOS transistor 86. Then, when the output of the vertical signal line 68 increases due to the feedthrough phenomenon at the time of transfer of the pixel signal, the applied voltage EMHIZ applied to the gate terminal of the N-type MOS transistor 86 also increases as illustrated in Fig. 17. As a result, a gate-source voltage of the N-type MOS transistor 86 serving as an acceleration current source is greatly opened.

[0141] Furthermore, in an analog integrated circuit 11D, by connecting the drain terminal of the N-type MOS transistor 86 serving as an acceleration current source and the output terminal of the vertical signal line 68 at the end of transfer of the pixel signal (time t4), the charge is rapidly extracted from a parasitic capacitance 89 of the vertical signal line 68, and as a result, the output of the vertical signal line 68 is accelerated. Note that in Fig. 17, the output of the vertical signal line in the settling in the related art is indicated by a broken line.

[0142] Then, by including an N-type MOS transistor 81 that cut offs the acceleration circuit unit and the current compensation unit from the vertical signal line 68 after the acceleration is finished (time t5), at the time of convergence, noise added from the acceleration circuit unit is reduced by the buffer unit 14 as illustrated in Fig. 17. That is, noise reduction can be realized as compared with the technique in the related art.

[0143] As described above, since the analog integrated circuit 11D does not depend on the negative capacitance by using the voltage of the vertical signal line 68 as the input of the acceleration current source via a capacitor 87, it is possible to realize efficient acceleration with a smaller area and power saving than before. Furthermore, since the analog integrated circuit 11D can reduce the circuit size more than before, for example, it can contribute to improvement of the process yield without making the sensor size lower chip rate.

[0144] Note that a circuit configuration in which the N-type MOS transistor and the P-type MOS transistor used in the description in the present embodiment are reversed may be used.

[0145] <Configuration example of electronic device> The above-described imaging element may be applied to various electronic devices such as an imaging system such as a digital still camera and a digital video camera, a mobile phone having an imaging function, or another device having an imaging function, for example.

[0146] Fig. 18 is a block diagram illustrating a configuration example of an imaging device mounted on an electronic device.

[0147] As illustrated in Fig. 18, an imaging device 101 includes an optical system 102, an imaging element 103, a signal processing circuit 104, the monitor 105, and the memory 106, and can capture a still image and a moving image.

[0148] The optical system 102 includes one or a plurality of lenses, guides image light (incident light) from an object to the imaging element 103, and forms an image on a light receiving face (sensor unit) of the imaging element 103.

[0149] As the imaging element 103, the imaging element described above is applied. Electrons are accumulated in the imaging element 103 for a certain period in accordance with the image formed on the light receiving face via the optical system 102. Then, a signal corresponding to the electrons accumulated in the imaging element 103 is supplied to the signal processing circuit 104.

[0150] The signal processing circuit 104 performs various types of signal process on a pixel signal output from the imaging element 103. An image (image data) obtained by the signal processing circuit 104 performing the signal processing is supplied to the monitor 105 to be displayed or supplied to the memory 106 to be stored (recorded).

[0151] In the imaging device 101 configured as described above, for example, a higher quality image can be captured speed by applying the above-described imaging element.

[0152] <Use example of image sensor> Fig. 19 is a diagram illustrating a use example of the above-mentioned image sensor (imaging element).

[0153] The above-described image sensor can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-ray as described below, for example.

[0154] - A device that captures an image to be used for viewing, such as a digital camera and a portable device with a camera function. - A device for traffic purpose such as an in-vehicle sensor which takes images of the front, rear, surroundings, interior and the like of an automobile, a monitoring camera for monitoring traveling vehicles and roads, and a ranging sensor which measures a distance between vehicles and the like for safe driving such as automatic stop, recognition of a driver's condition and the like. - A device for home appliance such as a television, a refrigerator, and an air conditioner that images a user’s gesture and performs device operation according to the gesture. - A device for medical and health care use such as an endoscope and a device that performs angiography by receiving infrared light. - A device for security use such as a security monitoring camera and an individual authentication camera. - A device used for beauty care, such as a skin measuring instrument for imaging skin, and a microscope for imaging the scalp. - A device used for sport, such as an action camera or a wearable camera for sports applications or the like. - A device used for agriculture, such as a camera for monitoring a condition of a field or crop.

[0155] <Combination examples of configurations> Note that the present technology can also have the following configurations. (1) An acceleration circuit comprising: a first transistor; a first capacitor connected in parallel with a first constant current source between a power supply terminal of the acceleration circuit and a source of the first transistor; a current mirror circuit, an input of the current mirror circuit is connected to a drain of the first transistor; and a first switch, a first end of the first switch is connected to an input terminal of the acceleration circuit and a second end of the first switch is connected to an output of the current mirror circuit and to an output terminal of the acceleration circuit. (2) The acceleration circuit of (1), wherein the first switch is enabled in association with a p-phase period and in association with a d-phase period to connect the acceleration circuit to the output terminal before and / or during a voltage decrease at the output terminal. (3) The acceleration circuit of (2), further comprising: a second constant current source connected to the output of the current mirror circuit. (4) The acceleration circuit of claim 3, further comprising: a second switch to connect the second constant current source to the output of the current mirror circuit, wherein the second switch is enabled according to the same control signal as the first switch. (5) The acceleration circuit of (3), further comprising: a second switch to cut off a current supplied to the current mirror circuit according to a control signal inversely related to a control signal of the first switch. (6) The acceleration circuit of (3), further comprising: a second switch to cut off a current supplied to the current mirror circuit according to detection of a settlement condition of the acceleration circuit. (7) The acceleration circuit of (2), further comprising: an auto-zero circuit including a second transistor, a source of the second transistor is connected to the power supply terminal and a drain of the second transistor is connected to the output of the current mirror circuit, a second capacitor, a first end of the second capacitor is connected to the power supply terminal and a second end of the second capacitor is connected to a gate of the second transistor, and a second switch, a first end of the second switch is connected to the second end of the second capacitor and to the gate of the second transistor, a second end of the second switch is connected to the output of the current mirror circuit. (8) The acceleration circuit of (7), wherein the second switch is enabled during an auto-zero period prior to enablement of the first switch. (9) The acceleration circuit of (2), further comprising: a second constant current source connected between the power supply terminal and the input of the current mirror circuit; and a second switch to cut off a connection of the second constant current source to the input of the current mirror circuit. (10) The acceleration circuit of (9), further comprising: a third constant current source connected between the power supply terminal and the output of the current mirror circuit; and a third switch to cut off a connection of the third constant current source to the output of the current mirror circuit, wherein the third switch is enabled inversely to the second switch. (11) The acceleration circuit of (10), wherein the second switch is enabled before and / or during a voltage decrease at the output terminal. (12) The acceleration circuit of (1), further comprising: a second capacitor to supply a current to the source of the first transistor according to a control signal that is activated before or during a voltage decrease at the input terminal. (13) An image sensor read out circuit comprising: a pixel circuit connected to a vertical signal line; and an acceleration circuit connected to the vertical signal line, the acceleration circuit including a first transistor to provide an acceleration current source, a gate of the first transistor is connected to the vertical signal line via a first capacitor such that a fluctuation voltage of the vertical signal line is directly input as a gate-source voltage of the first transistor, a compensation current source connected to the first transistor to compensate for a current flowing through the first transistor. (14) The image sensor read out circuit of (13), wherein the acceleration circuit further includes a second transistor; and a third transistor, wherein a source of the second transistor is connected to the vertical signal line and a drain of the second transistor is connected to a connection point between the compensation current source and a drain of the third transistor, and a source of the third transistor is connected to a source of the first transistor. (15) The image sensor read out circuit of (14), wherein the acceleration circuit further includes a parasitic capacitance connected to the vertical signal line to store noise associated with the acceleration circuit. (16) The image sensor read out circuit of claim of (14), wherein the compensation current source includes a fourth transistor, a second capacitor, and a fifth transistor, a drain of the third transistor is connected to a power supply terminal, a source of the third transistor is connected to a drain of the third transistor. (17) An image sensor read out circuit comprising: a pixel circuit connected to a vertical signal line; and an acceleration circuit connected to the vertical signal line, the acceleration circuit comprising: a first transistor; a first capacitor connected in parallel with a first constant current source between a power supply terminal of the acceleration circuit and a source of the first transistor; a current mirror circuit, an input of the current mirror circuit is connected to a drain of the first transistor; and a first switch, a first end of the first switch is connected to the vertical signal line and a second end of the first switch is connected to an output of the current mirror circuit and to an output terminal of the acceleration circuit. (18) The image sensor read out circuit of (17), wherein the first switch is enabled in association with a p-phase period and in association with a d-phase period to connect the acceleration circuit to the output terminal before and / or during a voltage decrease at the output terminal. (19) The image sensor read out circuit of (18), wherein the acceleration circuit further includes a second constant current source connected to the output of the current mirror circuit, and a second switch to connect the second constant current source to the output of the current mirror circuit, wherein the second switch is enabled according to the same control signal as the first switch. (20) The image sensor read out circuit of (19), wherein the acceleration circuit further includes a second switch to cut off a current supplied to the current mirror circuit according to a control signal inversely related to a control signal of the first switch.

[0156] Note that, the present embodiment is not limited to the embodiment described above, and various modifications can be made without departing from the gist of the present disclosure. Furthermore, effects described in the present description are merely examples and are not limited, and other effects may also be provided.

[0157] 11 Analog integrated circuit 12 Buffer unit 13 Settling acceleration circuit 14 Buffer unit 21 Voltage buffer 22 Resistor 23 Capacitor 31 P-type MOS transistor 32 Constant current source 33 Capacitor 34 N-type MOS transistor 35 N-type MOS transistor 36 Constant current source 37 Connection cutoff switch 38 Current cutoff switch 39 Current cutoff switch 40 Inverter 41 Current cutoff switch 42 Comparator 43 P-type MOS transistor 44 Capacitor 45 Auto-zero switch 46 Connection cutoff switch 47 Inverter 48 Changeover switch 49 Constant current source 50 Current connection switch 51 Current cutoff switch 52 Inverter 53 Inverter 54 Capacitor

Claims

1. An acceleration circuit comprising: a first transistor; a first capacitor connected in parallel with a first constant current source between a power supply terminal of the acceleration circuit and a source of the first transistor; a current mirror circuit, an input of the current mirror circuit is connected to a drain of the first transistor; and a first switch, a first end of the first switch is connected to an input terminal of the acceleration circuit and a second end of the first switch is connected to an output of the current mirror circuit and to an output terminal of the acceleration circuit.

2. The acceleration circuit of claim 1, wherein the first switch is enabled in association with a p-phase period and in association with a d-phase period to connect the acceleration circuit to the output terminal before and / or during a voltage decrease at the output terminal.

3. The acceleration circuit of claim 2, further comprising: a second constant current source connected to the output of the current mirror circuit.

4. The acceleration circuit of claim 3, further comprising: a second switch to connect the second constant current source to the output of the current mirror circuit, wherein the second switch is enabled according to the same control signal as the first switch.

5. The acceleration circuit of claim 3, further comprising: a second switch to cut off a current supplied to the current mirror circuit according to a control signal inversely related to a control signal of the first switch.

6. The acceleration circuit of claim 3, further comprising: a second switch to cut off a current supplied to the current mirror circuit according to detection of a settlement condition of the acceleration circuit.

7. The acceleration circuit of claim 2, further comprising: an auto-zero circuit including a second transistor, a source of the second transistor is connected to the power supply terminal and a drain of the second transistor is connected to the output of the current mirror circuit, a second capacitor, a first end of the second capacitor is connected to the power supply terminal and a second end of the second capacitor is connected to a gate of the second transistor, and a second switch, a first end of the second switch is connected to the second end of the second capacitor and to the gate of the second transistor, a second end of the second switch is connected to the output of the current mirror circuit.

8. The acceleration circuit of claim 7, wherein the second switch is enabled during an auto-zero period prior to enablement of the first switch.

9. The acceleration circuit of claim 2, further comprising: a second constant current source connected between the power supply terminal and the input of the current mirror circuit; and a second switch to cut off a connection of the second constant current source to the input of the current mirror circuit.

10. The acceleration circuit of claim 9, further comprising: a third constant current source connected between the power supply terminal and the output of the current mirror circuit; and a third switch to cut off a connection of the third constant current source to the output of the current mirror circuit, wherein the third switch is enabled inversely to the second switch.

11. The acceleration circuit of claim 10, wherein the second switch is enabled before and / or during a voltage decrease at the output terminal.

12. The acceleration circuit of claim 1, further comprising: a second capacitor to supply a current to the source of the first transistor according to a control signal that is activated before or during a voltage decrease at the input terminal.

13. An image sensor read out circuit comprising: a pixel circuit connected to a vertical signal line; and an acceleration circuit connected to the vertical signal line, the acceleration circuit including a first transistor to provide an acceleration current source, a gate of the first transistor is connected to the vertical signal line via a first capacitor such that a fluctuation voltage of the vertical signal line is directly input as a gate-source voltage of the first transistor, a compensation current source connected to the first transistor to compensate for a current flowing through the first transistor.

14. The image sensor read out circuit of claim 13, wherein the acceleration circuit further includes a second transistor; and a third transistor, wherein a source of the second transistor is connected to the vertical signal line and a drain of the second transistor is connected to a connection point between the compensation current source and a drain of the third transistor, and a source of the third transistor is connected to a source of the first transistor.

15. The image sensor read out circuit of claim 14, wherein the acceleration circuit further includes a parasitic capacitance connected to the vertical signal line to store noise associated with the acceleration circuit.

16. The image sensor read out circuit of claim of claim 14, wherein the compensation current source includes a fourth transistor, a second capacitor, and a fifth transistor, a drain of the third transistor is connected to a power supply terminal, a source of the third transistor is connected to a drain of the third transistor.

17. An image sensor read out circuit comprising: a pixel circuit connected to a vertical signal line; and an acceleration circuit connected to the vertical signal line, the acceleration circuit comprising: a first transistor; a first capacitor connected in parallel with a first constant current source between a power supply terminal of the acceleration circuit and a source of the first transistor; a current mirror circuit, an input of the current mirror circuit is connected to a drain of the first transistor; and a first switch, a first end of the first switch is connected to the vertical signal line and a second end of the first switch is connected to an output of the current mirror circuit and to an output terminal of the acceleration circuit.

18. The image sensor read out circuit of claim 17, wherein the first switch is enabled in association with a p-phase period and in association with a d-phase period to connect the acceleration circuit to the output terminal before and / or during a voltage decrease at the output terminal.

19. The image sensor read out circuit of claim 18, wherein the acceleration circuit further includes a second constant current source connected to the output of the current mirror circuit, and a second switch to connect the second constant current source to the output of the current mirror circuit, wherein the second switch is enabled according to the same control signal as the first switch.

20. The image sensor read out circuit of claim 19, wherein the acceleration circuit further includes a second switch to cut off a current supplied to the current mirror circuit according to a control signal inversely related to a control signal of the first switch.

Images