Voltage mode logic circuit with improved transition speed

Abstract

A voltage mode logic circuit with an improved transition speed, according to an embodiment of the disclosed invention, comprises: a first transistor having one end connected to a power supply; a second transistor having one end connected to the first transistor; a third transistor having one end connected to the second transistor; a fourth transistor having one end connected to the third transistor; an input terminal connected to gate nodes of the second transistor and the third transistor and to which an input voltage is applied; and an output terminal connected between the second transistor and the third transistor.

Description

Voltage-mode logic circuit with improved transition speed

[0001] The present invention relates to a voltage mode logic circuit with improved transition speed, and more specifically, to a voltage mode logic circuit capable of shortening the transition time by amplifying current through a delay inverter and a transistor.

[0002] Voltage-Mode Logic (VML) is a technique used in digital logic circuit design that allows logic operations to be performed based on the voltage level of an input signal.

[0003] These voltage mode logic (VML) circuits can be used to implement digital logic circuits, which are mainly suitable for mobile devices and ultra-small devices with low power and high performance requirements.

[0004] High-speed signal processing circuits are implemented using voltage mode logic circuits or current mode logic circuits, and since they are generally configured in a form that uses a resistance element as a load in a differential amplifier, they have the advantage of being able to achieve higher operating speeds than the CMOS (Complementary metal-oxide semiconductor) method that pairs NMOS (N-channel metal oxide semiconductor) or PMOS (N-channel metal oxide semiconductor) elements.

[0005] Furthermore, voltage-mode logic circuits offer advantages in noise reduction because they can transmit signals as differential signals. Therefore, voltage-mode logic circuits can be used in gigabit-band integrated circuits (GICs) that require high-speed operation to support 10-Gbps Gigabit-capable Passive Optical Networks (GPON).

[0006] In addition, among the voltage mode logic circuits, there is a cascode voltage mode logic circuit in which two different transistors are connected to each other to form a multi-stage transistor. Such a cascode voltage mode logic circuit can increase the output impedance and reduce the risk of transistor damage even in a large output swing.

[0007] However, in the case of conventional cascode voltage mode logic circuits, there is a problem that the size of the coupling capacitor must be configured to be considerably large in order to obtain a boosting effect, as the GM-boosting of the voltage mode logic circuit is implemented using an inverter and a coupling capacitor.

[0008] Accordingly, a voltage mode logic circuit with improved transition speed according to one embodiment of the disclosed invention is an invention created to solve the above-described problem, and more specifically, a voltage mode logic circuit with improved transition speed that can shorten the transition time of a circuit by quickly controlling the flow of current using a delay inverter and an auxiliary transistor can be provided.

[0009] A voltage mode logic circuit with improved transition speed according to one embodiment of the disclosed invention may include a first transistor having one end connected to a power supply, a second transistor having one end connected to the first transistor, a third transistor having one end connected to the second transistor, a fourth transistor having one end connected to the third transistor, an input terminal connected to gate nodes of the second transistor and the third transistor and to which an input voltage is applied, and an output terminal connected between the second transistor and the third transistor.

[0010] The voltage mode logic circuit with improved transition speed may further include a first auxiliary transistor connected between the first transistor and the second transistor, and a second auxiliary transistor connected between the third transistor and the fourth transistor.

[0011] The voltage mode logic circuit with improved transition speed may further include an inverter disposed between the input terminal and the gate node of the first auxiliary transistor and the gate node of the second auxiliary transistor.

[0012] The inverter may be configured to delay a transition of an output voltage output from the inverter.

[0013] The first auxiliary transistor and the second transistor can be turned off during the delay time generated by the inverter during the rising transition period of the input voltage.

[0014] The second auxiliary transistor can be turned ON during the delay time generated by the inverter during the rising transition period of the input voltage.

[0015] The voltage mode logic circuit with improved transition speed may further include a plurality of pulse generators arranged between the input terminal and the gate node of the first auxiliary transistor and arranged between the gate node of the second auxiliary transistor.

[0016] The first transistor and the second transistor may be P-type transistors, and the third transistor and the fourth transistor may be N-type transistors.

[0017] The voltage mode logic circuit with improved transition speed may further include an output resistor disposed between the output terminal and the second transistor and the third transistor.

[0018] A voltage mode logic circuit with improved transition speed according to one embodiment of the disclosed invention may include a first transistor having one end connected to a power supply, a second transistor having one end connected to the first transistor, a third transistor having one end connected to the second transistor, a fourth transistor having one end connected to the third transistor, an input terminal connected to gate nodes of the second transistor and the third transistor and to which an input voltage is applied, a first auxiliary transistor connected between the first transistor and the second transistor, a second auxiliary transistor connected between the third transistor and the fourth transistor, and an inverter disposed between the input terminal and a gate node of the first auxiliary transistor and a gate node of the second auxiliary transistor.

[0019] The inverter may be configured to delay a transition of an output voltage output from the inverter.

[0020] The first auxiliary transistor and the second transistor can be turned off during the delay time generated by the inverter during the rising transition period of the input voltage.

[0021] The first transistor and the second transistor may be P-type transistors, and the third transistor and the fourth transistor may be N-type transistors.

[0022] The voltage mode logic circuit with improved transition speed can be configured as a pair that is symmetrical to operate in differential mode.

[0023] A voltage mode logic circuit with improved transition speed according to one embodiment of the disclosed invention may include a first transistor having one end connected to a power supply, a second transistor having one end connected to the first transistor, a third transistor having one end connected to the second transistor, a fourth transistor having one end connected to the third transistor, an input terminal connected to gate nodes of the second transistor and the third transistor and to which an input voltage is applied, a first auxiliary transistor connected between the first transistor and the second transistor, a second auxiliary transistor connected between the third transistor and the fourth transistor, and a plurality of pulse generators disposed between the input terminal and the gate node of the first auxiliary transistor and disposed between the gate node of the second auxiliary transistor.

[0024] A voltage mode logic circuit with improved transition speed according to one embodiment of the disclosed invention has the advantage of being able to shorten the transition time of the circuit by quickly controlling the flow of current using a delay inverter and an auxiliary transistor.

[0025] In addition, a voltage mode logic circuit with improved transition speed according to one embodiment of the disclosed invention can switch signals at a faster cycle due to a shortened transition time, thereby providing a driver circuit with reduced signal distortion and reduced data loss or errors.

[0026] In addition, a voltage mode logic circuit with improved transition speed according to one embodiment of the disclosed invention enables implementation of a high-speed transmitter in high-speed signal transmission, and has the advantage of improving overall system performance and signal accuracy.

[0027] In addition, the voltage mode logic circuit with improved transition speed according to one embodiment of the disclosed invention has the advantage of being usable in drive circuits in various application fields requiring high-speed operation where data transmission speed and reliability are important.

[0028] FIG. 1 is a diagram illustrating a voltage mode logic circuit of a cascode structure according to the prior art.

[0029] FIG. 2 is a diagram showing the voltage of each node during a rising transition when a pulse signal is applied to the voltage mode logic circuit illustrated in FIG. 1.

[0030] FIG. 3 is a diagram illustrating a voltage mode logic circuit configured to boost the flow of current by adding an inverter and a coupling capacitor to the voltage mode logic circuit illustrated in FIG. 1.

[0031] FIG. 4 is a diagram illustrating a voltage mode logic circuit with improved transition speed according to one embodiment of the disclosed invention.

[0032] FIG. 5 is a diagram showing the voltage of each node during a rising transition when a step signal is applied to the voltage mode logic circuit illustrated in FIG. 4.

[0033] FIG. 6 is a diagram showing the voltage of each node during a downward transition when a step signal is applied to the voltage mode logic circuit illustrated in FIG. 4.

[0034] FIG. 7 is a diagram comparing the waveforms of differential output voltages output during a rising transition after changing a voltage mode logic circuit according to the prior art and a voltage mode logic circuit according to the disclosed invention to a differential mode.

[0035] FIG. 8 is a diagram comparing the waveforms of differential output voltages output during a downward transition after changing a voltage mode logic circuit according to the prior art and a voltage mode logic circuit according to the disclosed invention to a differential mode.

[0036] FIG. 9 is a diagram illustrating a voltage mode logic circuit with improved transition speed implemented in differential mode according to one embodiment of the disclosed invention.

[0037] Fig. 10 is a diagram showing the voltage of each node when a step signal is applied to the voltage mode logic circuit illustrated in Fig. 9.

[0038] FIG. 11 is a diagram illustrating a voltage mode logic circuit with improved transition speed according to another embodiment of the disclosed invention.

[0039] FIG. 12 is a diagram showing the voltage of each node during a rising transition when a step signal is applied to the voltage mode logic circuit shown in FIG. 11.

[0040] Fig. 13 is a diagram showing the voltage of each node during a downward transition when a step signal is applied to the voltage mode logic circuit illustrated in Fig. 11.

[0041] The embodiments described in this specification and the configurations illustrated in the drawings are merely preferred examples of the disclosed invention, and there may be various modified examples that can replace the embodiments and drawings of this specification at the time of filing of this application.

[0042] Additionally, the same reference numbers or symbols presented in each drawing of this specification represent parts or components that perform substantially the same function.

[0043] Additionally, the terminology used herein is for the purpose of describing embodiments and is not intended to limit and / or restrict the disclosed invention. Singular expressions include plural expressions unless the context clearly dictates otherwise.

[0044] In this specification, terms such as “include” or “have” are intended to specify the presence of a feature, number, step, operation, component, part or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

[0045] Additionally, terms including ordinal numbers such as “first,” “second,” etc., used herein may be used to describe various components, but the components are not limited by the terms, and the terms are used only for the purpose of distinguishing one component from another.

[0046] For example, without departing from the scope of the present invention, a first component could be referred to as a second component, and similarly, a second component could also be referred to as a first component. The term "and / or" includes any combination of a plurality of related listed items or any one of a plurality of related listed items.

[0047] Hereinafter, embodiments according to the present invention will be described in detail with reference to the attached drawings.

[0048]

[0049] Fig. 1 is a diagram illustrating a voltage mode logic circuit having a cascode structure according to the prior art. Fig. 2 is a diagram illustrating the voltage of each node during a rising transition when a pulse signal is applied to the voltage mode logic circuit illustrated in Fig. 1. Fig. 3 is a diagram illustrating a voltage mode logic circuit configured to boost the flow of current by adding an inverter and a coupling capacitor to the voltage mode logic circuit illustrated in Fig. 1.

[0050] Referring to FIG. 1, a voltage mode logic circuit of a cascode structure according to the prior art can be composed of a circuit including a first transistor (11), a second transistor (12), a third transistor (13), a fourth transistor (14), and an output resistor (R).

[0051] More specifically, a voltage mode logic circuit of a cascode structure according to the prior art can be configured so that an input terminal (IN) is connected to the gate node of the second transistor (12) and the gate node of the third transistor (13) to apply an input voltage.

[0052] In addition, the voltage mode logic circuit of the cascode structure according to the prior art can output an output voltage for an input voltage through an output resistor (R) and an output terminal (OUT) connected between the second transistor (12) and the third transistor (13).

[0053] These cascode voltage mode logic circuits can be located at the transmitter end of the driver and used to transmit signals at high speed.

[0054] Referring to FIG. 2, a voltage mode logic circuit according to the prior art can have an input voltage applied to the gate nodes of the second transistor (12) and the third transistor (13) in a rising transition section.

[0055] Accordingly, in the transition section, the voltage VINTN of one node of the third transistor (13) rises momentarily due to the gate-source coupling parasitic capacitor of the input transistor.

[0056] Additionally, the voltage VINTP of one node of the second transistor (12) also rises momentarily.

[0057] Accordingly, when the input voltage transitions from a LOW level to a HIGH level, the output voltage can transition from a HIGH level to a LOW level.

[0058] Referring to FIG. 3, a boosting voltage mode logic circuit implemented to boost the flow of current in a voltage mode logic circuit of a cascode structure according to the prior art may be configured as a circuit including a first transistor (11), a second transistor (12), a third transistor (13), a fourth transistor (14), an output resistor (R), an inverter (100), and a coupling capacitor.

[0059] More specifically, a voltage mode logic circuit according to the prior art may include an inverter (100) connected to an input terminal (IN).

[0060] Additionally, a coupling capacitor may be connected between the inverter (100) and one terminal of the second transistor (12), and may be connected between the inverter (100) and one terminal of the third transistor (13).

[0061] However, in the case of a method of boosting current using an inverter (100) and a coupling capacitor according to the conventional technology, there is a problem that the size of the coupling capacitor must be significantly large to obtain the desired boosting effect.

[0062] Accordingly, the voltage mode logic circuit according to the disclosed invention can provide a circuit capable of implementing a boosting effect using an inverter (100) and an auxiliary transistor. Details regarding this will be described later.

[0063]

[0064] FIG. 4 is a diagram illustrating a voltage mode logic circuit with improved transition speed according to one embodiment of the disclosed invention. FIG. 5 is a diagram illustrating the voltage of each node during a rising transition when a step signal is applied to the voltage mode logic circuit illustrated in FIG. 4. FIG. 6 is a diagram illustrating the voltage of each node during a falling transition when a step signal is applied to the voltage mode logic circuit illustrated in FIG. 4.

[0065] Referring to FIG. 4, a voltage mode logic circuit with improved transition speed according to one embodiment of the disclosed invention may include a first transistor (11), a second transistor (12), a third transistor (13), a fourth transistor (14), an output resistor (R), an inverter (100), a first auxiliary transistor (21), and a second auxiliary transistor (22).

[0066] More specifically, the first transistor (11) of the voltage mode logic circuit according to the disclosed invention can be connected to a power supply at one end.

[0067] Additionally, the first transistor (11) can have one terminal connected to one terminal of the second transistor (12).

[0068] Additionally, the first transistor (11) can be turned ON or OFF through a signal applied to the gate node.

[0069] Additionally, the second transistor (12) of the voltage mode logic circuit according to the disclosed invention can have one end connected to the other end of the first transistor (11).

[0070] Additionally, the second transistor (12) can have one terminal connected to one terminal of the third transistor (13).

[0071] Specifically, the second transistor (12) can receive an input voltage transmitted from the input terminal (IN) as input to the gate node.

[0072] More specifically, the gate node of the second transistor (12) can be connected to the input terminal (IN).

[0073] Additionally, the third transistor (13) of the voltage mode logic circuit according to the disclosed invention can have one end connected to the other end of the second transistor (12).

[0074] Additionally, the third transistor (13) can be connected to one end of the fourth transistor (14).

[0075] Specifically, the third transistor (13) can receive an input voltage transmitted from the input terminal (IN) as an input to the gate node.

[0076] More specifically, the gate node of the third transistor (13) can be connected to the input terminal (IN).

[0077] The second transistor (12) and third transistor (13) described above can be defined as input transistors of a cascode type voltage mode logic circuit according to the present invention.

[0078] Additionally, the fourth transistor (14) can have one end connected to the other end of the third transistor (13) and the other end grounded.

[0079] Specifically, the fourth transistor (14) can be turned ON or OFF through a signal applied to the gate node.

[0080] The input terminal (IN) can be connected to the gate nodes of the second transistor (12) and the third transistor (13). An input voltage can be applied to the voltage mode logic circuit of the disclosed invention through the input terminal (IN).

[0081] The output terminal (OUT) can be connected to a node between the second transistor (12) and the third transistor (13). More specifically, the output terminal (OUT) can be connected to the other terminal of the second transistor (12) and one terminal of the third transistor (13) through an output resistor (R).

[0082] The output resistor (R) can be connected to the node between the output terminal (OUT) and the second transistor (12) and the third transistor (13).

[0083] The first auxiliary transistor (21) can be connected to a node between the first transistor (11) and the second transistor (12).

[0084] More specifically, the first auxiliary transistor (21) can have one end connected to a power supply and the other end connected to one end of the second transistor (12).

[0085] Additionally, the gate node of the first auxiliary transistor (21) can be connected to the output node of the inverter (100).

[0086] The second auxiliary transistor (22) can be connected between the third transistor (13) and the fourth transistor (14).

[0087] More specifically, the second auxiliary transistor (22) may have one end connected to one end of the fourth transistor (14) and the other end grounded.

[0088] Additionally, the gate node of the second auxiliary transistor (22) can be connected to the output node of the inverter (100).

[0089] Therefore, the first auxiliary transistor (21) and the second auxiliary transistor (22) can be connected in parallel based on the output node of the inverter (100).

[0090] The inverter (100) can be placed between the input terminal (IN) and the gate node of the first auxiliary transistor (21) and the gate node of the second auxiliary transistor (22).

[0091] More specifically, the inverter (100) may be configured to receive an input voltage of an input terminal (IN) through an input node and delay the transition of an output voltage output from the inverter (100) when the input voltage transitions. Details regarding this will be described later.

[0092] In addition, the first transistor (11) and the second transistor (12) of the voltage mode logic circuit according to the disclosed invention may be configured as P-type transistors, and the third transistor (13) and the fourth transistor (14) may be configured as N-type transistors.

[0093] Referring to FIG. 5, a pulse signal is applied to a voltage mode logic circuit according to the disclosed invention, and the voltage change of each node according to the rising transition of the input voltage is explained.

[0094] Referring to FIGS. 4 and 5, the input voltage VIN of the voltage mode logic circuit according to one embodiment of the disclosed invention can be transitioned from a LOW level to a HIGH level and applied to the inverter (100).

[0095] More specifically, in the rising transition section where the input voltage changes from a LOW level to a HIGH level, the voltage VINB of the output node of the inverter (100) may have a transition delay due to the delay time generated by the inverter (100).

[0096] Additionally, the second auxiliary transistor (22) can be turned ON during the delay time generated by the inverter (100) in the rising transition section of the input voltage.

[0097] Additionally, the gate-source voltage of the third transistor (13) may temporarily increase and reach a peak during a rising transition due to the gate-source coupling parasitic capacitor of the third transistor (13).

[0098] Accordingly, during the rising transition of the input voltage, the voltage VINTN of one node of the second auxiliary transistor (22) can be boosted after reaching the peak.

[0099] Accordingly, the voltage mode logic circuit according to one embodiment of the disclosed invention has a technical effect in that the current can be boosted through the inverter (100) and the auxiliary transistor and the transition time can be shortened.

[0100] Additionally, the first auxiliary transistor (21) and the second transistor (12) can be turned off during the delay time generated by the inverter (100) during the rising transition period of the input voltage.

[0101] Accordingly, when the input voltage rises in transition, the voltage VINTP of one node of the second transistor (12) floats and can be stabilized when the first auxiliary transistor (21) is turned ON after a delay time has elapsed.

[0102] Referring to FIG. 6, the input voltage VIN of the voltage mode logic circuit according to one embodiment of the disclosed invention can be transitioned from a HIGH level to a LOW level and applied to the inverter (100).

[0103] More specifically, in the downward transition section where the input voltage changes from a HIGH level to a LOW level, the voltage VINB of the output node of the inverter (100) may have a transition delay due to the delay time generated by the inverter (100).

[0104] Accordingly, the voltage mode logic circuit according to one embodiment of the disclosed invention has a technical effect in that the current can be boosted through the inverter (100) and the auxiliary transistor and the transition time can be shortened.

[0105]

[0106] FIG. 7 is a diagram comparing the waveforms of differential output voltages output during a rising transition after a voltage mode logic circuit according to the prior art and a voltage mode logic circuit according to the disclosed invention are changed to differential mode. FIG. 8 is a diagram comparing the waveforms of differential output voltages output during a falling transition after a voltage mode logic circuit according to the prior art and a voltage mode logic circuit according to the disclosed invention are changed to differential mode.

[0107] Referring to FIG. 7, the voltage mode logic circuit according to the prior art can be seen as a waveform shown in red, with a transition time of 7.179 ps in the rising transition section.

[0108] On the other hand, the voltage mode logic circuit according to the disclosed invention can be confirmed to have a transition time of 5.669 ps in the falling transition section, as shown in the waveform in blue.

[0109] Therefore, it can be experimentally confirmed that the rising transition time of the voltage mode logic circuit according to the disclosed invention is improved compared to the conventional one.

[0110] Referring to Fig. 8, the voltage mode logic circuit according to the prior art can be seen as a waveform shown in red, with a transition time of 7.176 ps in the falling transition section.

[0111] On the other hand, the voltage mode logic circuit according to the disclosed invention can be confirmed to have a transition time of 5.669 ps in the falling transition section, as shown in the waveform in blue.

[0112] Therefore, it can be experimentally confirmed that the falling transition time of the voltage mode logic circuit according to the disclosed invention is improved compared to the conventional one.

[0113]

[0114] FIG. 9 is a diagram illustrating a voltage mode logic circuit with improved transition speed implemented in differential mode according to one embodiment of the disclosed invention. FIG. 10 is a diagram illustrating the voltage of each node when a step signal is applied to the voltage mode logic circuit illustrated in FIG. 9.

[0115] Referring to FIG. 9, a voltage mode logic circuit according to one embodiment of the disclosed invention can be implemented in differential mode.

[0116] More specifically, a voltage mode logic circuit according to one embodiment of the disclosed invention may be configured as a pair that is symmetrical to operate in a differential mode.

[0117] The specific components that constitute the voltage mode logic circuit are the same as those described in the description of Fig. 4, so their description will be omitted.

[0118] Referring to FIG. 10, a voltage mode logic circuit according to the disclosed invention operating in a differential mode can apply input voltages VINP and VINN from an input terminal (IN) to an inverter (100) in a differential manner.

[0119] More specifically, the output voltages VINPB and VINNB of each inverter (100) of the voltage mode logic circuit operating in differential mode according to the disclosed invention may have their transitions delayed by the delay time generated by the inverter (100) in the transition section.

[0120] Accordingly, the voltage mode logic circuit according to one embodiment of the disclosed invention has a technical effect in that current can be boosted through the inverter (100) and the auxiliary transistor and the transition time can be shortened even when operating in a differential mode.

[0121]

[0122] FIG. 11 is a diagram illustrating a voltage mode logic circuit with improved transition speed according to another embodiment of the disclosed invention. FIG. 12 is a diagram illustrating the voltage of each node during a rising transition when a step signal is applied to the voltage mode logic circuit illustrated in FIG. 11. FIG. 13 is a diagram illustrating the voltage of each node during a falling transition when a step signal is applied to the voltage mode logic circuit illustrated in FIG. 11.

[0123] Referring to FIG. 11, a voltage mode logic circuit with improved transition speed according to another embodiment of the disclosed invention can be implemented by utilizing a pulse generator instead of an inverter (100), unlike the voltage mode logic circuit according to one embodiment of the disclosed invention.

[0124] The configuration other than the pulse generator is the same as that of the voltage mode logic circuit according to one embodiment of the disclosed invention, and thus, a description thereof will be omitted.

[0125] A voltage mode logic circuit with improved transition speed according to another embodiment of the disclosed invention may include a plurality of pulse generators arranged between an input terminal (IN) and a gate node of a first auxiliary transistor (21) and between a gate node of a second auxiliary transistor (22).

[0126] The plurality of pulse generators may include a first pulse generator (210) and a second pulse generator (220).

[0127] For example, the first pulse generator (210) may be placed between the input terminal (IN) and the gate node of the first auxiliary transistor (21).

[0128] Additionally, a second pulse generator (220) may be placed between the input terminal (IN) and the gate node of the second auxiliary transistor (22).

[0129] As illustrated in FIGS. 12 and 13, a plurality of pulse generators can apply a pulse signal in a positive direction with respect to the ground in a rising transition section, and can apply a pulse signal in a negative direction with respect to the ground in a falling transition section.

[0130] Accordingly, a voltage mode logic circuit according to another embodiment of the disclosed invention can amplify and transmit the current applied to the input transistor during the transition of the input voltage by utilizing a pulse generator instead of an inverter (100).

[0131] A voltage mode logic circuit with improved transition speed according to one embodiment of the disclosed invention has the advantage of being able to shorten the transition time of the circuit by quickly controlling the flow of current using a delay inverter and an auxiliary transistor.

[0132] In addition, a voltage mode logic circuit with improved transition speed according to one embodiment of the disclosed invention can switch signals at a faster cycle due to a shortened transition time, thereby providing a driver circuit with reduced signal distortion and reduced data loss or errors.

[0133] In addition, a voltage mode logic circuit with improved transition speed according to one embodiment of the disclosed invention enables implementation of a high-speed transmitter in high-speed signal transmission, and has the advantage of improving overall system performance and signal accuracy.

[0134] In addition, the voltage mode logic circuit with improved transition speed according to one embodiment of the disclosed invention has the advantage of being usable in drive circuits in various application fields requiring high-speed operation where data transmission speed and reliability are important.

[0135] The devices described above may be implemented as hardware components, software components, and / or a combination of hardware components and software components. For example, the devices and components described in the embodiments may be implemented using one or more general-purpose computers or special-purpose computers, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable array (FPA), a programmable logic unit (PLU), a microprocessor, or any other device capable of executing instructions and responding to them. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. Furthermore, the processing device may access, store, manipulate, process, and generate data in response to the execution of the software. For ease of understanding, the processing device is sometimes described as being used singly; however, those skilled in the art will appreciate that the processing device may include multiple processing elements and / or multiple types of processing elements. For example, the processing device may include multiple processors, or one processor and one controller. Additionally, other processing configurations, such as parallel processors, are also possible.

[0136] Software may include a computer program, code, instructions, or a combination of one or more of these, which may configure a processing device to perform a desired operation or may independently or collectively command the processing device. The software and / or data may be embodied in any type of machine, component, physical device, virtual equipment, computer storage medium, or device for interpretation by the processing device or for providing instructions or data to the processing device. The software may also be distributed over networked computer systems and stored or executed in a distributed manner. The software and data may be stored on one or more computer-readable recording media.

[0137] The method according to the embodiment may be implemented in the form of program commands that can be executed through various computer means and recorded on a computer-readable medium. The computer-readable medium may include program commands, data files, data structures, etc., alone or in combination. The program commands recorded on the medium may be those specially designed and configured for the embodiment or may be those known and available to those skilled in the art of computer software. Examples of the computer-readable recording medium include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs and DVDs, magneto-optical media such as floptical disks, and hardware devices specially configured to store and execute program commands such as ROMs, RAMs, and flash memories. Examples of program commands include not only machine language codes such as those generated by a compiler, but also high-level language codes that can be executed by a computer using an interpreter, etc.

[0138] Although the embodiments have been described with limited examples and drawings, those skilled in the art will appreciate that various modifications and variations can be made based on the above teachings. For example, appropriate results can be achieved even if the described techniques are performed in a different order than described, and / or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents. Therefore, other implementations, other embodiments, and equivalents of the claims also fall within the scope of the claims described below.

Claims

1. A first transistor connected to the power supply; A second transistor connected to the first transistor; A third transistor connected to the second transistor; A fourth transistor connected to the third transistor; An input terminal connected to the gate nodes of the second transistor and the third transistor and to which an input voltage is applied; and characterized in that it includes an output terminal connected between the second transistor and the third transistor; Voltage mode logic circuit with improved transition speed.

2. In paragraph 1, a first auxiliary transistor connected between the first transistor and the second transistor; and characterized in that it further includes a second auxiliary transistor connected between the third transistor and the fourth transistor; Voltage mode logic circuit with improved transition speed.

3. In paragraph 2, characterized in that it further includes an inverter disposed between the input terminal and the gate node of the first auxiliary transistor and the gate node of the second auxiliary transistor; Voltage mode logic circuit with improved transition speed.

4. In paragraph 3, The inverter is characterized in that it is configured to delay the transition of the output voltage output from the inverter. Voltage mode logic circuit with improved transition speed.

5. In paragraph 2 Characterized in that the first auxiliary transistor and the second transistor are turned off during the delay time generated by the inverter in the rising transition section of the input voltage. Voltage mode logic circuit with improved transition speed.

6. In paragraph 2, The second auxiliary transistor is characterized in that it is turned on during the delay time generated by the inverter in the rising transition section of the input voltage. Voltage mode logic circuit with improved transition speed.

7. In paragraph 2, characterized in that it further comprises a plurality of pulse generators arranged between the input terminal and the gate node of the first auxiliary transistor and arranged between the gate node of the second auxiliary transistor; Voltage mode logic circuit with improved transition speed.

8. In paragraph 1, The first transistor and the second transistor are P-type transistors, and the third transistor and the fourth transistor are N-type transistors. Voltage mode logic circuit with improved transition speed.

9. In paragraph 1, It is characterized by further including an output resistor arranged between the output terminal and the second transistor and the third transistor; Voltage mode logic circuit with improved transition speed.

10. A first transistor connected to the power supply; A second transistor connected to the first transistor; A third transistor connected to the second transistor; A fourth transistor connected to the third transistor; An input terminal connected to the gate nodes of the second transistor and the third transistor and to which an input voltage is applied; A first auxiliary transistor connected between the first transistor and the second transistor; A second auxiliary transistor connected between the third transistor and the fourth transistor; and characterized in that it includes an inverter disposed between the input terminal and the gate node of the first auxiliary transistor and the gate node of the second auxiliary transistor; Voltage mode logic circuit with improved transition speed.

11. In paragraph 10, The inverter is characterized in that it is configured to delay the transition of the output voltage output from the inverter. Voltage mode logic circuit with improved transition speed.

12. In paragraph 11, Characterized in that the first auxiliary transistor and the second transistor are turned off during the delay time generated by the inverter in the rising transition section of the input voltage. Voltage mode logic circuit with improved transition speed.

13. In paragraph 10, The first transistor and the second transistor are P-type transistors, and the third transistor and the fourth transistor are N-type transistors. Voltage mode logic circuit with improved transition speed.

14. In paragraph 10, characterized in that it consists of a pair that are symmetrical to operate in the same mode, Voltage mode logic circuit with improved transition speed.

15. A first transistor connected to the power supply; A second transistor connected to the first transistor; A third transistor connected to the second transistor; A fourth transistor connected to the third transistor; An input terminal connected to the gate nodes of the second transistor and the third transistor and to which an input voltage is applied; A first auxiliary transistor connected between the first transistor and the second transistor; A second auxiliary transistor connected between the third transistor and the fourth transistor; and characterized in that it comprises a plurality of pulse generators arranged between the input terminal and the gate node of the first auxiliary transistor and arranged between the gate node of the second auxiliary transistor; Voltage mode logic circuit with improved transition speed.

Images