Redistribution layer (RDL) fanout package design & chiplet die-to-die interconnect routing

Abstract

Systems, methods, and methods of manufacture are described for implementing a packaging platform for an integrated circuit package. The packaging platform includes a first region that has: i) respective first portions of at least two semiconductor die and ii) a die-to-die interconnect coupling the at least two semiconductor die. The packaging platform includes a second region that surrounds the first region and has respective second portions that are distinct from the respective first portions of the first region. The packaging platform includes multiple redistribution layers (RDLs) that: i) interconnect the respective first portions of the at least two semiconductor die via a first set of conductive traces, and ii) interconnect the respective second portions of the at least two semiconductor die via a second set of conductive traces.

Description

REDISTRIBUTION LAYER (RDL) FANOUT PACKAGE DESIGN & CHIPLET DIE- TO-DIE INTERCONNECT ROUTINGBACKGROUND

[0001] This specification relates to packaging techniques for semiconductor circuit dies.

[0002] Integrated circuits can be produced using fan-out packaging techniques that implement device connectivity by redistributing connection terminals such that the device pins are fanned-out of the chip. Fanning out the terminals relative to the surface or periphery' of an integrated circuit chip allows for additional input / output (I / O) connections at the chip. The semiconductor and dielectric elements of the chip are embedded or encapsulated using epoxy mold compounds that generally form an example mold-frame. A redistribution layer (RDL) can be positioned adjacent or atop the mold-frame and solder balls may be positioned at the RDL to facilitate I / O connections via a ball-grid array (BGA) of pins that extend beyond a periphery- of the semiconductor die.

[0003] As noted above, the semiconductor is paired with a dielectric material, for example, to improve or enhance performance of the semiconductor. Generally, dielectric materials or films are used extensively in semiconductor technology for processes that include masking against a diffusion of dopants into semiconductors, fabricating active and passive components, and establishing electrical isolation between components. Dielectric materials have a corresponding dielectric constant, k. The dielectric constant of a substance or material is a measure of its ability to store electrical energy and indicates the extent to which a material holds or concentrates electric flux.SUMMARY

[0004] An integrated circuit package includes at least two distinct semiconductor die for establishing circuitry' of an system-on-chip (“SoC”), where the SoC can be used in an example computing device, such as a smartphone, tablet, or laptop. The respective circuitry of the two semiconductor die exchanges signal communications using a die-to-die interconnect defined based on an interconnect specification. The two semiconductor die are enclosed in an example integrated circuit package using fanout packaging technology7that includes multiple redistribution layers (RDLs). Each RDL can include a structured layout of metal traces, and corresponding insulating materials, that redistribute input / output (I / O) connections within the integrated circuit package.

[0005] In some implementations, the integrated circuit package includes five, 5, redistribution layers (RDLs), RDL1 - RDL5. In this implementation the signal communications routed along the metal traces of RDL5 are referenced to a power routing layer represented by RDL4. To achieve desired data rates, an additional RDL (RDL6) can be included as a ground reference layer. This additional RDL is inserted between RDL5 and an example under bump metallization (UBM) layer. The UBM layer facilitates signal connections between at least RDL5 and a ball grid array (BGA) of the integrated circuit package, where the BGA is used to connect the circuit package to a printed circuit board (PCB). The interconnect specification can include certain signal integrity requirements for signaling routed via the die-to-die interconnect.

[0006] Accordingly, in a first embodiment, techniques are described for implementing a Vss ground plane as a complimentary UBM structure that addresses or mitigates occurrences of degraded signal integrity from crosstalk emissions that result when high-speed signals are routed along conductors / traces of an RDL. For example, the Vss ground plane achieves these performance advantages without the expense of inserting additional RDLs as ground reference layers. The signal integrity requirements can include certain minimum threshold values for acceptable crosstalk (and / or signal loss) with reference to the desired data rate (e.g., 16 Gigabytes / sec (Gbps)). The respective threshold values can be calculated based on a voltage transfer function (VTF) in connection with a corresponding RC circuit. The Vss ground plane can be disposed at a bottom side of a RDL routing area as a complementary UBM structure of an integrated circuit package.

[0007] In a second embodiment, techniques are described for implementing an integrated chiplet & RDL packaging platform with a streamlined design configured for direct coupling to a printed circuit board. For example, the enhanced design permits direct coupling to a printed circuit board without requiring an intermediate substrate layer. The packaging platform includes at least two semiconductor die, e.g., a first die and a second die adjacent to the first die. Each of the first die and the second die includes a respective die-to-die interconnect region that facilitates I / O coupling and interconnection to an adjacent, neighboring die. For example, the die-to-die interconnect region of a first die facilitates input / output (I / O) coupling and interconnection to a second, different die, whereas the die-to- die interconnect region of the second die facilitates I / O coupling and interconnection to the first die.

[0008] Each of the first die and the second die also includes a respective on-die interconnect region that facilitates at least local on-die I / O coupling and interconnections to neighboring Intellectual Property ("IP") blocks within a given die. The die-to-die interconnect region can be described more generally as a first region (or portion) of a die, whereas the on-die interconnect region can be described more generally as a second region (or portion) of a die. The interconnects at the respective first region of the first and second die are provided via RDLs. Each RDL includes a structured layout of metal traces that distribute I / O connections between the first and second die as well as within an integrated circuit package. The RDLs have an interconnect density that is partitioned into distinct density regions corresponding to the first and second regions of a given die.

[0009] One aspect of the subject matter described in this specification can be embodied in a packaging platform for an integrated circuit package. The packaging platform includes a first semiconductor die and a second semiconductor die, where the first and second semiconductor die are disposed adjacent one another in a die-to-die configuration. The packaging platform includes multiple redistribution layers (RDLs), each of the multiple RDLs comprising a conductive trace having a first end in connection with the first semiconductor die and a second end in connection with the second semiconductor die. The packaging platform includes a Vss ground plane adjacent a particular RDL of the multiple RDLs. The Vss ground plane provides a ground path for dissipating crosstalk signals that are generated at the particular RDL of the multiple RDLs.

[0010] These and other implementations can each optionally include one or more of the following features. For example, in some implementations, the particular RDL is: i) furthest away from a top surface of the packaging platform that is co-planar with a top surface of the first and second semiconductor die, and ii) adjacent a bottom surface of the packaging platform that is opposite the top surface of the packaging platform. The particular RDL can be adjacent an RDL of the multiple RDLs that supplies power signals to each of the first and second semiconductor die. In some implementations, the Vss ground plane is configured as a reference plane that provides a return path for data signals routed along conductive traces of the particular RDL.

[0011] The Vss ground plane can be configured to mitigate adverse effects from the occurrence of crosstalk signal emissions when high-speed signals are routed between the first and second semiconductor die along conductive traces of the particular RDL. The multipleRDLs comprises a first side on which the first and second semiconductor die are disposed, and a second side opposite to the first side. And the Vss ground plane can be disposed on the second side. The packaging platform further includes at least one Vss solder connection point directly attached to the Vss ground plane. The at least one Vss solder connection point can be configured to facilitate solder connect! on(s) between the Vss ground plane and a printed circuit board (PCB). In some implementations, the Vss ground plane is also configured as an under-bump metallization (UBM) structure of the integrated circuit package. The Vss ground plane can have a smaller dimension than the multiple RDLs along a surface of the multiple RDLs.

[0012] In some implementations, the i) the multiple RDLs are disposed at a die-to-die interconnect routing area for coupling the first and second semiconductor die to each other; ii) the conductive traces of the multiple RDLs are arranged in the die-to-die interconnect routing area; and iii) the Vss ground plane is arranged underneath the die-to-die interconnect routing area. A dimension of the Vss ground plane can correspond substantially to a dimension of the die-to-die interconnect routing area.

[0013] The packaging platform can also have a die-to-die interconnect region that includes: i) a first die-to-die interconnect of the first semiconductor die; ii) a second die-to- die interconnect of the second semiconductor die; and iii) the die-to-die interconnect routing area of the multiple RDLs. A dimension of the Vss ground plane can correspond substantially to a dimension of the die-to-die interconnect region, and / or a dimension of the first and second die-to-die interconnects. The packaging platform can include a UBM layer at a bottom surface of the packaging platform, where the UBM layer can substantially surround the Vss ground plane. In some implementations, the UBM layer is co-planar with the Vss ground plane.

[0014] Another aspect of the subject matter described in this specification can be embodied in an apparatus that includes a first region comprising: i) respective first portions of at least two semiconductor die, and ii) a die-to-die interconnect that couples the at least two semiconductor die. The apparatus includes a second region that surrounds the first region, where the second region includes respective second portions of the at least two semiconductor die that are distinct from the respective first portions. The apparatus includes multiple redistribution layers (RDLs) that: i) interconnects the respective first portions of the at least two semiconductor die via a first set of conductive traces, and ii) interconnects therespective second portions of the at least two semiconductor die via a second set of conductive traces.

[0015] These and other implementations can each optionally include one or more of the following features. For example, in some implementations, the apparatus further includes multiple first connection pillars configured to facilitate solder connections between the apparatus and an item that connects to the apparatus. The apparatus can be configured for direct mounting to a printed circuit board (PCB) via the multiple first connection pillars. The multiple first connection pillars include a ball grid array (BGA). In some implementations, the at least two semiconductor die disposed adjacent one another in a die-to-die configuration. An interconnect density of the multiple RDLs can be partitioned into distinct density regions that correspond to the first region and the second region.

[0016] In some implementations, a first density region of the multiple RDLs includes a first interconnect density corresponding to the first set of conductive traces, and ii) a second density region of the multiple RDLs includes a second, different interconnect density corresponding to the second set of conductive traces. The first interconnect density can be a higher interconnect density than the second interconnect density. The interconnect density can be defined based at least on: i) a width of a conductive trace that represents an interconnection path and ii) a spacing between two or more conductive traces. In some implementations, the first density region includes a first interconnect pitch, the second density region includes a second, different interconnect pitch, and the first interconnect pitch can be less than the second interconnect pitch. The first interconnect pitch can be 45 micrometers (pm), whereas the second interconnect pitch can be 110 pm.

[0017] The apparatus can further include a power delivery' network collocated with the first region. The power delivery network can include multiple second connection pillars and a micro-bump pitch that defines a spacing between two or more of the multiple second connection pillars. The die-to-die interconnect can be a universal package-level interconnect routing configuration based on open standard. The die-to-die interconnect can be a universal package-level interconnect routing configuration based on the Universal Chiplet Interconnect Express (UCIe) standard.

[0018] Another aspect of the subject matter described in this specification can be embodied in a packaging platform for an integrated circuit package. The packaging platform includes a first interconnect region comprising die-to-die interconnections; a second, differentinterconnect region comprising interconnections to a memory device of the integrated circuit package; and multiple redistribution layers (RDLs) that include: i) conductive traces for the die-to-die interconnections of the first interconnect region, and ii) conductive traces for the interconnections of the second interconnect region. These and other implementations can each optionally include one or more of the following features. For example, in some implementations, the packaging platform includes a ball grid array (BGA) configured to facilitate multiple solder connections between the packaging platform and a printed circuit board.

[0019] Any of the features included in the examples corresponding to the embodiments and aspects described above may be similarly applied to, or combined with, other examples corresponding to any of the other embodiments and aspects disclosed herein.

[0020] Other implementations of this and other aspects include corresponding systems, apparatus, and computer programs, configured to perform the actions of the methods, encoded on computer storage devices. A system of one or more computers can be so configured by virtue of software, firmware, hardware, or a combination of them installed on the system that in operation causes the system to perform the actions. One or more computer programs can be so configured by virtue of having instructions that, when executed by a data processing apparatus, cause the apparatus to perform the actions.

[0021] The details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other potential features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Fig. 1 illustrates a cross-sectional view of an example RDL packaging platform for an integrated circuit package.

[0023] Fig. 2 is a block diagram showing a top-down view of an example RDL packaging platform for an integrated circuit package.

[0024] Fig. 3 illustrates an example circuit for calculating a voltage-transfer-function (VTF) and associated channel characteristics for VTF loss and VTF crosstalk.

[0025] Fig. 4 illustrates example graphical information and data tables representing certain signal integrity requirements for an integrated circuit.

[0026] Fig. 5 illustrates a bottom view of an example BGA UBM layer of a RDL packaging platform.

[0027] Fig. 6A is a first portion of an example process or method of making a Vss ground plane based on a process associated with under bump metallization structures.

[0028] Fig. 6B is a second portion of an example process or method of making a Vss ground plane based on a process associated with under bump metallization structures.

[0029] Fig. 7 illustrates an example RDL fanout package design for chiplets with die-to- die interconnect.

[0030] Fig. 8 illustrates an example interconnect region with die-to-die interconnections.

[0031] Fig. 9 is an example table that shows trace width and spacing for different RDLs.

[0032] Like reference numbers and designations in the various drawings indicate like elements.DETAILED DESCRIPTION

[0033] Fig. 1 illustrates a cross-sectional view of an example RDL packaging platform 100 (“packaging platform 100”) for an integrated circuit package. The packaging platform 100 can be included in, or even representative of, an example fan-out w afer-level package (FOWLP) in which semiconductor dies are stacked and interconnected vertically within an example integrated circuit package. The semiconductor die can be silicon or bulk silicon, however other semiconductor materials or w afers can be used, such as germanium, selenium, gallium, etc.

[0034] In the example of Fig. 1, the packaging platform 100 includes a device 102 that has at least two semiconductor die 104, 106. The device 102 is a System-on-Chip (“SoC”) formed from one or more semiconductor die. In some implementations, a first semiconductor die 104 and a second semiconductor die 106 are respective hardware circuits that form or represent a single SoC. In some other implementations, the first semiconductor die 104 and the second semiconductor die 106 are respective hardware circuits that represent different SoCs, such as SoC-1 and SoC-2, respectively.

[0035] The semiconductor die 104, 106 are used to establish respective portions of circuitry of the SoC device (“SoC 102”). The SoC 102 can be used in an example computing device, such as a smartphone, tablet, or laptop. The packaging platform 100 includes a die- to-die (D2D) connectivity region 108 where respective circuitry of the distinct semiconductordie 104, 106 exchange signal communications using a die-to-die interconnect 110-1, 110-2 within the die-to-die (D2D) region 108. Therefore, the semiconductor die 104. 106 are disposed adjacent to one another in a die-to-die configuration (e.g., a die-to-die interconnected configuration).

[0036] Each of the die-to-die interconnects 110-1, 110-2 can be based on an interconnect specification or standard. For example, the interconnect standard is an open industry standard such as the Universal Chiplet Interconnect Express (UCIe) standard that establishes a universal interconnect at the package-level at least by defining technical details of the interconnect betw een chiplets within a package, such as chiplets corresponding to semiconductor die 104, 106. Other interconnect standards or specifications (e.g., open or proprietary) are also within the scope of this disclosure.UBM Structure for Chiplet Die-To-Die Routing in RDL Fanout Package Design

[0037] The packaging platform 100 includes multiple RDLs 112. Each RDL can include a structured layout of metal traces, as well as corresponding insulating materials. In some implementations, the RDLs 112. the semiconductor die 104, 106, or both, can be encapsulated in a mold portion. For example, the packaging platform 100 can include a mold portion such as an epoxy-molding compound that surrounds, embeds, or encapsulates at least the RDLs 112, and any associated dielectric layers. The example mold portion and the RDLs 112 can form an RDL structure of the packaging platform 100.

[0038] In the example of Fig. 1, the example RDL structure of the packaging platform 100 includes five RDLs, RDL1 - RDL5. In this example, RDL2 is a ground reference layer, whereas RDL1, RDL3, and RDL5 are configured for routing signal communications between semiconductor dies 104, 106. For example, metal traces of RDL1 are used to route KK signals, metal traces of RDL3 are used to route MM signals. and metal traces of RDL5 are used to route NN signals. Each of KK, MM, NN are integers greater than 1. For example, RDL1 can route 55 signals (KK = 55), RDL3 can route 55 signals (MM = 55), and RDL5 can route 46 signals (NN = 46).

[0039] In prior approaches to RDL structures for die-to-die interconnects between chiplets, the signals routed along the metal traces of RDL 118 (RDL5) are referenced to a power routing layer represented by RDL4. These prior approaches lacked an effective ground reference layer that provides a reliable return path for crosstalk signal emissions that are generated when high-speed signal communications traverse the metal traces of RDL5.

[0040] In general, RDLs redistribute input / output (I / O) connections within the integrated circuit package. The RDLs in the region of 118 are configured to provide high interconnection density, whereas elsewhere in the packaging platform 100 has lower interconnection density. This also applies to other layers of RDLs 112, relative to elsewhere in the packaging platform 100. The higher interconnect density in region 118 is provided byleveraging an RDL routing that allows for compact inter-chip connections between semiconductor dies 104. 106. The disclosed techniques address deficiencies in the prior approaches by providing a cost-effective method of integrating a unique Vss ground plane 120, with corresponding Vss solder connection points 122, 124. The Vss plane 120 is configured as a ground reference layer that provides a robust signal return path for dissipating crosstalk emissions at RDL 5. In the present disclosure, the term “Vss ground plane’" may also be referred to as a “ground plane” or “ground reference layer.”

[0041] Thus, the Vss ground plane 120 can be used to achieve desired transmission frequency and data rates by mitigating the occurrence of VTF crosstalk that degrades the signal integrity at RDL5. Notably, the disclosed techniques and Vss ground plane 120 can be leveraged to achieve these performance advantages without the expensive costs of adding or inserting an additional ground reference RDL between RDL5 and an example under bump metallization (UBM) layer. Notably, the disclosed techniques are not limited to fan-out package designs that have five RDLs. The described techniques of implementing a Vss ground plane as a complimentary UBM structure can be used in package designs with any RDL count, to provide a cost-effective, robust ground reference layer without increasing the number of RDLs in the design.

[0042] The semiconductor die 104, 106 can be enclosed in an example integrated circuit package using fanout packaging technology that includes at least one redistribution layer (RDL). In some implementations, an exemplary FOWLP that incorporates packaging platform 100 can include one or more RDLs 112 (or interposers) that are larger than the die as well as fan-out interconnect vias that allow for high-density interconnects. This semiconductor manufacturing approach can be used to incorporate large arrays of semiconductor die in an integrated circuit package by housing multiple die using a stacked configuration within fan-out wafer level chip scale packages (WLCSP).

[0043] Fig. 2 is a block diagram showing a top-down view of an example RDL packaging structure 200 for an integrated circuit package.

[0044] The implementation of Fig. 2 includes example dimensional values that can be used to manufacture a packaging platform 100 based on the disclosed techniques. In some implementations, the structure 200 corresponds to the packaging platform 100 described above with reference to Fig. 1. In some other implementations, the structure 200 is a subfeature of the packaging platform 100, such as a sub-feature that indicates an outline or structure of the RDL portion of the packaging platform 100.

[0045] Each die-to-die interconnect 110-1, 110-2 includes a respective transmitter (Tx) and receiver (Rx), which can correspond to the Universal Chiplet Interconnect Express Advanced (UCIeA) industry standard architecture 202. The Tx / Rx architecture 202 can include 64 signal Tx pins and 64 signal Rx pins, based on the five RDLs, to facilitate an x64 UCIe die-to-die interconnect routing scheme. In some implementations, when additional clocks and other signal redundancies are accounted for the Tx / Rx architecture 202 can reflect a total of 74 pins. The RDL packaging platform can include a power delivery network 204 that is collocated with the die-to-die interconnect 110-1, 110-2.

[0046] Fig. 3 illustrates an example circuits 302, 304 for calculating a voltage-transfer- function (VTF) and an associated data table 306 that indicates channel characteristics for VTF loss and VTF crosstalk with reference to signal communications at one or more of RDL1, RDL3, and RDL5. As discussed above, each of the die-to-die interconnects 110-1, 110-2 can be based on an interconnect specification or standard. The interconnect specification can include certain signal integrity requirements for signals communications routed via the die-to-die interconnect. Fig. 4 illustrates example graphical information 402 and data tables 404 representing certain signal integrity requirements for an integrated circuit that includes the semiconductor dies 104, 106 the corresponding die-to-die interconnect 110- 1, 110-2.

[0047] Fig. 5 illustrates a bottom view of an example BGA UBM layer 502 of a RDL packaging platform 100, 200. As discussed above, to achieve desired data rates, a unique, small metal ground plane 504 can be included as an efficient and low-cost ground reference layer at a bottom side of an RDL structure 200 in the packaging platform 100. More specifically, the small metal plane 504 can be inserted at a UBM layer underneath (or at the bottom of) a die-to-die interconnect routing area of the RDL structure 200.

[0048] In some implementations, the small metal plane 504 can have a dimensionality that corresponds substantially to the dimensions of the die-to-die interconnect region 108, andmore specifically, to the die-to-die interconnect 110-1, 110-2. The expression ‘‘corresponds substantially to" is intended to mean that a dimensionality’ of the small metal plane 504 is within a range of 100% ± about 25% of the dimensions of the die-to-die interconnect region 108 and / or the die-to-die interconnect 110-1, 110-2.

[0049] The UBM layer 502 facilitates signal connections between at least RDL5 and a ball grid array (BGA) of the integrated circuit package. The BGA includes a grid of pins that are used to connect the BGA circuit package to a printed circuit board (PCB). In some implementations, the metal plane is a Vss ground plane 120 that is connected to a ground of the UBM / BGA layer of the packaging platform 100 to provide a robust return path for highspeed signals that are routed along metal traces of RDL5. The unique, metal plane is an extremely low-cost alternative to the more expensive manufacturing processes that would otherwise be required to include an additional RDL inserted between RDL5 and an example under bump metallization layer. With reference to the example of Fig. 5, the UBM layer 502 can be designed or configured to substantially surround the metal plane 504. In some examples the metal plane 504 may be coplanar with the UBM layer 502.

[0050] As indicated above, the packaging platform 100 can represent a portion of an integrated circuit that is configured for mounting on a printed circuit board (“PCB”) of an electronic or consumer device, such as a smartphone, laptop, tablet, notebook, smart speaker, network server, or gaming device. For example, the packaging platform 100 can include a bottom BGA layer that facilitates mounting the integrated circuit package on the PCB.

[0051] In some implementations, the packaging platform 100 can include multiple fanout interconnect vias, and respective sets of solder balls connections. The fan-out interconnect vias and solder ball connections cooperate to provide electrical interconnections between the device 102, a package that encloses or encapsulates device 102, and a corresponding I / O device within the package (e.g., a DRAM memory device). The fan-out interconnect vias and solder ball connections also cooperate to provide electrical interconnections betw een the device 102 and an example PCB where the packaging platform 100 is ultimately mounted or soldered for installation in an example consumer device.

[0052] In some implementations, an integrated circuit package that incorporates packaging platform 100 is an integrated fan-out package-on-package design that features a high density RDL and fan-out interconnect vias that allow' for a stacked die configuration. The stacked configuration can integrate a memory circuit and an SoC (e.g., semiconductordies 104, 106) for use in certain mobile or edge computing applications. In some implementations, the memory circuit is a random access memory (RAM) circuit, such as a static or dynamic RAM (e.g., DRAM or SRAM).

[0053] Fig. 6A is a first portion of an example process 600 or method of making a Vss ground plane based on a process associated with under bump metallization structures. Fig. 6B is a second portion of the process 600 for making a Vss ground plane based on a process associated with under bump metallization structures. In the example of Fig. 6A the first portion of process 600 is identified as process 600A, whereas in the example of Fig. 6B, the second portion of process 600 is identified as process 600B.

[0054] Each of process 600A, 600B can be implemented or executed using an example computing system described herein. In some examples, the steps or actions of process 600 A, 600B are enabled by programmed software instructions, firmware instructions, or both. Each type of instruction may be stored in a non-transitory machine-readable storage device and is executable by one or more processors or other computing resources described in this specification.

[0055] In some implementations, one or more steps of process 600 A. 600B can be performed using a hardware integrated circuit that implements machine-learning (ML) models. A portion of the integrated circuit can include a special-purpose processor, such as a neural network processor or hardw are ML accelerator configured to accelerate computations for generating different types of data processing outputs that are associated with manufacturing processes or methods for making an example semiconductor device.

[0056] Process 600A includes UBM exposure steps (604) and (610) that are performed using photoresist, PR, 606. Process 600A also includes a UBM copper (Cu) plating step (612) followed by a UBM stripping step, where the PR 606 is stripped away while using the Cu plating as a blocker. Example top views 602, 616 illustrate additional aspects of process 600A.

[0057] Process 600B includes UBM seed layer wet etching step (624) and a BGA ball mount step (626), where balls (or pins) of a grid array are mounted onto a Cu layer. For example, the balls (or pins) of the grid array are mounted onto the Cu layer using a stencil that outlines the grid array pattern. The BGA ball mount step (626) is followed by an example reflow^ operation (628), for example, to enhance the structural and electrical connection between the BGA balls and Cu layer, including the INFO RDL layers as well.Example top view 630 illustrates additional aspects of process 600B and provides an alternative illustration of the Vss ground plane 120.

[0058] In some implementations, the design of an RDL structure 200 may have a layer count constraint of five layers (RDL1-RDL5), where die-to-die signal routings are assigned to RDL1 / RDL3 / RDL5, power (PWR) routing is assigned to RDL4, and a ground (GND) reference routing is assigned to RDL2. Communication signals routed along metal traces of the RDL5 can also lack an appropriate ground reference layer that provides a robust return path. Accordingly, the disclosed techniques can be used to ensure that signal interconnections between semiconductor die 104, 106 that traverse traces of RDL5 at a desired data rate (e.g., 16 Gbps) can also meet or satisfy, for example, the UCIe spec signal quality requirements.

[0059] Rather than insert an additional RDL layer (RDL6) as a ground reference layer between RDL5 and a UBM layer, which would violate the five-layer constraint, the disclosed techniques can be used to insert a robust VSS ground plane 120. More specifically, the five- layer constraint, RDL die-to-die interconnect signal, and power / ground routing layer assignments can be maintained. And. as discussed above, the UBM layer / pad process can be effectively and efficiently utilized to create a small, robust Vss ground plane 120 on a bottom surface (e.g., underneath) of a RDL routing area of the packaging platform 100.RDL Fanout Package Design for Chiplets with Die-to-Die Interconnect

[0060] Fig. 7 illustrates an example package design of an RDL fanout package for chiplets with die-to-die interconnect. The package design is for a packaging platform 700, which can be used as an integrated circuit package. In some implementations, the packaging platform 700 is an integrated chiplet & RDL platform 700. Relative to prior RDL design approaches, the integrated chiplet & RDL platform 700 includes a streamlined design configured for direct coupling to a printed circuit board. For example, the enhanced design permits direct coupling to a printed circuit board without requiring an intermediate substrate layer.

[0061] The packaging platform 700 can include at least two semiconductor die, e.g., a first die 104 and a second die 106 adjacent to the first die 104. Each of the first die 104 and the second die 106 includes a respective die-to-die interconnect region 702 that facilitates I / O coupling and interconnection to an adjacent, neighboring die. For example, the die-to-die interconnect region 702 of a first die 104 facilitates input / output (I / O) coupling andinterconnection to a second, different die 106, whereas the die-to-die interconnect region 702 of the second die 106 facilitates I / O coupling and interconnection to the first die 104.

[0062] Each of the first die and the second die also includes a respective on-die interconnect region 704 that facilitates at least local on-die I / O coupling and interconnections to neighboring Intellectual Property7(“IP”) blocks within a given die 104, 106. The die-to-die interconnect region 702 can be described more generally as a first region (or portion) 702 of a die. whereas the on-die interconnect region 704 can be described more generally as a second region (or portion) 704 of a die.

[0063] For example, the on-die interconnect region 704 of first die 104 can include one or more IP blocks, such as an image signal processor (ISP), a digital signal processor (DSP), or even an ML hardware accelerator. Relatedly, the on-die interconnect region 708 of second die 106 can be similarly configured. In this example, the ISP and ML accelerator can represent neighboring IP blocks and the local on-die I / O coupling and interconnections of region 704 enables signal and data communications between the ISP and ML accelerator, as well as between other neighboring IP blocks.

[0064] In some implementations, an example IP block is a memory device (e.g., DRAM) and, relative to die-to-die interconnect region 702, the on-die interconnect region 704 represents a second, different interconnect region that includes interconnections to the memory device. For example, the memory device may be included in an integrated circuit package with other IP blocks or devices. In this implementation, the RDL includes conductive traces for the interconnections of the second, different interconnect region. For example, the memory device can exchange data and signal communications with a neighboring IP block (e.g., an ISP or ML accelerator) via conductive traces of the RDLs.

[0065] In this manner, the packaging platform 700 includes a first region 702 that has: i) respective first portions 706 of at least two semiconductor die and ii) a die-to-die interconnect coupling the at least two semiconductor die. The die-to-die interconnect may be included within the first portions 706. The die-to-die interconnect may be similar to the die-to-die interconnect 110-1, 110-2 as described above. The packaging platform includes a second region 704 that surrounds the first region 702 and has respective second portions 708 that are distinct from the respective first portions 706 of the first region 702. The at least two semiconductor die (e.g., the first die 104 and the second die 106) may comprise the first region 702 and the second region 704. In some implementations, each of the first and seconddie 104, 106 comprises a respective first region 702 and a respective second region 704. The packaging platform includes multiple redistribution layers (RDLs) 710 that: i) interconnect the respective first portions 706 of the at least two semiconductor die via a first set of conductive traces, and ii) interconnect the respective second portions 708 of the at least two semiconductor die via a second set of conductive traces. The RDLs 710 may include some or all the features of the RDLs 112 as described herein.

[0066] The integrated chiplet & RDL platform 700 includes multiple connection pillars configured to facilitate solder connections between the integrated chiplet & RDL platform 700 and an item that connects to the platform 700. The packaging platform 700 includes a ball grid array (BGA) 718 configured to facilitate solder connections between the packaging platform 700 and a printed circuit board. In some implementations, the BGA 718, including other connection pillars, are configured to facilitate direct mounting of the packaging platform 700 to an item such as a printed circuit board. The BGA 718 is an example of the connection pillars. The connection pillars disclosed in this specification can be copper (Cu) pillars that represent connection terminals of an integrated circuit.

[0067] Fig. 8 illustrates an example interconnect region with die-to-die interconnections.

[0068] As described above, each of the first die and the second die includes a respective die-to-die interconnect region that facilitates I / O coupling and interconnection to an adjacent, neighboring die. In some implementations, the at least two semiconductor die 104, 106 are disposed adjacent one another in a die-to-die configuration. The die-to-die configuration may be a die-to-die interconnected configuration. As discussed above, the interconnects at the respective first region 702 of the first and second die 104, 106 are provided via RDLs 710 (Fig. 7). Each RDL 710 includes a structured layout of metal traces 118 that distribute I / O connections between the first and second die as well as within an integrated circuit package.

[0069] The RDLs 710 have an interconnect density that is partitioned into distinct density regions 714, 716 corresponding to the first and second regions of a given die. A first density region 714 of the RDLs includes a first interconnect density corresponding to (a density of) the first set of conductive traces, a second density region 716 of the RDLs includes a second, different interconnect density corresponding to (a density of) the second set of conductive traces. The first interconnect density is a higher interconnect density than the second interconnect density. In some implementations, the first interconnect density represents theinterconnect density of the die-to-die interconnect region 702, whereas the second interconnect density represents the interconnect density of the on-die interconnect region 704.

[0070] In some implementations, the interconnect pitch or bump density of the die-to-die interconnect region 702 can be much denser than the pitch or bump density of the on-die interconnect region 704. As shown in the example table of Fig. 9, the line width and spacing of conductive traces in the die-to-die interconnect region 714 can be 2pm (line width) / 2pm (spacing), whereas the line width and spacing of conductive traces in the on-die interconnect region 716 can be 5pm / 8pm or 10pm / 10pm. Other line width and spacing options for conductive traces in both regions are also w ithin the scope of this disclosure. The 2pm line width of conductive traces in the die-to-die interconnect region 714 can provide higher current density relative to smaller trace widths.

[0071] In some implementations, the first density region 702 includes a first interconnect pitch 802 (Fig. 8) that generally defines a spacing between connection pillars of the die-to-die interconnect region. The connection pillars of the die-to-die interconnect region 702 are for electrically connecting the respective first portions 706 of at least two semiconductor die to the first density region 714 of the RDLs. Relatedly, the second density region 704 includes a second interconnect pitch 720 (Fig. 7) that generally defines a spacing between connection pillars of the on-die interconnect region. With reference to Fig. 7, the connection pillars of the on-die interconnect region 704 are for electrically connecting the second portions 708 of at least two semiconductor die to the second density region 716 of the RDLs 710. In this implementation, the first interconnect pitch 802 is less than the second interconnect pitch 720. In the example of Fig. 8, the first interconnect pitch is 45pm, whereas the second interconnect pitch is 110 pm. These are example values and other pitch values are within the scope of this disclosure.

[0072] Fig. 9 is an example table 900 that shows trace width and spacing for different RDLs. The trace width (W) and spacing (S) data of table 900 are descriptive of the interconnect density7. For example, the interconnect density is defined based at least on i) a width of a conductive trace that represents an interconnection path and ii) a spacing between two or more of those conductive traces.

[0073] In the example of Fig. 9, data / values for trace width, W, and spacing, S, in table 900 are indicated by the descriptor “Min. Line W / S (pm).” These example minimum line width and spacing values are identified with reference to corresponding pitch values of 45pm (P45) for the die-to-die interconnect region 702 and 110 gm (Pl 10) for the on-die interconnect region 704. In some implementations, the P45 pitch value represents a microbump pitch 902, corresponding to higher interconnect density, whereas the Pl 10 pitch value represents a more standard bump pitch 904, corresponding to a less dense interconnect region.

[0074] Additionally, as described above with reference to Fig. 2, the RDL packaging platform can include a power delivery network 204 that is collocated with the die-to-die interconnect region 702. The power delivery network 204 includes multiple connection pillars and a corresponding micro-bump pitch 902 that defines a spacing between two or more of the multiple connection pillars. It would be understood that the multiple connection pillars may be for electrically connecting the power delivery network 204 to the RDLs 710 (e.g., the first density region 714 of the RDLs 710). The micro-bump pitch of the power delivery network can be based on a pitch of the connection pillars of the die-to-die interconnect region 702.

[0075] Embodiments of the subject matter and the functional operations described in this specification can be implemented in digital electronic circuitry, in tangibly-embodied computer software or firmware, in computer hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible non-transitory program carrier for execution by, or to control the operation of, data processing apparatus. These embodiments can include processes and methods of making or manufacturing a semiconductor device, a wafer-level package, packaging platform, or package structures / features described in this specification.

[0076] Alternatively, or in addition, the program instructions can be encoded on an artificially generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode information for transmission to suitable receiver apparatus for execution by a data processing apparatus. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them.

[0077] The term “computing system” encompasses all kinds of apparatus, devices, and machines for processing data, including by way of example a programmable processor, acomputer, or multiple processors or computers. The apparatus can include special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit). The apparatus can also include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0078] A computer program (which may also be referred to or described as a program, software, a software application, a module, a software module, a script, or code) can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0079] A computer program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data, e.g., one or more scripts stored in a markup language document, in a single file dedicated to the program in question, or in multiple coordinated files, e.g., files that store one or more modules, sub programs, or portions of code. A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.

[0080] The processes and logic flows described in this specification can be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array), an ASIC (application specific integrated circuit), or a GPGPU (General purpose graphics processing unit).

[0081] Computers suitable for the execution of a computer program include, by way of example, can be based on general or special purpose microprocessors or both, or any other kind of central processing unit. Generally, a central processing unit will receive instructions and data from a read only memory or a random access memory or both. Some elements of a computer are a central processing unit for performing or executing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one ormore mass storage devices for storing data, e.g., magnetic, magneto optical disks, or optical disks. However, a computer need not have such devices. Moreover, a computer can be embedded in another device, e.g., a mobile telephone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a Global Positioning System (GPS) receiver, or a portable storage device, e.g., a universal serial bus (USB) flash drive, to name just a few.

[0082] Computer readable media suitable for storing computer program instructions and data include all forms of nonvolatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto optical disks; and CD ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0083] To provide for interaction with a user, embodiments of the subject matter described in this specification can be implemented on a computer having a display device, e.g., LCD (liquid cry stal display ) monitor, for display ing information to the user and a keyboard and a pointing device, e.g., a mouse or a trackball, by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback, e.g., visual feedback, auditory7feedback, or tactile feedback; and input from the user can be received in any form, including acoustic, speech, or tactile input. In addition, a computer can interact with a user by sending documents to and receiving documents from a device that is used by the user; for example, by sending web pages to a web browser on a user’s client device in response to requests received from the web browser.

[0084] Embodiments of the subject matter described in this specification can be implemented in a computing system that includes a back end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front end component, e.g., a client computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the subject matter described in this specification, or any combination of one or more such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication, e.g., a communication network.Examples of communication networks include a local area network (“LAN”) and a wide area network (“WAN”), e.g., the Internet.

[0085] The computing system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other.

[0086] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

[0087] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0088] Particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.

Claims

What is claimed is:

1. A packaging platform for an integrated circuit package, the packaging platform comprising: a first semiconductor die and a second semiconductor die. wherein the first and second semiconductor die are disposed adjacent one another in a die-to-die configuration; a plurality' of redistribution layers (RDLs), each of the plurality of RDLs comprising a conductive trace having a first end in connection with the first semiconductor die and a second end in connection with the second semiconductor die; and a Vss ground plane adjacent a particular RDL of the plurality of RDLs, wherein the Vss ground plane provides a ground path for dissipating crosstalk signals that are generated at the particular RDL of the plurality of RDLs.

2. The packaging platform of claim 1, wherein the particular RDL is: i) furthest away from a top surface of the packaging platform that is co-planar with a top surface of the first and second semiconductor die, and ii) adjacent a bottom surface of the packaging platform that is opposite the top surface of the packaging platform.

3. The packaging platform of claim 1 or 2, wherein the particular RDL is adjacent an RDL of the plurality of RDLs that supplies power signals to each of the first and second semiconductor die.

4. The packaging platform of any preceding claim, wherein the Vss ground plane is configured as a reference plane that provides a return path for data signals routed along conductive traces of the particular RDL.

5. The packaging platform of any preceding claim, wherein: the Vss ground plane is configured to mitigate adverse effects from the occurrence of crosstalk signal emissions when high-speed signals are routed between the first and second semiconductor die along conductive traces of the particular RDL.

6. The packaging platform of any preceding claim, wherein the plurality of RDLs comprises a first side on which the first and second semiconductor die are disposed, and a second side opposite to the first side, and wherein the Vss ground plane is disposed on the second side.

7. The packaging platform of any preceding claim, further comprising at least one Vss solder connection point directly attached to the Vss ground plane.

8. The packaging platform of claim 7, wherein the at least one Vss solder connection point is configured to facilitate solder connection(s) between the Vss ground plane and a printed circuit board (PCB).

9. The packaging platform of any preceding claim, wherein the Vss ground plane is also configured as an under-bump metallization (UBM) structure of the integrated circuit package.

10. The packaging platform of any preceding claim, wherein the Vss ground plane has a smaller dimension than the plurality of RDLs along a surface of the plurality of RDLs.

11. The packaging platform of any preceding claim, wherein: i) the plurality of RDLs are disposed at a die-to-die interconnect routing area for coupling the first and second semiconductor die to each other; ii) the conductive traces of the plurality of RDLs are arranged in the die-to-die interconnect routing area; and iii) the Vss ground plane is arranged underneath the die-to-die interconnect routing area.

12. The packaging platform of claim 11, wherein a dimension of the Vss ground plane corresponds substantially to a dimension of the die-to-die interconnect routing area.

13. The packaging platform of claim 11 or 12, further comprising a die-to-die interconnect region comprising: i) a first die-to-die interconnect of the first semiconductor die:ii) a second die-to-die interconnect of the second semiconductor die; and iii) the die-to-die interconnect routing area of the plurality of RDLs.

14. The packaging platform of claim 13, wherein a dimension of the Vss ground plane corresponds substantially to a dimension of the die-to-die interconnect region, and / or a dimension of the first and second die-to-die interconnects.

15. The packaging platform of any preceding claim, further comprising: a UBM layer at a bottom surface of the packaging platform, wherein the UBM layer substantially surrounds the Vss ground plane.

16. The packaging platform of claim 15, wherein the UBM layer is co-planar with the Vss ground plane.

17. An apparatus comprising: a first region compnsing: i) respective first portions of at least two semiconductor die, and ii) a die-to-die interconnect that couples the at least two semiconductor die; a second region that surrounds the first region, the second region comprising respective second portions of the at least two semiconductor die that are distinct from the respective first portions; a pl urality of redistribution layers (RDLs) that: i) interconnects the respective first portions of the at least two semiconductor die via a first set of conductive traces, and ii) interconnects the respective second portions of the at least two semiconductor die via a second set of conductive traces.

18. The apparatus of claim 17, further comprising: a plurality of first connection pillars configured to facilitate solder connections between the apparatus and an item that connects to the apparatus.

19. The apparatus of claim 18, wherein the apparatus is configured for direct mounting to a printed circuit board (PCB) via the plurality of first connection pillars.

20. The apparatus of claim 18 or 19, wherein the plurality of first connection pillars comprise a ball grid array (BGA).

21. The apparatus of any one of claims 17 to 20. wherein the at least two semiconductor die are disposed adjacent one another in a die-to-die configuration.

22. The apparatus of any one of claims 17 to 21, wherein an interconnect density of the plurality of RDLs is partitioned into distinct density regions that correspond to the first region and the second region.

23. The apparatus of claim 22, wherein: i) a first density region of the plurality of RDLs comprises a first interconnect density corresponding to the first set of conductive traces, and ii) a second density' region of the plurality of RDLs comprises a second, different interconnect density corresponding to the second set of conductive traces.

24. The apparatus of claim 23. wherein the first interconnect density is a higher interconnect density than the second interconnect density.

25. The apparatus of any one of claims 22 to 24. wherein interconnect density is defined based at least on: i) a width of a conductive trace that represents an interconnection path and ii) a spacing between two or more conductive traces.

26. The apparatus of any one of claims 23 to 25 as dependent from claim 9, wherein: i) the first density region comprises a first interconnect pitch, ii) the second density region comprises a second, different interconnect pitch, and ii) the first interconnect pitch is less than the second interconnect pitch.

27. The apparatus of claim 26, wherein:i) the first interconnect pitch is 45 micrometers (pm); and ii) the second interconnect pitch is 110 pm.

28. The apparatus of any one of claims 17 to 27, further comprising: a power delivery network collocated with the first region, the power delivery network comprising a plurality of second connection pillars and a micro-bump pitch that defines a spacing between two or more of the plurality of second connection pillars.

29. The apparatus of any one of claims 17 to 28, wherein the die-to-die interconnect is a universal package-level interconnect routing configuration based on open standard.

30. The apparatus of any one of claims 17 to 28, wherein the die-to-die interconnect is a universal package-level interconnect routing configuration based on the Universal Chiplet Interconnect Express (UCIe) standard.

31. A packaging platform for an integrated circuit package, the packaging platform comprising: a first interconnect region comprising die-to-die interconnections; a second, different interconnect region comprising interconnections to a memory device of the integrated circuit package; and a plurality of redistribution layers (RDLs) comprising: i) conductive traces for the die-to-die interconnections of the first interconnect region, and ii) conductive traces for the interconnections of the second interconnect region.

32. The packaging platform of claim 31, further comprising: a ball grid array (BGA) configured to facilitate a plurality of solder connections between the packaging platform and a printed circuit board.

Images