Chip and manufacturing method therefor, and electronic device

Abstract

The present application relates to the technical field of semiconductors. Provided are a chip and a manufacturing method therefor, and an electronic device, which reduce the probability of a short circuit occurring between a gate contact electrode and a source (or a drain). The chip comprises a field effect transistor arranged on a substrate, and the field effect transistor comprises a source, a drain, a gate, a first dielectric layer, a second dielectric layer, a third dielectric layer and a gate contact electrode, which are arranged on the substrate, wherein the gate is located in a region between the source and the drain, and the top of the gate is lower than the top of the source and the top of the drain; the first dielectric layer extends from side walls of the source and the drain to cover a gate region to form a recess structure, and a first via hole is provided at a position, which corresponds to the gate, at the bottom of the recess structure; the second dielectric layer is arranged on the first dielectric layer; the gate contact electrode penetrates the second dielectric layer, the recess structure and the first via hole to connect to the top of the gate; and the third dielectric layer comprises a portion filled between the gate contact electrode and a sidewall of the recess structure.

Description

Chip and manufacturing method thereof, and electronic device Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a chip, a manufacturing method thereof, and an electronic device. Background Art

[0002] DUV (deep ultraviolet) lithography is a key semiconductor manufacturing process used for pattern transfer during semiconductor chip fabrication. This technology has been widely used in semiconductor manufacturing for decades and boasts a relatively mature process and equipment foundation, providing high reliability and stability in large-scale chip production. However, with the continuous advancement of semiconductor manufacturing technology, the line widths within chips are shrinking, and DUV lithography continues to face challenges in manufacturing smaller chips.

[0003] As shown in Figure 1, the field-effect transistor in the chip includes a source S (source), a drain D (drain), and a gate G (gate) disposed on a substrate. The source S and drain D are located on the metal-0 layer M0A (metal-0 on active area) of the active region, while the gate G is located on the metal-0 layer M0P (metal-0 on gate area) of the gate region. The source S and drain D are located on either side of the gate G, and the tops of the source S and drain D are higher than the top of the gate G. During chip fabrication, as shown in Figure 1 (a), after the source S, drain D, and gate G are fabricated, a via V0 is formed above the gate G through multiple photolithography patterning / etching (nPnE) processes to expose the gate G. Then, as shown in Figure 1 (b), a gate contact electrode COAG (contact over active gate, also known as the connection point on the gate of the active device) is formed in the via V0 to connect to the gate G.

[0004] However, as the line width continues to shrink, the distance d between the gate contact electrode COAG and the source S and drain D also continues to decrease. The process difficulty of manufacturing the gate contact electrode COAG using DUV lithography technology continues to increase. As shown in Figure 2, it is easy to expose the side source S (or drain D) when manufacturing the via V0, thereby causing a short circuit problem between the gate contact electrode COAG and the source S (or drain D).

[0005] Summary of the Invention

[0006] The present application provides a chip and its manufacturing method, and an electronic device, which can manufacture a gate contact electrode by self-aligned contact etch (SAC) based on DUV lithography technology, thereby reducing the probability of short circuit between the gate contact electrode and the source (or drain).

[0007] The present application provides a chip, which includes a field effect transistor arranged on a substrate. The field effect transistor includes a source, a drain, a gate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a gate contact electrode arranged on the substrate. The gate is located in the area between the source and the drain, and the top of the gate is lower than the top of the source and the drain. The first dielectric layer extends from the side walls of the source and the drain to cover the gate area to form a groove structure, and a first via is provided at the bottom of the groove structure corresponding to the position of the gate. The second dielectric layer is provided on the first dielectric layer. The gate contact electrode passes through the second dielectric layer, the groove structure and the first via, and is connected to the top of the gate. The third dielectric layer includes a first portion filled between the gate contact electrode and the side walls of the groove structure.

[0008] In the chip provided in the present application, a first dielectric layer is provided on the gate, source and drain, and the height difference between the gate and the source and drain on both sides is utilized so that the first dielectric layer can naturally form a groove structure in the gate area. Therefore, when the gate contact electrode is made on the top of the gate, the groove structure can be directly exposed by self-aligned contact etching (SAC), which reduces the etching difficulty, provides greater flexibility and better control, and the use of DUV lithography technology can also well meet the etching requirements.

[0009] In some possible implementations, the first portion of the third dielectric layer extends from the bottom of the recessed structure to a point above, or flush with, the tops of the source and drain electrodes. This allows the third dielectric layer to better protect the first dielectric layer on the sides of the source and drain electrodes, significantly reducing the likelihood of a short circuit between the gate contact electrode and the source (or drain).

[0010] In some possible implementations, the lateral distance between the sidewalls of the above-mentioned groove structure and the sidewalls of the gate is within 3 nm. In this case, the sidewalls of the groove structure are roughly aligned with the sidewalls of the underlying gate in the laterally direction, thereby enabling the aperture of the gate contact electrode to be close to the aperture of the gate to better meet the needs of the chip.

[0011] In some possible implementations, the thickness of the third dielectric layer is in the range of 6 nm to 12 nm.

[0012] In some possible implementations, the third dielectric layer further includes a second portion filled between the gate contact electrode and the second dielectric layer, which can avoid adding processes and thus save manufacturing costs.

[0013] In some possible implementations, the first dielectric layer includes silicon nitride SiN.

[0014] In some possible implementations, the second dielectric layer includes silicon dioxide SiO2.

[0015] In some possible implementations, the third dielectric layer includes silicon dioxide SiO2.

[0016] The present application also provides a method for manufacturing a chip, which may include: manufacturing a source, a drain and a gate on a substrate; wherein the gate is located in the area between the source and the drain, and the top of the gate is lower than the top of the source and the drain. A first dielectric layer and a second dielectric layer are formed on the source, the drain and the gate in sequence; wherein the first dielectric layer extends from the side of the source and the drain to cover the gate area to form a groove structure. The second dielectric layer is etched at a position corresponding to the groove structure to expose the groove structure in a self-aligned manner. A third dielectric layer is deposited in the groove structure. The third dielectric layer at the bottom of the groove structure is removed, and at least a portion of the third dielectric layer at the sidewall of the groove structure is retained, and the film layer at the bottom of the groove structure is etched to form a through hole on the gate (that is, the gate is exposed at the bottom of the through hole). A gate contact electrode is formed in the through hole.

[0017] The above-mentioned manufacturing method is used to form a first dielectric layer on the gate, source and drain, and utilize the height difference between the gate and the source and drain electrodes on both sides to naturally form a groove structure in the gate area of ​​the first dielectric layer. Therefore, when etching the second dielectric layer, the groove structure can be directly exposed by self-aligned contact etching (SAC), which reduces the etching difficulty, provides greater flexibility and better control, and adopts DUV lithography technology to well meet the etching requirements.

[0018] In some possible implementations, forming the source, drain, and gate on the substrate may include: forming the gate on the substrate within a fourth dielectric layer, and forming a fifth dielectric layer on the gate; forming vias on either side of the gate, respectively, through the fifth dielectric layer and the fourth dielectric layer; and forming the source and drain in the vias on either side of the gate. Removing the fifth dielectric layer.

[0019] In some possible implementations, sequentially forming the first dielectric layer and the second dielectric layer on the source, drain, and gate may include depositing SiN on the source, drain, and gate using an atomic layer deposition process to form the first dielectric layer, and depositing SiO2 on the first dielectric layer to form the second dielectric layer.

[0020] In some possible implementations, the above-mentioned removing the third dielectric layer at the bottom of the groove structure and retaining at least a portion of the third dielectric layer at the sidewalls of the groove structure includes: removing the third dielectric layer at the bottom of the groove structure by adjusting the etching selectivity, and controlling the top of the third dielectric layer retained at the sidewalls of the groove structure to be higher than the tops of the source and drain, or to be flush with the tops of the source and drain.

[0021] The present application also provides an electronic device, which includes a circuit board and a chip provided in any of the possible implementation methods described above, and the chip is electrically connected to the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] FIG1 is a schematic diagram of a chip manufacturing process provided in the prior art;

[0023] FIG2 is a schematic diagram of a short circuit between a gate contact electrode and a source electrode in a chip provided in the prior art;

[0024] FIG3 is a schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0025] FIG4 is a schematic diagram of the structure of a chip during the manufacturing process provided in an embodiment of the present application;

[0026] FIG5 is a schematic diagram of the structure of a chip during the manufacturing process provided in an embodiment of the present application;

[0027] FIG6 is a schematic diagram of the structure of a chip during the manufacturing process provided in an embodiment of the present application;

[0028] FIG7 is a schematic diagram of a partial structure of a chip during the manufacturing process provided in an embodiment of the present application;

[0029] FIG8 is a schematic diagram of a chip manufacturing process provided in an embodiment of the present application;

[0030] FIG9 is a schematic structural diagram of a chip during the manufacturing process provided in an embodiment of the present application;

[0031] FIG10 is a schematic diagram of the structure of a chip during the manufacturing process provided in an embodiment of the present application;

[0032] FIG11 is a schematic diagram of the structure of a chip during the manufacturing process provided in an embodiment of the present application;

[0033] FIG12 is a schematic structural diagram of a chip during the manufacturing process provided in an embodiment of the present application;

[0034] FIG13 is a schematic diagram of the structure of a chip during the manufacturing process provided in an embodiment of the present application;

[0035] FIG14 is a schematic diagram of the structure of a chip during the manufacturing process provided in an embodiment of the present application;

[0036] FIG15 is a schematic diagram of the structure of a chip during the manufacturing process provided in an embodiment of the present application;

[0037] FIG16 is a schematic diagram of the structure of a chip during the manufacturing process provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0039] The terms "first", "second", etc. in the specification, embodiments, claims, and drawings of this application are only used for the purpose of distinguishing descriptions and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects before and after the association are in an "or" relationship. "At least one (item)" means one or more, and "multiple" means two or more. "Installation", "connection", "connected", etc. should be understood in a broad sense, for example, it can be an electrical connection or a mechanical connection; it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, an indirect connection through an intermediate medium, or a connection between two elements. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, including a series of steps or units. Methods, systems, products, or devices are not necessarily limited to the steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to the processes, methods, products, or devices. "Up," "down," "left," "right," etc. are used only with respect to the orientation of components in the drawings. These directional terms are relative concepts and are used for relative description and clarification. They may change accordingly depending on the orientation of the components in the drawings.

[0040] An embodiment of the present application provides an electronic device that uses a chip with a novel structure. The chip uses self-aligned contact etching (SAC) to produce a gate contact electrode (COAG), which can reduce the probability of a short circuit between the gate contact electrode (COAG) and the source (or drain), reduce the difficulty of device manufacturing, and use DUV lithography technology to well meet process requirements.

[0041] This application does not limit the configuration of the above-mentioned electronic device. The electronic device can be any electronic product equipped with a chip, such as consumer electronic products, household electronic products, vehicle-mounted electronic products, financial terminal products, communication electronic products, etc.

[0042] For example, the above-mentioned consumer electronic products may include mobile phones, tablet computers, laptop computers, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smart watches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products may include smart door locks, televisions, smart speakers, refrigerators, robot vacuums, etc. Car-mounted electronic products may include car navigation systems, car displays, etc. Financial terminal products may include automated teller machines (ATMs) and electronic devices for self-service transactions, etc. Communication electronic products may include communication equipment such as servers, storage devices, radars, and base stations.

[0043] Of course, according to actual needs, the above-mentioned electronic device can also be provided with other devices electrically connected to the chip, such as a printed circuit board (PCB; also called a printed circuit board), input and output devices, etc. This application does not impose any restrictions on this, and in practice it can be set as needed.

[0044] The gate contact electrode (COAG) fabricated by self-aligned contact etching (SAC) provided in this application can be applied to both fin field effect transistor (FinFET) and gate all around field effect transistor (GAA) processes, without limitation in this application. The following embodiments are all illustrated using the application in a chip using the FinFET process as an example.

[0045] The following describes the gate contact electrode COAG and related structures in the chip provided in the embodiments of the present application.

[0046] Schematically, an embodiment of the present application provides a chip, as shown in FIG3 , which includes a substrate 1 and a field effect transistor T, such as a fin field effect transistor (FinFET), disposed on the substrate 1. The field effect transistor T includes a source S, a drain D, and a gate G disposed on the substrate 1. The gate G is disposed in a region between the source S and the drain D, and the top of the gate G is lower than the tops of the source S and the drain D. That is, there is a height difference between the top of the gate G and the tops of the source S and the drain D.

[0047] It should be noted that the "top" and "bottom" involved in this application are all based on the substrate in the device as a reference object. The "top" of the component refers to the end away from the substrate, and the "bottom" refers to the end close to the substrate.

[0048] On this basis, referring to FIG. 3 , the chip has a first dielectric layer 21 disposed on the source S, the drain D, and the gate G, and a second dielectric layer 22 disposed on the first dielectric layer 21 .

[0049] As shown in FIG4 , because the top of the gate G is lower than the tops of the source S and drain D, when forming the first dielectric layer 21, the first dielectric layer 21 extends from the sides of the source S and drain D to cover the gate G region, thereby naturally forming a groove structure a in the gate G region. When forming the second dielectric layer 22 on the first dielectric layer 21, the second dielectric layer 22 covers the first dielectric layer 21 and fills the groove structure a.

[0050] Continuing with FIG3 , the chip (or field effect transistor T) further includes a gate contact electrode 3, which is located above the gate G and connected to the top of the gate G. Therefore, when fabricating the gate contact electrode 3, it is necessary to etch the film layer (including 21 and 22) on the gate G to form a through hole to expose the gate G, and then form the gate contact electrode 3 in the through hole.

[0051] As shown in FIG5 , since the first dielectric layer 21 forms a recess structure a in the gate G region, a self-aligned contact etch (SAC) method can be used to remove the second dielectric layer 22 above the recess structure a, forming a via v2 (also referred to as a second via) that penetrates the recess structure a. Using this self-aligned contact etch (SAC) method reduces etching difficulty, provides greater flexibility and better control, and can also effectively meet etching requirements using DUV lithography technology.

[0052] On this basis, referring to FIG5 , in order to expose the top of the gate G, the first dielectric layer 21 and the underlying film layers (such as an etch stop layer) need to be further etched along the bottom of the recess structure a. To prevent damage to the first dielectric layer 21 on the sidewalls of the recess structure a during the etching process, as shown in FIG3 , a third dielectric layer 23 can be coated on the sidewalls of the recess structure a as a protective layer. This protects the first dielectric layer 21 on the sidewalls of the recess structure a when etching the bottom of the recess structure a to form a via v1 (also referred to as a first via), preventing damage to the first dielectric layer 21 on the side of the source S (or drain D), which could cause a short circuit between the gate contact electrode 3 and the source S (or drain D). In this case, after the gate contact electrode 3 is formed in the through-hole v1, the recess structure a, and the via v2, the third dielectric layer 23 is filled between the gate contact electrode 3 and the sidewalls of the recess structure a.

[0053] Schematically, in some possible implementations, as shown in FIG6 , during chip fabrication, a third dielectric layer 23 can be formed by depositing a dielectric material on the inner wall of deep trench a1 (including v2 and a). In this case, the third dielectric layer 23 will simultaneously cover the sidewalls of the recess structure a and the sidewalls of the via v2. Alternatively, a portion of the third dielectric layer 23 covers part or all of the sidewalls of the recess structure a, and a portion covers the sidewalls of the via v2. To avoid additional processing steps, as shown in FIG3 , in some possible implementations, the third dielectric layer 23 can be retained between the gate contact electrode 3 and the sidewalls of the via v2 (or the second dielectric layer 22).

[0054] Schematically, referring to Figures 3 and 6, when the third dielectric layer 23 at the bottom of the groove structure a is removed, the third dielectric layer 23 in a portion of the sidewall area of ​​the deep trench a1 will inevitably be removed, especially the third dielectric layer 23 covering the step at the interface between the first dielectric layer 21 and the second dielectric layer 22. Due to process reasons, this portion of the third dielectric layer 23 may be removed, so that the third dielectric layer 23 on the sidewall of the groove structure a and the sidewall of the via v2 is not a continuous film layer. The specific process can be referred to the subsequent manufacturing method, which will not be repeated here.

[0055] Of course, in order to better protect the first dielectric layer 21 on the sidewall of the groove structure a, when etching the bottom of the groove structure a, the third dielectric layer 23 covering the sidewall of the groove structure a should be retained as much as possible.

[0056] As an illustration, the amount of the third dielectric layer 23 retained on the sidewalls of the recess structure a can be adjusted by controlling the etching selectivity of the third dielectric layer 23 and the first dielectric layer 21. For example, in some possible implementations, the etching selectivity can be adjusted to control the third dielectric layer 23 covering the sidewalls of the recess structure a to extend upward from the bottom of the recess structure a to a point above the top of the source S and the drain D, or to be flush with the top of the source S and the drain D. In this way, the third dielectric layer 23 can better protect the first dielectric layer 21 on the sides of the source S and the drain D, thereby significantly reducing the probability of a short circuit between the gate contact electrode 3 and the source S (or the drain D).

[0057] In summary, in the chip provided in the embodiment of the present application, a first dielectric layer 21 is formed on the gate G, the source S and the drain D, and the height difference between the gate G and the source S and the drain D on both sides is utilized, so that the first dielectric layer 21 naturally forms a groove structure a in the gate G area. Therefore, when the gate contact electrode 3 is formed on the top of the gate G, the groove structure a can be directly exposed by self-aligned contact etching (SAC), which reduces the etching difficulty, provides greater flexibility and better control, and the use of DUV lithography technology can also well meet the etching requirements.

[0058] It can be understood that, as shown in Figure 3, the middle section of the gate contact electrode 3 is filled in the groove structure a, and the aperture of this part of the gate contact electrode 3 is roughly the same as the width of the groove structure a, and the width of the groove structure a depends on the thickness of the first dielectric layer 21. Therefore, in practice, the aperture manufacturing requirements of the gate contact electrode 3 can be met by controlling the thickness of the first dielectric layer 21.

[0059] Schematically, in some possible implementations, the thickness of the first dielectric layer 21 can be controlled so that the aperture of the gate contact electrode 3 filled in the groove structure a is substantially the same as the aperture of the underlying gate G. In this case, referring to FIG7 , when forming the first dielectric layer 21, the thickness of the first dielectric layer 21 can be controlled so that the sidewall S1 of the groove structure a and the sidewall S2 of the underlying gate G are substantially aligned in the horizontal direction.

[0060] For example, in some possible implementations, the lateral distance between the sidewall S1 of the groove structure a and the sidewall S2 of the gate G can be controlled to be within 3 nm. Specifically, in the lateral direction, the sidewall S1 of the groove structure a can be located outside the sidewall S2 of the gate G, and the lateral distance d1 between S1 and S2 is ≤ 3 nm; the sidewall S1 of the groove structure a can also be located inside the sidewall S2 of the gate G, and the lateral distance d2 between S1 and S2 is ≤ 3 nm.

[0061] In order to prevent a short circuit between the gate contact electrode 3 and the source S (or drain D) to a greater extent, in some possible implementations, the thickness of the first dielectric layer 21 can be controlled so that the sidewall S1 of the groove structure a is located 0 to 2 nm within the sidewall S2 of the gate G, thereby ensuring that the first dielectric layer 21 has a large thickness, thereby preventing the first dielectric layer 21 on the side of the source S (or drain D) from being etched through when etching the bottom of the groove structure a, thereby preventing a short circuit between the gate contact electrode 3 and the source S (or drain D).

[0062] The present application does not impose any limitation on the actual thickness of the first dielectric layer 21 , as long as it can meet the requirements of the chip.

[0063] Illustratively, in some possible implementations, the thickness of the first dielectric layer 21 may be in the range of 6 nm to 12 nm.

[0064] In addition, the present application does not impose any restrictions on the dielectric materials used for the first dielectric layer 21 , the second dielectric layer 22 , and the third dielectric layer 23 , and they can be selected according to process requirements in practice.

[0065] Schematically, the first dielectric layer 21 and the second dielectric layer 22 should be made of different dielectric materials to ensure a high selective etching ratio between the first dielectric layer 21 and the second dielectric layer 22, thereby meeting the chip manufacturing process requirements. For details, please refer to the corresponding manufacturing method below. For example, in some possible implementations, the first dielectric layer 21 may include a nitride such as silicon nitride (SiN), and the second dielectric layer 22 may include an oxide such as silicon dioxide (SiO2).

[0066] Schematically, the first dielectric layer 21 and the third dielectric layer 23 should be made of different dielectric materials to ensure a high selective etching ratio between the first dielectric layer 21 and the third dielectric layer 23, thereby meeting the chip manufacturing process requirements. For details, please refer to the corresponding manufacturing methods below. For example, in some possible implementations, the first dielectric layer 21 may include a nitride such as silicon nitride (SiN), and the third dielectric layer 23 may include an oxide such as silicon dioxide (SiO2).

[0067] The dielectric materials used in the second dielectric layer 22 and the third dielectric layer 23 may be the same or different, and this application does not impose any limitation thereto. In practice, the dielectric materials may be selected according to actual needs.

[0068] The gate contact electrode 3 and related structures in the chip are further described below in conjunction with the chip manufacturing method.

[0069] Schematically, an embodiment of the present application provides a method for manufacturing a chip, as shown in FIG8 , the manufacturing method may include:

[0070] Step 10, referring to FIG9 , a source S, a drain D and a gate G are formed on the substrate 1 ; wherein the gate G is located in the region between the source S and the drain D, and the top of the gate G is lower than the tops of the source S and the drain D.

[0071] Schematically, in some possible implementations, step 10 may include: Referring to FIG10(a), providing a substrate 1 (e.g., a silicon wafer), forming doped regions corresponding to the source and drain of the field-effect transistor in the active region of substrate 1, and forming a gate G disposed in a dielectric layer 24 (also referred to as a fourth dielectric layer) on substrate 1; wherein gate G may be formed by replacing polysilicon. Next, referring to FIG10(b), sequentially forming an etch stop layer (ESL) and a dielectric layer 25 (also referred to as a fifth dielectric layer) on gate G, and etching dielectric layer 25, etch stop layer ESL, dielectric layer 24, and other film layers at locations corresponding to the doped regions on both sides of gate G to form a via b. Next, referring to FIG10(c), first forming a dielectric layer 26 in via b, and then filling the inner portion of dielectric layer 26 with metal material to form a source S and a drain D, with the tops of source S and drain D protruding above the top of gate G. Next, referring to FIG. 10 ( d ), the dielectric layer 25 is removed, and a height difference is formed between the top of the gate G and the tops of the source S and the drain D.

[0072] Step 20, referring to FIG11 , a first dielectric layer 21 and a second dielectric layer 22 are sequentially formed on the source S, the drain D and the gate G; wherein the first dielectric layer 21 extends from the sides of the source S and the drain D to cover the gate G region to form a groove structure a.

[0073] Schematically, in some possible implementations, the above step 20 may include: referring to FIG11(a), using an atomic layer deposition (ALD) process to deposit SiN on the source S, drain D, and gate G to form a first dielectric layer 21. Due to the height difference between the gate G and the source S and drain D, the first dielectric layer 21 can extend from the sides of the source S and drain D to cover the gate G region, naturally forming a groove structure a. Next, referring to FIG11(b), SiO2 is deposited on the first dielectric layer 21 to form a second dielectric layer 22, and a chemical mechanical polishing (CMP) process is used to smooth the surface of the second dielectric layer 22.

[0074] Step 30 , referring to FIG. 12 , the second dielectric layer 22 is etched at a position corresponding to the groove structure a to expose the groove structure a in a self-aligned manner.

[0075] As shown, step 30 is used to etch the second dielectric layer 22 at the position corresponding to the groove structure a. The etching process is self-aligned contact etching (SAC), which can self-align to expose the groove structure a, thereby providing greater flexibility and better control of the etching process, reducing the etching difficulty, and using DUV lithography technology can also well meet the etching requirements.

[0076] Schematically, the multiple photolithography shaping / etching (nPnE) process used in step 30 is used to etch the second dielectric layer 22. The specific process may include:

[0077] First, referring to FIG. 13 (a), a hard mask layer HM (hard mask), a spin on carbon coating SOC (spin on carbon), an anti-reflection coating SAR (anti-reflection coating), and a photoresist layer PR are sequentially formed on the second dielectric layer 22, and the photoresist layer PR is opened at a position corresponding to the groove structure a by lithography.

[0078] Then, as shown in FIG13( b ), a photolithography patterning / etching process can be performed on the anti-reflective coating SAR and the carbon coating SOC along the opening area in the photoresist layer PR to form a through hole in the anti-reflective coating SAR and the carbon coating SOC. This etching process stops on the hard mask layer HM (e.g., SiN layer).

[0079] Next, referring to FIG. 13( c ), the anti-reflection layer SAR may be removed, and a through hole may be formed along the carbon coating SOC. The hard mask layer HM may be subjected to a photolithography / etching process to extend the through hole into the hard mask layer HM.

[0080] Next, as shown in FIG13(d), a photolithography / etching process can be performed on the second dielectric layer 22 along the through hole in the hard mask layer HM, forming a via v2 in the second dielectric layer 22. The via v2 and the recess structure a penetrate to form a deep trench a1. This etching process stops on the first dielectric layer 21 (e.g., SiN layer). The carbon coating SOC can then be removed by an ash process, retaining the hard mask layer HM.

[0081] It should be understood that when the second dielectric layer 22 is made of SiO2 (oxide) and the first dielectric layer 21 is made of SiN, an etching process with a high SiO2 / SiN selectivity ratio is required when etching the second dielectric layer 22 and leaving it on the first dielectric layer 21. For example, in some possible implementations, the ALE (atomic layer etch) function of a CCP (capacitively coupled plasma) machine can be used to achieve this.

[0082] Step 40 , referring to FIG. 13 and FIG. 14 , a third dielectric layer 23 is deposited in the groove structure a.

[0083] After step 30, the first dielectric layer 21 at the bottom of the recess structure a needs to be opened. To prevent damage to the first dielectric layer 21 on the sidewalls of the recess structure a during the opening process, referring to FIG14 , the present application first deposits SiO2 (oxide) in the deep trench a1 (a and v2) in step 40 to form a third dielectric layer 23 as a protective layer to protect the first dielectric layer 21 on the sidewalls of the recess structure a. The third dielectric layer 23 can extend to cover the surface of the hard mask layer HM.

[0084] Step 50, referring to Figures 14 and 15, remove the third dielectric layer 23 at the bottom of the groove structure a, retain at least a portion of the third dielectric layer 23 at the sidewall of the groove structure a, and etch the film layer at the bottom of the groove structure a to form a through hole 30 on the gate G.

[0085] The etching of the groove structure a in step 50 can be divided into two steps. First, the third dielectric layer 23 at the bottom of the groove structure a is removed, and then the first dielectric layer 21 and other film layers are further etched to form a first via hole v1 at the bottom of the groove structure a, exposing the top of the gate G.

[0086] When etching the third dielectric layer 23 at the bottom of the groove structure a, the first dielectric layer 21 at the bottom of the groove structure a is exposed, and exposure of the first dielectric layer 21 in other areas is minimized. Of course, due to process reasons, when removing the first dielectric layer 21 at the bottom of the groove structure a, the third dielectric layer 23 at the interface step between the first dielectric layer 21 and the second dielectric layer 22 may also be removed simultaneously, resulting in the third dielectric layer 23 not being a continuous film layer on the sidewalls of the groove structure a and the sidewalls of the via v2 (see FIG. 15 ).

[0087] Schematically, when etching the bottom of the recess structure a, the etching selectivity between the first dielectric layer 21 (SiN) and the third dielectric layer 23 (oxide) can be increased to preserve as much of the third dielectric layer 23 as possible on the sidewalls of the recess structure a. For example, this can be achieved by using a CCP machine and controlling the etching gas to select a gas with a high selectivity ratio, such as (CH3F / H2).

[0088] As an example, in some possible implementations, the etching selectivity of the first dielectric layer 21 (SiN) and the third dielectric layer 23 (oxide) can be adjusted to remove the third dielectric layer 23 at the bottom of the recess structure a. The third dielectric layer 23 remaining on the sidewalls of the recess structure a is controlled so that the bottom of the recess structure a extends upward to be higher than the top of the source S and the drain D, or is flush with the top of the source S and the drain D. In this way, the first dielectric layer 21 on the sides of the source S and the drain D can be better protected, greatly reducing damage to the first dielectric layer 21 on the side surfaces.

[0089] Furthermore, it is also understood that by controlling the etching selectivity through LRM (liner remove) in step 50, a funnel-shaped via v1 structure is achieved, and the via v1 can maintain a sufficient distance from the source S and the drain D. Liner refers to the bottom etch stop layer (including 21 and ESL), and LRM refers to the step of opening the first dielectric layer 21 and the etch stop layer ESL.

[0090] Step 60 , referring to FIG. 15 and FIG. 16 , a gate contact electrode 3 is formed in the through hole 30 .

[0091] As shown, in some possible implementations, metal tungsten is deposited in the through hole 30 (i.e., the through second via v2, the groove structure a and the first via v1) to form a gate contact electrode 3 in step 60, and the surface is leveled by a chemical mechanical polishing (CMP) process to remove the hard mask layer HM.

[0092] Of course, after step 60, subsequent process flows may be performed according to chip manufacturing requirements, and this application does not impose any restrictions on this.

[0093] The above-mentioned manufacturing method is used to form a first dielectric layer 21 on the gate G, the source S, and the drain D. By utilizing the height difference between the gate G and the source S and the drain D on both sides, the first dielectric layer 21 naturally forms a groove structure a in the gate G region. Therefore, when etching the second dielectric layer 22, the groove structure a can be directly exposed by self-aligned contact etching (SAC), which reduces the etching difficulty, provides greater flexibility and better control, and adopts DUV lithography technology to well meet the etching requirements.

[0094] It should be understood that in the embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by the chip function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0095] For other relevant contents in the above-mentioned manufacturing method, you can refer to the corresponding parts in the above-mentioned chip structure embodiment, which will not be repeated here; for other setting structures in the above-mentioned chip structure embodiment, you can refer to the above-mentioned manufacturing method and related manufacturing methods for adjustment, which will not be repeated here one by one.

[0096] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A chip, characterized in that: including a field effect transistor disposed on a substrate; The field effect transistor comprises: A source electrode, a drain electrode, and a gate electrode are provided on the substrate, wherein the gate electrode is located in a region between the source electrode and the drain electrode, and a top portion of the gate electrode is lower than a top portion of the source electrode and the drain electrode; A first dielectric layer extends from the sidewalls of the source and the drain to cover the gate region to form a groove structure, and a first via hole is provided at the bottom of the groove structure at a position corresponding to the gate; a second dielectric layer, disposed on the first dielectric layer; a gate contact electrode, penetrating the second dielectric layer, the groove structure and the first via hole, and connected to the top of the gate; The third dielectric layer includes a first portion filled between the gate contact electrode and the sidewall of the groove structure.

2. The chip according to claim 1, characterized in that The first portion extends upward from the bottom of the recess structure to be higher than the top of the source electrode and the drain electrode, or is flush with the top of the source electrode and the drain electrode.

3. The chip according to claim 1 or 2, characterized in that: A lateral distance between a sidewall of the groove structure and a sidewall of the gate is within 3 nm.

4. The chip according to any one of claims 1 to 3, characterized in that The thickness of the third dielectric layer is in the range of 6 nm to 12 nm.

5. The chip according to any one of claims 1 to 4, characterized in that: The third dielectric layer further includes a second portion filled between the gate contact electrode and the second dielectric layer.

6. The chip according to any one of claims 1 to 5, characterized in that: The first dielectric layer includes silicon nitride SiN.

7. The chip according to any one of claims 1 to 6, characterized in that: The second dielectric layer includes silicon dioxide SiO2.

8. The chip according to any one of claims 1 to 7, characterized in that: The third dielectric layer includes silicon dioxide SiO2.

9. A method for manufacturing a chip, characterized in that: include: A source electrode, a drain electrode, and a gate electrode are fabricated on a substrate; wherein the gate electrode is located in a region between the source electrode and the drain electrode, and a top portion of the gate electrode is lower than a top portion of the source electrode and the drain electrode; forming a first dielectric layer and a second dielectric layer on the source, the drain and the gate in sequence; wherein the first dielectric layer extends from the sides of the source and the drain to cover the gate region to form a groove structure; Etching the second dielectric layer at a position corresponding to the groove structure to expose the groove structure; depositing a third dielectric layer in the groove structure; removing the third dielectric layer at the bottom of the groove structure, retaining at least a portion of the third dielectric layer at the sidewall of the groove structure, and etching the film layer at the bottom of the groove structure to form a through hole on the gate; A gate contact electrode is formed in the through hole.

10. The chip manufacturing method according to claim 9, characterized in that: The method of fabricating a source electrode, a drain electrode, and a gate electrode on a substrate, wherein the gate electrode is located in a region between the source electrode and the drain electrode, and a top portion of the gate electrode is lower than a top portion of the source electrode and the drain electrode, comprises: forming a gate electrode located in a fourth dielectric layer on a substrate, and forming a fifth dielectric layer on the gate electrode; forming via holes penetrating the fifth dielectric layer and the fourth dielectric layer on both sides of the gate, and forming a source electrode and a drain electrode in the via holes on both sides of the gate; The fifth dielectric layer is removed.

11. The method for manufacturing a chip according to claim 9 or 10, characterized in that: include: The step of sequentially forming a first dielectric layer and a second dielectric layer on the source, the drain, and the gate comprises: Depositing SiN on the source, the drain and the gate to form a first dielectric layer using an atomic layer deposition process; SiO2 is deposited on the first dielectric layer to form a second dielectric layer.

12. The method for manufacturing a chip according to any one of claims 9 to 11, characterized in that: include: The removing of the third dielectric layer at the bottom of the groove structure and retaining at least a portion of the third dielectric layer at the sidewall of the groove structure comprises: By adjusting the etching selectivity, the third dielectric layer at the bottom of the groove structure is removed, and the top of the third dielectric layer remaining on the sidewall of the groove structure is controlled to be higher than the top of the source and the drain, or to be flush with the top of the source and the drain.

13. An electronic device, characterized in that: The device comprises a circuit board and the chip according to any one of claims 1 to 8, wherein the chip is electrically connected to the circuit board.

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