Multi-accelerator-card heterogeneous server and resource link reconstruction method

Abstract

Provided in the present application are a multi-accelerator-card heterogeneous server and a resource link reconstruction method. The server comprises a switch unit, a heterogeneous accelerated-computing pooling unit and a general-purpose computing resource pooling unit, wherein the general-purpose computing resource pooling unit comprises at least one processor, the heterogeneous accelerated-computing pooling unit comprises at least two accelerator cards, and the processor and the accelerator cards are heterogeneous relative to each other; the switch unit comprises a management controller and at least two switch chips, any switch chip is connected to at least one of the other switch chips in the switch unit by means of an internal port, and the processor and the accelerator cards are respectively connected to the switch chips; and the management controller is connected to the switch chips, and is used for reconstructing a resource link on the basis of preset task resource requirements and chip information of the current switch chips.

Description

Multi-accelerator card heterogeneous server and resource link reconstruction method

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to a Chinese patent application filed with the Patent Office of China on January 31, 2024, with application number 202410131445.7 and application name “Multi-acceleration card heterogeneous server and resource link reconstruction method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to a multi-acceleration card heterogeneous server and a resource link reconstruction method. Background Art

[0004] Dedicated computing acceleration servers are typically heterogeneous servers. For example, artificial intelligence (AI) servers require high computing power. Currently, AI application workloads are rapidly developing, and computing power demands are exponentially increasing. This is especially true with the rapid development of typical AI applications such as generative AI, large models, and deep learning intelligent recommendations. AI heterogeneous server systems also face numerous challenges, such as improving computing efficiency and enhancing system performance. This requires continued research and innovation to support the continued development of high-performance computing infrastructure.

[0005] The overall training speed of the AI ​​model is equal to the product of the single-card speed, the number of accelerator cards, and the multi-card acceleration ratio.

[0006] The speed of a single card is determined by the computing speed and the speed of data IO (Input / Output). Therefore, single-card training needs to be optimized. The main technical means to accelerate the training performance of a single card include precision training, operator fusion, and gradient accumulation.

[0007] Regarding the number of accelerator cards, theoretically, more accelerator cards means faster model training. However, as the size of the training dataset continues to grow, data parallelism becomes limited. When training resources reach a certain scale, communication bottlenecks create a significant marginal benefit from increasing computing resources (i.e., accelerator cards), sometimes even to the point of failing to accelerate the training process. This requires optimizing the network communication topology to optimize the training model.

[0008] Regarding the multi-GPU acceleration ratio: The multi-GPU acceleration ratio is determined by computing and communication efficiency and needs to be optimized in conjunction with the algorithm and the network communication topology in the cluster. A multi-dimensional hybrid parallel strategy combining data parallelism (DP), model parallelism (MP), and pipeline parallelism (PP) can be used to increase the efficiency of multi-GPU training.

[0009] Currently, the performance of a single accelerator card (e.g., GPU, Graphics Processing Unit) is limited, and the speedup of multi-card parallel computing reaches the limits of parallel algorithms and inter-device communication bandwidth. Therefore, increasing the number of accelerator cards is a direct and effective way to increase the computing power and training speed of heterogeneous AI server systems. Therefore, when increasing the number of accelerator cards, optimizing the network communication efficiency between multiple accelerator cards and general computing resources (e.g., CPU, Central Processing Unit) to improve the processing performance of tasks (e.g., training large models) is a technical problem that needs to be solved urgently.

[0010] Summary of the Invention

[0011] According to the embodiments disclosed in the present application, in a first aspect, a multi-accelerator card heterogeneous server is provided, comprising: a switching unit, a heterogeneous accelerated computing pooling unit, and a general computing resource pooling unit;

[0012] The general computing resource pooling unit includes at least one processor, and the heterogeneous accelerated computing pooling unit includes at least two accelerator cards, where the processor and the accelerator cards are heterogeneous.

[0013] The switching unit includes: a management controller and at least two switching chips, any switching chip is connected to at least one other switching chip in the switching unit through an internal port, the processor is connected to the uplink port of the switching chip, and the accelerator card is connected to the downlink port of the switching chip;

[0014] The management controller is connected to each switching chip and is used to determine the resource link reconstruction instruction based on the preset task resource requirements and the current chip information of each switching chip, and send the resource link reconstruction instruction to each target switching chip to form a resource link for completing the computing task corresponding to the task resource requirements.

[0015] In a second aspect, a resource link reconstruction method is further provided, which is implemented based on any of the above-mentioned multi-accelerator card heterogeneous servers and is applied to a management controller. The method includes:

[0016] Obtain task resource requirements and chip information of each current switching chip;

[0017] Determine resource link reconstruction instructions based on task resource requirements and current chip information of each switching chip;

[0018] The resource link reconstruction instruction is sent to each target switching chip to form a resource link for completing the computing task corresponding to the task resource requirement.

[0019] In a third aspect, a resource link reconstruction device is provided, which is implemented based on any of the above-mentioned multi-accelerator card heterogeneous servers, and is applied to a management controller. The device includes:

[0020] Information acquisition module, used to obtain task resource requirements and chip information of each current switching chip;

[0021] An instruction determination module is used to determine resource link reconstruction instructions based on task resource requirements and chip information of each current switching chip;

[0022] The instruction sending module is used to send a resource link reconstruction instruction to each target switching chip to form a resource link for completing the computing task corresponding to the task resource requirement.

[0023] In a fourth aspect, an electronic device is also provided, comprising a memory, a processor, and computer-readable instructions stored in the memory and executable on the processor, wherein when the processor executes the program, the resource link reconstruction method according to the second aspect described above is implemented.

[0024] In a fifth aspect, a non-transitory computer-readable storage medium is also provided, on which computer-readable instructions are stored. When the computer-readable instructions are executed by a processor, the resource link reconstruction method of the second aspect as described above is implemented.

[0025] The details of one or more embodiments of the present application are set forth in the accompanying drawings and the description below. Other features and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] FIG1 is a schematic diagram of a multi-accelerator card heterogeneous server structure according to one or more embodiments of the present application;

[0028] FIG2 is a schematic diagram of fabric interconnection routing of dual switching chips in a multi-accelerator card heterogeneous server according to one or more embodiments of the present application;

[0029] 3 is a functional diagram of a management controller in a switching unit of a multi-accelerator card heterogeneous server according to one or more embodiments of the present application;

[0030] 4 is a switching network topology diagram of a switching unit of a multi-accelerator card heterogeneous server, wherein eight switching chips are divided into two groups according to one or more embodiments of the present application;

[0031] FIG5 is a schematic diagram of a heterogeneous server structure with 32 accelerator cards based on the switching network topology diagram in FIG4 according to one or more embodiments of the present application;

[0032] FIG6 is a schematic diagram of a heterogeneous server structure having 16 accelerator cards in a switching network composed of five switching chips according to one or more embodiments of the present application;

[0033] 7 is a schematic diagram of the hardware connection structure of a switching unit in a multi-accelerator card heterogeneous server according to one or more embodiments of the present application;

[0034] FIG8 is a schematic diagram of a data management link of a switching unit in a heterogeneous server with multiple accelerator cards according to one or more embodiments of the present application;

[0035] FIG9 is a data management link topology diagram of a switching unit and a heterogeneous accelerated computing pooling unit in a multi-accelerator card heterogeneous server according to one or more embodiments of the present application;

[0036] FIG10 is a schematic diagram of the hardware connection structure of a switching unit and a heterogeneous accelerated computing pooling unit in a multi-accelerator card heterogeneous server according to one or more embodiments of the present application;

[0037] FIG11 is a reset logic topology diagram of a heterogeneous server with multiple accelerator cards according to one or more embodiments of the present application;

[0038] FIG12 is a schematic flow chart of a resource link reconstruction method based on a multi-accelerator card heterogeneous server according to one or more embodiments of the present application;

[0039] FIG13 is a schematic structural diagram of a resource link reconstruction device based on a multi-accelerator card heterogeneous server according to one or more embodiments of the present application;

[0040] FIG14 is a schematic structural diagram of an electronic device according to one or more embodiments of the present application;

[0041] FIG15 is a schematic diagram of the structure of a non-transitory computer-readable storage medium according to one or more embodiments of the present application. DETAILED DESCRIPTION

[0042] To make the technical solutions and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0043] The multi-accelerator card heterogeneous server of an embodiment of the present application is shown in FIG1 , and includes: a switching unit 100 , a heterogeneous accelerated computing pooling unit 200 , and a general computing resource pooling unit 300 .

[0044] The general computing resource pooling unit 300 includes at least one processor 301, i.e., a CPU. One or more processors 301 form a general computing resource pool to provide general computing resources for computing tasks. The heterogeneous accelerated computing pooling unit 200 includes at least two accelerator cards 201. Two or more accelerator cards 201 form an accelerated computing resource pool to provide accelerated computing resources for computing tasks. The processor 301 and the accelerator card 201 are heterogeneous. The accelerator card 201 can be divided into different types according to different computing tasks, such as a graphics processing unit (GPU) for training graphics artificial intelligence models or an FPGA (Field Programmable Gate Array) chip of other computing types.

[0045] The switching unit 100 includes a management controller 102 and at least two switch chips 101, each of which is a high-performance I / O switch chip. Each switch chip 101 is connected to at least one other switch chip 101 in the switching unit 100 via an internal port. The processor 301 is connected to the uplink port of the switch chip 101, and the accelerator card 201 is connected to the downlink port of the switch chip 101. It should be noted that all ports on the switch chip 101 are high-speed interfaces and are not logically divided. The ports connecting two switch chips 101 are referred to as internal ports, the ports connecting the processor 301 are referred to as uplink ports, and the ports connecting the accelerator card 201 are referred to as downlink ports. Since the switching chip 101 connects the processor 301 and the accelerator card 201, and there is also interconnection between the switching chips 101, it can provide high-bandwidth, low-latency and multi-channel interconnection between the accelerator cards 201, meeting the computing power requirements of high-performance computing tasks. According to the differences in the categories of processor resources for general computing and accelerator card resources for heterogeneous accelerated computing, similar computing resources in the resource pool can be integrated according to the computing tasks, providing the prerequisite for the on-demand reorganization of different processor resources and accelerator card resources to form resource links in terms of hardware structure.

[0046] The management controller 102 is connected to each switch chip 101 and is used to determine resource link reconfiguration instructions based on the preset task resource requirements and the current chip information of each switch chip 101. The resource link reconfiguration instructions are then sent to each target switch chip to form a resource link for completing the computing task corresponding to the task resource requirements. Task resource requirements refer to the information about the processor resources and accelerator card resources required to complete a computing task. This information includes the resource quantity (for example, completing a large model training task requires 4 CPU resources and 16 GPU resources), as well as the allocation relationship (for example, 4 GPUs are allocated to one CPU). Chip information includes: switching chip ID, port IDs of the switching chip 101, port bandwidth, port rate and port status information. Port status information includes: port connection information and port usage information. Port connection information includes whether the port is connected to a processor 301, an accelerator card 201 or other switching chip 101, and resource information of the connected processor 301 or accelerator card 201 (for example, model and performance parameters, etc.). Port usage information indicates whether the port has been assigned to a resource link reconstructed corresponding to a computing task. If it has been assigned, the port is in use, and the processor 301 or accelerator card 201 connected to the port is also in use. If it has not been assigned, it means that if the processor 301 or accelerator card 201 corresponding to the port is not in use, it can be used for resource allocation of new computing tasks.

[0047] Among them, the resource link reconstruction instruction includes: the ID of each target switching chip involved in the link and the target port ID on each target switching chip, so that the resource link reconstruction instruction is sent to the corresponding target switching chip, thereby establishing a communication protocol between the target switching chip and its port on the resource link, and the processor 301 and accelerator card 201 connected to the port. The data processed by the processor 301 and the accelerator card 201 can be communicated efficiently through the target switching chip to complete the computing task.

[0048] In the multi-accelerator card heterogeneous server of the embodiment of the present application, the switching chip 101 connects the processor 301 and the accelerator card 201, and there is also interconnection between the switching chips 101, so as to provide high-bandwidth, low-latency and multi-channel interconnection between the accelerator cards 201, meet the computing power requirements of high-performance computing tasks, and integrate similar computing resources in the resource pool according to the differences in the processor resources of general computing and the accelerator card resources of heterogeneous accelerated computing according to the computing tasks, and provide the prerequisite for the on-demand reorganization of different processor resources and accelerator card resources to form a resource link in terms of hardware structure. On this basis, the management controller 102 manages the resources according to the preset task resources. The resource link reconstruction instruction is determined based on the task resource requirements and the current chip information of each switching chip 101, and the resource link reconstruction instruction is sent to each target switching chip to form a resource link for completing the computing task corresponding to the task resource requirements. That is, according to the task resource requirements and the current chip information of each switching chip 101, a suitable switching chip 101 and the corresponding port are selected, so that there is a higher network communication efficiency between multiple accelerator cards 201, and between the accelerator card 201 and the processor 301, so as to improve the task processing performance, and achieve the purpose of improving the system computing performance by improving communication efficiency when more accelerator cards 201 are integrated into the server system. Moreover, the resource link is dynamically reconstructed based on the preset task resource requirements and the current chip information of each switching chip 101. Compared with the traditional fixed resource link, it can more flexibly allocate processor resources and accelerator card resources to avoid resource waste.

[0049] In some embodiments, to facilitate the management controller 102 in obtaining the chip information of each current switch chip 101, as shown in FIG2 , each switch chip 101 includes an embedded controller 1011. The embedded controller 1011 is used to enumerate the chip information of the switch chip 101 in which it is located and send the chip information to the management controller 102. Specifically, the specific process of enumeration is as follows: the embedded controller 101 obtains the ID of the switch chip 101 in which it is located. Each switch chip 101 has a unique ID, which can be a unique identification code of the switch chip 101. The embedded controller 1011 also obtains the number of each port on the switch chip 101, and concatenates the ID of the switch chip 101 and the port number to form the ID of each port. The port ID is a global ID, and each port ID of each switch chip 101 is unique. Figure 2 shows two switch chips 101, each with three ports. Their respective switch chip IDs are 0001 and 0002. For each port on the switch chip 101 with the switch chip ID 0001, the corresponding port IDs are 0001:01:00.0, 0001:02:00.0, and 0001:03:00.0. For each port on the switch chip 101 with the switch chip ID 0002, the corresponding port IDs are 0002:01:00.0, 0002:02:00.0, and 0002:03:00.0. For each port, the embedded controller 1011 determines whether the port is connected to an accelerator card 201, a processor 301, or a port on another switch chip 101. If so, it also obtains resource information about the accelerator card 201 or processor 301. The bandwidth and rate of the port are technical parameters of the switch chip 101 , and the embedded controller 1011 can obtain the technical parameters of the switch chip 101 .

[0050] In this embodiment, the embedded controller 1011 in each switching chip 101 actively uploads chip information to the management controller 102, and the management controller 102 does not need to actively access the switching chip 101 to obtain the corresponding chip information, thereby reducing the occupancy of the communication network in the switching unit 100 and improving the communication efficiency during computing task processing.

[0051] Specifically, after the management controller 102 receives the chip information sent by each embedded controller 1011, it has a global control of the communication network topology formed by each switching chip 101 in the switching unit 100, and can maintain a global information table containing the chip information of each switching chip 101. Based on the global information table, the virtual bridge (Virtual Bridge) of the switching unit 100 can be enumerated, thereby uniformly managing the acceleration card resources and processor resources connected to the switching chip 101.

[0052] It should be noted that: after the target switching chip receives the resource link reconstruction instruction issued by the management controller 102, the embedded controller 1011 in each target switching chip is also used to change the port usage information of the corresponding port in the target switching chip, and send the updated chip information to the management controller 102, so that the management controller 102 updates the chip information of each switching chip 101, that is, updates the above-mentioned global information table.

[0053] In some embodiments, the management controller 102 is configured to minimize link communication overhead, based on preset task resource requirements, the switch chip ID, the IDs of each switch chip port, the bandwidth of the port, the rate of the port, port connection information, and port usage information, to search for the target switch chip ID and the target port ID on each target switch chip, and generate a resource link reconstruction instruction including the target switch chip ID and the target port ID on each target switch chip. Specifically, the management controller 102 can configure TLP (Transaction Layer Packet) forwarding based on global address ID routing and establish destination address lookup tables (DLUTs) to implement TLP routing for complex topologies. Among them, the minimum link communication overhead can be the minimum data transmission delay. With the minimum data transmission delay as the goal, according to the task resource requirements, the switch chip ID, the IDs of each port of the switch chip, the port connection information and port usage information of the switch chip 101, first find out the unassigned ports of the switch chip 101, and then find the target switch chip ID and the target port ID on each target switch chip that can minimize the data transmission delay of the resource link according to the port bandwidth and the port rate. The specific search algorithm is similar to the routing algorithm of network routing, and it is only necessary to write the routing algorithm into the management controller 102 in advance.

[0054] The management controller 102 can not only reconfigure resource links by searching for the target switch chip ID and the target port ID on each target switch chip according to a preset routing algorithm, but can also reconfigure resource links based on the target switch chip ID and the target port ID on each target switch chip selected by the user. Therefore, in some embodiments, the management controller 102 is further configured to display the preset task resource requirements, switch chip ID, switch chip port IDs, port bandwidth, port rate, port connection information, and port usage information on a display device in a graphical interface, and receive resource link reconfiguration instructions input via the graphical interface. Specifically, the management controller 102 displays the acquired switching chip ID, switching chip port IDs, port bandwidth, port rate, port connection information and port usage information of the switching chip 101 in the form of a network topology diagram on the display interface. The user can intuitively see which ports of the switching chip 101 have been allocated to the resource link, and then select the resource link that meets the task resource requirements from the unallocated ports. Of course, the user can choose a resource link with the lowest communication overhead based on manual calculation.

[0055] As shown in FIG3 , the management controller 102 in the above embodiment is different from the management controller in the traditional heterogeneous resource server system with fixed links. It can communicate with the embedded controller 1011 in the switch chip 101, obtain relevant information about the port (IO port in FIG3 ) of the switch chip 101 in real time, and can also configure the properties of the port, including: the type of port (uplink port, internal port or downlink port), the port Bifurcation setting, the port clock setting, the port resource reservation setting (not connected to the accelerator card 201, the processor 301 and other switch chips 101), etc. Based on the Fabric connection between the switch chips 101, TLP forwarding, GID (Global Identification) address routing and DLUT establishment and maintenance are realized, so as to find the target switch chip ID corresponding to the resource link and the port ID on the target switch chip. Of course, the management controller 102 also has other functions in the traditional heterogeneous resource server system with fixed links, such as: providing a rich peripheral low-speed protocol, such as: UART (Universal Asynchronous Receiver / Transmitter), GPIO (General-Purpose Input / Output Ports), etc., supporting secure boot, ensuring chip security, and supporting AER (Advanced Error Reporting), real-time monitoring of I / O resource health status and other fault monitoring mechanisms.

[0056] In some embodiments, as shown in FIG4 , the switching unit 100 includes two switching chips groups. In FIG4 , the upper row of switching chips 101 is one group, and the lower row of switching chips 101 is another group. Each switching chips group includes at least one switching chip 101. In FIG4 , each group includes four switching chips 101, and the number of switching chips 101 in each switching chips group is less than the total number of ports of the switching chips 101. Any switching chip 101 in the first switching chips group is connected to each switching chip 101 in the second switching chips group through an internal port, and any switching chip 101 in the second switching chips group is connected to each switching chip 101 in the first switching chips group through an internal port. That is, any switching chip 101 in the same group is fully connected to all switching chips 101 in the other group, and the switching chips in the same switching chips group are not directly connected. Of the remaining ports on all switch chips 101, at least one port serves as an uplink port connected to the processor 301, and at least two ports serve as downlink ports connected to the accelerator card 201. Specifically, all remaining ports on the switch chips 101 are connected to either the processor 301 or the accelerator card 201. The server system of this embodiment enables multiple processors 301 to share an accelerator card resource pool, while also integrating multiple heterogeneous accelerator cards 201 within a single server system.

[0057] Furthermore, as shown in FIG5 , each switching chipset includes four switching chips 101, each having nine ports. Each switching chip 101 in the first switching chipset is connected to four switching chips 101 in the second switching chipset via four internal ports, and each switching chip 101 in the second switching chipset is connected to four switching chips 101 in the first switching chipset via four internal ports. In other words, each switching chip 101 provides five external ports. Of the remaining 40 ports on all switching chips 101, eight serve as uplink ports connected to the eight processors 301, and the remaining 32 serve as downlink ports connected to the 32 accelerator cards 201. Figure 5 is a schematic diagram of the structure of a multi-accelerator heterogeneous server with 8 processors 301 and 32 accelerator cards. The switching chips 101 are designed in two groups. The switching chips 101 between the groups are fully connected through internal ports. The remaining 40 ports, 8 uplink ports are connected to 8 processors 301, and 32 downlink ports are connected to 32 accelerator cards 201. 32 accelerator cards 201, for example: 32 GPUs can complete large-scale graphics training of artificial intelligence models.

[0058] Among them, the 32 accelerator cards 201 and the 8 processors 301 can all be different types of devices. As shown in Figure 5, the accelerator card 201 includes: GPU, FPGA and NPU (Neural Processing Unit) to complete different types of computing tasks at the same time, and the processor 301 includes: AMD CPU and Intel CPU, which can complete computing tasks developed under different CPU architectures, and is more flexible in processing computing tasks.

[0059] In some embodiments, the switching unit 100 includes multiple switching chips 101, the number of switching chips 101 is less than the number of ports of the switching chip 101, and any switching chip 101 is connected to the remaining switching chips 101 through an internal port, that is, any switching chip 101 is fully connected to the other switching chips 101. Among the remaining ports of all switching chips 101, at least one port is connected to the processor 301 as an uplink port, and at least two ports are connected to the accelerator card 201 as downlink ports. In this embodiment, all switching chips 101 are fully connected. While the server system integrates multiple accelerator cards 201, the server internal bus switching is used as the core, and non-blocking internal bus switching is used to ensure the communication bandwidth and efficiency of multiple accelerator cards, reduce communication delays, improve the parallel capability of artificial intelligence, effectively solve the problem of insufficient computing power of a single accelerator card, and thus improve the computing power of the system.

[0060] Furthermore, as shown in Figure 6 , the switching unit includes six switching chips 101, namely SW0 to SW5 in Figure 6 . Each switching chip 101 has nine ports. Any switching chip 101 is connected to the remaining switching chips 101 via five internal ports. Of the remaining ports on all switching chips 101, 16 ports serve as downlink ports connected to accelerator cards, namely GPU0 to GPU15 in Figure 6 , and at least four remaining ports serve as uplink ports connected to four processors, namely CPU0 to CPU3. This embodiment is a schematic diagram of a multi-accelerator card heterogeneous server structure with four processors 301 and 16 accelerator cards 201. The switching chips 101 form a fully connected communication topology network.

[0061] In some embodiments, at least one processor 301 is connected to the uplink ports of different switch chips 101. For example, CPU3 in Figure 6 can be replaced with CPU0, where CPU0 is connected to ports connected to SW0 and SW2, respectively. In particular, when the number of processor 301 resources is small, one processor 301 can be connected to the uplink ports of two or more switch chips 101. When resource links are reconfigured, links passing through fewer switch chips 101 can be selected, thereby improving communication efficiency and enhancing the processing performance of computing tasks.

[0062] As shown in Figures 7 and 8 , the switching unit 100 further includes a first baseboard controller 103 and a first complex programmable logic chip 104. The first baseboard controller 103 connects the first complex programmable logic chip 104 to the management controller 102, and the first complex programmable logic chip 104 connects the management controller 102 to the switching chip 101. The switching unit 100 also includes a clock generator 105 and a power module 106. The power module 106 provides power to the switching chip 101, the management controller 102, the first baseboard controller 103, the first complex programmable logic chip 104, and the clock generator 105. It should be noted that the ports connecting the accelerator card 201 and the processor 301 to the switching chip 101, as well as the ports interconnecting the switching chips 101, are high-speed interfaces for data transmission. The management controller 102, the first baseboard controller 103, and the first complex programmable logic chip 104 are each connected to the switching chip 101 via a control interface (i.e., a low-speed interface).

[0063] The first complex programmable logic chip 104 is used to control the power-on and power-off timing of the management controller 102 and the switch chip 101 . Specifically, it is combined with the clock generator 105 to control the power-on and power-off timing of the management controller 102 and the switch chip 101 .

[0064] The first baseboard controller 103 is used to write preset task resource requirements to the management controller 102 and receive link information of the resource link from the management controller. This link information includes the processor ID, accelerator card ID, switch chip ID, and port ID on the switch chip occupied by the resource link. The task resource requirements are input to the first baseboard controller 103 by the application, then written to the management controller 102 by the first baseboard controller 103. After receiving the link information of the resource link, the first baseboard controller 103 feeds back the link information to the front-end application.

[0065] 7 and 8 , the management controller 102 and the first baseboard controller 103 are connected to the switching chip 101 based on a variety of interconnection links such as a UART expansion board, a USB expansion board, and an I2C expansion board, thereby establishing an internal management network of the high-performance switching unit 100 .

[0066] Furthermore, as shown in Figures 7 to 9, the management controller 102 is two, two redundant management controllers: a first management controller 1021 and a second management controller 1022. The first management controller 1021 and the second management controller 1022 are connected through a first switching chip 107, and the first switching chip 107 is connected to the first baseboard controller 103; the first baseboard controller 103 is also used to receive fault information sent by the first management controller 1021 or the second management controller 1022. After receiving the fault information of the first management controller 1021, the first switching chip 107 is controlled to disconnect the first management controller 1021 from the switching chip 101 and switch the second management controller 1022 to the switching chip 101; or after receiving the fault information of the second management controller 1022, the first switching chip 107 is controlled to disconnect the second management controller 1022 from the switching chip 101 and switch the first management controller 1021 to the switching chip 101. In the actual hardware structure, due to the large number of switching chips 101 and acceleration cards 201, the first management controller 1021 and the second management controller 1022 are connected to the switching chip 101 through an I2C expansion board, and the switching chip 101 is connected to the acceleration card 201 through an I2C expansion board.

[0067] In this embodiment, the first management controller 1021 and the second management controller 1022 are designed to be redundant with each other. The first baseboard controller 103 will write the task resource requirements into the first management controller 1021 and the second management controller 1022. When one management controller 102 fails, the other management controller 102 will be switched to continue running, thereby ensuring the stability of the server system.

[0068] In some embodiments, as shown in FIG9 , the heterogeneous accelerated computing pooling unit 200 further includes: a second baseboard controller 202 and a second complex programmable logic chip 203 , wherein the second baseboard controller 202 is connected to the second complex programmable logic chip 203 and the acceleration card 201 .

[0069] The second complex programmable logic chip 203 is used to control the power-on and power-off timing of the accelerator card 201 .

[0070] The second baseboard controller 202 is used to obtain status information of the acceleration card 201 .

[0071] Furthermore, the heterogeneous accelerated computing pooling unit 200 also includes a second switching chip 204, through which the accelerator card 201 connects to the second baseboard controller 202, the second complex programmable logic chip 203, and the switch chip 101. The second baseboard controller 202 is configured to control the second switching chip 204 to switch the connection between the accelerator card 201 and the second baseboard controller 202. In particular, when there are a large number of accelerator cards 201, the second switching chip 204 controls the connection between the accelerator card 201 assigned to the resource link and the second baseboard controller 202 to obtain status information of the accelerator card 201.

[0072] In some embodiments, as shown in FIG10 , the heterogeneous accelerated computing pooling unit 200 further includes: an interface board 400 and an adapter substrate 500, and the adapter substrate 500 is provided with an adapter interface 501 and a slot 502 (slot). Among them, the interface board 400 is a high-speed interface board, which is used for connecting between the accelerator card 201 and the switching chip 101. Each connection of the interface board 400 includes two high-speed interfaces and a high-speed signal retimer. The two high-speed interfaces are respectively connected to the high-speed signal retimer. Of the two high-speed interfaces, one is used to connect to the accelerator card 201, and the other is used to connect to the switching chip 101. In actual applications, especially when there are a large number of accelerator cards 201 and switching chips 101, considering the actual size of the server chassis and the spatial layout, multiple switching chips 101 and accelerator cards 201 can be connected in the following three ways:

[0073] Method 1: The accelerator card 201 is connected to the interface board 400 via the adapter card 600, and the interface board 400 is connected to the downlink port of the switch chip 101. Specifically, the accelerator card 201 is connected to the high-speed port on the interface board 400 near the heterogeneous accelerated computing pooling unit 200 through the adapter card 600, and the high-speed port on the interface board 400 near the switching unit 100 is connected to the switch chip 101.

[0074] Method 2: The accelerator card 201 connects to the adapter interface 501 in the adapter baseboard 500 via the adapter card 600. The adapter interface 501 connects to the interface board 400, which in turn connects to the downlink port of the switch chip 101. Specifically, the adapter interface 501 connects to the high-speed interface on the interface board 400 near the heterogeneous accelerated computing pooling unit 200, while the high-speed interface on the interface board 400 near the switching unit 100 connects to the switch chip 101.

[0075] Method 3: Accelerator card 201 is connected to slot 502, slot 502 is connected to adapter interface 501, adapter interface 501 is connected to interface board 400, and interface board 400 is connected to the downlink port of switch chip 101. Specifically, adapter interface 501 is connected to the high-speed interface on the interface board 400 near the heterogeneous accelerated computing pooling unit 200, and the high-speed interface on the interface board 400 near the switching unit 100 is connected to the switch chip 101.

[0076] The three connection methods described above can achieve flexible layout of the switch chip 101 and the accelerator card 201 in a multi-accelerator card server.

[0077] In some embodiments, as shown in FIG11 , the general computing resource pooling unit 300 further includes: a third baseboard controller 302 and a third complex programmable logic chip 303 , and the third baseboard controller 302 is connected to the third complex programmable logic chip 303 and the processor 301 .

[0078] The third complex programmable logic chip 303 is used to control the power-on and power-off timing of the processor 301 .

[0079] The third baseboard controller 302 is used to obtain status information of the processor 301 .

[0080] In some embodiments, as shown in Figure 11, the switching unit 100 also includes: a first baseboard controller 103 and a first complex programmable logic chip 104, the first complex programmable logic chip 104 is respectively connected to the switching chip 101, the first baseboard controller 103 and the management controller 102, and the management controller 102 is connected to the first baseboard controller 103.

[0081] The heterogeneous accelerated computing pooling unit 200 further includes: a second baseboard controller 202 and a second complex programmable logic chip 203 , and the second complex programmable logic chip 203 is connected to the acceleration card 201 and the second baseboard controller 202 respectively.

[0082] The general computing resource pooling unit 300 further includes: a third baseboard controller 302 and a third complex programmable logic chip 303 . The third complex programmable logic chip 303 is connected to the processor 301 and the third baseboard controller 302 , respectively.

[0083] The first baseboard controller 103 , the second baseboard controller 202 , the third baseboard controller 302 and the management controller 102 are all connected to an external TOR switch 700 via Ethernet, and interact with external applications via the TOR switch 700 .

[0084] In this embodiment, the third complex programmable logic chip 303 is connected to the first complex programmable logic chip 104, and the first complex programmable logic chip 104 is connected to the second complex programmable logic chip 203. Each complex programmable logic chip is used to control the power-on and power-off timing of its respective unit. The second complex programmable logic chip 203 first controls the heterogeneous accelerated computing pooling unit 200 to power on first, specifically, controls the accelerator card 201 and the second baseboard controller 202 to power on first. Then, the first complex programmable logic chip 104 controls the switching unit 100 to power on, specifically, controls the switching chip 101 and the first baseboard controller 103 to power on. Finally, the third complex programmable logic chip 303 controls the general computing resource pooling unit 300 to power on, specifically, controls the processor 301 and the third baseboard controller 302 to power on last, to ensure the correct timing of the entire server system. For a certain resource link, the accelerator card 201, the switching chip 101, and the processor 301 are powered on in sequence, and the power-off sequence is the opposite of the power-on sequence. In the event of an emergency (for example, a resource link failure), each complex programmable logic chip resets and restarts or powers off each device in the corresponding link to ensure the stability and reliability of other links.

[0085] In actual applications, the management controller 102 of each of the above-mentioned embodiments establishes a business-aware resource reconstruction decision system through software definition, realizing functions such as dynamic allocation of uplink and downlink resource links, link topology switching, and dynamic reconstruction of data links, completing intelligent reconstruction of hardware resources, and realizing pooling and centralized management of processor resources and accelerator card resources, thereby dynamically adjusting, flexibly combining, and intelligently allocating them, improving the computing efficiency and response rate of the entire system, and realizing intelligent and efficient heterogeneous computing. This enables the multi-accelerator card heterogeneous servers of each of the above-mentioned embodiments to meet the application requirements of current mainstream artificial intelligence large models and other large-scale computing business scenarios. In the multi-accelerator card heterogeneous servers of the above-mentioned embodiments, multiple machines can achieve ultra-large-scale computing power clustering through system network whole-machine clustering, and the clustering method is implemented through Ethernet switches.

[0086] The present application also provides a resource link reconstruction method, which is implemented based on the multi-accelerator card heterogeneous server of each of the above embodiments. The method is applied to a management controller, as shown in FIG12 , and includes:

[0087] Step S1210: Obtain the task resource requirements and the chip information of each current switching chip. Specifically, referring to Figures 1 and 2, the management controller 102 obtains the task resource requirements and the chip information of each current switching chip 101, and can obtain the chip information of each current switching chip 101 from the embedded controller 1011 in the switching chip 101. After the management controller 102 receives the chip information sent by each embedded controller 1011, it has a global understanding of the communication network topology formed by each switching chip 101 in the switching unit 100, and can maintain a global information table containing the chip information of each switching chip 101. Based on the global information table, the virtual bridge (Virtual Bridge) of the switching unit 100 can be enumerated, thereby uniformly managing the accelerator card resources and processor resources connected to the switching chip 101.

[0088] Step S1220: Determine resource link reconfiguration instructions based on task resource requirements and current chip information of each switch chip. Specifically, the management controller 102 determines resource link reconfiguration instructions based on preset task resource requirements, switch chip ID, port bandwidth, port rate, port connection information, and port usage information.

[0089] Step S1230: Send a resource link reconfiguration instruction to each target switch chip to form a resource link for completing the computing task corresponding to the task resource requirement. Specifically, the management controller 102 sends a resource link reconfiguration instruction, including the ID of each target switch chip and the ID of the target port on each target switch chip, to the target switch chip. This establishes a communication protocol between the target switch chip and its port on the resource link, as well as the processor 301 and accelerator card 201 connected to the port. This allows efficient communication of data processed by the processor 301 and accelerator card 201 through the target switch chip to complete the computing task.

[0090] The resource link reconstruction method of the present application is implemented based on the above-mentioned multi-accelerator card heterogeneous server. The switching chip 101 connects the processor 301 and the accelerator card 201, and there is also interconnection between the switching chips 101, so as to provide high-bandwidth, low-latency and multi-channel interconnection between the accelerator cards 201, meeting the computing power requirements of high-performance computing tasks. According to the differences in the categories of processor resources for general computing and accelerator card resources for heterogeneous accelerated computing, similar computing resources in the resource pool can be integrated according to the computing tasks, and the hardware structure provides the prerequisite for the on-demand reorganization of different processor resources and accelerator card resources to form a resource link. On this basis, the management controller 102 Based on the task resource requirements and the current chip information of each switching chip 101, a resource link reconstruction instruction is determined, and the resource link reconstruction instruction is sent to each target switching chip to form a resource link for completing the computing task corresponding to the task resource requirements. That is, according to the task resource requirements and the current chip information of each switching chip 101, a suitable switching chip 101 and the corresponding port are selected, so that there is a higher network communication efficiency between multiple accelerator cards 201, and between the accelerator card 201 and the processor 301, so as to improve the task processing performance, and achieve the purpose of improving the system computing performance by improving communication efficiency when more accelerator cards 201 are integrated into the server system. Moreover, the resource link is dynamically reconstructed based on the preset task resource requirements and the current chip information of each switching chip 101. Compared with the traditional fixed resource link, it can more flexibly allocate processor resources and accelerator card resources to avoid resource waste.

[0091] Step S1220 specifically includes: with the goal of minimizing link communication overhead, based on preset task resource requirements, switch chip ID, switch chip port IDs, port bandwidth, port rate, port connection information, and port usage information, searching for the target switch chip ID and the target port ID on each target switch chip, and generating a resource link reconstruction instruction including the target switch chip ID and the target port ID on each target switch chip. Specifically, with reference to Figures 1 and 7, the management controller 102 can implement TLP (Transaction Layer Packet) forwarding configuration based on global address ID routing and establish destination address lookup tables (DLUTs) to implement TLP routing for complex topologies. Among them, the minimum link communication overhead can be the minimum data transmission delay. With the minimum data transmission delay as the goal, according to the task resource requirements, the switch chip ID, the IDs of each port of the switch chip, the port connection information and the port usage information, first find out the unassigned ports of the switch chip 101, and then find the target switch chip ID and the target port ID on each target switch chip that can minimize the data transmission delay of the resource link according to the port bandwidth and the port rate. The specific search algorithm is similar to the routing algorithm of network routing, and it is only necessary to write the routing algorithm into the management controller 102 in advance.

[0092] The above step S1220 may also be implemented as follows. The step S1220 includes:

[0093] The preset task resource requirements, switch chip ID, switch chip port connection information and port usage information are displayed on a display device in a graphical interface.

[0094] Receive resource link reconstruction instructions input through the graphical interface.

[0095] Specifically, referring to Figures 1 and 7, the management controller 102 displays the preset task resource requirements, the switch chip ID, the port connection information and port usage information of the switch chip 101 on a graphical interface on a display device, and receives a resource link reconstruction instruction input through the graphical interface. Specifically, the management controller 102 displays the switch chip ID, the port ID of each switch chip, the bandwidth of the port, the port rate, the port connection information and port usage information of the switch chip 101 in the form of a network topology diagram on the display interface based on the obtained switch chip ID, the port ID of each switch chip, the bandwidth of the port, the port rate, the port connection information and port usage information of the switch chip 101. The user can intuitively see which ports of the switch chip 101 have been allocated to the resource link, and then select the resource link that meets the task resource requirements from the unallocated ports, and input the resource link reconstruction instruction to the management controller 102 through the graphical interface exchange. Of course, the user can choose a resource link with the lowest communication overhead based on manual calculation.

[0096] The resource link reconstruction device provided in the present application is described below. The resource link reconstruction device described below and the resource link reconstruction method described above can be referenced to each other.

[0097] The resource link reconstruction device of the present application is implemented based on the aforementioned multi-accelerator card heterogeneous server. The device is applied to the management controller in the multi-accelerator card heterogeneous server. The device is shown in FIG13 and includes:

[0098] The information acquisition module 1310 is used to obtain task resource requirements and chip information of each current switching chip.

[0099] The instruction determination module 1320 is used to determine the resource link reconstruction instruction according to the task resource requirement and the chip information of each current switching chip.

[0100] The instruction sending module 1330 is used to send a resource link reconstruction instruction to each target switching chip to form a resource link for completing the computing task corresponding to the task resource requirement.

[0101] The resource link reconstruction device of the present application is implemented based on the above-mentioned multi-accelerator card heterogeneous server. The switching chip connects the processor and the accelerator card, and there is also interconnection between the switching chips, thereby providing high-bandwidth, low-latency and multi-channel interconnection between the accelerator cards to meet the computing power requirements of high-performance computing tasks. According to the differences in the categories of processor resources for general computing and accelerator card resources for heterogeneous accelerated computing, the same type of computing resources in the resource pool can be integrated according to the computing tasks. In terms of hardware structure, it provides the prerequisite for the on-demand reorganization of different processor resources and accelerator card resources to form resource links. On this basis, the management controller determines the resource link reconstruction instruction based on the preset task resource requirements and the current chip information of each switching chip, and sends the resource link reconstruction instruction to each target switching chip to form a resource link for completing the computing task corresponding to the task resource requirement. That is, the appropriate switching chip and corresponding port are selected according to the task resource requirement and the current chip information of each switching chip, thereby achieving higher network communication efficiency between multiple accelerator cards and between the accelerator card and the processor, thereby improving task processing performance, achieving the purpose of improving system computing performance by improving communication efficiency when more accelerator cards are integrated in the server system. Moreover, the resource link is dynamically reconstructed based on the preset task resource requirements and the current chip information of each switching chip. Compared with the traditional fixed resource link, it can more flexibly allocate processor resources and accelerator card resources to avoid resource waste.

[0102] Optionally, the instruction determination module 1320 is specifically used to search for the target switching chip ID and the target port ID on each target switching chip based on preset task resource requirements, switching chip ID, each port ID of the switching chip, port bandwidth, port rate, port connection information and port usage information, with the goal of minimizing link communication overhead, and generate a resource link reconstruction instruction including the target switching chip ID and the target port ID on each target switching chip.

[0103] Optionally, the instruction determination module 1320 is specifically used to display the preset task resource requirements, switching chip ID, switching chip port IDs, port bandwidth, port rate, port connection information and port usage information on a display device in a graphical interface; and receive resource link reconstruction instructions input by the graphical interface.

[0104] FIG14 illustrates a schematic diagram of the physical structure of an electronic device. As shown in FIG14 , the electronic device may include: a processor 1410, a communications interface 1420, a memory 1430, and a communication bus 1440. The processor 1410, the communications interface 1420, and the memory 1430 communicate with each other via the communication bus 1440. The processor 1410 may invoke logic instructions in the memory 1430 to execute the resource link reconstruction method of any one or more of the above-described embodiments.

[0105] In addition, the logic instructions in the above-mentioned memory 1430 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0106] On the other hand, the present application also provides a computer-readable instruction product, which includes computer-readable instructions. The computer-readable instructions can be stored on a non-transitory computer-readable storage medium. When the computer-readable instructions are executed by a processor, the computer can execute the resource link reconstruction method of any one or more of the above-mentioned embodiments.

[0107] On the other hand, the present application also provides a non-transitory computer-readable storage medium, as shown in Figure 15, on which computer-readable instructions are stored. When the computer-readable instructions are executed by the processor, they are implemented to execute the resource link reconstruction method of any one or more of the above-mentioned embodiments. The method is implemented based on a multi-acceleration card heterogeneous server of any one or more of the above-mentioned embodiments, and the method is applied to a management controller.

[0108] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units. That is, they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the solutions of this embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0109] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, or of course, by hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the existing technology can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or certain parts of the embodiments.

[0110] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application.

Claims

1. A multi-accelerator card heterogeneous server, characterized in that: include: Switching unit, heterogeneous accelerated computing pooling unit and general computing resource pooling unit; The general computing resource pooling unit includes at least one processor, and the heterogeneous accelerated computing pooling unit includes at least two accelerator cards, wherein the processor and the accelerator cards are heterogeneous. The switching unit includes: a management controller and at least two switching chips, any of the switching chips is connected to at least one other switching chip in the switching unit through an internal port, the processor is connected to the uplink port of the switching chip, and the accelerator card is connected to the downlink port of the switching chip; as well as The management controller is connected to each of the switching chips, and is used to determine the resource link reconstruction instruction based on the preset task resource requirements and the current chip information of each switching chip, and send the resource link reconstruction instruction to each target switching chip to form a resource link for completing the computing task corresponding to the task resource requirements.

2. The multi-accelerator card heterogeneous server according to claim 1, characterized in that: Each of the switching chips includes an embedded controller, and the embedded controller is used to enumerate chip information of the switching chip where it is located and send the chip information to the management controller.

3. The multi-accelerator card heterogeneous server according to claim 1, characterized in that: The management controller is used to search for the target switch chip ID and the target port ID on each target switch chip based on the preset task resource requirements, switch chip ID, each port ID of the switch chip, port bandwidth, port rate, port connection information and port usage information, with the goal of minimizing link communication overhead, and generate a resource link reconstruction instruction including the target switch chip ID and the target port ID on each target switch chip.

4. The multi-accelerator card heterogeneous server according to claim 1, characterized in that: The management controller is also used to display the preset task resource requirements, switch chip ID, switch chip port IDs, port bandwidth, port rate, port connection information and port usage information on a display device in a graphical interface, and receive the resource link reconstruction instructions input by the graphical interface.

5. The multi-accelerator card heterogeneous server according to any one of claims 1 to 4, characterized in that: The switching unit includes two switching chips groups, each switching chips group includes at least one switching chip, the number of switching chips in each switching chips group is less than the total number of ports of the switching chips, any switching chip in the first switching chips group is connected to each switching chip in the second switching chips group through an internal port, and any switching chip in the second switching chips group is connected to each switching chip in the first switching chips group through an internal port. Among the remaining ports of all switching chips, at least one port is connected to the processor as an uplink port, and at least two ports are connected to the accelerator card as downlink ports.

6. The multi-accelerator card heterogeneous server according to claim 5, characterized in that: Each switching chipset includes four switching chips, each switching chip has nine ports. Any switching chip in the first switching chipset is connected to the four switching chips in the second switching chipset through four internal ports, and any switching chip in the second switching chipset is connected to the four switching chips in the first switching chipset through four internal ports. Among the remaining ports of all switching chips, 8 ports serve as uplink ports to connect to the 8 processors, and the remaining 32 ports serve as downlink ports to connect to the 32 acceleration cards.

7. The multi-accelerator card heterogeneous server according to any one of claims 1 to 4, characterized in that: The switching unit includes multiple switching chips, the number of switching chips is less than the number of ports of the switching chip, any switching chip is connected to the remaining switching chips through an internal port, and among the remaining ports of all switching chips, at least one port is connected to the processor as an uplink port, and at least two ports are connected to the accelerator card as downlink ports.

8. The multi-accelerator card heterogeneous server according to claim 7, characterized in that: The switching unit includes six switching chips, each switching chip has nine ports. Any switching chip is connected to the remaining switching chips through five internal ports. Among the remaining ports of all switching chips, 16 ports are connected to the acceleration card as downlink ports, and the remaining at least 4 ports are connected to the 4 processors as uplink ports.

9. The multi-accelerator card heterogeneous server according to any one of claims 1 to 4, characterized in that: At least one processor is connected to uplink ports of different switch chips.

10. The multi-accelerator card heterogeneous server according to any one of claims 1 to 4, characterized in that: The switching unit further includes: a first baseboard controller and a first complex programmable logic chip, wherein the first baseboard controller is connected to the first complex programmable logic chip and the management controller, and the first complex programmable logic chip is connected to the management controller and the switching chip; The first complex programmable logic chip is used to control the power-on and power-off timing of the management controller and the switch chip; and The first baseboard controller is used to write the preset task resource requirements into the management controller and receive link information of the resource link fed back by the management controller. The link information includes: the processor ID, accelerator card ID, switch chip ID and port ID on the switch chip occupied by the resource link.

11. The multi-accelerator card heterogeneous server according to claim 10, characterized in that: There are two management controllers, which are redundant with each other: a first management controller and a second management controller, wherein the first management controller and the second management controller are connected via a first switching chip, and the first switching chip is connected to the first substrate controller; The first baseboard controller is further configured to receive fault information sent by the first management controller or the second management controller, and upon receiving the fault information from the first management controller, control the first switching chip to disconnect the first management controller from the switching chip and switch the connection between the second management controller and the switching chip; Alternatively, after receiving the fault information of the second management controller, the first switching chip is controlled to disconnect the second management controller from the switching chip, and switch the connection between the first management controller and the switching chip.

12. The multi-accelerator card heterogeneous server according to any one of claims 1 to 4, characterized in that: The heterogeneous accelerated computing pooling unit further includes: a second baseboard controller and a second complex programmable logic chip, wherein the second baseboard controller is connected to the second complex programmable logic chip and the accelerator card; The second complex programmable logic chip is used to control the power-on and power-off timing of the accelerator card; and The second baseboard controller is used to obtain status information of the accelerator card.

13. The multi-accelerator card heterogeneous server according to claim 12, characterized in that: The heterogeneous accelerated computing pooling unit further includes: a second switching chip, and the acceleration card is connected to the second baseboard controller, the second complex programmable logic chip and the switching chip through the second switching chip.

14. The multi-accelerator card heterogeneous server according to any one of claims 1 to 4, characterized in that: The general computing resource pooling unit further includes: a third baseboard controller and a third complex programmable logic chip, wherein the third baseboard controller is connected to the third complex programmable logic chip and the processor; The third complex programmable logic chip is used to control the power-on and power-off timing of the processor; and The third baseboard controller is used to obtain status information of the processor.

15. The multi-accelerator card heterogeneous server according to any one of claims 1 to 4, characterized in that: The heterogeneous accelerated computing pooling unit further includes: an interface board and a transfer substrate, wherein the transfer substrate is provided with a transfer interface and a slot. The accelerator card is connected to the interface board via an adapter card, and the interface board is connected to the downlink port of the switch chip; Alternatively, the accelerator card is connected to the adapter interface via an adapter card, the adapter interface is connected to the interface board, and the interface board is connected to the downlink port of the switch chip; Alternatively, the acceleration card is connected to the slot, the slot is connected to the adapter interface, the adapter interface is connected to the interface board, and the interface board is connected to the downlink port of the switching chip.

16. The multi-accelerator card heterogeneous server according to any one of claims 1 to 4, characterized in that: The switching unit further includes: a first baseboard controller and a first complex programmable logic chip, wherein the first complex programmable logic chip is respectively connected to the switching chip, the first baseboard controller and the management controller, and the management controller is connected to the first baseboard controller; The heterogeneous accelerated computing pooling unit further includes: a second baseboard controller and a second complex programmable logic chip, wherein the second complex programmable logic chip is connected to the acceleration card and the second baseboard controller respectively; The general computing resource pooling unit further includes: a third baseboard controller and a third complex programmable logic chip, wherein the third complex programmable logic chip is connected to the processor and the third baseboard controller respectively; and The third complex programmable logic chip is connected to the first complex programmable logic chip, and the first complex programmable logic chip is connected to the second complex programmable logic chip.

17. A resource link reconstruction method, characterized in that: The method is implemented based on a multi-accelerator card heterogeneous server according to any one of claims 1 to 16 and is applied to a management controller, the method comprising: Obtain task resource requirements and chip information of each current switching chip; Determining a resource link reconstruction instruction according to the task resource requirement and the current chip information of each switching chip; and The resource link reconstruction instruction is sent to each target switching chip to form a resource link for completing the computing task corresponding to the task resource requirement.

18. The resource link reconstruction method according to claim 17, characterized in that: Determining a resource link reconstruction instruction based on the task resource requirement and the current chip information of each switching chip includes: With the goal of minimizing link communication overhead, based on the preset task resource requirements, switch chip ID, switch chip port IDs, port bandwidth, port rate, port connection information and port usage information, the target switch chip ID and the target port ID on each target switch chip are searched, and a resource link reconstruction instruction including the target switch chip ID and the target port ID on each target switch chip is generated.

19. The resource link reconstruction method according to claim 17, characterized in that: Determining a resource link reconstruction instruction based on the task resource requirement and the current chip information of each switching chip includes: Displaying the preset task resource requirements, switch chip ID, switch chip port IDs, port bandwidth, port rate, port connection information, and port usage information on a display device in a graphical interface; and The resource link reconstruction instruction inputted through the graphical interface is received.

20. A resource link reconstruction device, characterized in that: The device is implemented based on a multi-accelerator card heterogeneous server according to any one of claims 1 to 15 and is applied to a management controller. The device includes: Information acquisition module, used to obtain task resource requirements and chip information of each current switching chip; An instruction determination module, configured to determine a resource link reconstruction instruction based on the task resource requirements and chip information of each current switching chip; and The instruction sending module is used to send the resource link reconstruction instruction to each target switching chip to form a resource link for completing the computing task corresponding to the task resource requirement.

21. An electronic device comprising a memory, a processor, and computer-readable instructions stored in the memory and executable on the processor, wherein: When the processor executes the program, the resource link reconstruction method according to any one of claims 17 to 19 is implemented.

22. A non-transitory computer-readable storage medium having computer-readable instructions stored thereon, characterized in that: When the computer-readable instructions are executed by a processor, the resource link reconstruction method according to any one of claims 17 to 19 is implemented.

23. The multi-accelerator card heterogeneous server according to claim 1, characterized in that: The switching unit further includes: a first baseboard controller and a first complex programmable logic chip, wherein the first complex programmable logic chip is respectively connected to the switching chip, the first baseboard controller and the management controller, and the management controller is connected to the first baseboard controller; The heterogeneous accelerated computing pooling unit further includes: a second baseboard controller and a second complex programmable logic chip, wherein the second complex programmable logic chip is connected to the acceleration card and the second baseboard controller respectively; The general computing resource pooling unit further includes: a third baseboard controller and a third complex programmable logic chip, wherein the third complex programmable logic chip is connected to the processor and the third baseboard controller respectively; The third complex programmable logic chip is connected to the first complex programmable logic chip, and the first complex programmable logic chip is connected to the second complex programmable logic chip; and The second complex programmable logic chip first controls the acceleration card and the second baseboard controller to power on, the first complex programmable logic chip then controls the switching chip, the management controller and the first baseboard controller to power on, and the third complex programmable logic chip finally controls the processor and the third baseboard controller to power on. The power-off order is the opposite of the power-on order.

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