Display panel and display apparatus

Abstract

The present application discloses a display panel and a display apparatus. A non-display region of the display panel comprises a bending region and a DEMUX circuit located on the side of the bending region away from a display region. In the display panel, the non-display region in which the DEMUX circuit is provided comprises: a substrate; and a buffer layer, a thin-film transistor element, a first organic layer, a metal layer, and a second organic layer which are sequentially arranged on the substrate. Further, the metal layer covers the thin-film transistor element, and is used for receiving a direct-current signal and transmitting the direct-current signal to the display region.

Description

Display panel and display device

[0001] This application claims priority to Chinese patent application No. 202410132227.5 filed on January 30, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present application relates to the field of display technology. Background Art

[0003] Active-matrix organic light-emitting diode (AMOLED) display panels are becoming the next-generation display technology due to their high contrast, wide color gamut, and low power consumption. Compared to traditional LCD (Liquid Crystal Display) panels, OLED (Organic Light-Emitting Diode) display panels are easier to make flexible, making them a key technology for wearable and foldable products. With the advancement of OLED panel technology, narrow bezels have become a differentiating feature that attracts a wide range of users. Furthermore, the use of Ramless Integrated Circuits (ICs) can significantly reduce the overall cost of display screens, attracting the attention of numerous terminal manufacturers. Regarding screen design, the use of Ramless ICs requires the inclusion of a demux circuit (multi-channel selection circuit) in the panel driver architecture. This demux circuit takes up a lot of space, compromising the narrow bezel design. Panels currently using demux circuits place the demux circuit above the bending area, which increases the size of the bottom bezel of the entire screen. SUMMARY OF THE INVENTION

[0004] The Demux panel places the Demux circuit above the Bending area, which will increase the bottom border of the entire screen.

[0005] In a first aspect, an embodiment of the present application provides a display panel, comprising a display area and a non-display area surrounding the display area, wherein the non-display area comprises a bending area and a multi-way selection circuit, wherein the multi-way selection circuit is located on a side of the bending area away from the display area, and wherein the non-display area of ​​the display panel, in which the multi-way selection circuit is located, comprises:

[0006] substrate;

[0007] a buffer layer formed on the substrate;

[0008] a thin film transistor element, formed on the buffer layer;

[0009] a first organic layer formed on the thin film transistor element;

[0010] a metal layer formed on the first organic layer, the metal layer covering the thin film transistor element, the metal layer being used to receive a DC signal and transmit it to the display area;

[0011] a second organic layer formed on the metal layer;

[0012] Wherein, the metal layer extends to an area of ​​the non-display area where the multi-way selection circuit is not provided;

[0013] Wherein, the metal layer is set as a power signal line.

[0014] In a second aspect, an embodiment of the present application provides a display panel, comprising a display area and a non-display area surrounding the display area, wherein the non-display area comprises a bending area and a multi-way selection circuit, wherein the multi-way selection circuit is located on a side of the bending area away from the display area, and wherein the non-display area of ​​the display panel, in which the multi-way selection circuit is located, comprises:

[0015] substrate;

[0016] a buffer layer formed on the substrate;

[0017] a thin film transistor element, formed on the buffer layer;

[0018] a first organic layer formed on the thin film transistor element;

[0019] a metal layer formed on the first organic layer, the metal layer covering the thin film transistor element, the metal layer being used to receive a DC signal and transmit it to the display area;

[0020] A second organic layer is formed on the metal layer.

[0021] In a third aspect, the present application provides a display device, comprising the display panel described in any one of the above items. Beneficial effects

[0022] The display panel and display device provided by the embodiments of the present application place the multiplexing circuit on the side of the bending region away from the display area. When bent, the multiplexing circuit bends behind the display panel, thereby achieving a narrow chin design. Furthermore, a metal layer for transmitting DC signals is provided above the thin-film transistor elements to cover the thin-film transistor elements, achieving signal shielding and preventing crosstalk between different AC transition signals, which could lead to unstable or inaccurate transmitted signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0024] FIG1 is a schematic structural diagram of an existing display panel;

[0025] FIG2 is a schematic structural diagram of a display panel according to an embodiment of the present application;

[0026] FIG3 is a partial schematic diagram of a display panel provided with a multi-way selection circuit in one embodiment of the present application;

[0027] FIG4 is a schematic cross-sectional view of a display panel according to an embodiment of the present application;

[0028] FIG5 is a partial schematic diagram of a display panel provided with a multi-way selection circuit in one embodiment of the present application;

[0029] FIG6 is a partial schematic diagram of a display panel provided with a multi-way selection circuit in one embodiment of the present application;

[0030] FIG. 7 is a schematic diagram showing a display panel in which a multiplexing circuit is disposed on a side of a bending region away from a display region in accordance with an embodiment of the present application.

[0031] Figure Numbers

[0032] 100, bending region; 200, multi-way selection circuit; 210, selection sub-circuit; 300, fan-shaped routing region; 400; chip; 1, substrate; 2, buffer layer; 3, thin-film transistor element; 31, semiconductor; 32, gate insulating layer; 33, gate electrode; 34, interlayer insulating layer; 35, source-drain electrode; 4, first organic layer; 5, metal layer; 6, second organic layer; 7, pixel defining layer; 8, control signal electrode. Modes for Carrying Out the Invention

[0033] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0034] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the described features. In the description of this application, "plurality" means two or more, unless otherwise specifically specified.

[0035] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or mutual communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0036] In this application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0037] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples, and the purpose is not to limit the present application. It should be understood by those skilled in the art that the embodiments of the present application can be modified or replaced by equivalents without departing from the spirit and scope of the present application, and such modifications or equivalent replacements should all be included in the scope of the present application.

[0038] As shown in Figure 1, the current display panel structure, the multiplexer circuit 200 is located between the display area AA and the non-display area NA bending area 100, the fan-shaped routing area 300 connects the multiplexer circuit 200 and the control chip, and the multiplexer circuit 200 and the fan-shaped routing area 300 occupy a height of about 200um, which is extremely unfavorable for the design of narrow chin products.

[0039] Please refer to Figure 2. An embodiment of the present application provides a display panel, which includes a display area AA and a non-display area NA surrounding the display area AA. The non-display area NA includes a bending area 100 and a multi-way selection circuit 200. The multi-way selection circuit 200 is located on the side of the bending area 100 away from the display area AA. The multi-way selection circuit 200 is located between the bending area 100 and the control chip 400, that is, the multi-way selection circuit 200 is placed in the sparse area of ​​the fan-shaped routing area 300 of the bending area 100 away from the display area AA, which can effectively save the space of the bending area 100 close to the display area AA, thereby realizing a narrow chin design.

[0040] As shown in Figures 3 and 4 , the non-display area NA of the display panel, which includes the multiplexer circuit 200, includes a substrate 1, a buffer layer 2, a thin-film transistor element 3, a first organic layer 4, a metal layer 5, and a second organic layer 6, which are stacked in sequence. The substrate 1 has insulating properties and includes, but is not limited to, a glass substrate. The substrate 1 may also be formed into multiple layers by repeatedly coating and curing a polymer material.

[0041] A buffer layer 2 is formed on substrate 1. The buffer layer 2 may include one or more inorganic insulating layers, such as silicon oxide or silicon nitride. The buffer layer 2 can provide a planarization layer on the upper surface of substrate 1, preventing or preventing impurities and moisture from penetrating from substrate 1 into the components above. A barrier layer may also be provided between the buffer layer 2 and substrate 1. The barrier layer may include various insulating materials (such as silicon oxide or silicon nitride) and may be a single layer or a multilayer structure, without limitation. The barrier layer can provide a planarization layer on the upper surface of the substrate and improve the interfacial bonding performance between the upper and lower film layers.

[0042] The thin film transistor element 3 is formed on the buffer layer 2. The thin film transistor element 3 is a component for implementing switch control in the multiplexer circuit 200. The gate of the thin film transistor element 3 receives a control signal (Mux signal), and one end of the source and drain of the thin film transistor element 3 receives a data signal. Based on the control signal, the received data signals are transmitted to the corresponding pixels in the display area AA.

[0043] The first organic layer 4 is formed on the thin film transistor element 3 . Since part of the structure of the thin film transistor element 3 needs to be patterned during the preparation process, the first organic layer 4 provides a planarization layer on the surface of the thin film transistor element 3 .

[0044] The thin-film transistor element 3 in the multiplexer circuit 200 receives control signals and data signals and selects the data signal based on the control signal. The control signal received by the multiplexer circuit 200 is an AC hopping signal. A metal layer 5 is formed on the first organic layer 4. The metal layer 5 is used to receive a DC signal and transmit it to the display area. The DC signal transmitted by the metal layer 5 does not crosstalk with the control signal received by the thin-film transistor element 3. Furthermore, when the non-display area is bent, the multi-way selection circuit 200 will bend to the rear of the display panel. After the whole machine is assembled, the multi-way selection circuit 200 behind the display panel will be close to other end components of the whole machine. The control signal of the thin-film transistor element 3 in the multi-way selection circuit 200 is extremely sensitive to external interference. The control signal of the thin-film transistor element 3 is an AC jump signal, which causes radio frequency interference with the AC signals of other end components of the whole machine, resulting in unstable or inaccurate transmitted signals. The metal layer 5 can effectively shield the AC jump signal transmitted by the thin-film transistor element 3. Therefore, the metal layer 5 is set between the thin-film transistor element 3 and other end components of the display panel to block the AC signals of the two and avoid radio frequency interference between different AC signals. In order to achieve a good signal shielding effect, the metal layer 5 completely covers the thin-film transistor element 3.

[0045] The second organic layer 6 is formed on the metal layer 5, and the second organic layer 6 provides a planarization layer on the surface of the metal layer 5. In addition, other layers may be provided on the second organic layer 6, for example, a pixel defining layer 7 is formed on the second organic layer 6. This is not specifically limited in this embodiment.

[0046] In one embodiment, in order to ensure the signal shielding effect of the metal layer 5 , the metal layer 5 extends to the area of ​​the non-display area NA where the multiplexing circuit 200 is not provided.

[0047] In one embodiment, if an organic film layer is located between two large metal blocks, moisture trapped in the organic film layer may be unable to be released during the manufacturing process. Upon heating, the gas in the organic film layer expands and pushes against the metal, increasing the risk of film peeling. Furthermore, since the moisture cannot be discharged vertically, it will spread horizontally. If it approaches the display area, the moisture can cause the pixels to shrink, resulting in functional display failure. In this embodiment, the gate electrode 33 and source / drain electrodes 35 of the thin-film transistor element 3 are both metal film layers. The first organic layer 4 is located between the thin-film transistor element 3 and the metal layer 5. Therefore, as shown in Figures 4 and 5, the metal layer 5 is provided with a through hole 51. The second organic layer 6 is located within the through hole 51 and contacts the first organic layer 4 to release moisture trapped in the first organic layer 4.

[0048] Via 51 is provided in an area of ​​metal layer 5 that does not correspond to multiplexer circuit 200. That is, via 51 is not provided above the metal film layer through which thin-film transistor element 3 transmits AC transition signals. Via 51 is positioned away from active signals and located near them, effectively shielding the control signals of multiplexer circuit 200 and providing an effective path for moisture removal. The size of via 51 depends on the precision of the etching process for metal layer 5. For example, via 51 is preferably set to be at least 10 μm × 10 μm to prevent via 51 from being too small to penetrate metal layer 5, thereby ensuring effective moisture removal.

[0049] In one embodiment, as shown in FIG6 , the multi-channel selection circuit 200 includes multiple groups of selection sub-circuits 210 arranged in parallel. Within the same area around each selection sub-circuit 210, the distribution density of through-holes 51 is the same, that is, the environment around each group of selection sub-circuits 210 is kept consistent as much as possible. For example, the number and relative positions of through-holes 51 around each group of selection sub-circuits 210 are consistent to ensure that the arrangement of through-holes 51 has a consistent effect on each group of selection sub-circuits 210, thereby ensuring signal stability.

[0050] In one embodiment, the power signal line extends from the non-display area NA to the display area AA. The power signal itself is a DC signal and will not cause radio frequency interference with the control signal of the multiplexer circuit 200. Therefore, the power signal line above the multiplexer circuit 200 is extended to form a metal layer 5 that completely covers the thin film transistor element 3. In this embodiment, the existing power signal line is widened and extended to shield the control signal of the multiplexer circuit 200. There is no need to prepare an additional shielding layer, thereby avoiding additional steps.

[0051] In one embodiment, as shown in FIG7 , the multiplexer circuit 200 is positioned on the side of the flexure 100 away from the display area AA, but the power signal lines are not extended to serve as metal layer 5 to shield the control signals. The power signal lines include a positive power supply voltage signal line (VDD signal line) and a negative power supply voltage signal line (VSS signal line). As shown in FIG7 , both the VDD signal line and the VSS signal line extend from the non-display area NA to the display area AA. The VDD signal line connects the control chip 400 to the side of the display area AA near the multiplexer circuit 200. Portions of the VDD signal line overlap with the multiplexer circuit 200, potentially bypassing the layout area of ​​the multiplexer circuit 200. The VSS signal line is positioned on both sides of the display panel and does not overlap with the multiplexer circuit 200. Widening and extending the overlapping area of ​​the VDD signal line with the multiplexer circuit 200 to form a metal layer 5 that completely covers the thin-film transistor element 3 can minimize interference with other components. Therefore, the metal layer 5 is configured as the VDD signal line.

[0052] In one embodiment, as shown in FIG. 4 , the thin film transistor element 3 includes a semiconductor 31 , a gate insulating layer 32 , a gate electrode 33 , an interlayer insulating layer 34 , and a source-drain electrode 35 , which are stacked in sequence.

[0053] Semiconductor 31 is formed on buffer layer 2 and is made of polycrystalline silicon. Semiconductor 31 is divided into a channel region and source and drain regions formed on either side of the channel region. The channel region of semiconductor 31 is polycrystalline silicon without impurities, i.e., an intrinsic semiconductor. The source and drain regions are polycrystalline silicon doped with conductive impurities, i.e., impurity semiconductors. The impurities doped in the source and drain regions can be either P-type or N-type impurities.

[0054] The gate insulating layer 32 is formed on the semiconductor 31. The gate insulating layer 32 may be a single layer or a plurality of layers including at least one of tetraethylorthosilicate (TEOS), silicon nitride, and silicon oxide.

[0055] The gate electrode 33 is formed on the gate insulating layer 32 and overlaps the channel region. The gate electrode 33 may be formed as a single layer or multiple layers including a low resistance material such as Al, Ti, Mo, Cu, Ni, or alloys thereof, or a material having high corrosion resistance.

[0056] An interlayer insulating layer 34 is formed on the gate electrode 33. The interlayer insulating layer 34 can be formed as multiple layers or a single layer, for example, of tetraethylorthosilicate (TEOS), silicon nitride, or silicon oxide. The interlayer insulating layer 34 is provided with source-drain vias, which penetrate the gate insulating layer 32 to expose a portion of the semiconductor 31. The source-drain vias include a source contact hole and a drain contact hole, through which the source region and the drain region are exposed, respectively.

[0057] The source-drain electrode 35 is formed on the interlayer insulating layer 34, and the source-drain electrode 35 is connected to the semiconductor 31 through the source-drain through-hole. The source-drain electrode 35 includes a source electrode and a drain electrode. The source electrode is connected to the source region through the source contact hole, and the drain electrode is connected to the drain region through the drain contact hole. The source electrode and the drain electrode can be formed as multiple layers or a single layer of a low-resistance material such as Al, Ti, Mo, Cu, Ni, or an alloy thereof, or a material with high corrosion resistance. For example, the source electrode and the drain electrode can be a triple layer of Ti / Cu / Ti, Ti / Ag / Ti, Ti / Al / Ti, or Mo / Al / Mo, among others.

[0058] It should be noted that the cross-sectional view of the multiplexer circuit 200 shown in FIG4 can be understood as the interface diagram corresponding to the "cross-section" marked in FIG6 . However, in actual applications, other film layers not shown in the figure may be provided above the thin-film transistor element 3 , which can be freely provided as needed. When other metal film layers are provided above the source and drain electrodes 35 of the multiplexer circuit 200 in the display panel, and the metal film layer transmits a DC signal, the metal film layer can be extended to serve as the metal layer 5 of this embodiment. In addition, if a separate metal film layer is provided only for shielding the control signal of the multiplexer circuit 200 and does not transmit any signal, on the one hand, it increases the process and the thickness of the display panel, and on the other hand, it leads to parasitic capacitance and signal instability. For example, the film layers used in the multiplexer circuit 200 mainly include Poly (polysilicon) / GE1 (gate) / SD1 (source and drain). For the 2SD Flow product, the multiplexer circuit 200 includes a double-layer source and drain metal layer SD1 and SD2, SD2 is arranged above SD1, and SD2 can be selected to be widened as the metal layer 5 to shield the control signal. For the 3SD Flow product, the multiplexer circuit 200 includes a three-layer source and drain metal layer SD1, SD2 and SD3, SD1, SD2 and SD3 are stacked, SD2 is arranged between SD1 and SD3, and SD2 / SD3 can be selected to be widened as the metal layer 5 to shield the control signal.

[0059] In one embodiment, the display panel further includes a control signal electrode 8 disposed on the interlayer insulating layer 34. The control signal electrode 8 transmits a control signal. The control signal electrode 8 overlaps with the gate electrode 33 and is disposed on the same layer as the source / drain electrode 35. The number of control signal electrodes 8 is equal to the number of thin-film transistors included in each selection sub-circuit 210. As shown in FIG5 , a metal layer 5 covers the multiplexer circuit 200 and the control signal electrode 8. The control signal electrode 8 is connected to one end of the source / drain of the thin-film transistor element 3 in the multiplexer circuit 200. The control signal electrode 8 transmits the control signal to one end of the source / drain of the thin-film transistor element 3. The metal layer 5 is used to shield the control signal, so the through-hole 51 in the metal layer 5 avoids the control signal electrode 8 and one end of the source / drain of the thin-film transistor element 3.

[0060] In one embodiment, a fan-shaped routing area 300 and a control chip 400 are provided on the side of the multiplexer circuit 200 away from the bending area 100 in the non-display area NA. The multiplexer circuit 200 and the control chip 400 are connected through the fan-shaped routing area 300. The control chip 400 sends the data signal to the multiplexer circuit 200 through the fan-shaped routing area 300. The multiplexer circuit 200 transmits the data signal to the pixels in the display area based on the control signal.

[0061] In this embodiment, the multiplexer circuit 200 is placed on the side of the flexure 100 away from the display area AA. When bent, the multiplexer circuit 200 bends behind the display panel, thereby achieving a narrow chin design. Furthermore, to prevent radio frequency interference (RFI) between the multiplexer circuit 200 and other components of the entire device after it bends behind the display panel, i.e., crosstalk between different AC transition signals, which could lead to unstable or inaccurate transmitted signals, a metal layer 5 for transmitting DC signals is provided above the thin-film transistor element 3 to shield the thin-film transistor element 3 and achieve signal shielding.

[0062] The present application provides a display device, which includes the display panel as described in any one of the above embodiments.

[0063] In some embodiments, the display panel includes a display area and a non-display area surrounding the display area. The non-display area includes a bending area 100 and a multiplexer circuit 200. The multiplexer circuit 200 is located on a side of the bending area 100 away from the display area. The non-display area of ​​the display panel includes:

[0064] substrate1;

[0065] a buffer layer 2 formed on the substrate 1;

[0066] a thin film transistor element 3, formed on the buffer layer 2;

[0067] A first organic layer 4 formed on the thin film transistor element 3;

[0068] a metal layer 5 formed on the first organic layer 4 and covering the thin film transistor element 3, and configured to receive a DC signal and transmit it to the display area;

[0069] The second organic layer 6 is formed on the metal layer 5 .

[0070] In some embodiments, the metal layer extends to a region of the non-display area where the multiplexing circuit is not provided.

[0071] In some embodiments, the metal layer 5 is provided with a through hole 51 , the second organic layer 6 is provided in the through hole 51 and contacts the first organic layer 4 , and the through hole 51 is provided in an area of ​​the metal layer 5 not corresponding to the multiplexing circuit 200 .

[0072] In some embodiments, the multi-way selection circuit 200 includes a plurality of selection sub-circuits 210 arranged in parallel in sequence, and the distribution density of the through holes 51 in the same range around each of the selection sub-circuits 210 is the same.

[0073] In some embodiments, the metal layer 5 is configured as a power signal line.

[0074] In some embodiments, the metal layer 5 is configured as a positive power voltage signal line.

[0075] In some embodiments, the thin film transistor element 3 includes:

[0076] A semiconductor 31 is formed on the buffer layer 2;

[0077] a gate insulating layer 32 formed on the semiconductor 31;

[0078] a gate electrode 33 formed on the gate insulating layer 32;

[0079] an interlayer insulating layer 34 formed on the gate electrode 33 , wherein the interlayer insulating layer 34 is provided with a source-drain through-hole 51 , wherein the source-drain through-hole 51 penetrates the gate insulating layer 32 to expose a portion of the semiconductor 31 ;

[0080] The source-drain electrodes 35 are formed on the interlayer insulating layer 34 . The source-drain electrodes 35 pass through the source-drain through-holes 51 and are connected to the semiconductor 31 .

[0081] In some embodiments, the display panel further includes a control signal electrode 8 disposed on the interlayer insulating layer 34 , and the control signal electrode 8 overlaps with the gate electrode 33 .

[0082] In some embodiments, a fan-shaped wiring area 300 and a control chip 400 are provided in the non-display area on a side of the multiplexing circuit 200 away from the bending area 100 , and the multiplexing circuit 200 and the control chip 400 are connected through the fan-shaped wiring area 300 .

[0083] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0084] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0085] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, based on the ideas of the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, wherein: The display panel includes a display area and a non-display area surrounding the display area. The non-display area includes a bending area and a multi-way selection circuit. The multi-way selection circuit is located on a side of the bending area away from the display area. The non-display area of the display panel where the multi-way selection circuit is located includes: substrate; a buffer layer formed on the substrate; a thin film transistor element, formed on the buffer layer; a first organic layer formed on the thin film transistor element; a metal layer formed on the first organic layer, the metal layer covering the thin film transistor element, the metal layer being used to receive a DC signal and transmit it to the display area; a second organic layer formed on the metal layer; Wherein, the metal layer extends to an area of the non-display area where the multi-way selection circuit is not provided; Wherein, the metal layer is set as a power signal line.

2. The display panel according to claim 1, wherein: The metal layer is provided with a through hole, the second organic layer is provided in the through hole and contacts the first organic layer, and the through hole is provided in a region of the metal layer that does not correspond to the multiplexer circuit.

3. The display panel according to claim 2, wherein: The multi-way selection circuit includes a plurality of selection sub-circuits arranged in parallel, and the distribution density of the through holes in the same range around each of the selection sub-circuits is the same.

4. The display panel according to claim 1, wherein: The metal layer is configured as a positive power supply voltage signal line.

5. The display panel according to claim 4, wherein: In the non-display area, a fan-shaped wiring area and a control chip are provided on a side of the multiplexer circuit away from the bending area. The multiplexer circuit and the control chip are connected via the fan-shaped wiring area.

6. The display panel according to claim 5, wherein: The positive power supply voltage signal line connects the control chip and a side of the display area close to the multiplexer circuit. The orthographic projection of the positive power supply voltage signal line on the substrate overlaps with the orthographic projection of the multiplexer circuit on the substrate.

7. The display panel according to claim 1, wherein: The thin film transistor element comprises: a semiconductor formed on the buffer layer; a gate insulating layer formed on the semiconductor; a gate electrode formed on the gate insulating layer; an interlayer insulating layer formed on the gate electrode, wherein the interlayer insulating layer is provided with a source-drain through-hole, and the source-drain through-hole penetrates the gate insulating layer to expose a portion of the semiconductor; Source-drain electrodes are formed on the interlayer insulating layer, and the source-drain electrodes pass through the source-drain through-holes and are connected to the semiconductor.

8. The display panel according to claim 7, wherein: The display panel further includes a control signal electrode disposed on the interlayer insulating layer, wherein the control signal electrode overlaps with the gate electrode.

9. The display panel according to any one of claims 1 to 8, wherein: The thin film transistor element is a component for realizing switch control in the multi-way selection circuit. The gate of the thin film transistor element is used to receive a control signal, and the source or drain of the thin film transistor element is used to receive a data signal. The thin film transistor element is used to transmit the data signal to the pixels in the display area according to the control signal.

10. A display panel, wherein: The display panel includes a display area and a non-display area surrounding the display area. The non-display area includes a bending area and a multi-way selection circuit. The multi-way selection circuit is located on a side of the bending area away from the display area. The non-display area of the display panel where the multi-way selection circuit is located includes: substrate; a buffer layer formed on the substrate; a thin film transistor element, formed on the buffer layer; a first organic layer formed on the thin film transistor element; a metal layer formed on the first organic layer, the metal layer covering the thin film transistor element, the metal layer being used to receive a DC signal and transmit it to the display area; A second organic layer is formed on the metal layer.

11. The display panel according to claim 10, wherein: The metal layer extends to a region of the non-display area where the multi-way selection circuit is not provided.

12. The display panel according to claim 11, wherein: The metal layer is provided with a through hole, the second organic layer is provided in the through hole and contacts the first organic layer, and the through hole is provided in a region of the metal layer that does not correspond to the multiplexer circuit.

13. The display panel according to claim 12, wherein: The multi-way selection circuit includes a plurality of selection sub-circuits arranged in parallel, and the distribution density of the through holes in the same range around each of the selection sub-circuits is the same.

14. The display panel according to claim 10, wherein: The metal layer is configured as a power signal line.

15. The display panel according to claim 14, wherein: The metal layer is configured as a positive power supply voltage signal line.

16. The display panel according to claim 10, wherein: The thin film transistor element comprises: a semiconductor formed on the buffer layer; a gate insulating layer formed on the semiconductor; a gate electrode formed on the gate insulating layer; an interlayer insulating layer formed on the gate electrode, wherein the interlayer insulating layer is provided with a source-drain through-hole, and the source-drain through-hole penetrates the gate insulating layer to expose a portion of the semiconductor; Source-drain electrodes are formed on the interlayer insulating layer, and the source-drain electrodes pass through the source-drain through-holes and are connected to the semiconductor.

17. The display panel according to claim 16, wherein: The display panel further includes a control signal electrode disposed on the interlayer insulating layer, wherein the control signal electrode overlaps with the gate electrode.

18. The display panel according to any one of claims 10 to 17, wherein: In the non-display area, a fan-shaped wiring area and a control chip are provided on a side of the multiplexer circuit away from the bending area. The multiplexer circuit and the control chip are connected via the fan-shaped wiring area.

19. The display panel according to any one of claims 10 to 17, wherein: The thin film transistor element is a component for realizing switch control in the multi-way selection circuit. The gate of the thin film transistor element is used to receive a control signal, and the source or drain of the thin film transistor element is used to receive a data signal. The thin film transistor element is used to transmit the data signal to the pixels in the display area according to the control signal.

20. A display device, wherein: The display device comprises the display panel according to any one of claims 1 to 19.

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