Conductive channel structure of silicon carbide device, and fully integrated silicon carbide device and fully integrated manufacturing process therefor

Abstract

A conductive channel structure of a silicon carbide device. The conductive channel structure is a first-conductivity-type conductive channel structure (5), and comprises a first-conductivity-type lower-layer channel region (5a) provided in the middle of a second-conductivity-type buffer layer (3) of a silicon carbide device, wherein a first-conductivity-type sheet region (5a') is provided on the first-conductivity-type lower-layer channel region (5a), and the top of the first-conductivity-type sheet region (5a') is located on the upper surface of the second-conductivity-type buffer layer (3). Also disclosed are a fully integrated silicon carbide device and a fully integrated manufacturing process therefor. The present invention has the advantages of high withstand voltage and low channel resistance.

Description

Conductive channel structure of silicon carbide device, fully integrated silicon carbide device and fully integrated preparation process thereof Technical Field

[0001] The present invention relates to the technical field of semiconductor power devices, and in particular to a conductive channel structure of a silicon carbide device, a fully integrated silicon carbide device and a fully integrated preparation process thereof. Background Art

[0002] With the continuous development of microelectronics technology, traditional silicon-based devices have approached the theoretical limits of their inherent capabilities. In contrast, silicon carbide (SiC) is widely considered to be the most competitive alternative to silicon-based devices due to its wide bandgap, high critical electric field strength, high saturation velocity, and high thermal conductivity, especially in high-tech fields such as new energy vehicles, energy exploration and drilling, and nuclear power. However, there are currently two problems with silicon carbide devices: First, compared with silicon devices, due to the serious lattice mismatch of SiC / SiO2, the interface state density of silicon carbide devices is much greater than that of silicon-based devices, which makes the channel carrier mobility of silicon carbide devices much lower than that of silicon-based devices, and the channel resistance accounts for a higher proportion of the total on-resistance. Currently, a silicon carbide buried channel structure can be used to solve this problem. The so-called buried channel structure is to add a layer of area in the channel area of ​​the silicon carbide device. The doping type of this area is the same as the source and drain area. When the device is turned off, the channel is depleted through the interface state and PN junction. When it is turned on, the current can flow in the channel, thereby reducing the impact of the interface state. However, the interface state density of silicon carbide is related to the preparation process, and the interface state density cannot be accurately predicted, which makes it difficult to control the doping concentration and injection depth of the channel, so that the buried channel structure has not been well applied. Secondly, the problem of excessive silicon carbide channel resistance due to high interface state density is more serious in low-voltage devices. Therefore, the current applications of silicon carbide devices are all discrete devices, and the circuit parts used with silicon carbide discrete devices use silicon-based chips. However, traditional silicon-based chips have poor high-temperature resistance and radiation resistance, which cannot fully utilize the advantages of wide-bandgap power devices. Therefore, if a new channel structure can be proposed to improve the channel carrier mobility and reduce the channel resistance, the problems existing in current silicon carbide low-voltage devices can be solved, and silicon carbide power devices and their circuit parts can be monolithically integrated to improve the performance and reliability of power electronic systems. This is of great significance for high-temperature and radiation-resistant applications in special scenarios.

[0003] Summary of the Invention

[0004] In response to the above problems, the present invention proposes a conductive channel structure of a silicon carbide device, a fully integrated silicon carbide device and a fully integrated preparation process thereof, which can improve the withstand voltage of the silicon carbide device, reduce the influence of the interface state on the channel carrier mobility, and improve the channel carrier mobility of the silicon carbide device to reduce the channel resistance. The present invention solves the problems of large parasitics, poor high-temperature characteristics and poor radiation resistance existing in the traditional use of silicon-based chips as silicon carbide driving circuits.

[0005] The technical solutions of the present invention are as follows:

[0006] The present invention first provides a conductive channel structure of a silicon carbide device, wherein the conductive channel structure is a first conductive type conductive channel structure, comprising: a first conductive type lower layer channel region provided in the middle of a second conductive type buffer layer of the silicon carbide device, a first conductive type sheet region provided on the first conductive type lower layer channel region, and a top of the first conductive type sheet region located on the upper surface of the second conductive type buffer layer

[0007] The present invention provides another conductive channel structure of a silicon carbide device, which is a second conductive type conductive channel structure, including: a second conductive type lower channel region arranged in the middle of a second conductive type buffer layer of the silicon carbide device, a second conductive type sheet region provided on the second conductive type lower channel region, and the top of the second conductive type sheet region is located on the upper surface of the second conductive type buffer layer.

[0008] The present invention also provides a fully integrated silicon carbide device, comprising: a first conductive type silicon carbide substrate layer, a second conductive type epitaxial layer provided on the first conductive type silicon carbide substrate layer, a second conductive type buffer layer provided on the second conductive type epitaxial layer, a field effect oxide layer covering the second conductive type buffer layer, a second conductive type isolation structure provided in the second conductive type buffer layer, and the second conductive type buffer layer is divided into a low voltage region, a first high voltage region, and a second high voltage region by the second conductive type isolation structure.

[0009] A first conductive type silicon carbide LDMOS device is provided in the first high-voltage region, and a first conductive type silicon carbide MOS device and / or a second conductive type silicon carbide MOS device are provided in the low-voltage region and the second high-voltage region, respectively. The conductive channel structure of at least one of the first conductive type silicon carbide LDMOS device and the first conductive type silicon carbide MOS device is the first conductive type conductive channel structure of claim 2, and / or the conductive channel structure of the second conductive type silicon carbide MOS device is the second conductive type conductive channel structure of claim 2.

[0010] The silicon carbide LDMOS device includes a first conductivity type well region arranged in a second conductivity type buffer layer located in a first high voltage region and a first conductivity type drain region of the silicon carbide LDMOS device arranged in the first conductivity type well region; a first conductivity type well region is also provided in the second conductivity type buffer layer in the second high voltage region and a first conductivity type heavily doped region is provided therein, and a drain metal electrode is connected to the first conductivity type drain region of the silicon carbide LDMOS device and the first conductivity type heavily doped region.

[0011] Finally, the present invention provides a fully integrated preparation process for a fully integrated silicon carbide device, comprising the following steps:

[0012] forming a first conductive type substrate on a silicon carbide substrate, growing a second conductive type epitaxial layer on the first conductive type substrate, and growing a second conductive type buffer layer on the second conductive type epitaxial layer;

[0013] Using ion implantation, two second conductivity type isolation structures are formed in the second conductivity type buffer layer, which are as deep as the second conductivity type epitaxial layer, and the second conductivity type isolation structures divide the second conductivity type buffer layer into a low voltage region, a first high voltage region, and a second high voltage region;

[0014] Performing ion implantation on the second conductive type buffer layer and forming first conductive type well regions in the low voltage region, the first high voltage region, and the second high voltage region respectively; performing ion implantation on the second conductive type buffer layer in the first high voltage region and the first conductive type well region in the second high voltage region to form a second conductive type well region;

[0015] Ion implantation is used to form two first conductivity type heavily doped regions serving as source and drain regions of a first conductivity type silicon carbide MOS device and one first conductivity type heavily doped region of a second conductivity type MOS device in the second conductivity type buffer layer and the first conductivity type well region of the low voltage region, respectively; one first conductivity type heavily doped region serving as a drain region of a silicon carbide LDMOS device and one first conductivity type heavily doped region serving as a source region of the silicon carbide LDMOS device in the first conductivity type well region and the second conductivity type well region of the first high voltage region, respectively; and two first conductivity type heavily doped regions serving as source and drain regions of the first conductivity type silicon carbide MOS device and the first conductivity type heavily doped region of the second conductivity type MOS device, as well as a first conductivity type heavily doped region serving as a heavily doped ohmic contact region, respectively, in the second conductivity type well region and the first conductivity type well region of the second high voltage region;

[0016] Using ion implantation, forming a second conductivity type heavily doped region of a first conductivity type MOS device and two second conductivity type heavily doped regions serving as a source region and a drain region of a second conductivity type silicon carbide MOS device in the second conductivity type buffer layer and the first conductivity type well region of the low voltage region, respectively; forming a second conductivity type heavily doped region of a silicon carbide LDMOS device in the second conductivity type well region of the first high voltage region; and forming two second conductivity type heavily doped regions serving as a source region and a drain region of the second conductivity type silicon carbide MOS device and a second conductivity type heavily doped region of the first conductivity type MOS device in the first conductivity type well region and the second conductivity type well region of the second high voltage region, respectively;

[0017] Preparation of a conductive channel structure, including preparation of a first conductive type conductive channel structure and a second conductive type conductive channel structure: the first conductive type conductive channel structure is respectively prepared between the source region and the drain region of the first conductive type MOS device and between the source region and the first conductive type well region of the first high voltage region of the silicon carbide LDMOS device, firstly, ion implantation with an implantation depth of 0.1 μm to 0.3 μm is performed in the second conductive type buffer layer to form a first conductive type lower channel region, and the two ends of the first conductive type lower channel region in the first conductive type MOS device are respectively in contact with the source region and the drain region of the first conductive type MOS device, and the two ends of the first conductive type lower channel region in the silicon carbide LDMOS device are respectively in contact with the source region of the silicon carbide LDMOS device and the first conductive type well region of the first high voltage region, and then by adjusting the ion implantation window , ion implantation is performed in a partial area of ​​the second conductive type buffer layer above the first conductive type lower channel region to form a first conductive type section region isolated by the second conductive type buffer layer, and the first conductive type section region is in contact with the first conductive type lower channel region; the second conductive type conductive channel structure is prepared between the source region and the drain region of the second conductive type MOS device, firstly, ion implantation is performed in the first conductive type well region in the low voltage region and the first conductive type well region in the second high voltage region with an implantation depth of 0.1μm to 0.3μm to form the second conductive type lower channel region, and then, by adjusting the ion implantation window, ion implantation is performed in a partial area of ​​the first conductive type well region above the second conductive type lower channel region to form a second conductive type section region isolated by the first conductive type well region, and the first conductive type section region is in contact with the second conductive type lower channel region;

[0018] Thereafter, a gate oxide layer is formed by a wet method after annealing; polysilicon is deposited on the gate oxide layer above the first conductivity type conductive channel structure and the second conductivity type conductive channel structure to form a polysilicon gate of the first conductivity type MOS, a polysilicon gate of the LDMOS, and a polysilicon gate of the second conductivity type MOS;

[0019] A field effect oxide layer is deposited so that the oxygen effect oxide layer covers the entire surface of the device. The field effect oxide layer is etched and metal is deposited to form a drain metal electrode of the LDMOS, a gate metal electrode of the LDMOS, a source metal electrode of the LDMOS, a drain metal electrode of the first conductive type MOS, a gate metal electrode of the first conductive type MOS, a source metal electrode of the first conductive type MOS, a drain metal electrode of the second conductive type MOS, a gate metal electrode of the second conductive type MOS and a source metal electrode of the second conductive type MOS.

[0020] Compared with the prior art, the present invention has the following advantages:

[0021] This patent provides a new type of silicon carbide channel structure. Compared with traditional silicon carbide devices, when the silicon carbide device is turned on, the silicon carbide channel structure of the present invention can open the channel below the SiC / SiO2 interface under the action of the gate voltage, so that the channel current flows below the SiC / SiO2 interface, reducing the influence of the interface state on the channel carrier mobility, thereby improving the channel carrier mobility of the silicon carbide device, greatly reducing the channel resistance, and solving the problem of excessive channel resistance caused by low channel mobility of silicon carbide devices. The channel structure adopted by the present invention is divided into two parts, upper and lower. When the silicon carbide device is turned off, the silicon carbide channel structure of the present invention can be depleted by the lower channel region and the upper P-type region / N-type region, and gets rid of the existing technology that relies on the interface state to deplete the channel structure. In the off state, the traditional buried channel structure requires the interface state and the substrate to deplete it together, but the size of the interface state and the depletion of the buried channel are unpredictable, and it is easy to make a normally-on device. In addition, based on the novel channel structure, the present invention has invented a fully integrated process for silicon carbide devices, realizing the monolithic integration of silicon carbide devices and other silicon carbide circuits. Compared with traditional silicon-based circuits used in conjunction with silicon carbide power devices, this solves the problem that silicon-based devices cannot work normally in high-temperature, high-radiation environments, and can fully exert the performance of silicon carbide devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] FIG1 is a schematic diagram of a conventional silicon carbide buried channel structure.

[0023] FIG2 is a schematic diagram of a silicon carbide channel structure of the present invention, wherein FIG2(a) is one silicon carbide channel structure, and FIG2(b) is another silicon carbide channel structure.

[0024] FIG3 is a schematic diagram of a fully integrated silicon carbide device according to the present invention.

[0025] FIG4 is a schematic diagram of the preparation process of a fully integrated silicon carbide device, wherein FIG4( a ) to FIG4 ( p ) are schematic diagrams of the various steps of the preparation process, respectively. DETAILED DESCRIPTION

[0026] The first conductivity type in the present invention can be n-type or p-type. When the first conductivity type is n-type, the second conductivity type is p-type; when the first conductivity type is p-type, the second conductivity type is n-type.

[0027] Example 1

[0028] A conductive channel structure of a silicon carbide device, referring to Figure 2(a), the conductive channel structure is a first conductive type conductive channel structure 5, including: a first conductive type lower channel region 5a arranged in the middle of the second conductive type buffer layer 3 of the silicon carbide device, a first conductive type sheet 5a' is provided on the first conductive type lower channel region 5a, and the top of the first conductive type sheet 5a' is located on the upper surface of the second conductive type buffer layer 3. In this embodiment, there are 1 to 3 first conductive type sheets 5a', whose width is 0.2μm-4μm, and the spacing between adjacent first conductive type sheets 5a' is 0.2μm~4μm.

[0029] Example 2

[0030] A conductive channel structure for a silicon carbide device, wherein the conductive channel structure is a second-conductivity-type conductive channel structure 6, characterized by comprising: a second-conductivity-type lower channel region 6a disposed in the middle of a second-conductivity-type buffer layer 3 of the silicon carbide device; a second-conductivity-type sheet region 6a' disposed above the second-conductivity-type lower channel region 6a, with the top of the second-conductivity-type sheet region 6a' located on the upper surface of the second-conductivity-type buffer layer 3. In this embodiment, there are 1 to 3 second-conductivity-type sheets 6a', each having a width of 0.2 μm to 4 μm, and a spacing of 0.2 μm to 4 μm between adjacent second-conductivity-type sheets 6a'.

[0031] Example 3

[0032] 3 , a fully integrated silicon carbide device includes: a first conductive type silicon carbide substrate layer 1, a second conductive type epitaxial layer 2 provided on the first conductive type silicon carbide substrate layer 1, a second conductive type buffer layer 3 provided on the second conductive type epitaxial layer 2, a field effect oxide layer 4 covering the second conductive type buffer layer 3, a second conductive type isolation structure 7 provided within the second conductive type buffer layer 3, and the second conductive type buffer layer 3 is divided into a low voltage region 101, a first high voltage region 102, and a second high voltage region 103 by the second conductive type isolation structure 7.

[0033] A first conductive type silicon carbide LDMOS device is provided in the first high-voltage region 102, and a first conductive type silicon carbide MOS device and / or a second conductive type silicon carbide MOS device are provided in the low-voltage region 101 and the second high-voltage region 103, respectively. The conductive channel structure of at least one of the first conductive type silicon carbide LDMOS device and the first conductive type silicon carbide MOS device is the first conductive type conductive channel structure 5, and / or the conductive channel structure of the second conductive type silicon carbide MOS device is the second conductive type conductive channel structure 6. In this embodiment, the conductive channel structure of the first conductive type silicon carbide LDMOS device and each first conductive type silicon carbide MOS device all adopts the first conductive type conductive channel structure 5, and at the same time, the conductive channel structure of each second conductive type silicon carbide MOS device all adopts the second conductive type conductive channel structure 6.

[0034] The silicon carbide LDMOS device includes a first conductivity type well region 8 provided in the second conductivity type buffer layer 3 located in the first high voltage region 102 and a first conductivity type drain region 12D of the silicon carbide LDMOS device provided in the first conductivity type well region 8; a first conductivity type well region 8 is also provided in the second conductivity type buffer layer 3 in the second high voltage region 103 and a first conductivity type heavily doped region 10312 is provided therein, and a drain metal electrode 141D is connected to the first conductivity type drain region 12D of the silicon carbide LDMOS device and the first conductivity type heavily doped region 12. In this embodiment:

[0035] The silicon carbide LDMOS device also includes a second conductive type well region 9 arranged in the second conductive type buffer layer 3, and a first conductive type source region 121S, a second conductive type heavily doped region 131 and a conductive channel structure located between the first conductive type source region 121S and the first conductive type well region 8 of the LDMOS are provided in the second conductive type well region 9. A first source metal electrode 141S is connected to the first conductive type source region 121S and the second conductive type heavily doped region 131, a polysilicon gate 121G of the LDMOS is provided above the conductive channel structure, a gate metal electrode 141G of the LDMOS is connected to the polysilicon gate 121G, and a gate oxide layer 10 is provided between the polysilicon gate 121G and the conductive channel of the LDMOS.

[0036] The first conductive type silicon carbide MOS device includes a first conductive type source region 122S of the first conductive type MOS, a second conductive type heavily doped region 132, a first conductive type drain region 122D and a conductive channel structure located between the first conductive type source region 122S and the first conductive type drain region 122D. A polysilicon gate 122G of the first conductive type MOS is provided above the conductive channel structure, and a gate oxide layer 10 is provided between the conductive channel structure and the polysilicon gate 122G. A gate metal electrode 142G of the first conductive type MOS is connected to the polysilicon gate 122G, a source metal electrode 142S of the first conductive type MOS is connected to the first conductive type source region 122S and the second conductive type heavily doped region 132, and a drain metal electrode 142D of the first conductive type MOS is connected to the first conductive type drain region 122D.

[0037] The second conductive type silicon carbide MOS device includes a second conductive type source region 123S of the second conductive type MOS, a first conductive type heavily doped region 133, a second conductive type drain region 123D and a conductive channel structure located between the second conductive type source region 123S and the second conductive type drain region 123D. A polysilicon gate 123G of the second conductive type MOS is provided above the conductive channel structure, and a gate oxide layer 10 is provided between the conductive channel structure and the polysilicon gate 123G. A gate metal electrode 143G of the second conductive type MOS is connected to the polysilicon gate 123G, a source metal electrode 143S of the second conductive type MOS is connected to the second conductive type source region 123S and the first conductive type heavily doped region 133, and a drain metal electrode 143D of the second conductive type MOS is connected to the second conductive type drain region 123D.

[0038] Example 4

[0039] A fully integrated manufacturing process for a fully integrated silicon carbide device, referring to FIG4 , comprises the following steps:

[0040] A first conductive type substrate 1 is formed on a silicon carbide substrate. As an embodiment, the substrate thickness is 1 μm. When the first conductive type substrate 1 is an N-type substrate, the substrate doping type is nitrogen ions with a doping concentration of 1×10 19 cm -3 A second conductive type epitaxial layer 2 is grown on the first conductive type substrate 1. As an embodiment, the thickness of the second conductive type epitaxial layer 2 is 1 μm. When the second conductive type epitaxial layer 2 is a P-type epitaxial layer 2, the doping type is aluminum ions, and the doping concentration is 1.1×10 17 cm -3A second conductive type buffer layer 3 is grown on the second conductive type epitaxial layer 2. As an embodiment, the thickness of the second conductive type buffer layer 3 is 1 μm. When the second conductive type buffer layer 3 is a P-type epitaxial layer 2, the doping type is aluminum ions, and the doping concentration is 1×10 16 cm -3 ;

[0041] Ion implantation is used to form two second conductive type isolation structures 7 deep into the second conductive type epitaxial layer 2 in the second conductive type buffer layer 3, and the second conductive type isolation structure 7 divides the second conductive type buffer layer 3 into a low voltage region 101, a first high voltage region 102, and a second high voltage region 103. As an embodiment, the second conductive type isolation structure 7 is a p-type isolation structure, and the implanted ions are aluminum ions. The concentration of the second conductive type isolation structure 7 is 1×10 20 cm -3 , the implantation depth is 1 μm;

[0042] Ion implantation is performed on the second conductive type buffer layer 3 to form a first conductive type well region 8 in the low voltage region 101, the first high voltage region 102, and the second high voltage region 103, respectively. As an embodiment, the first conductive type well region 8 is an n-type well region, and the doping type is nitrogen ions with a doping concentration of 2×10 16 cm -3 , the depth of the well is 0.74 μm; ion implantation is performed on the second conductive type buffer layer 3 of the first high voltage region 102 and the first conductive type well region 8 of the second high voltage region 103 to form a second conductive type well region 9. As an embodiment, the second conductive type well region 9 is an n-type well region, the doping type is aluminum ions, and the doping concentration is 2.5×10 16 cm -3 , the depth of the well is 0.58 μm;

[0043] Ion implantation is used to form two first conductivity type heavily doped regions serving as the source region 122S and the drain region 122D of the first conductivity type silicon carbide MOS device and one first conductivity type heavily doped region 133 of the second conductivity type MOS device in the second conductivity type buffer layer 3 and the first conductivity type well region 8 of the low voltage region 101, and to form one first conductivity type heavily doped region serving as the drain region 12D of the silicon carbide LDMOS device and one first conductivity type heavily doped region serving as the source region of the silicon carbide LDMOS device in the first conductivity type well region 8 and the second conductivity type well region 9 of the first high voltage region 102. A first conductive type heavily doped region 121S is formed, and two first conductive type heavily doped regions serving as a source region 122S and a drain region 122D of a first conductive type silicon carbide MOS device and a first conductive type heavily doped region 133 of a second conductive type MOS device are formed in the second conductive type well region 9 and the first conductive type well region 8 of the second high voltage region 103, respectively. As an embodiment, the first conductive type heavily doped region 12 is an n-type heavily doped region, the doping type is nitrogen ions, and the doping concentration is 1×10 20 cm -3 , depth of 0.31 μm;

[0044] By ion implantation, a second conductive type heavily doped region 132 of a first conductive type MOS device and two second conductive type heavily doped regions serving as a source region 123S and a drain region 123D of a second conductive type silicon carbide MOS device are formed in the second conductive type buffer layer 3 and the first conductive type well region 8 of the low voltage region 101, a second conductive type heavily doped region 131 of a silicon carbide LDMOS device is formed in the second conductive type well region (9) of the first high voltage region 102, and two second conductive type heavily doped regions serving as a source region 123S and a drain region 123D of a second conductive type silicon carbide MOS device and a second conductive type heavily doped region 132 of the first conductive type MOS device are formed in the first conductive type well region 8 and the second conductive type well region 9 of the second high voltage region 103. As an embodiment, the second conductive type heavily doped region is a p-type heavily doped region, the doping type is aluminum ions, and the doping concentration is 1×10 20 cm -3 , depth of 0.28 μm;

[0045] Preparation of a conductive channel structure, including preparation of a first conductive type conductive channel structure 5 and a second conductive type conductive channel structure 6: the first conductive type conductive channel structure 5 is respectively prepared between the source region 122S and the drain region 122D of the first conductive type MOS device and between the source region 121S and the first high voltage region 102 of the silicon carbide LDMOS device. 8 of the first conductive type well region 8, first, ion implantation with an implantation depth of 0.1μm to 0.3μm is performed in the second conductive type buffer layer 3 to form a first conductive type lower channel region 5a, and the two ends of the first conductive type lower channel region 5a in the first conductive type MOS device are respectively in contact with the source region 122S and the drain region 122D of the first conductive type MOS device, and the two ends of the first conductive type lower channel region 5a in the silicon carbide LDMOS device are respectively in contact with the source region 121S of the silicon carbide LDMOS device and the first conductive type well region 8 of the first high voltage region 102, and then, by adjusting the ion implantation window, ion implantation is performed in a partial area of ​​the second conductive type buffer layer 3 above the first conductive type lower channel region 5a to form a first conductive type section region 5a' isolated by the second conductive type buffer layer 3, and the first conductive type section region 5a' is in contact with the first conductive type lower channel region 5a; the second conductive type conductive channel structure 6 is prepared on the second conductive type M Between the source region 123S and the drain region 123D of the OS device, ion implantation with a depth of 0.1 μm to 0.3 μm is first performed in the first conductive type well region 8 of the low voltage region 101 and the first conductive type well region 8 of the second high voltage region 103 to form a second conductive type lower channel region 6a. Then, by adjusting the ion implantation window, ion implantation is performed in a portion of the first conductive type well region 8 above the second conductive type lower channel region 6a to form a second conductive type well region 8 isolated from the first conductive type well region 8. The second conductive type region 6a' and the first conductive type region 6a' are in contact with the second conductive type lower channel region 6a; as a present embodiment, there are 1 to 3 first conductive type regions 5a', whose width is 0.2μm to 4μm, and the spacing between adjacent first conductive type regions 5a' is 0.2μm to 4μm. There are 1 to 3 second conductive type regions 6a', whose width is 0.2μm to 4μm, and the spacing between adjacent second conductive type regions 6a' is 0.2μm to 4μm.

[0046] Thereafter, a gate oxide layer 10 is formed by a wet method after annealing. As an embodiment, the annealing temperature is 1800° C. and the annealing time is 5 minutes. The gate oxide layer 10 is formed by the wet method by performing a high-temperature treatment at 1200° C. in a water vapor atmosphere for 60 minutes. The thickness of the formed gate oxide layer is 45 nm. Polysilicon is then deposited above the first conductive type conductive channel structure 5 and the second conductive type conductive channel structure 6 on the gate oxide layer 10 to form a polysilicon gate 122G of the first conductive type MOS, a polysilicon gate 121G of the LDMOS, and a polysilicon gate 123G of the second conductive type MOS. As an embodiment, the doping type of the polysilicon gate is phosphorus ions with a doping concentration of 1×10 19 cm -3 ;

[0047] A field effect oxide layer 4 is deposited so that the oxygen effect oxide layer 4 covers the entire surface of the device. 0.4 μm can be selected as the thickness of the oxygen effect oxide layer 4 in this embodiment. The field effect oxide layer 4 is etched and metal is deposited to form a drain metal electrode 141D of the LDMOS, a gate metal electrode 141G of the LDMOS, a source metal electrode 141S of the LDMOS, a drain metal electrode 142D of the first conductive type MOS, a gate metal electrode 142G of the first conductive type MOS, a source metal electrode 142S of the first conductive type MOS, a drain metal electrode 143D of the second conductive type MOS, a gate metal electrode 143G of the second conductive type MOS, and a source metal electrode 143S of the second conductive type MOS.

[0048] In this embodiment, there are 1 to 3 first conductive type areas 5a', whose width is 0.2μm to 4μm, and the spacing between adjacent first conductive type areas 5a' is 0.2μm to 4μm. There are 1 to 3 second conductive type areas 6a', whose width is 0.2μm to 4μm, and the spacing between adjacent second conductive type areas 6a' is 0.2μm to 4μm.

Claims

1. A conductive channel structure of a silicon carbide device, wherein the conductive channel structure is a first conductive type conductive channel structure (5), characterized in that: include: A first conductive type lower layer channel region (5a) is provided in the middle of a second conductive type buffer layer (3) of the silicon carbide device, a first conductive type sheet region (5a') is provided on the first conductive type lower layer channel region (5a), and the top of the first conductive type sheet region (5a') is located on the upper surface of the second conductive type buffer layer (3).

2. The conductive channel structure of the silicon carbide device according to claim 1, characterized in that: There are 1 to 3 first conductive type regions (5a'), the width of which is 0.2 μm to 4 μm, and the distance between adjacent first conductive type regions (5a') is 0.2 μm to 4 μm.

3. A conductive channel structure of a silicon carbide device, wherein the conductive channel structure is a second conductive type conductive channel structure (6), characterized in that: include: A second conductive type lower layer channel region (6a) is provided in the middle of the second conductive type buffer layer (3) of the silicon carbide device, a second conductive type sheet region (6a') is provided on the second conductive type lower layer channel region (6a), and the top of the second conductive type sheet region (6a') is located on the upper surface of the second conductive type buffer layer (3).

4. The conductive channel structure of the silicon carbide device according to claim 3, characterized in that: There are 1 to 3 second conductive type regions (6a'), the width of which is 0.2 μm to 4 μm, and the distance between adjacent second conductive type regions (6a') is 0.2 μm to 4 μm.

5. A fully integrated silicon carbide device comprising: A first conductive type silicon carbide substrate layer (1), a second conductive type epitaxial layer (2) is provided on the first conductive type silicon carbide substrate layer (1), a second conductive type buffer layer (3) is provided on the second conductive type epitaxial layer (2), and a field effect oxide layer (4) is covered on the second conductive type buffer layer (3), characterized in that a second conductive type isolation structure (7) is provided in the second conductive type buffer layer (3), and the second conductive type buffer layer (3) is divided into a low voltage region (101), a first high voltage region (102), and a second high voltage region (103) by the second conductive type isolation structure (7). A first conductive type silicon carbide LDMOS device is provided in a first high voltage region (102), and a first conductive type silicon carbide MOS device and / or a second conductive type silicon carbide MOS device are provided in a low voltage region (101) and a second high voltage region (103), respectively. The conductive channel structure of at least one of the first conductive type silicon carbide LDMOS device and the first conductive type silicon carbide MOS device is the first conductive type conductive channel structure (5) of claim 1, and / or the conductive channel structure of the second conductive type silicon carbide MOS device is the second conductive type conductive channel structure (6) of claim 2. The silicon carbide LDMOS device comprises a first conductive type well region (8) provided in a second conductive type buffer layer (3) located in a first high voltage region (102), and a first conductive type drain region (12D) of the silicon carbide LDMOS device provided in the first conductive type well region (8); a first conductive type well region (8) is also provided in the second conductive type buffer layer (3) in the second high voltage region (103), and a first conductive type heavily doped region (10312) is provided therein; a drain metal electrode (141D) is connected to the first conductive type drain region (12D) of the silicon carbide LDMOS device and the first conductive type heavily doped region (12).

6. The fully integrated silicon carbide device according to claim 5, characterized in that: The silicon carbide LDMOS device further comprises a second conductive type well region (9) provided in the second conductive type buffer layer (3); a first conductive type source region (121S) of the LDMOS, a second conductive type heavily doped region (131) and a conductive channel structure located between the first conductive type source region (121S) and the first conductive type well region (8) are provided in the second conductive type well region (9); a first source metal electrode (141S) is connected to the first conductive type source region (121S) and the second conductive type heavily doped region (131); a polysilicon gate (121G) of the LDMOS is provided above the conductive channel structure; a gate metal electrode (141G) of the LDMOS is connected to the polysilicon gate (121G); and a gate oxide layer (10) is provided between the polysilicon gate (121G) and the conductive channel of the LDMOS.

7. The fully integrated silicon carbide device according to claim 5 or 6, characterized in that: The first conductive type silicon carbide MOS device comprises a first conductive type source region (122S) of the first conductive type MOS, a second conductive type heavily doped region (132), a first conductive type drain region (122D), and a conductive channel structure located between the first conductive type source region (122S) and the first conductive type drain region (122D); a polysilicon gate (122G) of the first conductive type MOS is provided above the conductive channel structure; a gate oxide layer (10) is provided between the conductive channel structure and the polysilicon gate (122G); a gate metal electrode (142G) of the first conductive type MOS is connected to the polysilicon gate (122G); a source metal electrode (142S) of the first conductive type MOS is connected to the first conductive type source region (122S) and the second conductive type heavily doped region (132); and a drain metal electrode (142D) of the first conductive type MOS is connected to the first conductive type drain region (122D).

8. The fully integrated silicon carbide device according to claim 7, characterized in that: The second conductive type silicon carbide MOS device comprises a second conductive type source region (123S) of the second conductive type MOS, a first conductive type heavily doped region (133), a second conductive type drain region (123D), and a conductive channel structure located between the second conductive type source region (123S) and the second conductive type drain region (123D); a polysilicon gate (123G) of the second conductive type MOS is provided above the conductive channel structure; a gate oxide layer (10) is provided between the conductive channel structure and the polysilicon gate (123G); a gate metal electrode (143G) of the second conductive type MOS is connected to the polysilicon gate (123G); a source metal electrode (143S) of the second conductive type MOS is connected to the second conductive type source region (123S) and the first conductive type heavily doped region (133); and a drain metal electrode (143D) of the second conductive type MOS is connected to the second conductive type drain region (123D).

9. A fully integrated manufacturing process for a fully integrated silicon carbide device, characterized in that: The following steps are involved: A first conductive type substrate (1) is formed on a silicon carbide base, a second conductive type epitaxial layer (2) is grown on the first conductive type substrate (1), and a second conductive type buffer layer (3) is grown on the second conductive type epitaxial layer (2); Ion implantation is used to form two second conductive type isolation structures (7) that are as deep as the second conductive type epitaxial layer (2) in the second conductive type buffer layer (3), and the second conductive type isolation structures (7) divide the second conductive type buffer layer (3) into a low voltage region (101), a first high voltage region (102), and a second high voltage region (103); Ion implantation is performed on the second conductive type buffer layer (3) to form first conductive type well regions (8) in the low voltage region (101), the first high voltage region (102), and the second high voltage region (103); ion implantation is performed on the second conductive type buffer layer (3) in the first high voltage region (102) and the first conductive type well region (8) in the second high voltage region (103) to form a second conductive type well region (9); Ion implantation is used to form two first conductive type heavily doped regions serving as a source region (122S) and a drain region (122D) of a first conductive type silicon carbide MOS device and a first conductive type heavily doped region (133) of a second conductive type MOS device in the second conductive type buffer layer (3) and the first conductive type well region (8) of the low voltage region (101), and to form a first conductive type heavily doped region (133) serving as a drain region (122D) of a silicon carbide LDMOS device in the first conductive type well region (8) and the second conductive type well region (9) of the first high voltage region (102). A first conductive type heavily doped region and a first conductive type heavily doped region serving as a source region (121S) of a silicon carbide LDMOS device, and two first conductive type heavily doped regions serving as a source region (122S) and a drain region (122D) of a first conductive type silicon carbide MOS device and a first conductive type heavily doped region (133) of a second conductive type MOS device, and a first conductive type heavily doped region (10312) serving as a heavily doped ohmic contact region are formed in the second conductive type well region (9) and the first conductive type well region (8) of the second high voltage region (103); By ion implantation, a second conductive type heavily doped region (132) of a first conductive type MOS device and two second conductive type heavily doped regions serving as a source region (123S) and a drain region (123D) of a second conductive type silicon carbide MOS device are formed in the second conductive type buffer layer (3) and the first conductive type well region (8) of the low voltage region (101), a second conductive type heavily doped region (131) of a silicon carbide LDMOS device is formed in the second conductive type well region (9) of the first high voltage region (102), and a first conductive type well region (9) of the second high voltage region (103) is formed. (8) and the second conductive type well region (9) respectively form two second conductive type heavily doped regions serving as a source region (123S) and a drain region (123D) of a second conductive type silicon carbide MOS device and a second conductive type heavily doped region (132) of the first conductive type MOS device; The conductive channel structure is prepared, including the preparation of a first conductive type conductive channel structure (5) and a second conductive type conductive channel structure (6): the first conductive type conductive channel structure (5) is respectively prepared between a source region (122S) and a drain region (122D) of a first conductive type MOS device and between a source region (121S) of a silicon carbide LDMOS device and a first conductive type well region (8) of a first high voltage region (102); first, an ion implantation with a depth of 0.1 μm to 0.3 μm is performed in a second conductive type buffer layer (3); The first conductive type lower channel region (5a) is formed by implanting an ion implant into the first conductive type MOS device, and two ends of the first conductive type lower channel region (5a) in the first conductive type MOS device are respectively in contact with a source region (122S) and a drain region (122D) of the first conductive type MOS device, and two ends of the first conductive type lower channel region (5a) in the silicon carbide LDMOS device are respectively in contact with a source region (121S) of the silicon carbide LDMOS device and a first conductive type well region (8) of the first high voltage region (102), and then by adjusting the ion implantation window, an ion implantation window is formed in the first conductive type MOS device. Ion implantation is performed on a portion of the second conductive type buffer layer (3) above the conductive type lower channel region (5a) to form a first conductive type region (5a') isolated by the second conductive type buffer layer (3), and the first conductive type region (5a') contacts the first conductive type lower channel region (5a); the second conductive type conductive channel structure (6) is prepared between the source region (123S) and the drain region (123D) of the second conductive type MOS device, and is firstly respectively formed in the first conductive type well region (8) of the low voltage region (101) and the drain region (123D). and performing ion implantation at a depth of 0.1 μm to 0.3 μm in the first conductive type well region (8) of the second high voltage region (103) to form a second conductive type lower layer channel region (6a); and then performing ion implantation in a portion of the first conductive type well region (8) above the second conductive type lower layer channel region (6a) by adjusting the ion implantation window to form a second conductive type section region (6a') isolated by the first conductive type well region (8), and the first conductive type section region (6a') contacts the second conductive type lower layer channel region (6a); Afterwards, a gate oxide layer (10) is formed by wet method after annealing; and a first conductive Polysilicon is deposited above the first conductive type MOS conductive channel structure (5) and the second conductive type MOS conductive channel structure (6) to form a polysilicon gate (122G) of the first conductive type MOS, a polysilicon gate (121G) of the LDMOS, and a polysilicon gate (123G) of the second conductive type MOS; A field effect oxide layer (4) is deposited to allow the oxygen effect oxide layer (4) to cover the entire surface of the device; the field effect oxide layer (4) is etched and metal is deposited to respectively form a drain metal electrode (141D) of the LDMOS, a gate metal electrode (141G) of the LDMOS, a source metal electrode (141S) of the LDMOS, a drain metal electrode (142D) of the first conductive type MOS, a gate metal electrode (142G) of the first conductive type MOS, a source metal electrode (142S) of the first conductive type MOS, a drain metal electrode (143D) of the second conductive type MOS, a gate metal electrode (143G) of the second conductive type MOS, and a source metal electrode (143S) of the second conductive type MOS.

10. The fully integrated manufacturing process of a fully integrated silicon carbide device according to claim 7, characterized in that: There are 1 to 3 first conductive type areas (5a'), whose width is 0.2μm to 4μm, and the spacing between adjacent first conductive type areas (5a') is 0.2μm to 4μm. There are 1 to 3 second conductive type areas (6a'), whose width is 0.2μm to 4μm, and the spacing between adjacent second conductive type areas (6a') is 0.2μm to 4μm.

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