Resistive memory element and preparation method therefor

Abstract

A resistive memory element and a preparation method therefor. The resistive memory element comprises a lower electrode and an upper electrode, wherein a resistive layer (4) is provided between the upper electrode and the lower electrode; the lower electrode comprises a first lower electrode layer (2) and a second lower electrode layer (3) arranged on the first lower electrode layer (2); the second lower electrode layer (3) has a planar structure; and the vertical cross section of the resistive layer (4) and the vertical cross section of the upper electrode both have a U-shaped structure. The resistive memory element and the preparation method therefor can solve the problems of a short circuit easily occurring between upper and lower electrodes and the forming position of a "conductive filament" being unable to be controlled during a preparation process.

Description

Resistive memory element and preparation method thereof CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to Chinese patent application number 202410118704.2, filed on January 29, 2024, entitled “Resistive Memory Element and Method for Making the Same”. Technical Field

[0002] The disclosed embodiments relate to the field of semiconductor technology, and more specifically, to a resistive memory element and a method for preparing the same. Background Art

[0003] At present, the existing ReRAM (resistive RAM) manufacturing process is generally as follows: first, the lower electrode is prepared through thin film deposition, photolithography, etching, thin film deposition, and chemical mechanical polishing. The lower electrode includes a lower electrode first layer and a lower electrode second layer. Then, thin film deposition is performed to form a resistive switching layer and an upper electrode, and the corresponding resistive switching layer and upper electrode are prepared. The specific process is shown in Figure 1.

[0004] For ReRAM devices, a voltage is applied across the two ends of an RRAM (resistive random access memory) device. If this voltage exceeds the "forming voltage," a "conductive filament" (CF) will form between the electrodes, thereby putting the entire ReRAM device into a low-impedance state. However, for ReRAM fabricated using the aforementioned traditional manufacturing process, since its upper and lower electrodes cannot effectively concentrate the electric field, the voltage required to achieve the "conductive filament" state is relatively high, and this high voltage will have a significant impact on the performance of the ReRAM device.

[0005] In order to solve the above technical problems, those skilled in the art have proposed corresponding improvement processes. The specific improvement process scheme is shown in Figure 2, which includes the following steps: first, the preparation of the first layer of the lower electrode is completed by thin film deposition, photolithography, etching, thin film deposition, chemical mechanical grinding and other processes; then a concave cavity is formed above the first layer of the lower electrode by thin film deposition, photolithography, etching and other processes; then based on the concave cavity, the second layer of the lower electrode, a barrier layer and an upper electrode, all of which are U-shaped structures (concave structures) are formed in sequence on the first layer of the lower electrode by thin film deposition, chemical mechanical grinding and other processes, and finally the entire ReRAM is completed.

[0006] For the above-mentioned ReRAM prepared by improving the process, the U-shaped structure design can increase the curvature of the contact surface of the upper and lower electrodes, thereby effectively concentrating the electric field and making it easier to form a "conductive fiber" state.

[0007] However, the above-mentioned improvement scheme still has corresponding technical problems. For example, the second layer of the lower electrode, the resistive layer and the upper electrode are completed by the same chemical mechanical polishing process. In the chemical mechanical polishing process, too many metal film layer structures will increase the difficulty of the chemical mechanical polishing process. After the chemical mechanical polishing process is completed, due to the difficulty of the process, the electrode material residue on the cross-section of the entire chemical mechanical polishing process is likely to cause the upper and lower electrodes to short-circuit (the upper electrode and the second layer of the lower electrode are short-circuited); for example, the second layer of the lower electrode and the upper electrode use the same structural design (both are U-shaped structures) and cannot effectively control the formation position of the "conductive fiber". After applying voltage between the two electrodes, since the second layer of the lower electrode and the upper electrode are both U-shaped structures, "conductive fibers" may also be formed between the side walls of the second layer of the lower electrode and the side walls of the upper electrode, thereby affecting the stability of the entire device.

[0008] In view of this situation, there is an urgent need for a method that can effectively avoid the short circuit between the upper and lower electrodes of the resistive memory and the uncontrollable formation position of the "conductive fibers". Summary of the Invention

[0009] In view of the above problems, the purpose of the disclosed embodiments is to provide a new resistive memory element and its preparation method to solve the problems of upper and lower electrode short circuits and uncontrollable formation positions of "conductive fibers" in the existing resistive memory during the preparation process.

[0010] The resistive memory element provided by the disclosed embodiment includes a lower electrode and an upper electrode, a resistive layer is arranged between the upper electrode and the lower electrode, the lower electrode includes a lower electrode first layer and a lower electrode second layer arranged on the lower electrode first layer, wherein the lower electrode second layer is a planar structure, and the vertical cross-section of the resistive layer and the vertical cross-section of the upper electrode are both U-shaped structures.

[0011] In addition, a preferred solution is that the U-shaped structure includes a lower plane and a peripheral slope surface arranged outside the lower plane; wherein the angle between the peripheral slope surface and the lower plane is an obtuse angle.

[0012] In addition, a preferred solution is that the upper electrode includes a first upper electrode layer and a second upper electrode layer arranged on the first upper electrode layer, and the vertical cross-sections of the first upper electrode layer and the second upper electrode layer are both U-shaped structures.

[0013] In addition, a preferred solution is that the second lower electrode layer is prepared separately by an etching process, and the resistive layer, the first upper electrode layer and the second upper electrode layer are prepared together by chemical mechanical polishing.

[0014] In addition, a preferred solution is that the material of the second layer of the lower electrode includes tungsten.

[0015] In addition, a preferred solution is that the material of the upper electrode includes ALN.

[0016] On the other hand, the disclosed embodiment also provides a method for preparing a resistive memory element as described above, the preparation method comprising: preparing a first layer of a lower electrode on a copper substrate; preparing a second layer of a lower electrode on the first layer of the lower electrode, wherein the second layer of the lower electrode is a planar structure; forming a concave cavity above the second layer of the lower electrode; depositing a resistive layer film and an upper electrode film in sequence in the concave cavity; performing a grinding process on the resistive layer film and the upper electrode film together to form a resistive layer and an upper electrode above the second layer of the lower electrode; wherein the vertical cross-section of the resistive layer and the vertical cross-section of the upper electrode are both U-shaped structures.

[0017] In addition, a preferred solution is that the upper electrode includes a first upper electrode layer and a second upper electrode layer; in the process of preparing the resistive layer and the upper electrode: the resistive layer film, the first upper electrode film and the second upper electrode film are sequentially deposited in the concave cavity; the resistive layer film, the first upper electrode film and the second upper electrode film are jointly chemically mechanically polished to form a resistive layer, a first upper electrode layer and a second upper electrode layer above the second lower electrode layer; wherein the vertical cross-section of the resistive layer, the vertical cross-section of the first upper electrode layer and the vertical cross-section of the second upper electrode layer are all U-shaped structures.

[0018] In addition, a preferred solution is that the process of preparing the second lower electrode layer on the first lower electrode layer includes: depositing a second lower electrode layer thin film on the first lower electrode layer; and performing photolithography and etching on the second lower electrode layer thin film to form the second lower electrode layer on the first lower electrode layer.

[0019] In addition, a preferred solution is that, in the process of preparing the second layer of the lower electrode, an etch stop layer is also deposited on the second layer thin film of the lower electrode; and the process of forming a concave cavity above the second layer of the lower electrode includes: depositing a dielectric layer above the etch stop layer; performing photolithography and etching on the dielectric layer to form a concave cavity above the second layer of the upper electrode; wherein, the etching of the dielectric layer stops at the position of the etch stop layer.

[0020] In addition, a preferred solution is that the etch stop layer is removed by using wet diluted hydrofluoric acid after the concave cavity is formed.

[0021] In addition, a preferred solution is that the material of the etch stop layer includes ALO.

[0022] Compared with the prior art, the resistive memory element and the method for manufacturing the same according to the embodiments of the present disclosure have the following beneficial effects:

[0023] In the resistive memory element provided by the disclosed embodiments, the second layer of the lower electrode and the upper electrode have different structures. The second layer of the lower electrode is a planar structure formed by etching, while the upper electrode and the resistive switching layer are formed by chemical mechanical polishing to form a groove structure with a U-shaped vertical cross-section. When a voltage is applied between the upper and lower electrodes, since there is no portion corresponding to the second layer of the lower electrode below the sidewalls of the upper electrode, a forming state (i.e., no "conductive fibers") will not form on the sidewalls of the upper electrode. Instead, a forming state is easily formed at the corresponding portions of the two ends of the bottom of the upper electrode and the two ends of the planar structure of the lower electrode, thereby improving the stability of the entire device. In addition, in the method for fabricating the resistive memory element provided by the disclosed embodiments, the second layer of the lower electrode is fabricated by etching, and the barrier layer and the upper electrode are fabricated by chemical mechanical polishing. Since the second layer of the lower electrode is not fabricated together with the upper electrode by chemical mechanical polishing, a short circuit between the upper and lower electrodes will not occur during the fabrication of the upper electrode.

[0024] To achieve the above and related purposes, one or more aspects of the present disclosure include features that will be described in detail below and particularly pointed out in the claims. The following description and the accompanying drawings set forth certain exemplary aspects of the present disclosure in detail. However, these aspects are merely indicative of the various ways in which the principles of the present disclosure may be employed. Furthermore, the present disclosure is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] By referring to the following description in conjunction with the accompanying drawings, and with a more complete understanding of the present disclosure, other objects and results of the present disclosure will become more apparent and readily understood. In the accompanying drawings:

[0026] FIG1 is a flow chart of a conventional RRAM preparation process;

[0027] FIG2 is a flow chart showing an improvement to the conventional RRAM fabrication process;

[0028] FIG3 is a flow chart of a process for preparing a resistive memory element according to the first embodiment of the present disclosure;

[0029] FIG. 4 is a flow chart of a process for fabricating a resistive memory element according to a second embodiment of the present disclosure.

[0030] Reference numerals: copper substrate 1 , lower electrode first layer 2 , lower electrode second layer 3 , resistive layer 4 , upper electrode first layer 5 , upper electrode second layer 6 , etch-stop layer 7 .

[0031] The same reference numerals throughout the drawings indicate similar or corresponding features or functions. DETAILED DESCRIPTION

[0032] In the following description, for illustrative purposes, numerous specific details are set forth to provide a comprehensive understanding of one or more embodiments. However, it will be apparent that the embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form to facilitate description of one or more embodiments.

[0033] In the description of the present disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the devices or components referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as limiting the present disclosure; the terms "first", "second", and "third" are only used for descriptive purposes and should not be understood as indicating or implying relative importance; in addition, unless otherwise expressly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, an indirect connection through an intermediate medium, or it can be internal communication between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0034] Before introducing in detail the structure of the resistive memory element and its preparation method provided by the embodiments of the present disclosure, a brief introduction to RRAM is required. Resistive random access memory (RRAM) is a non-volatile memory based on the reversible conversion of the resistance of non-conductive materials between high-resistance and low-resistance states under the action of an external electric field. As an important electronic component of a resistive random access memory chip, the resistance of the memristor changes with the level of the applied voltage. Compared with other non-volatile memory technologies, RRAM is a high-speed memory. The obstacle that engineers encountered on the road to the research and development of memristor technology was precisely the stealth path of resistive random access memory (RRAM).

[0035] The structure of the resistive memory element and its manufacturing process provided by the embodiment of the present disclosure are described in detail below. FIG3 shows the process of manufacturing the resistive memory element according to the embodiment of the present disclosure.

[0036] As can be seen from the last step diagram in Figure 3, the resistive memory element provided by the embodiment of the present disclosure mainly includes a copper substrate 1 for supporting the main structure of RRAM, a lower electrode arranged on the copper substrate 1, a resistive layer 4 arranged on the lower electrode, and an upper electrode arranged on the resistive layer 4, wherein the resistive layer 4 is arranged between the upper electrode and the lower electrode.

[0037] Specifically, the upper electrode includes an upper electrode first layer 5 arranged on the resistive layer 4 and an upper electrode second layer 6 arranged on the upper electrode first layer 5; the lower electrode includes a lower electrode first layer 2 and a lower electrode second layer 3 arranged on the lower electrode first layer 2, the lower electrode first layer 2 is arranged on the copper substrate 11, and the resistive layer 4 is arranged between the lower electrode second layer 3 and the upper electrode first layer 5.

[0038] It should be noted that the lower electrode second layer 3 and the upper electrode (or resistive switching layer 4) in the resistive memory element provided in the disclosed embodiment are prepared separately from each other. The lower electrode second layer 3 in the resistive memory element provided in the disclosed embodiment is a planar structure manufactured by processes such as thin film deposition, photolithography, and etching. The barrier layer, the upper electrode first layer 5, and the upper electrode second layer 6 in the resistive memory element provided in the disclosed embodiment are groove-shaped structures with a U-shaped vertical cross-section, manufactured by processes such as sequential thin film deposition and joint chemical mechanical polishing. Through this design, when a voltage is applied between the upper and lower electrodes, since there is no corresponding portion of the lower electrode second layer 3 below the sidewall of the upper electrode, a forming state will not form at the sidewall of the upper electrode, that is, a "conductive fiber" state will not form. Instead, a forming state is easily formed at the corresponding portions at the two ends of the bottom of the upper electrode and the two ends of the planar structure of the lower electrode, thereby improving the stability of the entire device.

[0039] For RRAM, in order to realize its electrical characteristics, it is usually necessary to set a resistive switching layer 4 between the upper electrode and the lower electrode (i.e., between the lower electrode second layer 3 and the upper electrode first layer 5) to achieve the desired resistance switching effect.

[0040] Specifically, in order to achieve the electrical performance of RRAM, under normal circumstances, the upper electrode and the lower electrode are both arranged into a double-layer structure, that is, the upper electrode includes an upper electrode first layer 5 arranged on the resistive layer 4 and an upper electrode second layer 6 arranged on the upper electrode first layer 5; the lower electrode includes a lower electrode first layer 2 arranged on the copper substrate 1 and a lower electrode second layer 3 arranged on the lower electrode first layer 2.

[0041] It should be noted that the upper electrode first layer 5 and the upper electrode second layer 6 can be made of the same or different materials, and the lower electrode first layer 2 and the lower electrode second layer 3 can be made of the same or different materials; for example, for the lower electrode second layer 3, it is usually set to a tungsten film layer to achieve the required electrical effect, and the upper electrode first layer 5 is usually made of ALN (aluminum nitride or aluminum oxide), and the upper electrode second layer 6 is usually made of TIN (titanium nitride). Of course, for the selection of materials for the upper electrode first layer 5, the upper electrode second layer 6, the lower electrode first layer 2 and the lower electrode second layer 3, as long as they can meet the corresponding electrical properties, there is no restriction on the selection of specific materials.

[0042] To illustrate the preparation process of the resistive memory element provided by the present disclosure in detail, the preparation method of the resistive memory element provided by the present disclosure is described in detail below.

[0043] As shown in FIG3 , the method for preparing the resistive memory element provided in the embodiment of the present disclosure includes:

[0044] A first lower electrode layer 2 is prepared on a copper substrate 1;

[0045] A lower electrode second layer 3 is formed on the lower electrode first layer 2, wherein the lower electrode second layer 3 is a planar structure;

[0046] A concave cavity is formed above the second layer 3 of the lower electrode;

[0047] Depositing the resistive switching layer 4 and the upper electrode film in sequence in the concave cavity;

[0048] The resistive layer 4 film and the upper electrode film are polished together (preferably by chemical mechanical polishing) to form the resistive layer 4 and the upper electrode above the lower electrode second layer 3; wherein the vertical cross-sections of the resistive layer 4 and the upper electrode are both U-shaped structures.

[0049] Through the above steps of the method for preparing a resistive memory element provided by the embodiment of the present disclosure, it can be seen that, based on the original RRAM preparation improvement process route, the embodiment of the present disclosure separately prepares the second layer 3 of the lower electrode, and jointly prepares the resistive layer 4, the first layer 5 of the upper electrode, and the second layer 6 of the upper electrode using thin film deposition, chemical mechanical polishing processes, etc. Through this preparation process, it is possible to avoid short circuits between the upper electrode and the lower electrode during chemical mechanical polishing; in addition, the resistive memory element prepared by the method for preparing a resistive memory element provided by the embodiment of the present disclosure can also avoid the formation of a forming state at the sidewall position of the upper electrode, that is, no "conductive fiber" state is formed, and a forming state is easily formed at the corresponding positions at the two ends of the bottom of the upper electrode and the two ends of the lower electrode planar structure, thereby improving the stability of the entire device.

[0050] Specifically, the upper electrode includes a first upper electrode layer 5 and a second upper electrode layer 6. To prepare the resistive switching layer 4 and the upper electrode, the process of preparing the resistive switching layer 4 and the upper electrode includes:

[0051] First, a resistive layer 4 film, a top electrode first layer 5 film, and a top electrode second layer 6 film are deposited in sequence from bottom to top in the concave cavity; then, the resistive layer 4 film, the top electrode first layer 5 film, and the top electrode second layer 6 film are chemically mechanically polished as a whole based on a preset height to form the resistive layer 4, the top electrode first layer 5, and the top electrode second layer 6 above the bottom electrode second layer 3; wherein the vertical cross-sections of the resistive layer 4, the top electrode first layer 5, and the top electrode second layer 6 are all U-shaped structures.

[0052] It should be noted that the U-shaped structure generally includes a lower plane and a peripheral slope surface arranged outside the lower plane; wherein the angle between the peripheral slope surface and the lower plane is an obtuse angle, and the obtuse angle is close to 90 degrees.

[0053] More specifically, in order to realize the preparation of the lower electrode second layer 3, the process of preparing the lower electrode second layer 3 on the lower electrode first layer 2 may include: first depositing a layer of lower electrode second layer 3 thin film on the lower electrode first layer 2; and then performing photolithography and etching on the lower electrode second layer 3 thin film to form the lower electrode second layer 3 on the lower electrode first layer 2.

[0054] In addition, to prevent oxidation of the lower electrode second layer 3 during the photolithography and etching process, FIG4 shows a process flow for preparing a resistive memory element according to another embodiment of the present disclosure. As shown in FIG4 , during the preparation of the lower electrode second layer 3, an etch stop layer 7 is deposited on the lower electrode second layer 3 thin film; the material of the etch stop layer 7 can be selected from ALO or other films with anti-oxidation function; and the process of forming a concave cavity above the lower electrode second layer 3 includes: first depositing a dielectric layer above the etch stop layer 7; then photolithography and etching the dielectric layer to form a concave cavity above the upper electrode second layer 6; it should be noted that due to the presence of the etch stop layer 7, during the etching process of the dielectric layer, the etching will automatically stop at the position of the etch stop layer 7, thereby avoiding damage to the lower electrode second layer 3 when etching the dielectric layer and preventing oxidation of the lower electrode second layer 3.

[0055] After the concave cavity is formed (ie after the dielectric layer is etched), the etching stop layer is removed by wet diluted hydrofluoric acid, and then subsequent thin film deposition and chemical mechanical polishing of the resistive layer, the first upper electrode layer and the second upper electrode layer are performed.

[0056] As can be seen from the above specific embodiments, the resistive memory element and the manufacturing method thereof provided by the embodiments of the present disclosure have at least the following advantages:

[0057] 1. The first layer of the lower electrode and the second layer of the lower electrode are prepared separately to avoid the problem of residual electrode material sputtering to the RRAM and causing short circuit caused by the traditional process of preparing the upper and lower electrodes together.

[0058] 2. The resistive layer and the upper electrode are prepared by chemical mechanical polishing to prevent damage to the electrode material caused by etching and cleaning in the etching preparation process;

[0059] 3. The second layer of the lower electrode adopts a planar structure design, and the resistive layer and the upper electrode adopt a U-shaped structure with a vertical cross-section, which can reduce the forming voltage.

[0060] 4. The second layer of the lower electrode provided in the embodiment of the present disclosure is prepared by an etching process, and the resistive switching layer and the upper electrode are prepared by a mechanical chemical polishing process. Compared with the existing improvement scheme, the difficulty of the mechanical polishing process can be reduced, and the risk of residual residue causing short circuit or leakage of the upper and lower electrodes can be avoided;

[0061] 5. The disclosed embodiment can avoid damage to the second layer of the lower electrode when etching the dielectric layer by providing an etch stop layer on the second layer of the lower electrode, thereby preventing oxidation of the second layer of the lower electrode.

[0062] The resistive memory element and its preparation method according to the embodiments of the present disclosure are described above by way of example with reference to FIG3 and FIG4 . However, those skilled in the art will appreciate that various improvements may be made to the resistive memory element and its preparation method proposed in the above-mentioned embodiments of the present disclosure without departing from the content of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the content of the appended claims.

Claims

1. A resistive memory element, comprising a lower electrode and an upper electrode, wherein a resistive switching layer is provided between the upper electrode and the lower electrode, wherein: The lower electrode includes a lower electrode first layer and a lower electrode second layer disposed on the lower electrode first layer, wherein the lower electrode second layer is a planar structure, and the vertical cross-sections of the resistive layer and the upper electrode are both U-shaped structures.

2. The resistive memory element according to claim 1, wherein The U-shaped structure includes a lower plane and a peripheral slope surface arranged outside the lower plane; wherein, The included angle between the peripheral slope surface and the lower plane is an obtuse angle.

3. The resistive memory element according to claim 1, wherein The upper electrode includes a first upper electrode layer and a second upper electrode layer disposed on the first upper electrode layer. Both the vertical cross-sections of the first upper electrode layer and the second upper electrode layer are U-shaped structures.

4. The resistive memory element according to claim 3, wherein: The second layer of the lower electrode is prepared separately by an etching process, and the resistive layer, the first layer of the upper electrode and the second layer of the upper electrode are prepared together by chemical mechanical polishing.

5. The resistive memory element according to claim 4, wherein: The material of the second layer of the lower electrode includes tungsten.

6. The resistive memory element according to any one of claims 1 to 5, wherein: The material of the upper electrode includes ALN.

7. A method for preparing a resistive memory element according to any one of claims 1 to 6, characterized in that: The preparation method comprises: preparing a first layer of a lower electrode on a copper substrate; preparing a second lower electrode layer on the first lower electrode layer, wherein the second lower electrode layer is a planar structure; forming a concave cavity above the second layer of the lower electrode; Depositing a resistive switching layer film and an upper electrode film in sequence in the concave cavity; The resistive switching layer film and the upper electrode film are polished together to form a resistive switching layer and an upper electrode above the second layer of the lower electrode; wherein the vertical cross-sections of the resistive switching layer and the upper electrode are both U-shaped structures.

8. The method for preparing a resistive memory element according to claim 7, wherein: The upper electrode includes a first upper electrode layer and a second upper electrode layer; in the process of preparing the resistive switching layer and the upper electrode: Depositing a resistive switching layer film, a first upper electrode film, and a second upper electrode film in sequence in the concave cavity; The resistive layer film, the upper electrode first layer film and the upper electrode second layer film are jointly subjected to chemical mechanical polishing to form a resistive layer, an upper electrode first layer and an upper electrode second layer above the lower electrode second layer; wherein the vertical cross-section of the resistive layer, the vertical cross-section of the upper electrode first layer and the vertical cross-section of the upper electrode second layer are all U-shaped structures.

9. The method for preparing a resistive memory element according to claim 7, wherein: The process of preparing the second lower electrode layer on the first lower electrode layer includes: depositing a second lower electrode thin film layer on the first lower electrode layer; The lower electrode second layer thin film is subjected to photolithography and etching to form a lower electrode second layer on the lower electrode first layer.

10. The method for preparing a resistive memory element according to claim 9, wherein: During the preparation of the second layer of the lower electrode, an etching stop layer is deposited on the second layer of the lower electrode film; and, The process of forming a concave cavity above the second layer of the lower electrode comprises: depositing a dielectric layer above the etch stop layer; The dielectric layer is photolithographically and etched to form a concave cavity above the second layer of the upper electrode; wherein the etching of the dielectric layer stops at the position of the etch stop layer.

11. The method for preparing a resistive memory element according to claim 10, wherein: The etch stop layer is removed by using wet diluted hydrofluoric acid after the concave cavity is formed.

12. The method for preparing a resistive memory element according to claim 10, wherein: in, The material of the etch stop layer includes ALO.

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