Solar cell preparation method, solar cell and photovoltaic module

Abstract

The present application relates to the technical field of solar cells, in particular to a solar cell preparation method, a solar cell and a photovoltaic module. The preparation method comprises: preparing on a light-receiving surface of a silicon substrate a first dielectric layer, a first amorphous silicon layer and a first mask layer which are sequentially stacked away from the silicon substrate; removing the first mask layer, the first amorphous silicon layer and the first dielectric layer which are outside a first region; preparing on a back side of the silicon substrate a second dielectric layer, a second amorphous silicon layer and a second mask layer which are sequentially stacked away from the silicon substrate; and performing single-sided etching on the light-receiving surface, so as to remove a wrap-around plating layer of the second mask layer on the light-receiving surface and edges of the silicon substrate, wherein the second mask layer on the back side and the first mask layer of partial thickness are retained.

Description

A method for preparing a solar cell, a solar cell and a photovoltaic module

[0001] Related applications

[0002] This application claims priority to Chinese patent application No. 2024101374053, filed on February 1, 2024, entitled “A method for preparing a solar cell, a solar cell and a photovoltaic module,” the entire text of which is hereby incorporated by reference. Technical Field

[0003] The present application relates to the field of solar cell technology, and in particular to a method for preparing a solar cell, a solar cell, and a photovoltaic module. Background Art

[0004] The passivation contact structure consists of an ultra-thin layer of silicon oxide and a layer of heavily doped polysilicon. It is mainly used for passivation of the battery surface, which can achieve excellent surface passivation and selective collection of carriers. It can also be located between the silicon substrate and the metal electrode, replacing the silicon substrate and the metal electrode to form an ohmic contact, preventing the metal electrode from directly contacting the silicon substrate and generating a large number of recombination centers in the silicon substrate, thereby passivating the metallized area.

[0005] The passivated contact battery in traditional technology has a passivated contact structure on the backlight side, while the light-receiving side is still in direct contact with the metal and the semiconductor. The recombination loss at the contact between the metal and the semiconductor limits the further improvement of the battery efficiency. The above problem can be avoided by using a double-sided passivated contact structure, that is, a passivated contact structure is set on both the light-receiving side and the backlight side of the battery. Although the passivated contact structure can greatly reduce the metallization recombination, the light absorption characteristics of the poly layer of the passivated contact structure on the light-receiving side will affect the battery's absorption of light. Therefore, only the area on the light-receiving surface that needs to be metallized to make the electrode can be locally passivated. However, in the process of realizing local passivation of the light-receiving surface, there is a problem of damaging the battery structure due to the need to remove the wrap-around plating, which cannot really effectively improve the battery efficiency. Summary of the Invention

[0006] According to various embodiments of the present application, a method for preparing a solar cell, a solar cell, and a photovoltaic module are provided.

[0007] In a first aspect, an embodiment of the present application provides a method for preparing a solar cell, comprising the following steps:

[0008] A first dielectric layer, a first amorphous silicon layer, and a first mask layer are sequentially stacked on a light-receiving surface of a silicon substrate and are formed away from the silicon substrate; wherein the silicon substrate and the first amorphous silicon layer both have a first conductivity type, and the light-receiving surface has a first region for forming a light-receiving surface electrode;

[0009] removing the first mask layer, the first amorphous silicon layer, and the first dielectric layer outside the first region;

[0010] A second dielectric layer, a second amorphous silicon layer, and a second mask layer are sequentially stacked on the backlight side of the silicon substrate and away from the silicon substrate; wherein the second amorphous silicon layer has a second conductivity type opposite to the first conductivity type;

[0011] Annealing to crystallize the first amorphous silicon layer and the second amorphous silicon layer to form a first doped polysilicon layer and a second doped polysilicon layer respectively;

[0012] Performing single-sided etching on the light-receiving surface to remove the wrap-around coating of the second mask layer on the light-receiving surface and the edge of the silicon substrate, and stopping etching before the first mask layer is completely etched after the wrap-around coating of the second mask layer is removed; wherein the second mask layer on the backlight surface and a portion of the thickness of the first mask layer are retained;

[0013] Etching the area outside the area covered by the second mask layer and the first mask layer to remove the second doped polysilicon layer and the second dielectric layer on the light-receiving surface and the edge of the silicon substrate; and

[0014] The remaining first mask layer and the second mask layer are removed.

[0015] In some embodiments, the step of single-sided etching the light-receiving surface to remove the wrap-around coating of the second mask layer on the light-receiving surface and the edge of the silicon substrate, and stopping etching before the first mask layer is completely etched after the wrap-around coating of the second mask layer is removed, comprises:

[0016] The light-receiving surface is pickled on one side using hydrofluoric acid with a mass percentage concentration of x%, and the hydrofluoric acid cleaning time t1 is controlled to satisfy: t2≤t1<t3, t2 is the time required for the second mask layer to be completely removed in the hydrofluoric acid with a mass percentage concentration of x%, and t3 is the time required for the first mask layer to be completely removed in the hydrofluoric acid with a mass percentage concentration of x%.

[0017] In some embodiments, the thickness of the first mask layer is greater than the thickness of the second mask layer around the plating layer.

[0018] In some embodiments, in a hydrofluoric acid solution of the same concentration, the etching rate of the second mask layer around the plating layer is greater than the etching rate of the first mask layer.

[0019] In some embodiments, the step of removing the first mask layer, the first amorphous silicon layer, and the first dielectric layer outside the first region includes:

[0020] forming an acid-resistant slurry corresponding to the first region on a side of the first mask layer facing away from the first amorphous silicon layer;

[0021] removing the first mask layer, the first amorphous silicon layer, and the first dielectric layer outside the coverage of the acid-resistant slurry; and

[0022] The acid-resistant slurry is removed.

[0023] In some embodiments, the step of forming an acid-resistant slurry corresponding to the first region on a side of the first mask layer facing away from the first amorphous silicon layer includes:

[0024] The acid-resistant slurry is coated on the first mask layer by printing or spraying.

[0025] In some embodiments, the coating width of the acid-resistant slurry is about 60 μm to 200 μm.

[0026] In some embodiments, the step of removing the first mask layer, the first amorphous silicon layer, and the first dielectric layer outside the coverage of the acid-resistant slurry includes:

[0027] Etching is performed using a mixed solution of hydrofluoric acid and nitric acid.

[0028] In some embodiments, the mass percentage concentration of hydrofluoric acid in the mixed solution of hydrofluoric acid and nitric acid is 0.1% to 10%, and the mass percentage concentration of nitric acid is 10% to 50%.

[0029] In some embodiments, the step of removing the acid-resistant slurry comprises:

[0030] The anti-acid slurry is removed by washing with a mixed solution of alkali and hydrogen peroxide.

[0031] In some embodiments, the cleaning time using the mixed solution of alkali and hydrogen peroxide is about 1 min to 20 min.

[0032] In some embodiments, after the step of removing the first mask layer, the first amorphous silicon layer, and the first dielectric layer outside the first region, and before the step of forming a second dielectric layer, a second amorphous silicon layer, and a second mask layer stacked sequentially on the backlight side of the silicon substrate away from the silicon substrate, the method for preparing a solar cell further includes the following steps:

[0033] Alkali is used to etch the area outside the first region under the action of additives, and a backlight surface morphology is formed on the backlight surface, wherein the backlight surface morphology includes a polished surface or a velvet surface.

[0034] In some embodiments, the step of etching the area outside the area covered by the second mask layer and the first mask layer to remove the second doped polysilicon layer and the second dielectric layer on the light-receiving surface and edge of the silicon substrate includes:

[0035] Alkaline etching is performed on the areas outside the areas covered by the second mask layer and the first mask layer to remove the second doped polysilicon layer and the coating layer of the second dielectric layer on the light-receiving surface and the edge of the silicon substrate, the light-receiving surface is textured to form a textured surface on the light-receiving surface, and the exposed doped layer on the light-receiving surface is removed; wherein the doped layer is formed in the step of forming the first doped polysilicon layer and the second doped polysilicon layer respectively after annealing to crystallize the first amorphous silicon layer and the second amorphous silicon layer.

[0036] In some embodiments, before the step of preparing a first dielectric layer, a first amorphous silicon layer, and a first mask layer stacked in sequence away from the silicon substrate on the light-receiving surface of the silicon substrate, the method for preparing a solar cell further includes:

[0037] The silicon substrate is textured to form a textured surface on the light-receiving surface.

[0038] In some embodiments, the step of preparing a first dielectric layer, a first amorphous silicon layer, and a first mask layer stacked in sequence away from the silicon substrate on the light-receiving surface of the silicon substrate includes:

[0039] The first dielectric layer, the first amorphous silicon layer and the first mask layer are sequentially stacked from the inside to the outside on the light-receiving surface by using PECVD.

[0040] In some embodiments, the step of removing the remaining first mask layer and the second mask layer includes:

[0041] Acid washing is performed to remove the remaining first mask layer and the second mask layer.

[0042] In some embodiments, after the step of removing the remaining first mask layer and the second mask layer, the method for preparing a solar cell further includes the following steps:

[0043] forming a first functional layer on the light-receiving surface;

[0044] Producing a second functional layer on the backlight surface; and

[0045] A light-receiving surface electrode is fabricated on the light-receiving surface, and a backlight surface electrode is fabricated on the backlight surface; wherein the light-receiving surface electrode penetrates the first functional layer and is in ohmic contact with the first doped polysilicon layer, and the backlight surface electrode penetrates the second functional layer and is in ohmic contact with the second doped polysilicon layer.

[0046] In some embodiments, the first dielectric layer includes a silicon oxide layer.

[0047] In some embodiments, the thickness of the first dielectric layer is approximately 0.1 nm to 5 nm.

[0048] In some embodiments, the thickness of the first amorphous silicon layer is approximately 25 nm to 250 nm.

[0049] In some embodiments, the first functional layer includes an aluminum oxide passivation layer.

[0050] In some embodiments, the thickness of the first functional layer is about 2 nm to 10 nm.

[0051] In some embodiments, the first functional layer includes a silicon nitride passivation and anti-reflection layer.

[0052] In some embodiments, the thickness of the first functional layer is about 70 nm to 90 nm.

[0053] In some embodiments, the second dielectric layer includes a silicon oxide layer.

[0054] In some embodiments, the thickness of the second dielectric layer is approximately 0.1 nm to 5 nm.

[0055] In some embodiments, the thickness of the second amorphous silicon layer is approximately 30 nm to 300 nm.

[0056] In some embodiments, the second functional layer includes a silicon nitride passivation and anti-reflection layer.

[0057] In some embodiments, the second functional layer has a thickness of about 70 nm to about 90 nm.

[0058] In some embodiments, the first mask layer includes at least one of a silicon oxynitride layer and a silicon nitride layer.

[0059] In some embodiments, the thickness of the silicon oxynitride layer in the first mask layer is approximately 20 nm to 80 nm.

[0060] In some embodiments, the thickness of the silicon nitride layer in the first mask layer is approximately 10 nm to 50 nm.

[0061] In some embodiments, the second mask layer includes at least one of a silicon oxide layer and a silicon oxynitride layer.

[0062] In some embodiments, the thickness of the silicon oxide layer in the second mask layer is about 5 nm to 50 nm.

[0063] In some embodiments, the thickness of the silicon oxynitride layer in the second mask layer is about 3 nm to 30 nm.

[0064] In a second aspect, an embodiment of the present application provides a solar cell, which is prepared using the solar cell preparation method as described in the first aspect.

[0065] In a third aspect, an embodiment of the present application provides a photovoltaic module comprising the solar cell as described in the second aspect.

[0066] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0068] FIG1 is a flow chart of a method for preparing a solar cell according to the present application;

[0069] FIG2 is a schematic diagram of step 1 in the method for preparing a solar cell in Example 1;

[0070] FIG3 is a schematic diagram of step 2 in the method for preparing a solar cell in Example 1;

[0071] FIG4 is a schematic diagram of step 3 in the method for preparing a solar cell in Example 1;

[0072] FIG5 is a schematic diagram of step 4 in the method for preparing a solar cell in Example 1;

[0073] FIG6 is a schematic diagram of step 5-1 in the method for preparing a solar cell in Example 1;

[0074] FIG7 is a schematic diagram of step 5-2 in the method for preparing a solar cell in Example 1;

[0075] FIG8 is a schematic diagram of step 5-3 in the method for preparing a solar cell in Example 1;

[0076] FIG9 is a schematic diagram of step 6 in the method for preparing a solar cell in Example 1;

[0077] FIG10 is a schematic diagram of step 7 in the method for preparing a solar cell in Example 1;

[0078] FIG11 is a schematic diagram of step 8-1 in the method for preparing a solar cell in Example 1;

[0079] FIG12 is a schematic diagram of step 8-3 in the method for preparing a solar cell in Example 1;

[0080] FIG13 is a schematic diagram of step 8-5 in the method for preparing a solar cell in Example 1;

[0081] FIG14 is a schematic diagram of step 9 in the method for preparing a solar cell in Example 1;

[0082] FIG15 is a schematic diagram of step 10 in the method for preparing a solar cell in Example 1.

[0083] Explanation of the accompanying drawings: 100, solar cell; 101, silicon substrate; 1011, metallized area; 102, first dielectric layer; 103, first doped polysilicon layer; 104, first functional layer; 105, second dielectric layer; 106, second doped polysilicon layer; 107, second functional layer; 108, light-receiving surface electrode; 109, backlight surface electrode; 110, first amorphous silicon layer; 111, first mask layer; 112, second amorphous silicon layer; 113, second mask layer; 114, acid-resistant slurry. DETAILED DESCRIPTION

[0084] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0085] The efficiency of solar cells with passivated contacts is currently difficult to further improve. In traditional technology, the efficiency of this type of solar cell is improved by setting a double-sided passivated contact structure and performing local passivation on the passivated contact structure on the light-receiving surface. However, when performing local passivation on the light-receiving surface, operations such as de-plating are often required. De-plating may cause certain damage to the light-receiving surface of the cell structure, thereby affecting further improvement of the cell efficiency. For example, in order to achieve a double-sided passivated contact structure for a solar cell and set the light-receiving surface as a local passivated contact structure, the following operations can be used:

[0086] Depositing a first passivation contact structure on the light-receiving surface of the silicon substrate by PECVD or other methods, wherein the first passivation contact structure includes a first dielectric layer and a first doped polysilicon layer;

[0087] A second passivation contact structure is deposited on the backlit side of the silicon substrate using methods such as PECVD. The second passivation contact structure includes a second dielectric layer and a second polysilicon layer. After depositing the above structure, the second passivation contact structure will inevitably have wraparound plating on the light-receiving side and will be located on the same surface as the first passivation contact structure.

[0088] In order to obtain a locally passivated first passivation contact structure, the first passivation contact structure can be graphically etched before or after the deposition of the second passivation contact structure. Regardless of the method adopted, as long as the second passivation contact structure is formed, the problem of de-plating the second passivation contact structure on the light-receiving surface will be involved, and the chemicals used for de-plating the second passivation contact structure also have an etching effect on the first passivation contact structure. It can be seen that it is difficult to avoid the problem of damage to the light-receiving surface structure of the battery while removing the de-plating of the second passivation contact structure on the light-receiving surface. The present application proposes a solution based on this problem, which can not only obtain a double-sided passivation contact structure with local passivation of the light-receiving surface, but also avoid the problem of damage to the battery structure on the light-receiving surface due to the de-plating operation.

[0089] Other preparation methods, such as the preparation method of selective emitter cells, have problems such as long process flow, high production cost, and difficulty in mass production.

[0090] Based on the above analysis, the embodiment of the present application provides a method for preparing a solar cell, which performs a single-sided pickling on the light-receiving surface to remove the second mask layer and the first mask layer of the light-receiving surface and the edge, and retains the first mask layer of the first mask layer of the backlight side. When the second doped polysilicon layer and the second dielectric layer of the light-receiving surface and the edge are subsequently removed by alkaline etching, the first mask layer protects the patterned first dielectric layer and the first doped polysilicon layer corresponding to the metallized area, and the second mask layer of the backlight side protects the second doped polysilicon layer and the second dielectric layer of the backlight side, thereby smoothly removing the plating. Compared with the related art of using selective emitter passivation contact solar cell preparation, two processes can be saved, reducing production costs.

[0091] The technical solution of this application will be described below with reference to embodiments and drawings.

[0092] In a first aspect, an embodiment of the present application provides a method for preparing a solar cell, comprising the following steps:

[0093] A first dielectric layer, a first amorphous silicon layer, and a first mask layer are sequentially stacked and formed on a light-receiving surface of a silicon substrate, the first dielectric layer being away from the silicon substrate; wherein the silicon substrate and the first amorphous silicon layer both have a first conductivity type, and the light-receiving surface has a first region for forming a light-receiving surface electrode;

[0094] removing the first mask layer, the first amorphous silicon layer, and the first dielectric layer outside the first region;

[0095] A second dielectric layer, a second amorphous silicon layer, and a second mask layer are sequentially stacked on the backlight side of the silicon substrate and away from the silicon substrate; wherein the second amorphous silicon layer has a second conductivity type opposite to the first conductivity type;

[0096] Annealing to crystallize the first amorphous silicon layer and the second amorphous silicon layer to form a first doped polysilicon layer and a second doped polysilicon layer respectively;

[0097] Single-sided etching is performed on the light-receiving surface to remove the light-receiving surface and the wrap-around coating of the second mask layer on the edge of the silicon substrate, and etching is stopped after the wrap-around coating of the second mask layer is removed and before the first mask layer is completely etched; wherein the second mask layer and a portion of the first mask layer on the backlight surface are retained;

[0098] Etching the area outside the area covered by the second mask layer and the first mask layer to remove the second doped polysilicon layer and the surrounding coating of the second dielectric layer on the light-receiving surface and the edge of the silicon substrate; and

[0099] The remaining first mask layer and the second mask layer are removed.

[0100] The present application performs single-sided etching on the light-receiving surface to selectively remove the first mask layer and the second mask layer, and the second mask layer on the backlight side is retained without being exposed to the etching solution. At the same time, the difference in the time required for complete etching and removal of the first mask layer and the second mask layer is utilized to remove the coating layer of the second mask layer on the light-receiving surface and edge of the silicon substrate. A portion of the thickness of the first mask layer is inevitably exposed to the etching solution and removed, but at the same time a portion of the thickness of the first mask layer is retained.

[0101] In the step of etching the area outside the area covered by the second mask layer and the first mask layer to remove the second doped polysilicon layer and the second dielectric layer on the light-receiving surface and edge of the silicon substrate, since the second mask layer and the first mask layer react very little with the etching solution used in this step, the retained partial thickness of the first mask layer protects the local passivation contact structure of the light-receiving surface, that is, the first dielectric layer and the first doped polysilicon layer corresponding to the first area, and the second mask layer on the backlight side protects the passivation contact structure of the backlight side, that is, the second dielectric layer and the second doped polysilicon layer, thereby smoothly removing the dielectric layer of the passivation contact structure on the backlight side without damaging the local passivation contact structure on the light-receiving surface.

[0102] In the preparation method of the present application, annealing is performed after the first and second amorphous silicon layers are formed. In the step of annealing to crystallize the first and second amorphous silicon layers to form the first and second doped polycrystalline silicon layers, respectively, the first and second amorphous silicon layers can be annealed separately, i.e., annealed twice. Alternatively, the first and second amorphous silicon layers can be crystallized simultaneously in a single annealing step to save energy and reduce process steps.

[0103] It should be noted that the silicon substrate can be either N-type or P-type. When the silicon substrate is N-type, the first amorphous silicon layer is also N-type, and the second amorphous silicon layer is P-type. When the silicon substrate is P-type, the first amorphous silicon layer is also P-type, and the second amorphous silicon layer is N-type. However, regardless of whether the silicon substrate is N-type or P-type, after annealing, the dopant elements in the second doped polysilicon layer are pushed into the silicon substrate to form a PN junction.

[0104] After forming the local first amorphous silicon layer corresponding to the first region, annealing is performed to form a local diffusion region corresponding to the first region on the light-receiving surface of the silicon substrate. The local diffusion region can serve as a heavily doped region, allowing carriers in the silicon substrate to be easily transferred to the first doped polycrystalline silicon layer through the local diffusion region. In other words, the local diffusion region acts as a carrier transmission channel. No diffusion region is provided in areas of the light-receiving surface other than the first region, thereby preventing excessive doping concentration in areas other than the first region and suppressing Auger recombination.

[0105] Compared with the selective emitter passivation contact battery process route in the related art, the present application omits the boron diffusion process and the selective emitter process, making the preparation process more streamlined and requiring less equipment, which is conducive to reducing costs.

[0106] In some embodiments, single-sided etching is performed on the light-receiving surface to remove the wrap-around coating of the second mask layer on the light-receiving surface and the edge of the silicon substrate, and the etching is stopped before the first mask layer is completely etched after the wrap-around coating of the second mask layer is removed, comprising:

[0107] Use hydrofluoric acid with a mass percentage concentration of x% to perform single-sided pickling on the light-receiving surface, and control the hydrofluoric acid cleaning time t1 to satisfy: t2≤t1<t3, t2 is the time required for the second mask layer to be completely removed in the hydrofluoric acid with a mass percentage concentration of x%, and t3 is the time required for the first mask layer to be completely removed in the hydrofluoric acid with a mass percentage concentration of x%.

[0108] Illustratively, in hydrofluoric acid with a mass percentage concentration of x%, x in x% is 1 to 20, including any value within the numerical range, for example, 1, 5, 7, 8, 9, 10, 11, 12, 13, 14, 16, 17, 19 or 20.

[0109] It can be understood that the present application selectively removes the entire second mask layer on the light-receiving surface during single-sided etching of the light-receiving surface by controlling the acid resistance difference and etching time of the second mask layer and the first mask layer, but retains a partial thickness of the first mask layer.

[0110] In some embodiments, the thickness of the first mask layer is greater than that of the second mask layer. Even if the first mask layer and the second mask layer are made of the same material, the time required to completely remove the first mask layer and the second mask layer in hydrofluoric acid still satisfies: t3>t2.

[0111] In some embodiments, in a hydrofluoric acid solution of the same concentration, the etching rate of the second mask layer is greater than the etching rate of the first mask layer; even if the first mask layer and the second mask layer have the same thickness, the time required to completely remove the first mask layer and the second mask layer in hydrofluoric acid still satisfies: t3>t2.

[0112] It should be understood that the above embodiments are only some examples of making t3>t2.

[0113] In some embodiments, the step of removing the first mask layer, the first amorphous silicon layer, and the first dielectric layer outside the first region includes:

[0114] forming an acid-resistant slurry corresponding to the first area on a side of the first mask layer facing away from the first amorphous silicon layer;

[0115] removing the first mask layer, the first amorphous silicon layer, and the first dielectric layer outside the coverage of the acid-resistant slurry; and

[0116] Remove acid-resistant slurry.

[0117] This application uses a slurry method to produce a localized passivation contact structure. The acid-resistant slurry can contain paraffin wax, an organic solvent, or the like, and becomes waxy after drying and solidification. The acid-resistant slurry has a certain acid resistance, so a mixed acid solution can be used to sequentially remove the first mask layer, the first amorphous silicon layer, and the first dielectric layer outside the coverage area of ​​the acid-resistant slurry in a single etching and cleaning process.

[0118] It should be noted that the step of removing the first mask layer, the first amorphous silicon layer, and the first dielectric layer outside the first region can be performed not only by a slurry method but also by a laser removal method or other methods. Compared with the laser removal method, the slurry method is more capable of removing the first mask layer, the first amorphous silicon layer, and the first dielectric layer that are plated around the edge of the silicon substrate.

[0119] In some embodiments, the step of forming an acid-resistant paste corresponding to the first region on a side of the first mask layer facing away from the first amorphous silicon layer includes:

[0120] The acid-resistant slurry is coated on the first mask layer by printing or spraying.

[0121] Optionally, the coating width of the acid-resistant slurry is about 60 μm to 200 μm.

[0122] The acid-resistant paste can be applied more accurately according to the pattern of the first area by printing or spraying. Printing is an option, and the acid-resistant paste pattern obtained by printing has higher precision.

[0123] In some embodiments, the step of removing the first mask layer, the first amorphous silicon layer, and the first dielectric layer outside the coverage area of ​​the acid-resistant slurry includes:

[0124] Etching is performed using a mixed solution of hydrofluoric acid and nitric acid.

[0125] Optionally, in the mixed solution of hydrofluoric acid and nitric acid, the mass percentage concentration of hydrofluoric acid is approximately 0.1% to 10%, including any value within this mass percentage concentration range, such as 0.1%, 1%, 2%, 5%, 8%, or 10%. The mass percentage concentration of nitric acid is approximately 10% to 50%, including any value within this mass percentage concentration range, such as 10%, 20%, 25%, 30%, 40%, or 50%.

[0126] The hydrofluoric acid and nitric acid mixture in the above ratio can remove the first mask layer, the first amorphous silicon layer, and the first dielectric layer within 30 to 300 seconds, allowing for the rapid production of a localized passivation contact structure. It is understood that while the hydrofluoric acid and nitric acid mixture also has a certain etching effect on the textured surface on the light-receiving surface outside the slurry coverage area, this will be retextured to a textured surface in subsequent steps.

[0127] It should be noted that, in the step of removing the first mask layer, the first amorphous silicon layer and the first dielectric layer outside the coverage of the acid-resistant slurry, the etching removal can be performed step by step. For example, the first mask layer outside the coverage of the acid-resistant slurry is first removed by acid etching, and then the first amorphous silicon layer and the first dielectric layer outside the coverage of the acid-resistant slurry are removed by alkaline etching. However, step-by-step etching will cause the process flow to be too long. That is, etching with a mixed solution of hydrofluoric acid and nitric acid can simplify the process flow.

[0128] In some embodiments, the step of removing the acid-resistant slurry comprises:

[0129] Use a mixed solution of alkali and hydrogen peroxide to remove the acid-resistant slurry.

[0130] Optionally, the cleaning is performed using a mixed solution of alkali and hydrogen peroxide for about 1 to 20 minutes.

[0131] For example, in the mixed solution of alkali and hydrogen peroxide, the mass concentration of the alkali is 0.1% to 10%, and the mass concentration of the hydrogen peroxide is 0.1% to 10%. The use of the mixed solution of alkali and hydrogen peroxide has no special effect on the silicon substrate.

[0132] In some embodiments, after the step of removing the first mask layer, the first amorphous silicon layer, and the first dielectric layer outside the first region, and before the step of forming a second dielectric layer, a second amorphous silicon layer, and a second mask layer stacked sequentially on the backlight side of the silicon substrate away from the silicon substrate, the method for preparing a solar cell further includes the following steps:

[0133] Alkali is used to etch the area outside the first region under the action of the additive, and a backlight surface morphology is formed on the backlight surface, wherein the backlight surface morphology includes a polished surface or a velvet surface.

[0134] The backlight surface morphology formed by etching the backlight surface makes it meet the requirements of subsequent processes. This step is performed after the step of removing the acid-resistant slurry. Both steps are alkaline etching processes and can be completed in the same equipment, reducing the number of equipment and simplifying the process flow.

[0135] In some embodiments, the step of etching the area outside the area covered by the second mask layer and the first mask layer to remove the second doped polysilicon layer and the second dielectric layer on the light-receiving surface and the edge of the silicon substrate includes:

[0136] The areas outside the coverage areas of the second mask layer and the first mask layer are subjected to alkaline etching to remove the second doped polysilicon layer and the second dielectric layer on the light-receiving surface and the edge of the silicon substrate, and the light-receiving surface is textured to form a textured surface on the light-receiving surface, and the exposed doped layer on the light-receiving surface is removed; wherein, the doped layer is formed in the step of forming the first doped polysilicon layer and the second doped polysilicon layer respectively after annealing to crystallize the first amorphous silicon layer and the second amorphous silicon layer. Specifically, the doped layer is formed by the elements doped in the second amorphous silicon layer advancing toward the silicon substrate, and the term "exposed doped layer" refers to the doped layer outside the coverage area of ​​the first mask layer. Since this part of the doped layer will cause Auger recombination on the light-receiving surface, removing this part of the doped layer will help reduce Auger recombination on the light-receiving surface.

[0137] While removing the second doped polysilicon layer and the second dielectric layer by alkali, texturing of the light-receiving surface and removal of the doped layer are performed, thereby further simplifying the process flow and integrating multiple process steps into one step.

[0138] In some embodiments, before the step of forming a first dielectric layer, a first amorphous silicon layer, and a first mask layer stacked in sequence on the light-receiving surface of the silicon substrate and facing away from the silicon substrate, the method for preparing a solar cell further comprises:

[0139] The silicon substrate is textured to form a textured surface on the light-receiving surface.

[0140] The textured surface is beneficial to improving the performance of solar cells and is also beneficial to the preparation of solar cells. Optionally, the textured surface can be applied only to the light-receiving surface or to both the light-receiving surface and the backlight surface.

[0141] In some embodiments, the step of preparing a first dielectric layer, a first amorphous silicon layer, and a first mask layer stacked in sequence and facing away from the silicon substrate on the light-receiving surface of the silicon substrate includes:

[0142] A first dielectric layer, a first amorphous silicon layer and a first mask layer stacked in sequence from the inside to the outside are prepared on the light-receiving surface by using PECVD.

[0143] Compared with the related technology of forming a diffused doped layer on the light-receiving surface by boron diffusion, PECVD is used to make the first amorphous silicon layer doped in situ, and then annealing is performed to achieve advancement. The process temperature is lower, and the performance of the double-sided heterojunction solar cell is better.

[0144] In some embodiments, the step of removing the remaining first mask layer and the second mask layer includes:

[0145] Acid washing is performed to remove the remaining first mask layer and the second mask layer.

[0146] The pickling process has no substantial effect on the first doped polysilicon layer and the second doped polysilicon layer.

[0147] In some embodiments, after removing the remaining first mask layer and the second mask layer, the method for preparing a solar cell further includes the following steps:

[0148] Producing a first functional layer on the light-receiving surface;

[0149] Forming a second functional layer on the backlight side; and

[0150] A light-receiving surface electrode is fabricated on the light-receiving surface, and a backlight surface electrode is fabricated on the backlight surface; wherein the light-receiving surface electrode penetrates the first functional layer and is in ohmic contact with the first doped polysilicon layer, and the backlight surface electrode penetrates the second functional layer and is in ohmic contact with the second doped polysilicon layer.

[0151] Exemplarily, the first functional layer and the second functional layer independently include at least one of a passivation layer, an anti-reflection layer, a passivation and anti-reflection layer, and a conductive layer.

[0152] Optionally, the first dielectric layer and the second dielectric layer may include one or more dielectric materials, such as at least one of silicon oxide, magnesium fluoride, amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, and titanium oxide. Specifically, the first dielectric layer and the second dielectric layer may be formed of a silicon oxide layer containing silicon oxide. This is because the silicon oxide layer has excellent passivation properties, can minimize the recombination loss of minority carriers on the surface of the semiconductor substrate, and is a film with excellent durability for subsequent high-temperature processes.

[0153] The first and second dielectric layers act as a barrier between electrons and holes, combining with the polysilicon layer to prevent minority carriers from passing through. They can also function as pinhole channels, allowing carriers within the solar cell to move freely. The heavily doped polysilicon selectively allows majority carriers to pass through, thus reducing minority carrier recombination losses. Furthermore, the first and second dielectric layers can act as diffusion barriers to prevent dopants from the doped polysilicon layer from diffusing into the semiconductor substrate.

[0154] In some embodiments, the first dielectric layer includes a silicon oxide layer.

[0155] In some embodiments, the first dielectric layer has a thickness of approximately 0.1 nm to 5 nm, including any value within the thickness range, such as 0.1 nm, 1 nm, 1.2 nm, 1.5 nm, 1.6 nm, 1.8 nm, 2 nm, 2.2 nm, 2.4 nm, 2.8 nm, 3 nm, 4 nm, or 5 nm.

[0156] In some embodiments, the first amorphous silicon layer has a thickness of approximately 25 nm to 250 nm, including any value within the thickness range, such as 25 nm, 80 nm, 100 nm, 120 nm, 150 nm, 180 nm, 200 nm, 220 nm, 240 nm, or 250 nm.

[0157] In some embodiments, the first functional layer comprises an aluminum oxide passivation layer. Optionally, the first functional layer has a thickness of about 2 nm to about 10 nm.

[0158] In some embodiments, the first functional layer includes a silicon nitride passivation and anti-reflection layer. Optionally, the first functional layer has a thickness of about 70 nm to about 90 nm.

[0159] In some embodiments, the second dielectric layer includes a silicon oxide layer.

[0160] In some embodiments, the second dielectric layer has a thickness of approximately 0.1 nm to 5 nm, including any value within the thickness range, such as 0.1 nm, 1 nm, 1.2 nm, 1.5 nm, 1.6 nm, 1.8 nm, 2 nm, 2.2 nm, 2.4 nm, 2.8 nm, 3 nm, 4 nm, or 5 nm.

[0161] In some embodiments, the second amorphous silicon layer has a thickness of approximately 30 nm to 300 nm, including any value within the thickness range, such as 30 nm, 100 nm, 120 nm, 150 nm, 200 nm, 250 nm, or 300 nm.

[0162] In some embodiments, the second functional layer includes a silicon nitride passivation and anti-reflection layer.

[0163] In some embodiments, the second functional layer has a thickness of about 70 nm to about 90 nm.

[0164] In some embodiments, the first mask layer includes at least one of a silicon oxynitride layer and a silicon nitride layer.

[0165] Optionally, the thickness of the silicon oxynitride layer in the first mask layer is approximately 20 nm to 80 nm. Optionally, the thickness of the silicon nitride layer in the first mask layer is approximately 10 nm to 50 nm.

[0166] Optionally, the first mask layer includes a silicon oxynitride layer with a thickness of approximately 20 nm to 80 nm or a silicon nitride layer with a thickness of approximately 10 nm to 50 nm.

[0167] In some embodiments, the second mask layer includes at least one of a silicon oxide layer and a silicon oxynitride layer. Optionally, the thickness of the silicon oxide layer in the second mask layer is approximately 5 nm to 50 nm. Optionally, the thickness of the silicon oxynitride layer in the second mask layer is approximately 3 nm to 30 nm.

[0168] In some embodiments, the second mask layer includes a silicon oxide layer having a thickness of approximately 5 nm to 50 nm or a silicon oxynitride layer having a thickness of approximately 3 nm to 30 nm.

[0169] In a second aspect, an embodiment of the present application provides a solar cell, which is prepared using the solar cell preparation method as described in the first aspect.

[0170] In more detail, referring to Figure 15, the solar cell 100 manufactured using the solar cell manufacturing method of the first aspect includes a silicon substrate 101, a first dielectric layer 102, a first doped polysilicon layer 103, a first functional layer 104, a second dielectric layer 105, a second doped polysilicon layer 106, a second functional layer 107, a light-receiving surface electrode 108 and a backlight surface electrode 109.

[0171] A silicon substrate 101 has a light-receiving surface and a light-receiving surface. The light-receiving surface includes a first region 1011. A first dielectric layer 102 is disposed on the first region 1011 of the light-receiving surface. A first doped polysilicon layer 103 is disposed on the side of the first dielectric layer 102 facing away from the light-receiving surface. A first functional layer 104 covers the side of the first doped polysilicon layer 103 facing away from the first dielectric layer 102 and the area of ​​the light-receiving surface excluding the first region 1011.

[0172] The second dielectric layer 105 is disposed on the backlight side. The second doped polysilicon layer 106 is disposed on the side of the second dielectric layer 105 facing away from the silicon substrate 101, and the second doped polysilicon layer 106 forms a PN junction with the silicon substrate 101. The second functional layer 107 is disposed on the side of the second doped polysilicon layer 106 facing away from the silicon substrate 101.

[0173] The light-receiving electrode 108 is disposed corresponding to the first region 1011 and penetrates the first dielectric layer 102 to form an ohmic contact with the first doped polysilicon layer 103. The backlight-receiving electrode 109 penetrates the second dielectric layer 105 to form an ohmic contact with the second doped polysilicon layer 106.

[0174] Since the lateral resistance of the emitter seriously affects the resistance of the solar cell 100, and the lateral resistance of the emitter is inversely proportional to the square of the fine grid line spacing of the emitter, in order to reduce the lateral resistance of the emitter, the number of grid lines will be increased to reduce the grid line spacing. When the emitter is arranged on the light-receiving surface, increasing the number of grid lines will affect the absorption of light by the light-receiving surface, which is unfavorable for the conversion efficiency of the battery. The solar cell 100 of the present application, whose PN junction is arranged on the backlight side, can increase the number of grid lines on the backlight side in order to reduce the lateral resistance of the emitter. Therefore, there is no higher requirement for the number of grid lines on the light-receiving surface, which is more conducive to the distribution design of the light-receiving surface and the backlight side grid lines. By reducing the number of grid lines on the light-receiving surface, the amount of silver paste (grid line manufacturing material) can be reduced to reduce costs, which avoids that when the PN junction is arranged on the light-receiving surface of the battery, increasing the grid lines will affect the absorption of light by the battery, which is conducive to improving the efficiency of the solar cell 100 and reducing the metallization cost. In addition, the reduction in the number of light-receiving surface grid lines can also simplify the pattern of the light-receiving surface electrode 108. Since the pattern of the passivation contact structure (the first dielectric layer 102 and the first doped polysilicon layer 103) of the light-receiving surface is the same as the pattern of the light-receiving surface electrode 108, the difficulty of manufacturing the patterned first dielectric layer 102 and the first doped polysilicon layer 103 can be reduced, thereby improving the manufacturing yield.

[0175] In addition, the solar cell 100 only has the first dielectric layer 102 and the first doped polysilicon layer 103 disposed in the first region 1011 to passivate the light-receiving surface electrode 108, thereby preventing the first doped polysilicon layer 103 from covering the entire light-receiving surface and affecting the light absorption of the solar cell 100. The area outside the first region 1011 is covered with the first functional layer 104 to passivate the non-metallic area.

[0176] Furthermore, both the light-receiving surface and the backlight surface of the solar cell 100 are passivated with a polysilicon layer and a dielectric layer for metal region passivation, thereby improving the opening voltage of the solar cell 100 .

[0177] In a third aspect, an embodiment of the present application provides a photovoltaic module comprising the solar cell as described in the second aspect.

[0178] The technical solution of this application will be described below with reference to embodiments and drawings.

[0179] Example 1

[0180] The steps of the solar cell manufacturing method of this embodiment are as follows:

[0181] S1. Texturing the silicon substrate to form a textured surface on the light-receiving surface: As shown in FIG3 , at 80° C., 0.5% mass concentration NaOH is etched for 350 seconds with the aid of a texturing additive, with an etching depth of 3 μm and a reflectivity of 10%.

[0182] S2. Prepare a first dielectric layer, a first amorphous silicon layer and a first mask layer stacked in sequence away from the silicon substrate on the light-receiving surface of the silicon substrate: as shown in Figure 4, use PECVD equipment, at a temperature of 250°C, a pressure of 300Pa, and a power of 15000W, introduce 8000sccm of N2O and ionize for 500s to prepare a first dielectric layer 102 with a thickness of 2nm; at a pressure of 500Pa, introduce 1500sccm of SiH4 and 100sccm of borane, and ionize in multiple layers for 1200s to prepare a first P-type doped amorphous silicon layer 110 with a thickness of 200nm; introduce 1500sccm of silane, 6000sccm of N2O, and 4000sccm of NH3, and ionize together for 200s to prepare a first mask layer 111 of silicon oxynitride with a thickness of 30nm.

[0183] S3. An acid-resistant paste corresponding to the first area is prepared on the side of the first mask layer away from the first amorphous silicon layer: as shown in FIG5 , the acid-resistant paste 114 is coated on the first area 1011 of the light-receiving surface by screen printing, and is dried at 150° C. for 20 seconds to prepare a patterned acid-resistant paste 114 protection area with a line width of 100 μm.

[0184] S4. Use a tank cleaning machine to clean as follows:

[0185] S4-1. Removing the first mask layer, the first amorphous silicon layer and the first dielectric layer outside the coverage of the acid-resistant slurry: As shown in FIG6 , at room temperature, a mixture of HNO3 and HF is used for etching for 60 seconds to remove the first mask layer 111, the first amorphous silicon layer 110 and the first dielectric layer 102 outside the area covered by the acid-resistant slurry 114 on the light-receiving surface; the mass percentage concentration of HNO3 in the mixture is 20%, and the mass percentage concentration of HF is 1%.

[0186] S4-2. Removing the anti-acid slurry: As shown in FIG7 , at 65° C., the anti-acid slurry 114 is removed by washing with a mixture of NaOH and hydrogen peroxide for 5 minutes; the mass percentage concentration of NaOH in the mixture is 3%, and the mass percentage concentration of hydrogen peroxide is 3%.

[0187] S4-3. Use alkali to etch outside the first area under the action of additives, and form a backlight surface morphology on the backlight surface: As shown in Figure 8, at 75°C, use 2.5% mass concentration of NaOH to etch for 4 minutes under the action of alkali polishing additives to polish the silicon substrate outside the patterned area, and the reflectivity reaches 45%.

[0188] S4-4: At 60° C., organic residues on the battery surface are removed by washing with a mixture of NaOH and hydrogen peroxide for 2 minutes. The mass concentration of NaOH in the mixture is 0.5%, and the mass concentration of hydrogen peroxide is 2%.

[0189] S4-5: At room temperature, use 2% HCl to clean for 2 minutes to remove metal ions on the surface of the silicon substrate.

[0190] S5. Prepare a second dielectric layer, a second amorphous silicon layer and a second mask layer stacked in sequence away from the silicon substrate on the backlight side of the silicon substrate: as shown in Figure 9, use PECVD at a temperature of 450°C, a pressure of 300Pa, and an ionization power of 10,000W. 7,000sccm of N2O is introduced and ionized for 120s to prepare a second dielectric layer 105 with a thickness of 2nm on the backlight side; at a pressure of 500Pa, 1,500sccm of SiH4 and 100sccm of PH3 are introduced and ionized for 1,500s to prepare a 120nm thick in-situ phosphorus-doped N-type second amorphous silicon layer 112; 1,500sccm of SiH4 and 6,000sccm of N2O are introduced and ionized for 100s to prepare a 10nm second mask layer 113 made of silicon oxide.

[0191] S6. Annealing to crystallize the first amorphous silicon layer and the second amorphous silicon layer to form a first doped polysilicon layer and a second doped polysilicon layer respectively: As shown in FIG10 , high-temperature annealing is performed at 920° C. for 2500 s to crystallize the P-type doped first amorphous silicon layer 110 and the N-type doped second amorphous silicon layer 112 to form a first doped polysilicon layer 103 and a second doped polysilicon layer 106 respectively, activating the doped boron and phosphorus and advancing them to a certain extent in the silicon substrate 101, so that a PN junction is formed on the backlight side, and the sheet resistance of the backlight side is 80 Ω / sq;

[0192] S7, de-plating, texturing and cleaning:

[0193] S7-1. Single-sided etching is performed on the light-receiving surface to remove the second mask layer on the light-receiving surface and the edge of the silicon substrate. After the second mask layer is removed, etching is stopped before the first mask layer is completely etched. The second mask layer on the backlight surface and a portion of the first mask layer are retained. As shown in FIG11 , a chain cleaning machine is used to perform single-sided HF with 10% HF on the light-receiving surface downward to retain the second mask layer 113 on the backlight surface and remove the second mask layer 113 on the light-receiving surface and the edge of the silicon substrate. Part of the thickness of the first mask layer 111 is inevitably removed, but after the second mask layer is removed, etching is stopped before the first mask layer is completely etched, retaining a portion of the thickness of the first mask layer 111.

[0194] S7-2: Cleaning with a mixture of NaOH and hydrogen peroxide at 60° C. for 2 min, wherein the mass concentration of NaOH in the mixture is 0.5% and the mass concentration of hydrogen peroxide is 2%.

[0195] S7-3. Etch the area outside the area covered by the second mask layer and the first mask layer to remove the second doped polysilicon layer and the second dielectric layer on the light-receiving surface and edge of the silicon substrate: As shown in FIG12 , at 80° C., use 0.5% concentration of NaOH to perform etching for 400 seconds under the action of a texturing additive to texturing the area without mask protection to remove the second doped polysilicon layer 106 and the second dielectric layer 105 on the light-receiving surface and edge of the silicon substrate, and form a texturing surface with a reflectivity of 10% on the light-receiving surface to remove the doped layer formed when the second amorphous silicon layer on the light-receiving surface is annealed.

[0196] S7-4: At 60°C, use a mixture of NaOH and hydrogen peroxide to clean for 2 minutes to remove organic residues on the battery surface. The mass concentration of NaOH in the mixture is 0.5%, and the mass concentration of hydrogen peroxide is 2%.

[0197] S7-5, removing the remaining first mask layer and the second mask layer: As shown in FIG13 , at room temperature, use 15% mass concentration HF for 5 minutes to remove the remaining first mask layer 111 and the second mask layer 113 on the backlight side and the metal ions on the silicon substrate 101.

[0198] S8. Prepare a first functional layer on the light-receiving surface; prepare a second functional layer on the backlight surface: as shown in FIG14 , use ALD equipment to prepare a 4nm thick aluminum oxide functional layer on the light-receiving surface; use PECVD equipment to introduce SiH4 and NH3 to prepare 80nm silicon nitride as a passivation and anti-reflection film on the light-receiving surface and the backlight surface; the 4nm thick aluminum oxide functional layer on the light-receiving surface and the 80nm silicon nitride passivation and anti-reflection film constitute the first functional layer 104; the 80nm silicon nitride passivation and anti-reflection film on the backlight surface constitute the second functional layer 107.

[0199] S9. Fabricate a light-receiving electrode on the light-receiving surface and a backlight electrode on the backlight surface: Use a mixture paste primarily composed of silver to screen-print and metallize the front and backlight surfaces of the battery. Form silver grid lines 25 μm wide and 1.5 mm apart on the light-receiving surface, i.e., the light-receiving surface electrode 108; form silver grid lines 35 μm wide and 1.0 mm apart on the backlight surface, i.e., the backlight surface electrode 109; the pattern of the light-receiving surface electrode 108 corresponds to the first region 1011.

[0200] Example 2

[0201] The steps of the solar cell manufacturing method of this embodiment are as follows:

[0202] S1. Texturing the silicon substrate to form a textured surface on the light-receiving side and the backlight side: at 80°C, 0.5% mass concentration NaOH is used to etch the P-type silicon substrate for 350s with the aid of a texturing additive, with an etching depth of 3μm and a reflectivity of 10%.

[0203] S2. Prepare a first dielectric layer, a first amorphous silicon layer and a first mask layer stacked in sequence away from the silicon substrate on the light-receiving surface of the silicon substrate: use PECVD equipment, at a temperature of 400°C and a power of 15,000 W, introduce 8,000 sccm of N2O and ionize for 100 seconds to prepare a first dielectric layer with a thickness of 2 nm; introduce 1,500 sccm of SiH4 and 100 sccm of trimethylboron, ionize in multiple layers for 1,800 seconds to prepare a first P-type doped amorphous silicon layer with a thickness of 180 nm; introduce 1,500 sccm of silane, 6,000 sccm of N2O and 2,000 sccm of NH3, and ionize together for 200 seconds to prepare a first mask layer of silicon oxynitride with a thickness of 40 nm.

[0204] S3. Prepare an acid-resistant paste corresponding to the first area on the side of the first mask layer away from the first amorphous silicon layer: use screen printing to apply the acid-resistant paste on the area to be metallized on the light-receiving surface, that is, the first area, and dry it at 150°C for 20s to prepare a graphic acid-resistant paste protection area with a line width of 70μm.

[0205] S4. Use a tank cleaning machine to clean as follows:

[0206] S4-1. Remove the first mask layer, the first amorphous silicon layer and the first dielectric layer outside the coverage of the acid-resistant slurry: At room temperature, use a mixture of HNO3 and HF to etch for 50s to remove the first mask layer, the first amorphous silicon layer and the first dielectric layer outside the acid-resistant slurry area on the light-receiving surface; the mass percentage concentration of HNO3 in the mixture is 15%, and the mass percentage concentration of HF is 2%.

[0207] S4-2. Removal of anti-acid slurry: Clean with a mixture of 3% NaOH and 3% hydrogen peroxide at 65°C for 5 minutes to remove the anti-acid slurry.

[0208] S4-3. Use alkali to etch outside the first area under the action of additives, and form a backlight surface morphology on the backlight surface: at 75°C, use 0.5% mass concentration of NaOH to etch for 400s under the action of texturing additives to texturize the silicon substrate outside the patterned area, and the reflectivity reaches 11%.

[0209] S4-4: At 60° C., organic residues on the battery surface are removed by washing with a mixture of NaOH and hydrogen peroxide for 2 minutes. The mass concentration of NaOH in the mixture is 0.5%, and the mass concentration of hydrogen peroxide is 2%.

[0210] S4-5: At room temperature, use 2% mass concentration HCl to clean for 2 minutes to remove metal ions on the surface of the silicon substrate.

[0211] S5. Prepare a second dielectric layer, a second amorphous silicon layer and a second mask layer stacked in sequence away from the silicon substrate on the backlight side of the silicon substrate: use PECVD at a temperature of 450°C and an ionization power of 10,000 W to introduce 7,000 sccm of N2O and ionize for 120 seconds to prepare a second dielectric layer with a thickness of 2 nm on the backlight side; introduce 1,800 sccm of SiH4 and 80 sccm of PH3 and ionize for 1,500 seconds to prepare a second in-situ phosphorus-doped amorphous silicon layer with a thickness of 130 nm; introduce 1,500 sccm of SiH4 and 8,000 sccm of N2O and ionize for 150 seconds to prepare a second mask layer of silicon oxide material with a thickness of 15 nm.

[0212] S6. Annealing to crystallize the first amorphous silicon layer and the second amorphous silicon layer to form a first doped polysilicon layer and a second doped polysilicon layer respectively: high-temperature annealing is performed at 920°C for 2500s to activate the doped boron and phosphorus, and to advance them to a certain extent in the silicon substrate. A PN junction will be formed on the backlight side, and the sheet resistance of the backlight side is 100Ω / sq.

[0213] S7, de-plating, texturing and cleaning:

[0214] S7-1. Perform single-sided etching on the light-receiving surface to remove the second mask layer on the light-receiving surface and the edge of the silicon substrate. After the second mask layer is removed, the etching is stopped before the first mask layer is completely etched. The second mask layer on the backlight surface and a portion of the thickness of the first mask layer are retained. A chain cleaning machine is used to perform single-sided HF with 10% mass concentration of HF on the light-receiving surface downward to remove the second mask layer on the light-receiving surface and the edge and a portion of the thickness of the first mask layer, and a portion of the thickness of the first mask layer and the second mask layer on the backlight surface are retained.

[0215] S7-2: Cleaning with a mixture of NaOH and hydrogen peroxide at 60° C. for 2 min, wherein the mass concentration of NaOH in the mixture is 0.5% and the mass concentration of hydrogen peroxide is 2%.

[0216] S7-3. Perform alkaline etching on the areas outside the areas covered by the second mask layer and the first mask layer to remove the second doped polysilicon layer and the second dielectric layer on the light-receiving surface and the edge of the silicon substrate, perform texturing on the light-receiving surface to form a velvet surface on the light-receiving surface, and remove the doped layer on the light-receiving surface: at 80°C, use 0.5% mass concentration of NaOH to perform etching for 200s under the action of a texturing additive, perform texturing on the areas not protected by the mask to remove the second doped polysilicon layer and the second dielectric layer on the light-receiving surface and the edge, and form a velvet surface with a reflectivity of 10% on the light-receiving surface.

[0217] S7-4: At 60°C, use a mixture of NaOH and hydrogen peroxide to clean the battery surface for 2 minutes to remove organic residues. The mass concentration of NaOH in the mixture is 0.5%, and the mass concentration of hydrogen peroxide is 2%.

[0218] S7-5: At room temperature, use 15% mass concentration HF for cleaning for 5 minutes to remove a portion of the first mask layer on the silicon substrate, the second mask layer on the backlight side, and the metal ions.

[0219] S8. Prepare a first functional layer on the light-receiving surface; prepare a second functional layer on the backlight surface: use ALD equipment to prepare a 4nm thick aluminum oxide functional layer on the bottom layer of the light-receiving surface; use PECVD equipment to introduce SiH4 and NH3 to prepare 80nm silicon nitride as a passivation and anti-reflection film on the outer layer of the light-receiving surface and the backlight surface; the 4nm thick aluminum oxide functional layer on the light-receiving surface and the 80nm silicon nitride passivation and anti-reflection film constitute the first functional layer; the 80nm silicon nitride passivation and anti-reflection film on the backlight surface constitute the second functional layer.

[0220] S9. Fabricate a light-receiving electrode on the light-receiving surface and a backlight electrode on the backlight surface: Use a mixture paste mainly composed of silver to screen print and metallize the front and backlight surfaces of the battery. Form silver grid lines with a width of 25μm and a spacing of 1.5mm on the light-receiving surface, namely the light-receiving electrode; form silver grid lines with a width of 35μm and a spacing of 1.0mm on the backlight surface, namely the backlight electrode; the light-receiving surface electrode corresponds to the first area.

[0221] Example 3

[0222] The steps of the solar cell manufacturing method of this embodiment are as follows:

[0223] S1. Texturing the silicon substrate to form a textured surface on the light-receiving side and the backlight side: etching the N-type silicon substrate for 350 seconds at 80°C with 0.5% mass concentration of NaOH with the aid of a texturing additive, with an etching depth of 3 μm and a reflectivity of 10%.

[0224] S2. Prepare a first dielectric layer, a first amorphous silicon layer and a first mask layer stacked in sequence away from the silicon substrate on the light-receiving surface of the silicon substrate: use PECVD, under the ionization conditions of a temperature of 450°C and a power of 10,000 W, introduce 7,000 sccm of N2O and ionize for 120 seconds to prepare a first dielectric layer with a thickness of 2 nm on the backlight side; introduce 1,800 sccm of SiH4 and 80 sccm of PH3 and ionize for 1,500 seconds to prepare a first N-type doped amorphous silicon layer with a thickness of 130 nm; introduce 1,500 sccm of silane, 6,000 sccm of N2O and 2,000 sccm of NH3 and ionize together for 200 seconds to prepare a first mask layer of silicon oxynitride with a thickness of 40 nm.

[0225] S3. Prepare an acid-resistant paste corresponding to the first area on the side of the first mask layer away from the first amorphous silicon layer: use screen printing to apply the acid-resistant paste on the area to be metallized on the light-receiving surface, that is, the first area, and dry it at 150°C for 20s to prepare a graphic acid-resistant paste protection area with a line width of 70μm.

[0226] S4. Use a tank cleaning machine to clean as follows:

[0227] S4-1. Remove the first mask layer, the first amorphous silicon layer and the first dielectric layer outside the coverage of the acid-resistant slurry: At room temperature, use a mixture of HNO3 and HF to etch for 50s to remove the first mask layer, the first amorphous silicon layer and the first dielectric layer outside the acid-resistant slurry area on the light-receiving surface; the mass percentage concentration of HNO3 in the mixture is 15%, and the mass percentage concentration of HF is 2%.

[0228] S4-2. Removal of anti-acid slurry: at 65° C., use a mixture of NaOH and hydrogen peroxide to remove the anti-acid slurry for 5 minutes, wherein the mass concentration of NaOH in the mixture is 3%, and the mass concentration of hydrogen peroxide is 3%.

[0229] S4-3. Use alkali to etch outside the first area under the action of additives, and form a backlight surface morphology on the backlight surface: As shown in Figure 8, at 75°C, use 2.5% mass concentration of NaOH to etch for 4 minutes under the action of alkali polishing additives to polish the silicon substrate outside the patterned area, and the reflectivity reaches 45%.

[0230] S4-4: At 60° C., organic residues on the battery surface are removed by washing with a mixture of NaOH and hydrogen peroxide for 2 minutes. The mass concentration of NaOH in the mixture is 0.5%, and the mass concentration of hydrogen peroxide is 2%.

[0231] S4-5: At room temperature, use 2% HCl to clean for 2 minutes to remove metal ions on the surface of the silicon substrate.

[0232] S5. Prepare a second dielectric layer, a second amorphous silicon layer and a second mask layer stacked in sequence away from the silicon substrate on the backlight side of the silicon substrate: use PECVD equipment, at a temperature of 400°C and a power of 15000 W, introduce 8000 sccm of N2O ionization for 100 seconds to prepare a second dielectric layer with a thickness of 2nm; introduce 1500 sccm of SiH4 and 100 sccm of trimethylboron, ionize in multiple layers for 1800 seconds to prepare a P-type doped second amorphous silicon layer with a thickness of 180nm; introduce 1500 sccm of SiH4 and 8000 sccm of N2O ionization for 150 seconds to prepare a second mask layer of silicon oxide material of 15nm.

[0233] S6. Annealing to crystallize the first amorphous silicon layer and the second amorphous silicon layer to form a first doped polysilicon layer and a second doped polysilicon layer respectively, forming a PN junction on the backlight side: high-temperature annealing is performed at 920°C for 2500s to activate the doped boron and phosphorus, and a certain degree of advancement is performed in the silicon substrate. A PN junction will be formed on the backlight side, and the sheet resistance of the backlight side is 100Ω / sq.

[0234] S7, de-plating, texturing and cleaning:

[0235] S7-1. Perform single-sided etching on the light-receiving surface to remove the second mask layer on the light-receiving surface and the edge of the silicon substrate. After the second mask layer is removed, the etching is stopped before the first mask layer is completely etched. The second mask layer on the backlight surface and a portion of the thickness of the first mask layer are retained. A chain cleaning machine is used to perform single-sided HF with 10% mass concentration of HF on the light-receiving surface downward to remove the second mask layer on the light-receiving surface and the edge and a portion of the thickness of the first mask layer, and a portion of the thickness of the first mask layer and the second mask layer on the backlight surface are retained.

[0236] S7-2: Cleaning with a mixture of NaOH and hydrogen peroxide at 60° C. for 2 min, wherein the mass concentration of NaOH in the mixture is 0.5% and the mass concentration of hydrogen peroxide is 2%.

[0237] S7-3. Perform alkaline etching on the areas outside the areas covered by the second mask layer and the first mask layer to remove the second doped polysilicon layer and the second dielectric layer on the light-receiving surface and the edge of the silicon substrate, perform texturing on the light-receiving surface to form a texturing surface on the light-receiving surface, and remove the doped layer on the light-receiving surface: at 80°C, use 5% mass concentration of NaOH to perform etching for 200s under the action of an alkaline polishing additive to remove the second doped polysilicon layer; at 80°C, use 0.5% mass concentration of NaOH to perform etching for 200s under the action of a texturing additive to texturing the areas not protected by the mask to remove the second doped polysilicon layer and the second dielectric layer on the light-receiving surface and the edge, and form a texturing surface with a reflectivity of 10% on the light-receiving surface.

[0238] S7-4: At 60°C, use a mixture of NaOH and hydrogen peroxide to clean the battery surface for 2 minutes to remove organic residues. The mass concentration of NaOH in the mixture is 0.5%, and the mass concentration of hydrogen peroxide is 2%.

[0239] S7-5: At room temperature, use 15% mass concentration HF for cleaning for 5 minutes to remove a portion of the first mask layer on the silicon substrate, the second mask layer on the backlight side, and the metal ions.

[0240] S8. Prepare a first functional layer on the light-receiving surface; prepare a second functional layer on the backlight surface: use ALD equipment to prepare a 4nm thick aluminum oxide functional layer on the bottom layer of the light-receiving surface; use PECVD equipment to introduce SiH4 and NH3 to prepare 80nm silicon nitride as a passivation and anti-reflection film on the outer layer of the light-receiving surface and the backlight surface; the 4nm thick aluminum oxide functional layer on the light-receiving surface and the 80nm silicon nitride passivation and anti-reflection film constitute the first functional layer; the 80nm silicon nitride passivation and anti-reflection film on the backlight surface constitute the second functional layer.

[0241] S9. Fabricate a light-receiving electrode on the light-receiving surface and a backlight electrode on the backlight surface: Use a mixture paste mainly composed of silver to screen print and metallize the front and backlight surfaces of the battery. Form silver grid lines with a width of 25μm and a spacing of 1.5mm on the light-receiving surface, namely the light-receiving electrode; form silver grid lines with a width of 35μm and a spacing of 1.0mm on the backlight surface, namely the backlight electrode; the light-receiving surface electrode corresponds to the first area.

[0242] Example 4

[0243] The only difference between Example 4 and Example 1 is that: Step S2 prepares a P-type doped first amorphous silicon layer with a thickness of 150 nm.

[0244] Comparative Example 1

[0245] The preparation method of the solar cell provided in this comparative example comprises the following steps:

[0246] 1. Alkali texturing: Using a 182mm silicon substrate, etch the silicon substrate with 0.5% mass concentration of NaOH at 80°C for 350s with the aid of a texturing additive, to a depth of 3μm and a reflectivity of 10%;

[0247] 2. Boron diffusion: Using a high-temperature tubular diffusion furnace, at 820°C and 20 kPa, introduce 100 sccm of BCl3 and 300 sccm of O2 for 10 minutes. The temperature was then raised to 950°C and advanced for 20 minutes in a 10,000 sccm N2 atmosphere at 40 kPa. The temperature was then raised to 1030°C and oxidized for 90 minutes in a 10,000 sccm O2 atmosphere at 80 kPa. The resulting PN junction square resistance on the light-receiving side was 120 Ω / sq.

[0248] 3. Remove BSG: At room temperature, use a chain cleaning machine, use 15% mass concentration of HF, etch the backlight side downward for 2 minutes to remove the backlight side BSG;

[0249] 4. Alkali polishing: At a temperature of 75°C, use 2.5% mass concentration of NaOH in the presence of an alkaline polishing additive to etch for 4 minutes to polish the silicon substrate outside the patterned area to a reflectivity of 45%;

[0250] 5. Preparation of backlight n-poly: Using PECVD at 450°C and 10,000W ionization conditions, 7,000 sccm of N2O was introduced for 120 seconds to prepare a 2nm dielectric layer on the backlight side. 1800 sccm of SiH4 and 80 sccm of PH3 were introduced for 1,500 seconds to prepare a 130nm thick in-situ phosphorus-doped n-poly layer. 1500 sccm of SiH4 and 8,000 sccm of N2O were introduced for 100 seconds to prepare a 10nm silicon oxide mask layer.

[0251] 6. High temperature annealing: 2500s at 920℃ to activate phosphorus doping in n-poly and promote it in the silicon substrate;

[0252] 7. Remove PSG: At room temperature, use a chain cleaning machine and pass HF with a 10% mass concentration, with the light-receiving surface facing downward;

[0253] 8. RCA cleaning: Using a tank-type cleaning machine, etch with 3% NaOH in the presence of an alkaline polishing additive at 80°C for 200 seconds, then clean with a mixture of 0.5% NaOH and 2% hydrogen peroxide at 60°C for 2 minutes; then clean with 15% HF at room temperature for 5 minutes, and finally dry.

[0254] 9. Aluminum oxide passivation film coating: Use ALD equipment to prepare a 4nm thick aluminum oxide passivation film on the bottom layer of the light-receiving surface;

[0255] 10. Preparation of passivation and anti-reflection film on the light-receiving surface: Using PECVD equipment, introduce SiH4 and NH3 to prepare 80nm silicon nitride as passivation and anti-reflection film on the outer layer of the light-receiving surface;

[0256] 11. Preparation of backlight passivation and anti-reflection film: Using PECVD equipment, introduce SiH4 and NH3 to prepare 80nm silicon nitride as passivation and anti-reflection film on the backlight surface;

[0257] 12. Screen printing and metallization: A mixture paste mainly composed of silver is used to screen print and metallize the front and back surfaces of the battery. The light-receiving side is formed with silver grid lines with a width of 25μm and a spacing of 1.5mm; the backlight side is formed with silver grid lines with a width of 35μm and a spacing of 1.0mm.

[0258] Comparative Example 2

[0259] The preparation method of the selective emitter passivation contact cell provided in this comparative example comprises the following steps:

[0260] Step 1: Texturing and cleaning: Use a 182mm silicon substrate, etch the silicon substrate for 350s at 80°C using 0.5% NaOH with the aid of a texturing additive, to a depth of 3μm and a reflectivity of 10%.

[0261] Step 2: Boron diffusion: Using a high-temperature tubular diffusion furnace, at 820°C and 20 kPa, introduce 100 sccm of BCl₃ and 300 sccm of O₂ for 10 minutes. The deposition was then heated to 920°C and advanced for 20 minutes in a 10,000 sccm N₂ atmosphere at 40 kPa. The resulting PN junction resistance on the light-receiving side was 120 Ω / sq.

[0262] Step 3, laser SE: Use high-frequency red laser to advance the first area, so that the square resistance of the advancing area drops to 60Ω / sq;

[0263] Step 4: High temperature oxidation: Use a high temperature tubular diffusion furnace, raise the temperature to 1050°C under 100KPa pressure, and introduce 10000sccm of O 2， Oxidation in an O2 atmosphere for 90 minutes yielded a PN junction square resistance of 220Ω / sq in the non-laser region and a square resistance of 65Ω / sq in the laser-driven region, with an 80nm thick BSG layer grown.

[0264] Step 5: Remove BSG: At room temperature, use a chain cleaning machine and etch with 15% mass concentration of HF for 2 minutes with the backlight side facing down to remove the BSG on the backlight side.

[0265] Step 6: Alkali polishing: The temperature is 75°C, and 2.5% NaOH is used to etch for 4 minutes under the action of an alkaline polishing additive to polish the silicon substrate outside the patterned area to a reflectivity of 45%;

[0266] Step 7: Prepare the backlight side n-poly: Use PECVD at 450°C, 10,000W ionization conditions, introduce 7,000 sccm of N2O, ionize for 120 seconds, and prepare a 2nm dielectric layer on the backlight side; introduce 1,800 sccm of SiH4 and 80 sccm of PH3 and ionize for 1,500 seconds to prepare a 130nm thick in-situ phosphorus-doped n-poly layer; introduce 1,500 sccm of SiH4 and 8,000 sccm of N2O and ionize for 100 seconds to prepare a 10nm silicon oxide mask layer;

[0267] Step 8: High temperature annealing: Perform high temperature annealing at 920°C for 2500s to activate the phosphorus doped in the n-poly and to promote it within the silicon substrate.

[0268] Step 9: Remove PSG: At room temperature, use a chain cleaning machine and pass HF with 10% mass concentration, with the light-receiving side facing downward;

[0269] Step 10, RCA cleaning: using a tank cleaning machine, etch with 3% mass concentration NaOH in the presence of an alkaline polishing additive at 80°C for 200s, then clean with a mixture of NaOH and hydrogen peroxide at 60°C for 2 minutes, wherein the mass concentration of NaOH in the mixture is 0.5% and the mass concentration of hydrogen peroxide is 2%; then clean with 15% mass concentration HF at room temperature for 5 minutes, and finally dry;

[0270] Step 11: Aluminum oxide passivation film coating: A 4 nm thick aluminum oxide passivation film is prepared on the bottom layer of the light-receiving surface using an ALD device;

[0271] Step 12: Prepare a passivation and anti-reflection film on the light-receiving surface: Use PECVD equipment to introduce SiH4 and NH3 to prepare an 80nm silicon nitride passivation and anti-reflection film on the outer layer of the light-receiving surface;

[0272] Step 13: Prepare a backlight passivation and anti-reflection film: Use PECVD equipment to introduce SiH4 and NH3 to prepare 80nm silicon nitride as a passivation and anti-reflection film on the backlight surface;

[0273] Step 14: Screen printing and metallization: Use a mixture paste composed mainly of silver to screen print and metallize the front and back surfaces of the battery. Silver grid lines with a width of 25 μm and a spacing of 1.5 mm are formed on the light-receiving side; silver grid lines with a width of 35 μm and a spacing of 1.0 mm are formed on the back surface.

[0274] The electrical properties of the solar cells produced in Examples 1-4 and Comparative Examples 1 and 2 were tested. The test results are shown in Table 1.

[0275] Table 1. Electrical performance test results of solar cells

[0276] As can be seen from Table 1, Examples 1-4 have obvious advantages in conversion efficiency and open-circuit voltage. The reason is that the solar cells of Examples 1-4 only set the first dielectric layer and the first doped polysilicon layer in the first region as the passivation contact structure of the light-receiving surface electrode to avoid the first doped polysilicon layer covering the entire light-receiving surface of the solar cell and affecting the solar cell's absorption of light. In addition, the PN junction of the solar cells of Examples 1-4 is located on its backlight side. In order to reduce the lateral resistance of the emitter, the number of grid lines on the backlight side can be increased. Therefore, there is no high requirement for the number of grid lines on the light-receiving side, which is more conducive to the distribution design of the grid lines on the light-receiving surface and the backlight side. By reducing the number of grid lines on the light-receiving surface, the amount of silver paste (grid line manufacturing material) can be reduced, thereby reducing costs, and avoiding the effect of adding grid lines when the PN junction is set on the light-receiving surface of the battery on the absorption of light. Through the above improvements, the solar cell absorbs light better and has higher conversion efficiency.

[0277] In Example 4, the first amorphous silicon layer is made thinner to further reduce the thickness of the first doped polysilicon. The smaller the thickness of the first doped polysilicon, the less parasitic absorption of light caused by the first doped polysilicon, and the less leakage current caused by the first doped polysilicon, thereby improving the conversion efficiency of Example 4 and reducing the leakage current.

[0278] Comparative Example 1 is a single-sided passivation contact, that is, the backlight poly is set only on the backlight side for passivation contact; the solar cells of Examples 1-4 are double-sided passivation contacts, the light-receiving side is passivated in the metal area through the first doped polysilicon layer, and the backlight side is passivated in the metal area and non-metal area through the second doped polysilicon layer made by the PECVD method. The solar cells of Examples 1-4 use polysilicon layers on both sides for metal area passivation, which improves the minority carrier lifetime and open circuit voltage.

[0279] Comparative Example 2 is a selective emitter passivation contact cell. Although the first region used for subsequent metallization is heavily doped by laser propulsion, the efficiency improvement of the cell is still lower than that of Examples 1-4. Compared with Comparative Example 2, Examples 1-4 use a double-sided passivation contact structure, which makes the conversion efficiency and open-circuit voltage of Examples 1-4 better than those of Comparative Example 2. Example 1-4 removes the winding coating through steps S4-1 and 7-3, and the leakage current of the resulting solar cell is also significantly reduced compared to Comparative Example 2, indicating that the preparation method of the present application further solves the leakage problem.

[0280] The number of equipment used in the different preparation methods of Examples 1-4 and Comparative Examples 1 and 2 is shown in Table 3.

[0281] Table 3: Number of equipment used in different preparation methods

[0282] It can be seen from Table 3 that compared with the passivation contact cell process flow of Comparative Example 1, the equipment required for the embodiment of the present application has not increased, and there are also 12 equipment processes. Compared with the selective emitter passivation contact cell process flow of Comparative Example 2, the embodiment of the present application has two fewer equipment processes. At the same time, it can replace the boron expansion process, which is the current technical bottleneck process, and reduce the difficulty of industrial production. From the perspective of solar cell conversion efficiency gain, the solar cell prepared in the embodiment of the present application has an open circuit voltage gain of more than 15mV and a conversion efficiency gain of more than 0.5%, with higher theoretical efficiency and greater room for efficiency improvement. Therefore, the preparation method of the embodiment of the present application has multiple advantages of improving efficiency and reducing costs.

[0283] The above is a detailed introduction to a method for preparing a solar cell, a solar cell and a photovoltaic module disclosed in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method for preparing a solar cell, a solar cell and a photovoltaic module and their core ideas of the present application. At the same time, for general technicians in this field, according to the ideas of the present application, there will be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present application.

Claims

1. A method for preparing a solar cell, comprising the following steps: A first dielectric layer, a first amorphous silicon layer, and a first mask layer are sequentially stacked on a light-receiving surface of a silicon substrate and are formed away from the silicon substrate; wherein the silicon substrate and the first amorphous silicon layer both have a first conductivity type, and the light-receiving surface has a first region for forming a light-receiving surface electrode; removing the first mask layer, the first amorphous silicon layer, and the first dielectric layer outside the first region; A second dielectric layer, a second amorphous silicon layer, and a second mask layer are sequentially stacked on the backlight side of the silicon substrate and away from the silicon substrate; wherein the second amorphous silicon layer has a second conductivity type opposite to the first conductivity type; Annealing to crystallize the first amorphous silicon layer and the second amorphous silicon layer to form a first doped polysilicon layer and a second doped polysilicon layer respectively; Performing single-sided etching on the light-receiving surface to remove the wrap-around coating of the second mask layer on the light-receiving surface and the edge of the silicon substrate, and stopping etching before the first mask layer is completely etched after the wrap-around coating of the second mask layer is removed; wherein the second mask layer on the backlight surface and a portion of the thickness of the first mask layer are retained; Etching the area outside the area covered by the second mask layer and the first mask layer to remove the second doped polysilicon layer and the second dielectric layer on the light-receiving surface and the edge of the silicon substrate; and The remaining first mask layer and the second mask layer are removed.

2. The method for preparing a solar cell according to claim 1, wherein: The step of single-sidedly etching the light-receiving surface to remove the wrap-around coating of the second mask layer on the light-receiving surface and the edge of the silicon substrate, and stopping etching before the first mask layer is completely etched after the wrap-around coating of the second mask layer is removed, comprises: The light-receiving surface is pickled on one side using hydrofluoric acid with a mass percentage concentration of x%, and the hydrofluoric acid cleaning time t1 is controlled to satisfy: t2≤t1<t3, t2 is the time required for the second mask layer to be completely removed in the hydrofluoric acid with a mass percentage concentration of x%, and t3 is the time required for the first mask layer to be completely removed in the hydrofluoric acid with a mass percentage concentration of x%.

3. The method for preparing a solar cell according to claim 2, wherein: The thickness of the first mask layer is greater than the thickness of the second mask layer surrounding the plating layer.

4. The method for preparing a solar cell according to claim 2 or 3, wherein: In a hydrofluoric acid solution of the same concentration, the etching rate of the second mask layer around the plating layer is greater than the etching rate of the first mask layer.

5. The method for preparing a solar cell according to any one of claims 1 to 4, wherein: The step of removing the first mask layer, the first amorphous silicon layer, and the first dielectric layer outside the first region includes: forming an acid-resistant slurry corresponding to the first region on a side of the first mask layer facing away from the first amorphous silicon layer; removing the first mask layer, the first amorphous silicon layer, and the first dielectric layer outside the coverage of the acid-resistant slurry; and The acid-resistant slurry is removed.

6. The method for preparing a solar cell according to claim 5, wherein: The step of forming an acid-resistant slurry corresponding to the first region on a side of the first mask layer facing away from the first amorphous silicon layer comprises: The acid-resistant slurry is coated on the first mask layer by printing or spraying.

7. The method for preparing a solar cell according to claim 6, wherein: The coating width of the acid-resistant slurry is about 60 μm to 200 μm.

8. The method for preparing a solar cell according to any one of claims 4 to 7, wherein: The step of removing the first mask layer, the first amorphous silicon layer, and the first dielectric layer outside the coverage of the acid-resistant slurry includes: Etching is performed using a mixed solution of hydrofluoric acid and nitric acid.

9. The method for preparing a solar cell according to claim 8, wherein: In the mixed solution of hydrofluoric acid and nitric acid, the mass percentage concentration of hydrofluoric acid is about 0.1% to 10%, and the mass percentage concentration of nitric acid is about 10% to 50%.

10. The method for preparing a solar cell according to any one of claims 4 to 9, wherein: The step of removing the acid-resistant slurry comprises: The anti-acid slurry is removed by washing with a mixed solution of alkali and hydrogen peroxide.

11. The method for preparing a solar cell according to claim 10, wherein: The cleaning time of the mixed solution of alkali and hydrogen peroxide is about 1 minute to 20 minutes.

12. The method for preparing a solar cell according to any one of claims 1 to 11, wherein: After the step of removing the first mask layer, the first amorphous silicon layer, and the first dielectric layer outside the first region, and before the step of preparing a second dielectric layer, a second amorphous silicon layer, and a second mask layer stacked in sequence on the backlight side of the silicon substrate away from the silicon substrate, the method for preparing a solar cell further comprises the following steps: Alkali is used to etch the area outside the first region under the action of additives, and a backlight surface morphology is formed on the backlight surface, wherein the backlight surface morphology includes a polished surface or a velvet surface.

13. The method for preparing a solar cell according to any one of claims 1 to 12, wherein: The step of etching the area outside the area covered by the second mask layer and the first mask layer to remove the second doped polysilicon layer and the second dielectric layer on the light-receiving surface and the edge of the silicon substrate includes: Alkaline etching is performed on the areas outside the areas covered by the second mask layer and the first mask layer to remove the second doped polysilicon layer and the coating layer of the second dielectric layer on the light-receiving surface and the edge of the silicon substrate, the light-receiving surface is textured to form a textured surface on the light-receiving surface, and the exposed doped layer on the light-receiving surface is removed; wherein the doped layer is formed in the step of forming the first doped polysilicon layer and the second doped polysilicon layer respectively after annealing to crystallize the first amorphous silicon layer and the second amorphous silicon layer.

14. The method for preparing a solar cell according to any one of claims 1 to 13, wherein: Before the step of preparing a first dielectric layer, a first amorphous silicon layer, and a first mask layer stacked in sequence and facing away from the silicon substrate on the light-receiving surface of the silicon substrate, the method for preparing a solar cell further includes: The silicon substrate is textured to form a textured surface on the light-receiving surface.

15. The method for preparing a solar cell according to any one of claims 1 to 14, wherein: The step of preparing a first dielectric layer, a first amorphous silicon layer, and a first mask layer stacked in sequence and facing away from the silicon substrate on the light-receiving surface of the silicon substrate comprises: The first dielectric layer, the first amorphous silicon layer and the first mask layer are sequentially stacked from the inside to the outside on the light-receiving surface by using PECVD.

16. The method for preparing a solar cell according to any one of claims 1 to 15, wherein: The step of removing the remaining first mask layer and the second mask layer includes: Acid washing is performed to remove the remaining first mask layer and the second mask layer.

17. The method for preparing a solar cell according to any one of claims 1 to 16, wherein: After the step of removing the remaining first mask layer and the second mask layer, the method for preparing a solar cell further includes the following steps: forming a first functional layer on the light-receiving surface; Producing a second functional layer on the backlight surface; and A light-receiving surface electrode is fabricated on the light-receiving surface, and a backlight surface electrode is fabricated on the backlight surface; wherein the light-receiving surface electrode penetrates the first functional layer and is in ohmic contact with the first doped polysilicon layer, and the backlight surface electrode penetrates the second functional layer and is in ohmic contact with the second doped polysilicon layer.

18. The method for preparing a solar cell according to any one of claims 1 to 17, wherein: The first dielectric layer includes a silicon oxide layer.

19. The method for preparing a solar cell according to any one of claims 1 to 18, wherein: The thickness of the first dielectric layer is approximately 0.1 nm to 5 nm.

20. The method for preparing a solar cell according to any one of claims 1 to 19, wherein: The thickness of the first amorphous silicon layer is approximately 25 nm to 250 nm.

21. The method for preparing a solar cell according to any one of claims 17 to 20, wherein: The first functional layer includes an aluminum oxide passivation layer.

22. The method for preparing a solar cell according to any one of claims 17 to 21, wherein: The thickness of the first functional layer is about 2 nm to 10 nm.

23. The method for preparing a solar cell according to any one of claims 17 to 22, wherein: The first functional layer includes a silicon nitride passivation and anti-reflection layer.

24. The method for preparing a solar cell according to any one of claims 17 to 23, wherein: The thickness of the first functional layer is about 70 nm to 90 nm.

25. The method for preparing a solar cell according to any one of claims 1 to 24, wherein: The second dielectric layer includes a silicon oxide layer.

26. The method for preparing a solar cell according to any one of claims 1 to 25, wherein: The thickness of the second dielectric layer is approximately 0.1 nm to 5 nm.

27. The method for preparing a solar cell according to any one of claims 1 to 26, wherein: The thickness of the second amorphous silicon layer is approximately 30 nm to 300 nm.

28. The method for preparing a solar cell according to any one of claims 17 to 27, wherein: The second functional layer includes a silicon nitride passivation and anti-reflection layer.

29. The method for preparing a solar cell according to any one of claims 17 to 28, wherein: The thickness of the second functional layer is about 70 nm to 90 nm.

30. The method for preparing a solar cell according to any one of claims 1 to 29, wherein: The first mask layer includes at least one of a silicon oxynitride layer and a silicon nitride layer.

31. The method for preparing a solar cell according to any one of claims 1 to 30, wherein: The first mask layer includes at least one of a silicon oxynitride layer and a silicon nitride layer.

32. The method for preparing a solar cell according to claim 31, wherein: The thickness of the silicon oxynitride layer in the first mask layer is about 20 nm to 80 nm.

33. The method for preparing a solar cell according to claim 31, wherein: The thickness of the silicon nitride layer in the first mask layer is about 10 nm to 50 nm.

34. The method for preparing a solar cell according to any one of claims 1 to 33, wherein: The second mask layer includes at least one of a silicon oxide layer and a silicon oxynitride layer.

35. The method for preparing a solar cell according to claim 34, wherein: The thickness of the silicon oxide layer in the second mask layer is about 5 nm to 50 nm.

36. The method for preparing a solar cell according to claim 34, wherein: The thickness of the silicon oxynitride layer in the second mask layer is about 3 nm to 30 nm.

37. A solar cell prepared by the method for preparing a solar cell according to any one of claims 1 to 36.

38. A photovoltaic module comprising the solar cell according to claim 37.

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