Preparation method for solar cell, solar cell, and photovoltaic module

Abstract

A preparation method for a solar cell, a solar cell, and a photovoltaic module. The preparation method for the solar cell comprises: preparing, on a backlight surface of a silicon wafer (101) of a first conductivity type, a first dielectric layer (102), a first amorphous silicon layer (105) doped with a doping element of a second conductivity type opposite to the first conductive type, and a first mask layer (104) which are sequentially stacked in a direction away from the silicon wafer; preparing, on a light receiving surface of the silicon wafer, a second dielectric layer (106), a second amorphous silicon layer (109) doped with a doping element of the first conductivity type, and a second mask layer (108) which are sequentially stacked in the direction away from the silicon wafer; crystallizing the first amorphous silicon layer into a first doped polycrystalline silicon layer (103), and activating the doping element of the second conductive type; crystallizing the second amorphous silicon layer into a second doped polycrystalline silicon layer (107), and activating the doping element of the first conductive type; preparing a patterned second mask layer; removing the second doped polycrystalline silicon layer outside a coverage area of the patterned second mask layer, to form a patterned second doped polycrystalline silicon layer; removing the second dielectric layer outside a coverage area of the patterned second doped polycrystalline silicon layer, to form a patterned second dielectric layer; and removing the first mask layer and the patterned second mask layer.

Description

A method for preparing a solar cell, a solar cell and a photovoltaic module

[0001] Related applications

[0002] This application claims priority to Chinese patent application No. 2024101372950, ​​filed on February 1, 2024, entitled “A method for preparing a solar cell, a solar cell and a photovoltaic module,” the entire text of which is hereby incorporated by reference. Technical Field

[0003] The present application relates to the field of solar cell technology, and in particular to a method for preparing a solar cell, a solar cell, and a photovoltaic module. Background Art

[0004] The passivation contact structure consists of an ultra-thin layer of silicon oxide and a layer of heavily doped polysilicon. It is mainly used for the passivation of the backlight side of the battery, which can achieve excellent surface passivation and selective collection of carriers. However, the light-receiving side of this battery is still in direct contact between the metal and the semiconductor. The recombination loss at the contact between the metal and the semiconductor limits the further improvement of the battery efficiency. The above problem can be avoided by using a double-sided passivation contact structure, that is, a passivation contact structure is set on both the light-receiving side and the backlight side of the battery. Although the passivation contact structure can greatly reduce the metallization recombination, the light absorption characteristics of the poly layer of the passivation contact structure on the light-receiving side will affect the battery's absorption of light, so the passivation contact structure on the light-receiving side needs to be locally passivated. However, in the process of realizing local passivation of the light-receiving side, there is a problem of damaging the battery structure due to the need to remove the wrap-around plating, which cannot really effectively improve the battery efficiency. Summary of the Invention

[0005] According to various embodiments of the present application, a method for preparing a solar cell, a solar cell, and a photovoltaic module are provided.

[0006] In a first aspect, an embodiment of the present application provides a method for preparing a solar cell, comprising:

[0007] On the backlight surface of a silicon wafer of the first conductivity type, a first dielectric layer, a first amorphous silicon layer doped with a doping element of a second conductivity type opposite to the first conductivity type, and a first mask layer are sequentially stacked away from the silicon wafer;

[0008] On the light-receiving surface of the silicon wafer, a second dielectric layer, a second amorphous silicon layer doped with a doping element having the first conductivity type, and a second mask layer are sequentially stacked and separated from the silicon wafer;

[0009] crystallizing the first amorphous silicon layer to transform it into a first doped polysilicon layer, and activating the doping element of the second conductivity type;

[0010] crystallizing the second amorphous silicon layer to transform it into a second doped polysilicon layer, and activating the doping element of the first conductivity type;

[0011] manufacturing a patterned second mask layer;

[0012] removing the second doped polysilicon layer outside the coverage area of ​​the patterned second mask layer to form a patterned second doped polysilicon layer;

[0013] removing the second dielectric layer outside the coverage area of ​​the patterned second doped polysilicon layer to form a patterned second dielectric layer; and

[0014] The first mask layer and the patterned second mask layer are removed.

[0015] In some embodiments, the step of forming the patterned second mask layer includes:

[0016] coating an acid-resistant slurry on the second mask layer;

[0017] removing the second mask layer outside the area covered by the acid-resistant paste and removing a portion of the thickness of the first mask layer to form a patterned second mask layer and retaining a portion of the thickness of the first mask layer; and

[0018] The acid-resistant slurry is removed.

[0019] In some embodiments, the step of removing the second mask layer outside the area covered by the acid-resistant slurry and removing a portion of the thickness of the first mask layer to form a patterned second mask layer and retaining a portion of the thickness of the first mask layer includes:

[0020] The surface of the silicon wafer is cleaned simultaneously using hydrofluoric acid with a mass percentage concentration of x% and the cleaning time t1 is controlled to satisfy: t2≤t1<t3, t2 is the time required for the second mask layer to be completely removed in the hydrofluoric acid with a mass percentage concentration of x%, and t3 is the time required for the first mask layer to be completely removed in the hydrofluoric acid with a mass percentage concentration of x%; wherein x is approximately 0.1 to 10.

[0021] In some embodiments, the thickness of the first mask layer is greater than the thickness of the second mask layer.

[0022] In some embodiments, in a hydrofluoric acid solution of the same concentration, the etching rate of the first mask layer is lower than the etching rate of the second mask layer.

[0023] In some embodiments, the step of forming the patterned second mask layer includes:

[0024] A portion of the second mask layer is removed using a laser to obtain a patterned second mask layer.

[0025] In some embodiments, the step of removing the second doped polysilicon layer outside the coverage area of ​​the patterned second mask layer to form the patterned second doped polysilicon layer includes:

[0026] Using alkali to remove the second doped polysilicon layer outside the coverage area of ​​the patterned second mask layer, and continuing to etch the second dielectric layer at a reduced etching rate;

[0027] The step of removing the second dielectric layer outside the coverage area of ​​the patterned second doped polysilicon layer to form a patterned second dielectric layer includes:

[0028] Use alkali to perform etching again with the assistance of texturing additives to remove the second dielectric layer outside the coverage area of ​​the patterned second mask layer and the patterned second doped polysilicon layer to form a patterned second dielectric layer, and continue etching into the silicon wafer to texturize the light-receiving surface again.

[0029] In some embodiments, the step of removing the second doped polysilicon layer outside the coverage area of ​​the patterned second mask layer to form the patterned second doped polysilicon layer includes:

[0030] removing the second doped polysilicon layer outside the coverage area of ​​the patterned second mask layer by using alkali, and stopping etching when etching reaches the second dielectric layer;

[0031] The step of removing the second dielectric layer outside the coverage area of ​​the patterned second doped polysilicon layer to form a patterned second dielectric layer includes:

[0032] The second dielectric layer outside the covered area of ​​the patterned second doped polysilicon layer is removed by using hydrofluoric acid cleaning.

[0033] In some embodiments, before the step of preparing, on the backlight side of a silicon wafer of the first conductivity type, a first dielectric layer, a first amorphous silicon layer doped with an element of a second conductivity type opposite to the first conductivity type, and a first mask layer stacked in sequence, facing away from the silicon wafer, the method for preparing a solar cell further comprises:

[0034] The backlight surface of the silicon wafer is alkali-etched to make the backlight surface reach the morphology required by the backlight surface process.

[0035] In some embodiments, the step of preparing, on the backlight side of a silicon wafer of the first conductivity type, a first dielectric layer, a first amorphous silicon layer doped with an element of a second conductivity type opposite to the first conductivity type, and a first mask layer stacked in sequence, facing away from the silicon wafer, comprises:

[0036] The first dielectric layer, the first amorphous silicon layer doped with the second conductive type doping element, and the first mask layer are sequentially stacked away from the silicon wafer and formed on the backlight surface by PECVD.

[0037] In some embodiments, before the step of preparing, on the light-receiving surface of the silicon wafer, a second dielectric layer, a second amorphous silicon layer doped with a doping element of the first conductivity type, and a second mask layer stacked in sequence and facing away from the silicon wafer, the method for preparing a solar cell further comprises:

[0038] Using a mixed solution of hydrofluoric acid and an oxidant, removing the first dielectric layer, the first amorphous silicon layer, and the wrap-around coating of the first mask layer on the light-receiving surface and edge of the silicon wafer;

[0039] The light-receiving surface of the silicon wafer is textured to form a textured surface on the light-receiving surface.

[0040] In some embodiments, the oxidant comprises at least one of nitric acid, hydrogen peroxide, and ozone.

[0041] In some embodiments, the step of preparing, on the light-receiving surface of the silicon wafer, a second dielectric layer, a second amorphous silicon layer doped with a doping element of the first conductivity type, and a second mask layer stacked in sequence away from the silicon wafer includes:

[0042] The second dielectric layer, the second amorphous silicon layer doped with the first conductive type doping element, and the second mask layer are sequentially stacked away from the silicon wafer and formed on the light-receiving surface of the silicon wafer by using PECVD.

[0043] In some embodiments, the steps of crystallizing the first amorphous silicon layer into a first doped polysilicon layer, activating the second conductive type doping element, and forming a PN junction on the backlight surface of the silicon wafer are performed simultaneously with the steps of crystallizing the second amorphous silicon layer into a second doped polysilicon layer and activating the first conductive type doping element.

[0044] In some embodiments, the step of coating the acid-resistant slurry on the second mask layer includes:

[0045] The acid-resistant paste is coated on the second mask layer by printing; wherein the width of the acid-resistant paste is about 40 μm to 200 μm.

[0046] In some embodiments, the steps of removing the second mask layer outside the area covered by the acid-resistant slurry and removing a portion of the thickness of the first mask layer to form a patterned second mask layer, and retaining a portion of the thickness of the first mask layer, the step of removing the acid-resistant slurry, the step of removing the second doped polysilicon layer outside the area covered by the patterned second mask layer to form a patterned second doped polysilicon layer, and the steps of removing the first mask layer and patterning the second mask layer are performed at one time in a tank cleaning machine, and between any two steps, the following steps are further included:

[0047] The silicon wafer is cleaned with water.

[0048] In some embodiments, the step of removing the acid-resistant slurry comprises:

[0049] The acid-resistant slurry is removed using a mixture of alkali and hydrogen peroxide.

[0050] In some embodiments, after the step of removing the first mask layer and the patterned second mask layer, the method for preparing a solar cell further includes:

[0051] A light-receiving surface functional film and a backlight surface functional film are formed on the light-receiving surface and the backlight surface, respectively; wherein the light-receiving surface functional film covers the side of the second doped polysilicon layer facing away from the silicon wafer and the exposed area of ​​the light-receiving surface not covered by the second doped polysilicon layer, and the backlight surface functional film covers the side of the first doped polysilicon layer facing away from the silicon wafer;

[0052] A light-receiving surface electrode corresponding to the metallized area is made on the light-receiving surface, and a backlight surface electrode is made on the backlight surface; wherein, the light-receiving surface electrode penetrates the light-receiving surface functional film and makes ohmic contact with the patterned second doped polysilicon layer, and the backlight surface electrode penetrates the backlight surface functional film and makes ohmic contact with the first doped polysilicon layer.

[0053] In some embodiments, the first dielectric layer includes a silicon oxide layer.

[0054] In some embodiments, the thickness of the first dielectric layer is approximately 0.1 nm to 5 nm.

[0055] In some embodiments, the second dielectric layer includes a silicon oxide layer.

[0056] In some embodiments, the thickness of the second dielectric layer is approximately 0.1 nm to 5 nm.

[0057] In some embodiments, the thickness of the first amorphous silicon layer is approximately 50 nm to 350 nm.

[0058] In some embodiments, the thickness of the second amorphous silicon layer is about 50 nm to 200 nm.

[0059] In some embodiments, the first mask layer includes at least one of a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer.

[0060] In some embodiments, the thickness of the first mask layer is approximately 20 nm to 80 nm.

[0061] In some embodiments, the second mask layer includes at least one of a silicon oxide layer and a silicon oxynitride layer.

[0062] In some embodiments, the second mask layer has a thickness of about 5 nm to about 50 nm.

[0063] In a second aspect, an embodiment of the present application provides a solar cell, which is prepared by the solar cell preparation method as described in the first aspect.

[0064] In a third aspect, an embodiment of the present application provides a photovoltaic module comprising the solar cell as described in the second aspect.

[0065] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0067] FIG1 is a flow chart of a method for preparing a solar cell provided in Example 1 of the present application;

[0068] FIG2 is a schematic diagram of step 1 of a method for preparing a solar cell provided in Example 1 of the present application;

[0069] FIG3 is a schematic diagram of step 2 of a method for preparing a solar cell provided in Example 1 of the present application;

[0070] FIG4 is a schematic diagram of step 3 of the method for preparing a solar cell provided in Example 1 of the present application;

[0071] FIG5 is a schematic diagram of step 4 of a method for preparing a solar cell provided in Example 1 of the present application;

[0072] FIG6 is a schematic diagram of step 5 of the method for preparing a solar cell provided in Example 1 of the present application;

[0073] FIG7 is a schematic diagram of step 6 of a method for preparing a solar cell provided in Example 1 of the present application;

[0074] FIG8 is a schematic diagram of step 7 of a method for preparing a solar cell provided in Example 1 of the present application;

[0075] FIG9 is a schematic diagram of step 8-1 of a method for preparing a solar cell provided in Example 1 of the present application;

[0076] FIG10 is a schematic diagram of step 8-2 of a method for preparing a solar cell provided in Example 1 of the present application;

[0077] FIG11 is a schematic diagram of step 8-3 of a method for preparing a solar cell provided in Example 1 of the present application;

[0078] FIG12 is a schematic diagram of step 8-5 of a method for preparing a solar cell provided in Example 1 of the present application;

[0079] FIG13 is a schematic diagram of step 9 of the method for preparing a solar cell provided in Example 1 of the present application;

[0080] FIG14 is a schematic diagram of step 10 of a method for preparing a solar cell provided in Example 1 of the present application;

[0081] FIG15 is a schematic structural diagram of a solar cell produced by the method for producing a solar cell provided in Example 2 of the present application.

[0082] Explanation of the accompanying drawings: 100, solar cell; 101, silicon wafer; 1011, metallized area; 102, first dielectric layer; 103, first doped polysilicon layer; 104, first mask layer; 105, first amorphous silicon layer; 106, second dielectric layer; 107, second doped polysilicon layer; 108, second mask layer; 109, second amorphous silicon layer; 110, acid-resistant paste; 111, light-receiving surface functional film; 112, backlight surface functional film; 113, light-receiving surface electrode; 114, backlight surface electrode; 115, diffusion region. DETAILED DESCRIPTION

[0083] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0084] The technical solution of this application will be described below with reference to embodiments and drawings.

[0085] The efficiency of solar cells with passivated contacts is currently difficult to further improve. In traditional technology, the efficiency of this type of solar cell is improved by setting a double-sided passivated contact structure and performing local passivation on the passivated contact structure on the light-receiving surface. However, when performing local passivation on the light-receiving surface, operations such as de-plating are often required. De-plating may cause certain damage to the light-receiving surface of the cell structure, thereby affecting further improvement of the cell efficiency. For example, in order to achieve a double-sided passivated contact structure for a solar cell and set the light-receiving surface as a local passivated contact structure, the following operations can be used:

[0086] Depositing a first poly structure on the backlight surface of the silicon substrate by PECVD or other methods, wherein the first poly structure includes a first dielectric layer and a first doped polysilicon layer;

[0087] A second poly structure is deposited on the light-receiving surface of the silicon substrate by PECVD or other methods. The second poly structure includes a second dielectric layer and a second polysilicon layer. After depositing the above structure, the second poly structure will inevitably have wrap-around plating on the backlight side and be located on the same surface as the first poly structure.

[0088] In order to obtain a locally passivated second poly structure, the second poly structure can be subjected to patterned etching and de-coating after the first poly structure is deposited. The chemicals used for patterned etching and de-coating of the second poly structure also have an etching effect on the first poly structure. It can be seen that it is difficult to avoid damage to the backlight surface structure of the battery while removing the de-coating of the second poly structure on the backlight surface. This application proposes a solution based on this problem, which can obtain a double-sided passivated contact structure and local passivation of the light-receiving surface, and can avoid the problem of damage to the battery structure on the backlight surface due to the de-coating operation.

[0089] Based on this, in a first aspect, as shown in FIG1 , an embodiment of the present application provides a method for preparing a solar cell, comprising:

[0090] On the backlight side of a silicon wafer of the first conductivity type, a first dielectric layer, a first amorphous silicon layer doped with a doping element of a second conductivity type opposite to the first conductivity type, and a first mask layer are sequentially stacked away from the silicon wafer;

[0091] On the light-receiving surface of the silicon wafer, a second dielectric layer, a second amorphous silicon layer doped with a doping element having a first conductivity type, and a second mask layer are sequentially stacked and separated from the silicon wafer;

[0092] crystallizing the first amorphous silicon layer to transform it into a first doped polysilicon layer, and activating a doping element of the second conductivity type;

[0093] crystallizing the second amorphous silicon layer to transform it into a second doped polysilicon layer, and activating the doping element of the first conductivity type;

[0094] forming a patterned second mask layer;

[0095] removing the second doped polysilicon layer outside the coverage area of ​​the patterned second mask layer to form a patterned second doped polysilicon layer;

[0096] removing the second dielectric layer outside the coverage area of ​​the patterned second doped polysilicon layer to form a patterned second dielectric layer; and

[0097] The first mask layer and the patterned second mask layer are removed.

[0098] In some embodiments, the step of forming the patterned second mask layer includes:

[0099] coating an acid-resistant slurry on the second mask layer;

[0100] removing the second mask layer outside the area covered by the acid-resistant paste and removing a portion of the thickness of the first mask layer to form a patterned second mask layer, and retaining a portion of the thickness of the first mask layer; and

[0101] Remove acid-resistant slurry.

[0102] The solar cell preparation method can realize the production of a local passivation contact structure on the light-receiving surface, and simultaneously remove the wrap-around plating of the poly structure of the light-receiving surface on the backlight surface without damaging the poly structure of the backlight surface.

[0103] The solar cell preparation method uses the obtained patterned second mask layer to produce a patterned second doped polysilicon layer and a patterned second dielectric layer, thereby obtaining a patterned light-receiving surface passivation contact structure; the second doped polysilicon layer removed when producing the light-receiving surface passivation contact structure includes the second doped polysilicon layer plated around the edge of the silicon wafer and the backlight surface, and the second dielectric layer removed includes the second dielectric layer plated around the edge of the silicon wafer.

[0104] During the process of manufacturing the patterned second doped polysilicon layer and the patterned second dielectric layer, the first mask layer prevents the backlight side poly structure, ie, the first doped polysilicon layer and the first dielectric layer, from being etched away.

[0105] Regarding conductivity types, it should be noted that one of the first conductivity type and the second conductivity type is N-type and the other is P-type. That is, the silicon wafer can be N-type, while the first amorphous silicon layer is P-type doped and the second amorphous silicon layer is N-type doped. Alternatively, the silicon wafer can be P-type, while the first amorphous silicon layer is N-type doped and the second amorphous silicon layer is P-type doped.

[0106] In some embodiments, the step of forming the patterned second mask layer includes:

[0107] coating an acid-resistant slurry on the second mask layer;

[0108] removing the second mask layer outside the area covered by the acid-resistant paste and removing a portion of the thickness of the first mask layer to form a patterned second mask layer, and retaining a portion of the thickness of the first mask layer; and

[0109] Remove acid-resistant slurry.

[0110] The method of using an acid-resistant slurry to create a patterned second mask layer is also known as the slurry method. This method can be performed in the same tank cleaning machine as the subsequent step of removing the second doped polysilicon layer outside the area covered by the patterned second mask layer to form the patterned second doped polysilicon layer. Using a laser method to create the patterned second mask layer requires an additional laser processing device and may also require a robot to transfer the solar cells from the laser processing device to the tank cleaning machine for the patterned second doped polysilicon layer. Therefore, compared to the laser removal method, the slurry method requires less processing equipment.

[0111] In some embodiments, the steps of removing the second mask layer outside the area covered by the acid-resistant paste and removing a portion of the first mask layer to form a patterned second mask layer and retaining a portion of the first mask layer include:

[0112] The surface of the silicon wafer is cleaned simultaneously using hydrofluoric acid with a mass percentage concentration of x%, and the cleaning time t1 is controlled to satisfy: t2≤t1<t3, t2 is the time required for the second mask layer to be completely removed in the hydrofluoric acid with a mass percentage concentration of x%, and t3 is the time required for the first mask layer to be completely removed in the hydrofluoric acid with a mass percentage concentration of x%. Wherein, x is approximately 0.1 to 10, including any point in this numerical range, for example, 0.1, 1, 3, 5, 7, 9 or 10.

[0113] The process of pickling to remove the second mask layer outside the acid-resistant slurry coverage area needs to be cleaned with hydrofluoric acid to the entire surface of the silicon wafer, including the light-receiving surface and the backlight surface edge. Inevitably, when the backlight surface is cleaned with hydrofluoric acid, there is an etching problem on the first mask layer. The present application is through designing different mask layer characteristics, that is, through designing the time difference of the first mask layer and the second mask layer to completely remove the required time in hydrofluoric acid, to complete the second mask layer outside the coverage area of ​​the acid-resistant slurry and the first mask layer of partial thickness selective removal, and then retain the first mask layer of partial thickness.

[0114] In some embodiments, the thickness of the first mask layer is greater than the thickness of the second mask layer.

[0115] In some embodiments, in hydrofluoric acid solutions of the same concentration, the etching rate of the first mask layer is lower than the etching rate of the second mask layer.

[0116] It can be understood that if the first mask layer and the second mask layer are made of the same material, their etching speeds in a hydrofluoric acid solution with the same concentration are the same. If the thickness of the first mask layer is greater than that of the second mask layer, then t3>t2.

[0117] The term "etching rate" refers to the physical quantity of how quickly a solid medium is etched by a chemical reagent. In this application, this can also be understood as meaning that the material of the first mask layer has better hydrofluoric acid resistance than the material of the second mask layer. For example, if the first mask layer is silicon oxynitride and the second mask layer is silicon oxide, the acid resistance of silicon oxynitride is better than that of silicon oxide, meaning that the etching rate of silicon oxynitride in hydrofluoric acid is lower than that of silicon oxide in hydrofluoric acid of the same concentration. Even if the two mask layers have the same thickness, t3 > t2.

[0118] In some embodiments, the step of forming the patterned second mask layer includes:

[0119] A portion of the second mask layer is removed using laser to obtain a patterned second mask layer.

[0120] By controlling the laser irradiation area and irradiation time, portions of the second mask layer can be selectively removed. Similar to the slurry method, the laser method does not require the use of an acid-resistant slurry, and thus does not require the removal step. This eliminates the generation of alkaline waste liquids that would be generated during the acid-resistant slurry removal step, making it more environmentally friendly.

[0121] In some embodiments, the step of removing the second doped polysilicon layer outside the coverage area of ​​the patterned second mask layer to form the patterned second doped polysilicon layer includes:

[0122] Using alkali to remove the second doped polysilicon layer outside the coverage area of ​​the patterned second mask layer, and continuing to etch the second dielectric layer at a reduced etching rate;

[0123] The step of removing the second dielectric layer outside the coverage area of ​​the patterned second doped polysilicon layer to form a patterned second dielectric layer includes:

[0124] Use alkali to perform etching again with the assistance of texturing additives to remove the second dielectric layer outside the coverage area of ​​the patterned second mask layer and the patterned second doped polysilicon layer to form a patterned second dielectric layer, and continue etching into the silicon wafer to texturize the light-receiving surface again.

[0125] The alkali used can be sodium hydroxide or potassium hydroxide, and the texturing additive can greatly reduce the amount of alkali used.

[0126] It is understood that the steps of removing the second doped polysilicon layer outside the area covered by the patterned second mask layer to form the patterned second doped polysilicon layer and removing the second dielectric layer outside the area covered by the patterned second doped polysilicon layer to form the patterned second dielectric layer can be completed sequentially through a single alkaline etch, thereby simplifying the process flow. Due to the presence of the second dielectric layer between the second doped polysilicon layer and the silicon wafer, the reaction slows down for a period of time after the alkaline etching of the second doped polysilicon layer. This slowdown period is the time it takes for the alkali to react with the second dielectric layer (20 seconds to 1000 seconds), which means that the etching rate decreases. The reaction rate is related to the concentration, temperature, and additives of the prepared alkaline solution. Therefore, it is possible to choose whether to etch into the silicon wafer during this process and then texture the surface again to form a textured surface. After etching into the silicon wafer, the second doped polysilicon layer is removed and annealed to advance the process into the phosphorus diffusion region within the silicon wafer. Not providing a phosphorus diffusion region in the silicon wafer outside the metallized area can facilitate the passivation effect of a passivation film such as aluminum oxide, preventing severe carrier recombination in areas outside the metallized area.

[0127] In some embodiments, the step of removing the second doped polysilicon layer outside the coverage area of ​​the patterned second mask layer to form the patterned second doped polysilicon layer includes:

[0128] Using alkali to remove the second doped polysilicon layer outside the coverage area of ​​the patterned second mask layer, and stopping etching when etching reaches the second dielectric layer;

[0129] The step of removing the second dielectric layer outside the coverage area of ​​the patterned second doped polysilicon layer to form a patterned second dielectric layer includes:

[0130] The second dielectric layer outside the covered area of ​​the patterned second doped polysilicon layer is removed by using hydrofluoric acid cleaning.

[0131] It is understood that the step of removing the second doped polysilicon layer outside the coverage area of ​​the patterned second mask layer to form a patterned second doped polysilicon layer only removes the second doped polysilicon layer and does not completely remove the second dielectric layer, thereby not etching the silicon wafer covered by the second dielectric layer. The step of removing the second dielectric layer outside the coverage area of ​​the patterned second doped polysilicon layer to form a patterned second dielectric layer and the step of removing the first mask layer and the patterned second mask layer can be removed simultaneously in a single hydrofluoric acid cleaning. This preserves the dopant element diffusion layer beneath the second dielectric layer that diffused into the silicon substrate during annealing. Preserving the dopant element diffusion layer is beneficial to surface carrier transport, but is not conducive to passivation using aluminum oxide. Silicon oxide + silicon nitride can be used to passivate the light-receiving surface.

[0132] In some embodiments, before the step of forming, on the backlight side of a silicon wafer of the first conductivity type, a first dielectric layer, a first amorphous silicon layer doped with an element of a second conductivity type opposite to the first conductivity type, and a first mask layer stacked in sequence, facing away from the silicon wafer, the method for preparing a solar cell further comprises:

[0133] The backlight surface of the silicon wafer is alkali-etched to achieve the morphology required by the backlight surface process. The morphology required by the backlight surface process is not limited to polishing, texturing or other morphologies.

[0134] In some embodiments, the step of preparing, on a backlight side of a silicon wafer of a first conductivity type, a first dielectric layer, a first amorphous silicon layer doped with an element of a second conductivity type opposite to the first conductivity type, and a first mask layer stacked in sequence, facing away from the silicon wafer, includes:

[0135] A first dielectric layer, a first amorphous silicon layer doped with a doping element of a second conductivity type, and a first mask layer are sequentially stacked away from the silicon wafer and formed on the backlight surface by using PECVD.

[0136] PECVD, or Plasma Enhanced Chemical Vapor Deposition. This application uses the PECVD process to replace the current high-temperature diffusion process. Compared with the high-temperature diffusion process with a process temperature of about 1050°C, the PECVD process is a low-temperature process with a process temperature below 500°C, which avoids damage to the silicon wafer caused by the high-temperature process. Compared with the high-temperature diffusion process, the electricity cost of this application is lower, and the heat loss of the machine is reduced, thereby achieving the purpose of cost reduction. The first amorphous silicon layer produced by the PECVD process can be further made into a first doped polysilicon layer with excellent passivation performance, which can improve the passivation of the backlight surface of the battery and further increase the battery opening voltage.

[0137] In some embodiments, before the step of forming a second dielectric layer, a second amorphous silicon layer doped with a doping element of the first conductivity type, and a second mask layer stacked sequentially on the light-receiving surface of the silicon wafer and facing away from the silicon wafer, the method for preparing a solar cell further includes:

[0138] Using a mixed solution of hydrofluoric acid and an oxidant, the first dielectric layer, the P-type doped first amorphous silicon layer, and the wrap-around coating of the first mask layer on the light-receiving surface and edge of the silicon wafer are removed;

[0139] The light-receiving surface of the silicon wafer is textured to form a textured surface on the light-receiving surface.

[0140] Optionally, the oxidant includes at least one of nitric acid, hydrogen peroxide and ozone.

[0141] First, hydrofluoric acid can remove silicon compounds such as silicon oxide, thereby removing the first dielectric layer and the first mask layer. Although the corrosion rate of silicon in pure hydrofluoric acid is extremely low for the P-type doped first amorphous silicon layer, corrosion can occur if oxidants such as nitric acid or hydrogen peroxide are added. Optionally, the mixed solution of hydrofluoric acid and the oxidant contains a concentration of 0.5% to 20% hydrofluoric acid by mass. Taking the hydrofluoric acid and nitric acid mixed solution as an example, the reaction chemical formula is as follows: Si + 4HNO3 + 6HF = H2SiF6 + 4NO2 + 4H2O. By using this mixed solution of hydrofluoric acid and the oxidant, combined with related processes such as single-side pickling, the first dielectric layer, the P-type doped first amorphous silicon layer, and the first mask layer can be simultaneously removed from the light-receiving surface and edges of the silicon wafer. This removal of the wraparound plating can be completed using a single process tool, such as a chain cleaning tool, simplifying the removal process for multiple film layers and reducing equipment costs.

[0142] In some embodiments, the step of preparing, on the light-receiving surface of the silicon wafer, a second dielectric layer, a second amorphous silicon layer doped with a doping element of the first conductivity type, and a second mask layer stacked in sequence and facing away from the silicon wafer, includes:

[0143] A second dielectric layer, a second amorphous silicon layer doped with a doping element of the first conductivity type, and a second mask layer are sequentially stacked away from the silicon wafer and prepared on the light-receiving surface by PECVD.

[0144] PECVD (Plasma Enhanced Chemical Vapor Deposition) is used. The second amorphous silicon layer and the first amorphous silicon layer, which are also made using PECVD, can be annealed once to complete the advancement of the doped elements in each layer.

[0145] In some embodiments, the steps of crystallizing the first amorphous silicon layer into a first doped polysilicon layer, activating the second conductive type of doping elements, and forming a PN junction on the backlight side of the silicon wafer are performed simultaneously with the steps of crystallizing the second amorphous silicon layer into a second doped polysilicon layer and activating the first conductive type of doping elements.

[0146] Exemplarily, annealing is performed at a temperature of 850°C to 1000°C to crystallize the first amorphous silicon layer and the second amorphous silicon layer and transform them into a first doped polysilicon layer and a second doped polysilicon layer, respectively, to activate the doped boron and phosphorus, and the first dielectric layer through which the boron element diffuses forms a PN junction with the silicon wafer.

[0147] Through one annealing process, the first amorphous silicon layer and the second amorphous silicon layer are crystallized into the first doped polysilicon layer and the second doped polysilicon layer, and the advancement of two doping elements is achieved at the same time, thereby achieving the purpose of saving energy consumption and simplifying the process.

[0148] In some embodiments, the step of coating the acid-resistant slurry on the second mask layer includes:

[0149] The acid-resistant paste is applied by printing, wherein the width of the acid-resistant paste is about 40 μm to 200 μm, including any value within the width range, such as 40 μm, 60 μm, 80 μm, 100 μm, 120 μm, 150 μm, 180 μm, and 200 μm.

[0150] The acid-resistant slurry is an acid-resistant slurry; the acid-resistant slurry may contain paraffin and organic solvents, etc., which are waxy after drying and solidification. It does not react with the hydrofluoric acid used for pickling, but reacts with alkali, thereby forming a patterned second mask layer without reacting in the pickling step S7, and is removed by alkali washing in step S8.

[0151] In some embodiments, in order to reduce the number of equipment required for the process, the steps of removing the second mask layer outside the area covered by the acid-resistant slurry and removing a portion of the thickness of the first mask layer to form a patterned second mask layer, and retaining a portion of the thickness of the first mask layer, removing the acid-resistant slurry, removing the second doped polysilicon layer outside the area covered by the patterned second mask layer to form a patterned second doped polysilicon layer, and removing the first mask layer and the patterned second mask layer are performed at one time in a tank cleaning machine, and between any two steps, the following steps are further included:

[0152] Rinse the silicon wafer with water.

[0153] Washing the silicon wafer with water can remove the reagents used in the previous step and avoid interference with the implementation of the next step.

[0154] In some embodiments, the step of removing the acid-resistant slurry comprises:

[0155] A mixture of alkali and hydrogen peroxide is used to remove the acid-resistant slurry.

[0156] As described above, the acid-resistant slurry does not react during acid washing and is removed by alkaline washing. The addition of hydrogen peroxide accelerates the cleaning process, and the alkaline washing process does not affect the second doped polysilicon layer. For example, the mass concentrations of the alkali and hydrogen peroxide in the mixed solution are both 0.1% to 10%.

[0157] Optionally, after the step of removing the first mask layer and the patterned second mask layer, the method for preparing a solar cell further includes:

[0158] A light-receiving surface functional film and a backlight surface functional film are formed on the light-receiving surface and the backlight surface, respectively; wherein the light-receiving surface functional film covers the side of the second doped polysilicon layer facing away from the silicon wafer and the exposed area of ​​the light-receiving surface not covered by the second doped polysilicon layer, and the backlight surface functional film covers the side of the first doped polysilicon layer facing away from the silicon wafer;

[0159] A light-receiving surface electrode corresponding to the metallized area is made on the light-receiving surface, and a backlight surface electrode is made on the backlight surface; wherein the light-receiving surface electrode penetrates the light-receiving surface functional film and makes ohmic contact with the patterned second doped polysilicon layer, and the backlight surface electrode penetrates the backlight surface functional film and makes ohmic contact with the first doped polysilicon layer.

[0160] Optionally, the material of the light-receiving surface functional film and the backlight surface functional film includes at least one of aluminum oxide, silicon oxide, silicon nitride and silicon oxynitride.

[0161] Exemplarily, the light-receiving surface functional film includes a passivation film made of aluminum oxide, silicon oxide, etc. with a thickness of about 2nm to 10nm, and a passivation and anti-reflection film made of silicon nitride, silicon oxynitride, silicon oxide, etc. with a thickness of about 70nm to 90nm.

[0162] In some embodiments, the backlight functional film includes a silicon nitride film.

[0163] In some embodiments, the backlight functional film has a thickness of approximately 70 nm to 90 nm, including any value within the thickness range, such as 70 nm, 75 nm, 80 nm, 85 nm, and 90 nm.

[0164] Exemplarily, silver paste is screen-printed on the light-receiving surface for metallization to obtain the light-receiving surface electrode; silver paste is screen-printed on the backlight surface for metallization to obtain the backlight surface electrode.

[0165] Optionally, the first dielectric layer and the second dielectric layer may include one or more dielectric materials, such as at least one of silicon oxide, magnesium fluoride, amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, and titanium oxide. Specifically, the dielectric layer may be composed of a silicon oxide layer containing silicon oxide. This is because the silicon oxide layer has excellent passivation properties, can minimize the recombination loss of minority carriers on the semiconductor substrate surface, and is a film with excellent durability for subsequent high-temperature processes.

[0166] The first and second dielectric layers act as a barrier between electrons and holes, combining with the polysilicon layer to prevent minority carriers from passing through. They can also function as pinhole channels, allowing carriers within the solar cell to move freely. The heavily doped polysilicon selectively allows majority carriers to pass through, thus reducing minority carrier recombination losses. Furthermore, the first and second dielectric layers can act as diffusion barriers to prevent dopants from the doped polysilicon layer from diffusing into the semiconductor substrate.

[0167] In some embodiments, the first dielectric layer includes a silicon oxide layer.

[0168] In some embodiments, the first dielectric layer has a thickness of approximately 0.1 nm to 5 nm, including any value within the thickness range, such as 0.1 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, or 5 nm.

[0169] In some embodiments, the second dielectric layer includes a silicon oxide layer.

[0170] In some embodiments, the second dielectric layer has a thickness of approximately 0.1 nm to 5 nm, including any value within the thickness range, such as 0.1 nm, 1 nm, 1.2 nm, 1.5 nm, 1.7 nm, 2 nm, 3 nm, 4 nm, or 5 nm.

[0171] In some embodiments, the thickness of the first amorphous silicon layer is approximately 50 nm to 350 nm, including any value within the thickness range, such as 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, and 350 nm.

[0172] In some embodiments, the second amorphous silicon layer has a thickness of about 50 nm to 200 nm, including any value within the thickness range, such as 50 nm, 100 nm, 150 nm, and 200 nm.

[0173] In some embodiments, the first mask layer includes at least one of a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer.

[0174] In some embodiments, the thickness of the first mask layer is approximately 20 nm to 80 nm, including any value within the thickness range, such as 20 nm, 40 nm, 60 nm, and 80 nm.

[0175] In some embodiments, the second mask layer includes at least one of a silicon oxide layer and a silicon oxynitride layer.

[0176] In some embodiments, the thickness of the second mask layer is approximately 5 nm to 50 nm, including any value within the thickness range, such as 5 nm, 10 nm, 20 nm, 30 nm, 40 nm, and 50 nm.

[0177] In summary, the solar cell preparation method can realize the production of a local passivation contact structure on the light-receiving surface, while removing the wrap-around plating of the poly structure of the light-receiving surface on the backlight surface without damaging the poly structure of the backlight surface.

[0178] Furthermore, the solar cell fabrication methods of the related art use high-temperature diffusion to form a PN junction, followed by high-temperature annealing to increase the crystallization rate of the poly layer. High-temperature diffusion processes, such as boron diffusion processes, require temperatures of 1050°C or even higher, requiring significant heating power. Furthermore, the high temperatures also place high demands on equipment, leading to numerous equipment failures and damage during the production process, impacting the stability of mass production. Furthermore, high temperatures can severely damage silicon wafers. Silicon wafers with slightly higher oxygen content are prone to concentric ring defects at high temperatures, thus requiring a higher oxygen content. In contrast, the solar cell fabrication method of the present application utilizes a low-temperature PECVD process, operating at temperatures below 500°C. This reduces energy consumption in cell production and eliminates the damage to silicon wafers caused by high-temperature processes, contributing to lower costs and improved yield. Furthermore, the present application simultaneously crystallizes the first and second amorphous silicon layers into a first doped polysilicon layer and a second doped polysilicon layer through a single annealing step, simultaneously advancing both doping elements. This simplifies the process flow and further reduces the energy consumption required for heating.

[0179] On the other hand, the preparation method of the solar cell makes the PN junction on the backlight side of the silicon wafer. In order to reduce the lateral resistance of the emitter, the number of grid lines on the backlight side can be increased. Therefore, there is no high requirement for the number of grid lines on the light-receiving side, which is more conducive to the distribution design of the grid lines on the light-receiving side and the backlight side. It avoids the problem that adding grid lines when the PN junction is set on the light-receiving side of the cell will affect the cell's absorption of light, which is beneficial to improving the efficiency of the solar cell and reducing the metallization cost.

[0180] Furthermore, the solar cell preparation method reduces the area of ​​the second doped polysilicon layer by making a patterned passivation contact structure, a patterned second doped polysilicon layer and a patterned second dielectric layer to avoid the second doped polysilicon layer with poor light transmittance affecting the solar cell's absorption of light.

[0181] In addition, reducing the number of grid lines on the light-receiving surface can also simplify the pattern of the light-receiving surface electrode. Since the pattern of the passivation contact structure of the light-receiving surface is the same as the pattern of the light-receiving surface electrode, the difficulty of manufacturing the patterned second dielectric layer and the second doped polysilicon layer can be reduced, thereby improving the manufacturing yield.

[0182] Compared with the current process flow of passivated contact cells, the equipment required for this application has not increased, and there are also 12 equipment processes. Compared with the process flow of selective emitter passivated contact cells in related technologies, there are two fewer equipment processes. At the same time, it can replace the boron diffusion process of the current related technology to achieve the purpose of simplifying the process. From the perspective of solar cell conversion efficiency gain, the solar cell prepared in this application is expected to have a gain of more than 0.5%, and the theoretical efficiency is higher. Therefore, the preparation method of this application has multiple advantages of improving efficiency and reducing costs.

[0183] In a second aspect, an embodiment of the present application provides a solar cell, which is prepared by the solar cell preparation method as described in the first aspect.

[0184] In a third aspect, an embodiment of the present application provides a photovoltaic module comprising the solar cell as described in the second aspect.

[0185] The technical solution of this application will be described below with reference to the examples and accompanying drawings. Furthermore, the hydrofluoric acid, sodium hydroxide solution, and various types of additives used in the solar cell preparation methods in the examples of this application are all commercially available and are not limited thereto. "Concentration" in the examples of this application refers to mass concentration unless otherwise specified.

[0186] Example 1

[0187] The steps of preparing a solar cell according to this embodiment are as follows:

[0188] S1. Alkaline etching is performed on the backlight side of the silicon wafer to achieve the required morphology of the backlight side process: As shown in Figure 2, at 80°C, silicon wafer 101 is etched for 200 seconds using 5% NaOH with a polishing additive to a depth of 3 μm and a reflectivity of 45%. The wafer is then cleaned for 2 minutes using a mixture of NaOH and hydrogen peroxide at 60°C, with the concentration of NaOH in the mixture being 0.5% and the concentration of hydrogen peroxide in the mixture being 2%. The wafer is then cleaned for 2 minutes using 5% HF at 25°C.

[0189] S2. A first dielectric layer, a first amorphous silicon layer doped with boron, and a first mask layer are sequentially stacked on the backlight side of the N-type silicon wafer, facing away from the silicon wafer. As shown in FIG3 , a first dielectric layer 102 with a thickness of 2 nm is formed on the backlight side of the silicon wafer 101 by PECVD at 400° C. and 10,000 W ionization power, while introducing 7,000 sccm of N2O for 120 seconds. Then, a first amorphous silicon layer 105 with a thickness of 250 nm is formed by introducing 1,500 sccm of SiH4 and 50 sccm of diborane for 1,600 seconds at 300° C. Then, a first mask layer 104 made of silicon oxynitride with a thickness of 40 nm is formed by introducing 1,500 sccm of SiH4 and 6,000 sccm of N2O for 150 seconds.

[0190] S3. Using a mixed solution of hydrofluoric acid and an oxidant, the first dielectric layer, the first amorphous silicon layer, and the wrap-around coating of the first mask layer on the light-receiving surface and edges of the silicon wafer are removed: As shown in FIG4 , using a chain cleaning device, at 25° C., etching is performed using a mixed solution of HNO 3 and HF for 60 seconds, where the concentration of HNO 3 in the mixed solution is 20% and the concentration of HF in the mixed solution is 5%, to remove the wrap-around coating of the first dielectric layer 102, the first amorphous silicon layer 105, and the first mask layer 104 on the light-receiving surface and edges;

[0191] S4. Texturing the light-receiving surface of the silicon wafer to form a textured surface: As shown in FIG5 , at 80° C., 1% NaOH is used to etch the silicon wafer 101 for 200 seconds in the presence of a texturing additive, to a depth of 2 μm and a reflectivity of 10%. During this process, the wafer is also cleaned for 2 minutes using a mixture of NaOH and hydrogen peroxide at a temperature of 60° C., with the concentration of NaOH in the mixture being 0.5% and the concentration of hydrogen peroxide in the mixture being 2%. The wafer is then cleaned for 2 minutes using 3% HCl at 25° C.

[0192] S5. A second dielectric layer, a second amorphous silicon layer doped with phosphorus, and a second mask layer are sequentially stacked on the light-receiving surface, facing away from the silicon wafer. As shown in FIG6 , a PECVD process is used at 450° C. and 10,000 W of ionization power to introduce 7,000 sccm of N2O for 120 seconds to form a second dielectric layer with a thickness of 2 nm on the light-receiving surface of the silicon wafer 101. 1,500 sccm of SiH4 and 100 sccm of PH3 are introduced for 1,500 seconds to form a second in-situ phosphorus-doped amorphous silicon layer 109 with a thickness of 120 nm. 1,500 sccm of SiH4 and 6,000 sccm of N2O are introduced for 80 seconds to form a second mask layer 108 of silicon oxide with a thickness of 20 nm.

[0193] S6. Crystallize the first amorphous silicon layer and transform it into a first doped polysilicon layer, activating the boron element; crystallize the second amorphous silicon layer and transform it into a second doped polysilicon layer, activating the phosphorus element: As shown in FIG7 , annealing is performed at 930° C. for 2000 seconds to crystallize the first amorphous silicon layer 105 and the second amorphous silicon layer 109 and transform them into a first doped polysilicon layer 103 and a second doped polysilicon layer 107, respectively. The doped boron and phosphorus are activated and further promoted within the silicon wafer 101. The square resistance of the PN junction on the backlight side reaches 80Ω / sq.

[0194] S7, coating the second mask layer with an acid-resistant paste: As shown in FIG8 , an acid-resistant acid-resistant paste 110 is printed on the light-receiving surface with a width of 130 μm, and then dried at 180° C. for 30 seconds;

[0195] S8, cleaning and etching: Use a tank cleaning machine to clean and etch, as follows:

[0196] S8-1, removing the second mask layer outside the area covered by the acid-resistant paste and removing a portion of the first mask layer to form a patterned second mask layer, and retaining a portion of the first mask layer: As shown in FIG9 , at 25° C., using 3% HF for cleaning for 120 seconds, remove the second mask layer 108 and a portion of the first mask layer 104 outside the area covered by the acid-resistant paste 110 on the light-receiving surface, and retaining a portion of the first mask layer 104;

[0197] S8-2, removing the anti-acid slurry: As shown in FIG10 , at 60° C., the anti-acid slurry 110 is removed using a mixture of NaOH and H 2 O 2 , where the concentrations of NaOH and H 2 O 2 in the mixture are both 1%;

[0198] S8-3, removing the second doped polysilicon layer outside the coverage area of ​​the patterned second mask layer to form a patterned second doped polysilicon layer; removing the second dielectric layer outside the coverage area of ​​the patterned second doped polysilicon layer to form a patterned second dielectric layer: as shown in FIG11 , at 80° C., using 5% concentration of NaOH, the silicon wafer 101 is etched for 500 seconds in the presence of a texturing additive to remove the second doped polysilicon layer 107 and the second dielectric layer 106 outside the coverage area of ​​the patterned second mask layer 108 to form a patterned second doped polysilicon layer 107 and a patterned second dielectric layer 106, and etching is continued into the silicon wafer 101, and the silicon wafer 101 in the mask-free area is texturized again, with a reflectivity of 10%;

[0199] S8-4. At 60°C, use a mixture of NaOH and hydrogen peroxide to clean the battery surface for 2 minutes to remove organic residues. The concentration of NaOH is 0.5% and the concentration of hydrogen peroxide is 2%.

[0200] S8-5, removing the first mask layer and the patterned second mask layer: As shown in FIG12 , at room temperature, use a 20% HF solution for cleaning for 5 minutes to remove the remaining first mask layer 104 and the patterned second mask layer 108;

[0201] S8-6, drying at 90°C for 10 minutes to finally form a local passivated contact structure;

[0202] S9. Forming a light-receiving surface functional film and a backlight surface functional film on the light-receiving surface and the backlight surface, respectively: As shown in FIG13 , using an ALD device, a 4 nm thick aluminum oxide passivation film is formed on the bottom layer of the light-receiving surface; using a PECVD device, SiH4 and NH3 are introduced to form an 80 nm thick silicon nitride as a passivation and anti-reflection film on the outer layer of the light-receiving surface and the backlight surface. The aluminum oxide film on the bottom layer of the light-receiving surface and the silicon nitride film on the outer layer of the light-receiving surface are combined to form the light-receiving surface functional film 111, and the silicon nitride film on the backlight surface is the backlight surface functional film 112;

[0203] S10. Fabricate a light-receiving electrode on the light-receiving surface corresponding to the metallized area, and a backlight electrode on the backlight surface: As shown in Figure 14, a mixture paste primarily composed of silver is used for screen printing and metallization on the front and backlight surfaces of the cell. Silver grid lines 25 microns wide and 1.5 mm apart are formed on the light-receiving surface, i.e., light-receiving surface electrodes 113; silver grid lines 35 microns wide and 1.0 mm apart are formed on the backlight surface, i.e., backlight surface electrodes 114. As S8-3 continues etching into the silicon wafer 101, the diffusion region outside the metallized region is removed, resulting in a diffusion region 115 corresponding to the metallized region 1011.

[0204] Example 2

[0205] The steps of preparing a solar cell according to this embodiment are as follows:

[0206] S1. Alkaline etching is performed on the backlight side of the silicon wafer to achieve the morphology required by the backlight process: the silicon wafer is etched for 200 seconds using 5% NaOH in the presence of a polishing additive at 80°C, and then etched for 60 seconds using 1% NaOH in the presence of a texturing additive. During this process, the wafer is also cleaned for 2 minutes using a mixture of NaOH and hydrogen peroxide at a temperature of 60°C, with the concentration of NaOH in the mixture being 0.5% and the concentration of hydrogen peroxide in the mixture being 2%. The wafer is then cleaned for 2 minutes using 5% HF at 25°C. The final etching depth of the silicon wafer is 3.5 μm, and the reflectivity reaches 38%.

[0207] S2. On the backlight side of an N-type silicon wafer, a first dielectric layer, a first amorphous silicon layer doped with boron, and a first mask layer are sequentially stacked and facing away from the silicon wafer. PECVD is performed at 400°C and 10,000W of ionization power, while introducing 7,000 sccm of N2O for 120 seconds to form a first dielectric layer with a thickness of 2 nm on the backlight side of the silicon wafer. 1,500 sccm of SiH4 and 50 sccm of diborane are then introduced at 300°C for 1,600 seconds to form a first in-situ boron-doped amorphous silicon layer with a thickness of 250 nm. 1,500 sccm of SiH4 and 6,000 sccm of N2O are then introduced for 300 seconds to form a first mask layer of silicon oxide with a thickness of 60 nm.

[0208] S3. Use a mixed solution of hydrofluoric acid and an oxidant to remove the first dielectric layer, the first amorphous silicon layer, and the wrap-around coating of the first mask layer on the light-receiving surface and edges of the silicon wafer: Use a chain cleaning device to etch with a mixture of HNO3 and HF at 25°C for 50 seconds, where the concentration of HNO3 in the mixture is 30% and the concentration of HF in the mixture is 3%, to remove the wrap-around coating of the first dielectric layer, the first amorphous silicon layer, and the first mask layer on the light-receiving surface and edges;

[0209] S4. Texturing the light-receiving surface of the silicon wafer to form a textured surface: Etching the silicon wafer with 1% NaOH at 75°C for 400 seconds in the presence of a texturing additive to a depth of 2.5 μm and a reflectivity of 9.5%. During this process, the wafer is rinsed with a mixture of 0.5% NaOH and 2% hydrogen peroxide at 60°C for 2 minutes; and then rinsed with 3% HCl at 25°C for 2 minutes.

[0210] S5. A second dielectric layer, a second amorphous silicon layer doped with phosphorus, and a second mask layer are sequentially stacked on the light-receiving surface, facing away from the silicon wafer. PECVD is used at 450°C and 10,000W ionization conditions to introduce 7,000 sccm of N2O for 120 seconds to form a second dielectric layer with a thickness of 2 nm on the light-receiving surface of the silicon wafer. 1,500 sccm of SiH4 and 100 sccm of PH3 are introduced for 1,500 seconds to form a second amorphous silicon layer in situ doped with phosphorus with a thickness of 120 nm. 1,000 sccm of SiH4 and 8,000 sccm of N2O are introduced for 50 seconds to form a second mask layer made of silicon oxide with a thickness of 10 nm.

[0211] S6. Crystallize the first amorphous silicon layer and transform it into a first doped polysilicon layer, activating the boron element; crystallize the second amorphous silicon layer and transform it into a second doped polysilicon layer, activating the phosphorus element: anneal at 940°C for 1500 seconds to crystallize the first amorphous silicon layer and the second amorphous silicon layer and transform them into a first doped polysilicon layer and a second doped polysilicon layer, respectively, activate the doped boron and phosphorus, and advance them within the silicon substrate to a certain extent, so that the PN junction square resistance on the backlight side reaches 80Ω / sq;

[0212] S7, coating the second mask layer with an acid-resistant paste: printing the acid-resistant paste on the light-receiving surface with a width of 100 μm, and drying at 180° C. for 30 seconds;

[0213] S8, cleaning and etching: Use a tank cleaning machine to clean and etch, as follows:

[0214] S8-1, removing the second mask layer outside the area covered by the acid-resistant paste and removing a portion of the first mask layer to form a patterned second mask layer, and retaining a portion of the first mask layer: using 3% HF cleaning at 25° C. for 120 seconds to remove the second mask layer and a portion of the first mask layer outside the area covered by the acid-resistant paste on the light-receiving surface, and retaining a portion of the first mask layer;

[0215] S8-2, removing the anti-acid slurry: using a mixture of NaOH and H2O2 at 60°C to remove the anti-acid slurry, wherein the concentration of NaOH and H2O2 in the mixture is 1%;

[0216] S8-3. Removing the second doped polysilicon layer outside the area covered by the patterned second mask layer to form a patterned second doped polysilicon layer: Etching the silicon wafer for 60 seconds using 5% NaOH in the presence of a texturing additive at 80° C., removing only the N-type doped second amorphous silicon layer outside the area covered by the patterned second mask layer, without etching the silicon wafer beneath the second dielectric layer.

[0217] S8-4. At 60°C, use a mixture of NaOH and hydrogen peroxide to clean the battery surface for 2 minutes to remove organic residues. The concentration of NaOH is 0.5% and the concentration of hydrogen peroxide is 2%.

[0218] S8-5, removing the second dielectric layer outside the area covered by the patterned second doped polysilicon layer to form a patterned second dielectric layer; removing the first mask layer and the patterned second mask layer: cleaning with a 20% HF solution at room temperature for 5 minutes to remove the remaining first mask layer, the patterned second mask layer, and the second dielectric layer outside the area covered by the patterned N-type doped second amorphous silicon layer, to obtain a patterned second dielectric layer;

[0219] S8-6, drying at 90°C for 10 minutes to finally form a patterned n-poly area on the light-receiving surface;

[0220] S9. Form a light-receiving surface functional film and a backlight surface functional film on the light-receiving surface and the backlight surface, respectively: use PECVD equipment, introduce N2O, and ionize for 300 seconds to prepare a silicon oxide passivation layer; then introduce SiH4 and NH3 to prepare 80nm silicon nitride as a passivation and anti-reflection film on the outer layer of the light-receiving surface and the backlight surface; the aluminum oxide film on the bottom layer of the light-receiving surface and the silicon nitride film on the outer layer of the light-receiving surface are combined to form the light-receiving surface functional film, and the silicon nitride film on the backlight surface is the backlight surface functional film;

[0221] S10. Fabricate a light-receiving electrode on the light-receiving surface corresponding to the metallized area, and a backlight electrode on the backlight surface: Use a mixture paste primarily composed of silver to screen-print and metallize the front and backlight surfaces of the cell. Silver lines 25 microns wide and 1.5 mm apart are formed on the light-receiving surface, serving as the light-receiving electrode; silver lines 35 microns wide and 1.0 mm apart are formed on the backlight surface, serving as the backlight electrode. The pattern of the metallized area on the light-receiving surface corresponds to the patterned n-poly area. The resulting solar cell is shown in Figure 15. Because the silicon wafer below the second dielectric layer is not etched in S8-3, the diffusion region 115 covers the entire light-receiving surface of the silicon wafer.

[0222] Comparative Example 1

[0223] The preparation method of the solar cell of this comparative example comprises:

[0224] Texturing: Use alkali and texturing additives at 80°C to etch the silicon wafer to a depth of 3μm and a reflectivity of 9.5%;

[0225] Boron diffusion on the light-receiving surface: Boron diffusion is carried out using high-temperature tube equipment at 1060°C, with N2, O2, and BCl3 introduced. The square resistance is 110Ω / sq and the junction depth is 1.0 micron.

[0226] Backlight surface alkali polishing: First, use a chain HF device to remove the backlight surface BSG, and then use a tank wet process device to polish the silicon wafer with 70°C alkali and polishing additives. The etching depth is 0.4 microns, and the reflectivity of the backlight surface is increased to 45%;

[0227] Backlight poly; use PECVD equipment to prepare a 1.5nm dielectric layer and a 120nm in-situ n-poly layer;

[0228] Annealing: Annealing at 910°C to crystallize the backlight side n-poly and activate the phosphorus;

[0229] Remove the light-receiving surface plating and clean it: First use the chain HF equipment to remove the PSG and part of the BSG on the light-receiving surface, then use the tank wet process equipment to perform alkaline etching to remove the plating, and then perform alkaline and acid washing to remove the surface mask and dirt, etc.

[0230] Prepare the front and back surface coating and anti-reflection film: 5nm aluminum oxide + 80nm silicon nitride is used as the passivation and anti-reflection layer on the light-receiving side, and 90nm silicon nitride film is coated on the back surface;

[0231] Screen printing and metallization; the light-receiving side is metallized with silver-aluminum paste, and the backlight side is metallized with back paste.

[0232] The passivation performance of Examples 1, 2 and Comparative Example 1 was tested using a Sinton minority carrier lifetime tester, and the results are shown in Table 1.

[0233] Table 1: Sinton minority carrier lifetime tester test results

[0234] The electrical properties of the solar cells prepared in Examples 1 and 2 and Comparative Example 1 were tested, and the results are shown in Table 2.

[0235] Table 2: Solar cell electrical performance test results

[0236] As can be seen from Table 1, the minority carrier lifetime, open circuit voltage and fill factor of the solar cells of Examples 1 and 2 are improved compared with those of Comparative Example 1, and the reverse saturation current density is lower. The reasons are as follows: Comparative Example 1 is a single-sided passivated contact, that is, the backlight surface poly is set only on the backlight surface for passivation contact; the solar cell of Example 1 is a double-sided passivated contact, the light-receiving surface is passivated in the metal area by the second doped polysilicon layer, and the backlight surface is passivated in the metal area and non-metallic area by the first doped polysilicon layer produced by the PECVD method. The polysilicon layer is used on both sides of the solar cell for metal area passivation, which improves the minority carrier lifetime and theoretical opening voltage; the second dielectric layer located on the light-receiving surface and the first dielectric layer located on the backlight surface can both block the passage of minority carriers while allowing majority carriers to pass through easily and unimpeded, thereby reducing recombination; carriers only need to be transported in one-dimensional direction without additional lateral transmission, so a higher theoretical fill factor can be obtained.

[0237] As can be seen from Table 2, the solar cells of Examples 1 and 2 have obvious conversion efficiency and open circuit voltage advantages over the comparative example. The reason is that the solar cells of Examples 1 and 2 only set the second dielectric layer and the second doped polysilicon layer in the metallized area as the passivation contact structure of the light-receiving surface electrode to avoid the second doped polysilicon layer covering the entire light-receiving surface of the solar cell and affecting the solar cell's absorption of light. In addition, the PN junction of the solar cells of Examples 1 and 2 is located on its backlight side. In order to reduce the lateral resistance of the emitter, the number of grid lines on the backlight side can be increased. Therefore, there is no high requirement for the number of grid lines on the light-receiving side, which is more conducive to the distribution design of the grid lines on the light-receiving surface and the backlight side. By reducing the number of grid lines on the light-receiving surface, the amount of silver paste (grid line manufacturing material) can be reduced, thereby reducing costs, and avoiding the effect of adding grid lines when the PN junction is set on the light-receiving surface of the battery on the absorption of light. Through the above improvements, the solar cell absorbs light better and has higher conversion efficiency.

[0238] Compared with Comparative Example 1 and the method for preparing a selective emitter passivation contact cell, the number of devices used in Examples 1 and 2 is shown in Table 3.

[0239] Table 3: Number of equipment used for different preparation methods

[0240] As can be seen from Table 3, compared with the process flow of the passivated contact cell in Comparative Example 1, the equipment required for the embodiment of the present application has not increased, and there are also 12 equipment processes. Compared with the preparation method of the selective emitter passivated contact cell, the embodiment of the present application has two fewer equipment processes and can replace the boron diffusion process to achieve the purpose of simplifying the process. From the perspective of solar cell conversion efficiency gain, the solar cell prepared in the embodiment of the present application has a gain of more than 0.5%, and the theoretical efficiency is higher. Therefore, the preparation method of the embodiment of the present application has multiple advantages of improving efficiency and reducing costs.

[0241] The above is a detailed introduction to a method for preparing a solar cell, a solar cell and a photovoltaic module disclosed in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method for preparing a solar cell, a solar cell and a photovoltaic module and their core ideas of the present application. At the same time, for general technicians in this field, according to the ideas of the present application, there will be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present application.

[0242] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0243] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and such modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A method for preparing a solar cell, comprising: On a backlight surface of a silicon wafer of a first conductivity type, a first dielectric layer, a first amorphous silicon layer doped with an element of a second conductivity type opposite to the first conductivity type, and a first mask layer are sequentially stacked away from the silicon wafer; On the light-receiving surface of the silicon wafer, a second dielectric layer, a second amorphous silicon layer doped with an element having the first conductivity type, and a second mask layer are sequentially stacked and separated from the silicon wafer; crystallizing the first amorphous silicon layer to transform it into a first doped polysilicon layer, and activating the doping element of the second conductivity type; crystallizing the second amorphous silicon layer to transform it into a second doped polysilicon layer, and activating the doping element of the first conductivity type; manufacturing a patterned second mask layer; removing the second doped polysilicon layer outside the coverage area of the patterned second mask layer to form a patterned second doped polysilicon layer; removing the second dielectric layer outside the coverage area of the patterned second doped polysilicon layer to form a patterned second dielectric layer; as well as, The first mask layer and the patterned second mask layer are removed.

2. The method for preparing a solar cell according to claim 1, wherein: The step of making the patterned second mask layer includes: coating an acid-resistant slurry on the second mask layer; removing the second mask layer outside the area covered by the acid-resistant paste and removing a portion of the thickness of the first mask layer to form a patterned second mask layer and retaining a portion of the thickness of the first mask layer; and The acid-resistant slurry is removed.

3. The method for preparing a solar cell according to claim 2, wherein: The step of removing the second mask layer outside the area covered by the acid-resistant slurry and removing a portion of the thickness of the first mask layer to form a patterned second mask layer and retaining a portion of the thickness of the first mask layer includes: The surface of the silicon wafer is cleaned simultaneously using hydrofluoric acid with a mass percentage concentration of x% and the cleaning time t1 is controlled to satisfy: t2≤t1<t3, t2 is the time required for the second mask layer to be completely removed in the hydrofluoric acid with a mass percentage concentration of x%, and t3 is the time required for the first mask layer to be completely removed in the hydrofluoric acid with a mass percentage concentration of x%; wherein x is approximately 0.1 to 10.

4. The method for preparing a solar cell according to claim 3, wherein: The thickness of the first mask layer is greater than the thickness of the second mask layer.

5. The method for preparing a solar cell according to claim 3 or 4, wherein: In a hydrofluoric acid solution of the same concentration, the etching rate of the first mask layer is lower than the etching rate of the second mask layer.

6. The method for preparing a solar cell according to any one of claims 1 to 5, wherein: The step of making the patterned second mask layer includes: A portion of the second mask layer is removed using a laser to obtain a patterned second mask layer.

7. The method for preparing a solar cell according to any one of claims 1 to 6, wherein: The step of removing the second doped polysilicon layer outside the coverage area of the patterned second mask layer to form the patterned second doped polysilicon layer includes: Using alkali to remove the second doped polysilicon layer outside the coverage area of the patterned second mask layer, and continuing to etch the second dielectric layer at a reduced etching rate; The step of removing the second dielectric layer outside the coverage area of the patterned second doped polysilicon layer to form a patterned second dielectric layer includes: Use alkali to perform etching again with the assistance of texturing additives to remove the second dielectric layer outside the coverage area of the patterned second mask layer and the patterned second doped polysilicon layer to form a patterned second dielectric layer, and continue etching into the silicon wafer to texturize the light-receiving surface again.

8. The method for preparing a solar cell according to any one of claims 1 to 7, wherein: The step of removing the second doped polysilicon layer outside the coverage area of the patterned second mask layer to form the patterned second doped polysilicon layer includes: removing the second doped polysilicon layer outside the coverage area of the patterned second mask layer by using alkali, and stopping etching when etching reaches the second dielectric layer; The step of removing the second dielectric layer outside the coverage area of the patterned second doped polysilicon layer to form a patterned second dielectric layer includes: The second dielectric layer outside the covered area of the patterned second doped polysilicon layer is removed by using hydrofluoric acid cleaning.

9. The method for preparing a solar cell according to any one of claims 1 to 8, wherein: Before the step of preparing, on the backlight side of the silicon wafer of the first conductivity type, a first dielectric layer, a first amorphous silicon layer doped with an element of a second conductivity type opposite to the first conductivity type, and a first mask layer stacked in sequence, facing away from the silicon wafer, the method for preparing a solar cell further comprises: The backlight surface of the silicon wafer is alkali-etched to make the backlight surface reach the morphology required by the backlight surface process.

10. The method for preparing a solar cell according to any one of claims 1 to 9, wherein: The step of preparing, on the backlight side of the silicon wafer of the first conductivity type, a first dielectric layer, a first amorphous silicon layer doped with an element of a second conductivity type opposite to the first conductivity type, and a first mask layer stacked in sequence away from the silicon wafer, comprises: The first dielectric layer, the first amorphous silicon layer doped with the second conductive type doping element, and the first mask layer are sequentially stacked away from the silicon wafer and formed on the backlight surface by PECVD.

11. The method for preparing a solar cell according to any one of claims 1 to 10, wherein: Before the step of preparing, on the light-receiving surface of the silicon wafer, a second dielectric layer, a second amorphous silicon layer doped with a doping element of the first conductivity type, and a second mask layer stacked in sequence away from the silicon wafer, the method for preparing a solar cell further comprises: Using a mixed solution of hydrofluoric acid and an oxidant, removing the first dielectric layer, the first amorphous silicon layer, and the wrap-around coating of the first mask layer on the light-receiving surface and edge of the silicon wafer; The light-receiving surface of the silicon wafer is textured to form a textured surface on the light-receiving surface.

12. The method for preparing a solar cell according to claim 11, wherein: The oxidant includes at least one of nitric acid, hydrogen peroxide and ozone.

13. The method for preparing a solar cell according to any one of claims 1 to 12, wherein: The step of preparing a second dielectric layer, a second amorphous silicon layer doped with a doping element of the first conductivity type, and a second mask layer stacked in sequence away from the silicon wafer on the light-receiving surface of the silicon wafer comprises: The second dielectric layer, the second amorphous silicon layer doped with the first conductive type doping element, and the second mask layer are sequentially stacked away from the silicon wafer and formed on the light-receiving surface by using PECVD.

14. The method for preparing a solar cell according to any one of claims 1 to 13, wherein: The steps of crystallizing the first amorphous silicon layer into a first doped polysilicon layer, activating the second conductive type doping element, and forming a PN junction on the backlight surface of the silicon wafer are carried out simultaneously with the steps of crystallizing the second amorphous silicon layer into a second doped polysilicon layer and activating the first conductive type doping element.

15. The method for preparing a solar cell according to any one of claims 2 to 5, wherein: The step of coating the acid-resistant slurry on the second mask layer includes: The acid-resistant paste is coated on the second mask layer by printing; wherein the width of the acid-resistant paste is about 40 μm to 200 μm.

16. The method for preparing a solar cell according to any one of claims 2 to 5 and 15, wherein: The steps of removing the second mask layer outside the area covered by the acid-resistant slurry and removing a portion of the thickness of the first mask layer to form a patterned second mask layer, and retaining a portion of the thickness of the first mask layer, the step of removing the acid-resistant slurry, the step of removing the second doped polysilicon layer outside the area covered by the patterned second mask layer to form a patterned second doped polysilicon layer, and the steps of removing the first mask layer and patterning the second mask layer are performed at one time in the tank cleaning machine, and between any two steps, the following further steps are included: The silicon wafer is cleaned with water.

17. The method for preparing a solar cell according to any one of claims 2 to 5 and 15 to 16, wherein: The step of removing the acid-resistant slurry comprises: The acid-resistant slurry is removed using a mixture of alkali and hydrogen peroxide.

18. The method for preparing a solar cell according to any one of claims 1 to 17, wherein: After the step of removing the first mask layer and the patterned second mask layer, the method for preparing a solar cell further includes: A light-receiving surface functional film and a backlight surface functional film are formed on the light-receiving surface and the backlight surface, respectively; wherein the light-receiving surface functional film covers the side of the second doped polysilicon layer facing away from the silicon wafer and the exposed area of the light-receiving surface not covered by the second doped polysilicon layer, and the backlight surface functional film covers the side of the first doped polysilicon layer facing away from the silicon wafer; A light-receiving surface electrode corresponding to the metallized area is made on the light-receiving surface, and a backlight surface electrode is made on the backlight surface; wherein, the light-receiving surface electrode penetrates the light-receiving surface functional film and makes ohmic contact with the patterned second doped polysilicon layer, and the backlight surface electrode penetrates the backlight surface functional film and makes ohmic contact with the first doped polysilicon layer.

19. The method for preparing a solar cell according to any one of claims 1 to 18, wherein: The first dielectric layer includes a silicon oxide layer.

20. The method for preparing a solar cell according to any one of claims 1 to 19, wherein: The thickness of the first dielectric layer is approximately 0.1 nm to 5 nm.

21. The method for preparing a solar cell according to any one of claims 1 to 20, wherein: The second dielectric layer includes a silicon oxide layer.

22. The method for preparing a solar cell according to any one of claims 1 to 21, wherein: The thickness of the second dielectric layer is approximately 0.1 nm to 5 nm.

23. The method for preparing a solar cell according to any one of claims 1 to 22, wherein: The thickness of the first amorphous silicon layer is about 50 nm to 350 nm.

24. The method for preparing a solar cell according to any one of claims 1 to 23, wherein: The thickness of the second amorphous silicon layer is about 50 nm to 200 nm.

25. The method for preparing a solar cell according to any one of claims 1 to 24, wherein: The first mask layer includes at least one of a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer.

26. The method for preparing a solar cell according to any one of claims 1 to 25, wherein: The thickness of the first mask layer is approximately 20 nm to 80 nm.

27. The method for preparing a solar cell according to any one of claims 1 to 26, wherein: The second mask layer includes at least one of a silicon oxide layer and a silicon oxynitride layer.

28. The method for preparing a solar cell according to any one of claims 1 to 27, wherein: The thickness of the second mask layer is about 5 nm to 50 nm.

29. A solar cell prepared by the method for preparing a solar cell according to any one of claims 1 to 28.

30. A photovoltaic module comprising the solar cell according to claim 29.

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