Semiconductor device and manufacturing method therefor, chip, electronic device, and vehicle

Abstract

Provided in the present application are a semiconductor device and a manufacturing method therefor, a chip, an electronic device, and a vehicle. The semiconductor device comprises: a substrate; a dielectric layer, which is arranged on the substrate; a first passivation layer, which is arranged on the side of the dielectric layer away from the substrate; and a first conductive layer, wherein the first conductive layer and the first passivation layer are arranged on the same side of the substrate, and part of the first conductive layer is stacked on the side of the dielectric layer away from the substrate. In a first direction, there is a first distance between the first conductive layer and the first passivation layer, the first direction being perpendicular to the direction of thickness of the semiconductor device. The present application can reduce cracking in a semiconductor device.

Description

Semiconductor device and manufacturing method thereof, chip, electronic equipment and vehicle Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a chip, an electronic device and a vehicle. Background Art

[0002] Semiconductor devices such as transistors are usually provided in power factor correction (PFC) rectifiers, inverters, on-board electric drive microcontroller units (MCUs) and on-board battery chargers (OBCs). The transistor may include a substrate and a conductive layer and a passivation layer provided on the substrate. After the transistor is packaged, reliability tests such as temperature cycling and temperature shock are required. During this test, shear stress is generated due to the mismatch in the coefficient of thermal expansion (CTE) between the substrate, the conductive layer and the passivation layer. Since the material rigidity of the passivation layer is relatively large, the shear stress will cause cracks to form inside the passivation layer, thereby causing the passivation layer to crack, and then causing the transistor to fail. Summary of the Invention

[0003] In order to solve the above technical problems, the present application provides a semiconductor device and a manufacturing method thereof, a chip, an electronic device and a vehicle, which can reduce the cracking of the semiconductor device.

[0004] In a first aspect of the present application, a semiconductor device is provided, which may be a transistor. The semiconductor device includes: a substrate, a dielectric layer, a first passivation layer, and a first conductive layer. The dielectric layer is provided on the substrate, and the first passivation layer is provided on the side of the dielectric layer facing away from the substrate. The first conductive layer and the first passivation layer are provided on the same side of the substrate, and a portion of the first conductive layer is stacked on the side of the dielectric layer facing away from the substrate. Along a first direction, there is a first spacing between the first conductive layer and the first passivation layer, the first direction is perpendicular to the thickness direction of the semiconductor device, and the first direction may be the length direction or the width direction of the semiconductor device. That is, along the length direction or the width direction of the semiconductor device, there is a first spacing between the first conductive layer and the first passivation layer. In this way, when the semiconductor device is tested such as temperature cycling and temperature shock, the substrate, the first passivation layer and the first conductive layer may produce different deformation amounts due to different CTEs. Since there is a first distance between the first conductive layer and the first passivation layer, the first passivation layer and the first conductive layer can be deformed to within the first distance after being deformed due to heat. Compared with the direct contact between the first conductive layer and the first passivation layer and the first passivation layer covering the top surface and side surfaces of the first conductive layer, which causes the first passivation layer to generate shear stress at the position where it contacts the corner of the first conductive layer, the technical solution of the present application can reduce the generation of shear stress, thereby reducing the cracking of the first passivation layer and the failure of the semiconductor device, thereby improving the reliability of the semiconductor device.

[0005] In some embodiments, the semiconductor device further includes a second passivation layer, which covers the side surface of the first conductive layer, and a second distance is provided between the second passivation layer and the first passivation layer along the first direction. In the process of manufacturing the semiconductor device, a dielectric layer and a first conductive layer can be first manufactured on the substrate, and then a passivation layer can be manufactured on the first conductive layer and the dielectric layer by deposition. The passivation layer located on the top surface of the first conductive layer and the passivation layer within a certain distance from the side surface of the first conductive layer are etched away to form the first passivation layer. Since the side surface of the first conductive layer is an inclined surface, the passivation layer covering the side surface of the first conductive layer is larger in the thickness direction. Within the same time as the passivation layer covering the top surface of the first conductive layer can be etched, the passivation layer covering the side surface of the first conductive layer cannot be completely etched away. The remaining passivation layer remaining on the side surface of the first conductive layer after etching is the second passivation layer. In this way, the etching time can be shortened and the cost can be reduced. Since the second passivation layer only covers the side surfaces of the first conductive layer and does not simultaneously cover the top surface, side surfaces and corners therebetween of the first conductive layer, shear stress generated in the second passivation layer can be reduced.

[0006] Based on this, the semiconductor device also includes a protective layer, part of which covers the first conductive layer, the second passivation layer and the first passivation layer, and part of the protective layer is located within the fourth distance. It can be understood that in the process of manufacturing the semiconductor device, after the protective layer is completed, when the semiconductor device needs to be packaged, that is, it is necessary to make a plastic packaging material on the outside of the protective layer. In order to alleviate the extrusion caused by the plastic seal during the packaging process, the material of the protective layer can generally be a material with greater flexibility and elasticity. When the semiconductor device is completed and reliability testing is performed, since part of the protective layer is located within the fourth distance between the second passivation layer and the first passivation layer, the protective layer will be subjected to shear stress. However, since the protective layer has greater flexibility and elasticity, it can buffer the shear stress, thereby reducing the cracking of the first passivation layer and the failure of the semiconductor device.

[0007] The semiconductor device also includes a second conductive layer, a first portion of which is located between the first conductive layer and the substrate, and a second portion of which is located between the first conductive layer and the dielectric layer. That is, the first conductive layer is located on the side of the second conductive layer facing away from the substrate and can serve as one of the electrodes of the semiconductor device. The thickness of the second conductive layer is less than that of the first conductive layer. Therefore, the first conductive layer can be referred to as a thick metal layer, and the second conductive layer can be referred to as a thin metal layer. The overlap between the second conductive layer and the dielectric layer is greater than the overlap between the first conductive layer and the dielectric layer. This results in a larger overlap between the second conductive layer and the dielectric layer, that is, a larger overlap between the thin metal layer and the dielectric layer. This effectively prevents moisture from invading the substrate through the gap between the second conductive layer and the dielectric layer, thus providing the semiconductor device with improved moisture resistance. Furthermore, the overlap between the first conductive layer and the dielectric layer is smaller, and because the first passivation layer is also disposed on the dielectric layer, the first spacing between the first conductive layer and the first passivation layer is larger, that is, a larger first spacing between the thick metal layer and the first passivation layer, thereby effectively reducing cracking in the first passivation layer. That is to say, this technical solution can reduce the cracking of the first passivation layer while also having better moisture resistance.

[0008] Regarding the positional relationship between the second conductive layer and the first passivation layer, in one possible embodiment, a third spacing is provided between the second conductive layer and the first passivation layer along the first direction, and the third spacing is smaller than the first spacing. In this way, the surface of the second conductive layer facing the first passivation layer is closer to the first passivation layer than the first conductive layer, thereby increasing the overlap area between the second conductive layer and the dielectric layer, thereby improving the moisture resistance of the semiconductor device.

[0009] In another possible embodiment, the second conductive layer contacts the first passivation layer along the first direction. In this way, the first passivation layer and the second conductive layer can cover more area on the top surface of the substrate. Therefore, the second conductive layer, the first passivation layer, and the dielectric layer can work together to improve moisture resistance.

[0010] In another possible embodiment, the third portion of the second conductive layer is located between the first passivation layer and the dielectric layer. Thus, an overlapping region exists between the second conductive layer and the first passivation layer. Thus, the first passivation layer and the second conductive layer can cover a larger area on the top surface of the substrate. Consequently, the second conductive layer, the first passivation layer, and the dielectric layer can work together to improve moisture resistance.

[0011] Furthermore, the first passivation layer includes at least two stacked sub-passivation layers, and the third portion of the second conductive layer is stacked between the at least one sub-passivation layer and the dielectric layer. Thus, the second conductive layer and the at least one sub-passivation layer have an overlapping region, thereby allowing the first passivation layer and the second conductive layer to cover a larger area on the top surface of the substrate. Consequently, the second conductive layer, the first passivation layer, and the dielectric layer work together to improve moisture resistance.

[0012] Furthermore, the thickness of the first passivation layer is greater than that of the second conductive layer and less than that of the first conductive layer. The overlap between the second conductive layer and the dielectric layer is relatively large, that is, the overlap between the thin metal layer and the dielectric layer is relatively large. Because the second conductive layer is thinner than the first passivation layer, the cross-section of contact between the two is small, thus preventing significant shear stress and preventing cracking of the first passivation layer at the point of contact with the second conductive layer.

[0013] In some embodiments, the semiconductor device further includes a doped region, a portion of the doped region being located between the substrate and the second conductive layer, a portion of the doped region being located between the substrate and the dielectric layer, and a projection of the second conductive layer on the first surface being located within the projection of the doped region on the first surface. Furthermore, because the overlap between the second conductive layer and the dielectric layer is greater than the overlap between the first conductive layer and the dielectric layer, the projection of the first conductive layer on the first surface is also located within the projection of the doped region on the first surface. It is understood that the semiconductor device further includes a third conductive layer, the third conductive layer being located on a side of the substrate facing away from the first conductive layer, and an electric field distribution can be generated between the third conductive layer and the first and second conductive layers. When the projections of the first and second conductive layers on the first surface are both located within the projection of the doped region on the first surface, the electric field distribution is not affected, thereby improving the withstand voltage stability of the semiconductor device.

[0014] To further improve the semiconductor device's moisture resistance, the semiconductor device also includes a third passivation layer. The third passivation layer covers at least the portion of the first conductive layer's surface facing away from the substrate, the second passivation layer, the portion of the second conductive layer's surface facing away from the substrate, the portion of the first passivation layer's surface facing the first conductive layer, and the portion of the first passivation layer's surface facing away from the substrate. The thickness of the third passivation layer is less than that of the second conductive layer. Thus, the third passivation layer provides moisture resistance. Furthermore, because the thickness of the third passivation layer is less than that of the second conductive layer (i.e., less than that of the thin metal layer), the third passivation layer possesses a certain degree of flexibility, thereby preventing cracking of the third passivation layer due to thermal deformation.

[0015] In some embodiments, the dielectric layer has a second surface facing the substrate, a third surface facing away from the substrate, and an inclined surface connected between the second and third surfaces and facing the second conductive layer, with a portion of the second conductive layer disposed on the inclined surface. This increases the contact area between the dielectric layer and the second conductive layer, and provides a smooth transition from the portion of the second conductive layer in contact with the doped region to the portion in contact with the dielectric layer, thereby preventing cracking at the inclined surface where the second conductive layer contacts the dielectric layer.

[0016] Based on this, the dielectric layer has at least two inclined surfaces, a partial projection of the first conductive layer on the dielectric layer is located between the at least two inclined surfaces, and a projection of the end surface of the first conductive layer facing the first passivation layer on the dielectric layer is located on the inclined surface. The first conductive layer can serve as one of the electrodes of the semiconductor device, and the third conductive layer can serve as the other electrode of the semiconductor device. The projection of the end surface of the first conductive layer facing the first passivation layer on the dielectric layer is located on the inclined surface, so that the size of the first conductive layer along the length direction of the semiconductor device is moderate. If the end surface of the first conductive layer facing the first passivation layer is located between the two inclined surfaces, the size of the first conductive layer along the length direction of the semiconductor device is too small, which may make it impossible to realize the basic function of the first conductive layer. If the projection of the end surface of the first conductive layer facing the first passivation layer on the dielectric layer is located outside the inclined surface, the size of the first conductive layer along the length direction of the semiconductor device is too large, and when the first conductive layer is manufactured, the top of the first conductive layer may form a curved surface. If the projection of the end face of the first conductive layer facing the first passivation layer on the dielectric layer is located on an inclined surface, the top surface of the first conductive layer tends to be flat, thereby reducing the shear stress occurring during the temperature test of the semiconductor device, thereby reducing the large deformation and stress generated in various parts of the first conductive layer, and reducing the stress from being transferred to the dielectric layer, the second conductive layer, the doped region, etc., thereby causing failure of the semiconductor device.

[0017] In a second aspect of the present application, a chip is provided, comprising a passive device and a semiconductor device according to any one of the above embodiments, wherein the passive device is electrically connected to the semiconductor device. The chip can achieve all the effects of the semiconductor device.

[0018] In a third aspect of the present application, an electronic device is provided, comprising a circuit board and the aforementioned chip, wherein the circuit board is electrically connected to the chip. The electronic device can achieve all the effects of the chip.

[0019] In a fourth aspect of the present application, a vehicle is provided, comprising a vehicle body and the aforementioned electronic device, wherein the electronic device is fixed inside the vehicle body. The vehicle can achieve all the effects of the electronic device.

[0020] In a fifth aspect, the present application further provides a method for fabricating a semiconductor device, the method comprising: providing a substrate; fabricating a dielectric layer on the substrate; fabricating a first conductive layer; and fabricating a first passivation layer on the dielectric layer, wherein the first conductive layer and the first passivation layer are disposed on the same side of the substrate, a portion of the first conductive layer is stacked on a side of the dielectric layer facing away from the substrate, and a first spacing is provided between the first conductive layer and the first passivation layer along a first direction, the first direction being perpendicular to the thickness direction of the semiconductor device and being the length direction or the width direction of the semiconductor device. In other words, the first conductive layer and the first passivation layer have a first spacing along the length direction or the width direction of the semiconductor device. In this way, when the semiconductor device is tested such as temperature cycling and temperature shock, the substrate, the first passivation layer and the first conductive layer may produce different deformation amounts due to different CTEs. Since there is a first distance between the first conductive layer and the first passivation layer, the first passivation layer and the first conductive layer can be deformed to within the first distance after being deformed due to heat. Compared with the direct contact between the first conductive layer and the first passivation layer and the first passivation layer covering the top surface and side surfaces of the first conductive layer, which causes the first passivation layer to generate shear stress at the position where it contacts the corner of the first conductive layer, the technical solution of the present application can reduce the generation of shear stress, thereby reducing the cracking of the first passivation layer and the failure of the semiconductor device, thereby improving the reliability of the semiconductor device.

[0021] Based on this, after the step of forming a dielectric layer on the substrate, the manufacturing method further includes: forming a second conductive layer on the substrate and the dielectric layer; and the step of forming the first conductive layer includes: forming the first conductive layer on the second conductive layer, wherein the thickness of the second conductive layer is less than the thickness of the first conductive layer, and the overlap area between the second conductive layer and the dielectric layer is greater than the overlap area between the first conductive layer and the dielectric layer. In other words, the first conductive layer is located on the side of the second conductive layer facing away from the substrate, and the first conductive layer can serve as one of the electrodes of the semiconductor device. The thickness of the second conductive layer is less than the thickness of the first conductive layer. Therefore, the first conductive layer can also be called a thick metal layer, and the second conductive layer can also be called a thin metal layer. The overlap area between the second conductive layer and the dielectric layer is greater than the overlap area between the first conductive layer and the dielectric layer. In this way, the overlap area between the second conductive layer and the dielectric layer is sufficiently large, thereby better preventing moisture from invading the substrate through the gap between the second conductive layer and the dielectric layer. In other words, the semiconductor device has better moisture resistance. Furthermore, the overlap between the first conductive layer and the dielectric layer is relatively small, and because the first passivation layer is also disposed on the dielectric layer, the first spacing between the first conductive layer and the first passivation layer is relatively large, thereby further reducing cracking in the first passivation layer. In other words, this technical solution can reduce cracking in the first passivation layer while also providing improved moisture resistance.

[0022] Furthermore, after forming the first conductive layer on the second conductive layer, the method further includes forming a third passivation layer, wherein the third passivation layer covers at least a portion of the surface of the first conductive layer facing away from the substrate, a portion of the surface of the first conductive layer facing the first passivation layer, a portion of the surface of the second conductive layer facing away from the substrate, a portion of the surface of the first passivation layer facing the first conductive layer, and a portion of the surface of the first passivation layer facing away from the substrate, and the thickness of the third passivation layer is less than that of the second conductive layer. In this way, the third passivation layer can provide moisture resistance. Moreover, because the thickness of the third passivation layer is less than that of the second conductive layer, that is, the thickness of the third passivation layer is less than that of the thin metal layer, the third passivation layer has a certain degree of flexibility, thereby preventing the third passivation layer from cracking due to thermal deformation. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0024] FIG1 is a schematic structural diagram of a semiconductor device in the related art;

[0025] FIG2 a is a schematic structural diagram of a semiconductor device according to a first embodiment of the present application;

[0026] FIG2 b is a schematic structural diagram of a semiconductor device in a second embodiment of the present application;

[0027] FIG3 is a schematic cross-sectional view of FIG2a along AA;

[0028] FIG4 is a schematic structural diagram of a semiconductor device according to a third embodiment of the present application;

[0029] FIG5 is a schematic structural diagram of a semiconductor device according to a fourth embodiment of the present application;

[0030] FIG6 is a schematic structural diagram of a semiconductor device according to a fifth embodiment of the present application;

[0031] FIG7 is a schematic structural diagram of a semiconductor device according to a sixth embodiment of the present application;

[0032] FIG8 is a schematic structural diagram of a semiconductor device according to a seventh embodiment of the present application;

[0033] FIG9 a is a schematic structural diagram of a semiconductor device according to an eighth embodiment of the present application;

[0034] FIG9 b is a schematic structural diagram of a semiconductor device according to a ninth embodiment of the present application;

[0035] FIG9 c is a schematic structural diagram of a semiconductor device according to a tenth embodiment of the present application;

[0036] FIG10 is a schematic structural diagram of a semiconductor device according to an eleventh embodiment of the present application;

[0037] FIG11 is a schematic structural diagram of a semiconductor device according to a twelfth embodiment of the present application;

[0038] FIG12 is a schematic structural diagram of a semiconductor device according to a thirteenth embodiment of the present application;

[0039] FIG13 is a schematic structural diagram of a semiconductor device according to a fourteenth embodiment of the present application;

[0040] FIG14 is a schematic structural diagram of a semiconductor device according to a fifteenth embodiment of the present application;

[0041] FIG15 is a schematic flow chart of a method for manufacturing the semiconductor device shown in FIG2a;

[0042] FIG16 is a schematic diagram of a specific process of the manufacturing method shown in FIG15;

[0043] FIG17 is a schematic flow chart of a method for manufacturing the semiconductor device shown in FIG10 ;

[0044] FIG18 is a schematic diagram showing the specific process of some steps of the manufacturing method shown in FIG17 .

[0045] Icon: 100-semiconductor device; 102-passivation layer; 10-substrate; 11-first surface; 20-epitaxial layer; 30-doped region; 40-dielectric layer; 41-second surface; 42-third surface; 43-inclined surface; 44-through hole; 50-first passivation layer; 51-sub-passivation layer; 60-first conductive layer; 70-second conductive layer; 80-third conductive layer; 90-third passivation layer; 110-protective layer; 111-grooving; 120-oxide layer; 130-polysilicon layer; 140-second passivation layer. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0047] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one (item)" refers to one or more, and "plurality" refers to two or more. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0048] In the description and claims of the embodiments of this application, the terms "first" and "second" are used to distinguish different objects, rather than to describe a specific order of objects. For example, the terms "first target object" and "second target object" are used to distinguish different objects, rather than to describe a specific order of objects.

[0049] "Connected", "connected" and similar words are used to express the intercommunication or interaction between different components, which may include direct connection or indirect connection through other components. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, including a series of steps or units. The method, system, product or device is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. "Up", "down", "left", "right" and the like are only used with respect to the orientation of the components in the drawings. These directional terms are relative concepts. They are used for description and clarification relative to the description, which may change accordingly according to the change in the orientation of the components in the drawings.

[0050] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0051] In the description of the embodiments of this application, unless otherwise specified, "multiple" means two or more. For example, "multiple processing units" means two or more processing units; "multiple systems" means two or more systems.

[0052] The vehicle is usually provided with electronic equipment and a vehicle body, and the electronic equipment is fixed inside the vehicle body. The electronic equipment may be, for example, a PFC rectifier, an inverter, an on-board electric drive MCU and an OBC. The electronic equipment usually includes a chip and a circuit board, and the chip is electrically connected to the circuit board. The chip is provided with semiconductor devices and passive devices, and the semiconductor devices are electrically connected to the passive devices. The semiconductor device may be, for example, a transistor, and the transistor may specifically be a diode, a triode, etc. For example, the diode may specifically be a Schottky barrier diode (Schottky Barrier Diode, SBD), and the triode may specifically be a metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor, MOSFET). Passive devices may be, for example, capacitors, resistors, etc.

[0053] The structure of the semiconductor device may be as shown in FIG1 . The semiconductor device 100 may include a substrate 10, an epitaxial layer 20, a dielectric layer 40, a first conductive layer 60, a second conductive layer 70, and a passivation layer 102. The material of the substrate 10 may include SiC, which is a wide-bandgap semiconductor material. Compared to Si, SiC has high critical breakdown field strength, high thermal conductivity, and high intrinsic operating temperature. Therefore, the semiconductor device 100 has the advantages of high operating junction temperature and low switching loss, which is conducive to achieving high-frequency and lightweight electronic devices.

[0054] As shown in FIG1 , an epitaxial layer 20 is disposed on a substrate 10, and a dielectric layer 40 is disposed on the epitaxial layer 20. A portion of a first conductive layer 60 is disposed on the epitaxial layer 20, and another portion of the first conductive layer 60 is stacked on the dielectric layer 40. A second conductive layer 70 is disposed on a side of the substrate 10 facing away from the first conductive layer 60. The first conductive layer 60 and the second conductive layer 70 may serve as two electrodes of the semiconductor device 100.

[0055] In order to resist external impurities and moisture invasion, the first conductive layer 60 and the dielectric layer 40 are usually covered with a passivation layer 102 . The material of the passivation layer 102 is an inorganic material such as silicon dioxide and silicon nitride.

[0056] The CTE value of SiC is relatively large, while the CTE values ​​of materials such as silicon dioxide and silicon nitride are relatively small. That is, the CTE value of the substrate 10 is relatively large, and the CTE value of the passivation layer 102 is relatively small, and the CTE values ​​of the two differ significantly. After the semiconductor device 100 is packaged, reliability tests such as temperature cycling and temperature shock need to be performed. During this test, shear stress is often generated due to the mismatch between the CTE values ​​of the substrate 10 and the passivation layer 102. The first conductive layer 60 is in direct contact with the passivation layer 102, and the passivation layer 102 covers the top and side surfaces of the first conductive layer 60. This causes shear stress to be generated at the corners of the passivation layer 102 where it contacts the first conductive layer 60. Since the material rigidity of the passivation layer 102 is relatively high, this shear stress can cause cracks to form inside the passivation layer 102, thereby causing the passivation layer 102 to crack, thereby causing the semiconductor device 100 to fail.

[0057] Based on this, as shown in FIG2 a , an embodiment of the present application provides a semiconductor device 100 , which may be a diode. The semiconductor device 100 may include: a substrate 10 , an epitaxial layer 20 , a doped region 30 , a dielectric layer 40 , a first passivation layer 50 , a first conductive layer 60 , a second conductive layer 70 , a third conductive layer 80 , and a protective layer 110 .

[0058] To better illustrate the semiconductor device 100 of this embodiment, three directions may be defined herein: a first direction (X direction), a second direction (Y direction), and a third direction (Z direction). The X direction refers to the length direction of the semiconductor device 100, the Y direction refers to the width direction of the semiconductor device 100, and the Z direction refers to the thickness direction of the semiconductor device 100. Furthermore, the X direction, the Y direction, and the Z direction are perpendicular to each other.

[0059] Substrate 10 may be a doped substrate, and its doping type may be a first type, which may be P-type or N-type. As shown in FIG2a , for ease of description, a first surface 11 may be defined on substrate 10, and first surface 11 may be the top surface of substrate 10. It will be understood that the "top surface" and "bottom surface" are surfaces defined with the third conductive layer 80 serving as the bottom of semiconductor device 100. The "top surface" of any component may be the surface of the component facing away from the third conductive layer 80, and the "bottom surface" of any component may be the surface of the component facing the third conductive layer 80.

[0060] As shown in FIG2 a , the epitaxial layer 20 is disposed on the first surface 11, and the size of the epitaxial layer 20 along the X-direction is the same as the size of the substrate 10 along the X-direction. The size of the epitaxial layer 20 along the Y-direction may also be the same as the size of the substrate 10 along the Y-direction. The epitaxial layer 20 may be a doped epitaxial layer, and its doping type may be the same as the doping type of the substrate 10. For example, when the doping type of the substrate 10 is the first type, the doping type of the epitaxial layer 20 may also be the first type.

[0061] As shown in FIG2 a , the third conductive layer 80 may be disposed on the bottom surface of the substrate 10. That is, the third conductive layer 80 and the epitaxial layer 20 may be disposed on opposite sides of the substrate 10. The size of the third conductive layer 80 along the X-direction may be the same as the size of the substrate 10 along the X-direction, and the size of the third conductive layer 80 along the Y-direction may also be the same as the size of the substrate 10 along the Y-direction.

[0062] The material of the third conductive layer 80 may include metal. Specifically, the material of the third conductive layer 80 may be pure metal or a metal compound. Exemplarily, the material of the third conductive layer 80 may include aluminum, copper, nickel, titanium, silver, gold, and related metal compounds. These metal materials have good electrical conductivity.

[0063] As shown in FIG2 a , the doped region 30 is located on the side of the epitaxial layer 20 facing away from the substrate 10, that is, the doped region 30 is located on the top surface of the epitaxial layer 20. There may be multiple doped regions 30, wherein the doped region 30 located in the middle has a larger size along the X-direction, and the doped regions 30 located on both sides of the doped region 30 have a smaller size along the X-direction. It will be understood that the doped region 30 below refers to the doped region 30 located in the middle.

[0064] As shown in Figure 2a, the two side surfaces of the doped region 30 are spaced a certain distance from the two side surfaces of the epitaxial layer 20. The doping type of the doped region 30 may be different from the doping type of the epitaxial layer 20. For example, the doping type of the doped region 30 may be a second type, which may be N-type or P-type. It is understood that the first type and the second type are different. For example, when the first type is P-type, the second type is N-type; when the first type is N-type, the second type is P-type.

[0065] As shown in FIG2 a , dielectric layer 40 is disposed on the side of epitaxial layer 20 and doped region 30 facing away from substrate 10. A through hole 44 is provided in the middle of dielectric layer 40 . Through hole 44 is located opposite doped region 30 to expose a portion of the top surface of doped region 30. In other words, dielectric layer 40 covers the top surface of epitaxial layer 20 and a portion of the top surface of doped region 30.

[0066] As shown in FIG. 2 a , the dielectric layer 40 has a second surface 41 facing the substrate 10 , a third surface 42 facing away from the substrate 10 , and an inclined surface 43 connecting the second surface 41 and the third surface 42 .

[0067] As shown in FIG2a , the first passivation layer 50 is disposed on the side of the dielectric layer 40 facing away from the substrate 10. The first passivation layer 50 includes one or more sub-passivation layers 51. In one example, as shown in FIG2a , the first passivation layer 50 includes two sub-passivation layers 51. The two sub-passivation layers 51 are stacked and disposed on the side of the dielectric layer 40 facing away from the substrate 10. Both sub-passivation layers 51 cover a portion of the dielectric layer 40. Exemplarily, the size of the sub-passivation layer 51 along the X-direction is smaller than the size of the dielectric layer 40 along the X-direction. In this embodiment, the two sub-passivation layers 51 have the same size along the X-direction. In other embodiments, the two sub-passivation layers 51 may have different sizes along the X-direction.

[0068] In another example, as shown in FIG4 , the first passivation layer 50 includes one sub-passivation layer 51. In yet another example, as shown in FIG5 , the first passivation layer 50 includes three sub-passivation layers 51. It is understood that in other embodiments, the number of sub-passivation layers 51 in the first passivation layer 50 may also be four, five, or more layers.

[0069] The thickness of the sub-passivation layer 51 may be greater than 0.1 um, and for example, the thickness of the sub-passivation layer 51 is 0.2 um, 0.5 um, 0.7 um, etc. When the first passivation layer 50 includes multiple sub-passivation layers 51 , the thickness of each sub-passivation layer 51 may be the same or different.

[0070] Furthermore, the material of the sub-passivation layer 51 may include common dielectric materials such as silicon dioxide, silicon nitride, semi-insulating polysilicon, or inorganic dielectric materials containing nitrogen, carbon, oxygen, phosphorus, boron, etc. In addition, when the first passivation layer 50 includes multiple sub-passivation layers 51, the material of each sub-passivation layer 51 may be the same or different.

[0071] As shown in FIG2 a , a portion of the second conductive layer 70 is disposed within the through hole 44 and contacts the doped region 30, while the remaining portion of the second conductive layer 70 is disposed on the dielectric layer 40. Furthermore, the second conductive layer 70 covers a portion of the dielectric layer 40. In other words, a portion of the doped region 30 is located between the substrate 10 and the second conductive layer 70, and a portion of the doped region 30 is located between the substrate 10 and the dielectric layer 40.

[0072] As shown in FIG2 a , a portion of the second conductive layer 70 is disposed on the inclined surface 43. This increases the contact area between the dielectric layer 40 and the second conductive layer 70, and allows for a smooth transition of the second conductive layer 70 from the portion in contact with the doped region 30 to the portion in contact with the dielectric layer 40, thereby preventing cracking at the inclined surface 43 where the second conductive layer 70 contacts the dielectric layer 40.

[0073] The material of the second conductive layer 70 may include metal. Specifically, the material of the second conductive layer 70 may be pure metal or metal compound. Exemplarily, the material of the second conductive layer 70 may include aluminum, copper, nickel, titanium, silver, gold, and related metal compounds. These metal materials have good electrical conductivity.

[0074] As shown in FIG2 a , the first conductive layer 60 is located on the side of the second conductive layer 70 facing away from the substrate 10 and covers a portion of the second conductive layer 70. That is, the size of the first conductive layer 60 along the X-axis is smaller than the size of the second conductive layer 70 along the X-axis. Furthermore, a portion of the first conductive layer 60 covers the portion of the second conductive layer 70 located on the doped region 30, and a portion of the first conductive layer 60 covers the portion of the second conductive layer 70 located on the dielectric layer 40. In other words, a first portion of the second conductive layer 70 is located between the first conductive layer 60 and the doped region 30, and a second portion of the second conductive layer 70 is located between the first conductive layer 60 and the dielectric layer 40.

[0075] As shown in FIG. 2 a , in a possible embodiment, part of the first conductive layer 60 is located in the through hole 44 , and the projection of the end surface of the first conductive layer 60 facing the first passivation layer 50 on the dielectric layer 40 is located outside the inclined surface 43 .

[0076] In another possible embodiment, as shown in FIG2b , a portion of the first conductive layer 60 is located within the through-hole 44, and the projection of the end surface of the first conductive layer 60 facing the first passivation layer 50 on the dielectric layer 40 is located on the inclined surface 43. Thus, the size of the first conductive layer 60 along the X-direction is moderate. If the end surface of the first conductive layer 60 facing the first passivation layer 50 is located between the two inclined surfaces 43, the size of the first conductive layer 60 along the X-direction is too small, which may result in the inability to perform the basic function of the first conductive layer 60. If the projection of the end surface of the first conductive layer 60 facing the first passivation layer 50 on the dielectric layer 40 is located on the inclined surface 43, the top surface of the first conductive layer 60 tends to be planar, thereby reducing the shear stress generated during the temperature test of the semiconductor device 100, thereby reducing the possibility of large deformation and stress in various parts of the first conductive layer 60, and the stress being transferred to the dielectric layer 40, the second conductive layer 70, the doped region 30, and the epitaxial layer 20, which may cause the semiconductor device 100 to fail.

[0077] As shown in FIG2a , portions of the first passivation layer 50 and the first conductive layer 60 are both disposed on the side of the dielectric layer 40 facing away from the substrate 10 . Furthermore, as shown in FIG3 , along the X-direction, a first spacing d1 is defined between the first conductive layer 60 and the first passivation layer 50, and the dimension of the first conductive layer 60 along the Y-direction is the same as the dimension of the first passivation layer 50 along the Y-direction. In other words, along the length direction of the semiconductor device 100, a first spacing d1 is defined between the first conductive layer 60 and the first passivation layer 50, and the dimension of the first conductive layer 60 along the width direction of the semiconductor device 100 is the same as the dimension of the first passivation layer 50 along the width direction. In other embodiments, along the Y-direction, a first spacing d1 is defined between the first conductive layer 60 and the first passivation layer 50, and the dimension of the first conductive layer 60 along the X-direction is the same as the dimension of the first passivation layer 50 along the X-direction.

[0078] It is understood that the first distance d1 may be the minimum distance between the first conductive layer 60 and the first passivation layer 50. For example, when the first passivation layer 50 includes a single sub-passivation layer 51, the first distance d1 may be the distance between the first conductive layer 60 and the sub-passivation layer 51. When the first passivation layer 50 includes multiple sub-passivation layers 51, and the dimensions of the multiple sub-passivation layers 51 along the X-direction are not completely identical, the first distance d1 may be the minimum value of the distances between the first conductive layer 60 and each sub-passivation layer 51.

[0079] When the semiconductor device 100 is subjected to tests such as temperature cycling and temperature shock, the substrate 10, the first passivation layer 50 and the first conductive layer 60 may produce different amounts of deformation due to different CTEs. Since there is a first distance d1 between the first conductive layer 60 and the first passivation layer 50, the first passivation layer 50 and the first conductive layer 60 can be deformed to within the first distance d1 after being deformed due to heat. Compared with the related technology shown in Figure 1, in which the first conductive layer 60 and the passivation layer 102 are in direct contact and the passivation layer 102 covers the top surface and side surfaces of the first conductive layer 60, the passivation layer 102 generates shear stress at the position where it contacts the corner of the first conductive layer 60. The technical solution of this embodiment can reduce the generation of shear stress, thereby reducing the cracking of the first passivation layer 50 and the failure of the semiconductor device 100, thereby improving the reliability of the semiconductor device 100.

[0080] Moreover, as shown in FIG2a , the first conductive layer 60 is located on the side of the second conductive layer 70 facing away from the substrate 10 . The first conductive layer 60 can serve as one of the electrodes of the semiconductor device 100 , and the third conductive layer 80 can serve as the other electrode of the semiconductor device 100 . The thickness of the second conductive layer 70 is less than that of the first conductive layer 60 . For example, the thickness of the second conductive layer 70 can be less than 1 μm, for example, the thickness of the second conductive layer 70 can be 0.2 μm, 0.4 μm, etc. The thickness of the first conductive layer 60 can be greater than 1 μm, for example, the thickness of the first conductive layer 60 can be 2 μm, 4 μm, etc. Therefore, the first conductive layer 60 can also be referred to as a thick metal layer, and the second conductive layer 70 can also be referred to as a thin metal layer.

[0081] As shown in Figure 2a, the overlap area between the second conductive layer 70 and the dielectric layer 40 is greater than the overlap area between the first conductive layer 60 and the dielectric layer 40. This larger overlap area between the second conductive layer 70 and the dielectric layer 40, that is, the larger overlap area between the thin metal layer and the dielectric layer 40, can better prevent moisture from invading the substrate 10 from between the second conductive layer 70 and the dielectric layer 40. In other words, the semiconductor device 100 has improved moisture resistance. Furthermore, the overlap area between the first conductive layer 60 and the dielectric layer 40 is smaller. Since the first passivation layer 50 is also disposed on the dielectric layer 40, the first distance d1 between the first conductive layer 60 and the first passivation layer 50 is larger. In other words, the first distance d1 between the thick metal layer and the first passivation layer 50 is larger, thereby further reducing cracking in the first passivation layer 50. In other words, this technical solution can reduce cracking in the first passivation layer 50 while also providing improved moisture resistance.

[0082] As shown in FIG2a , the projection of the second conductive layer 70 on the first surface 11 is within the projection of the doped region 30 on the first surface 11. Furthermore, because the overlapping area between the second conductive layer 70 and the dielectric layer 40 is greater than the overlapping area between the first conductive layer 60 and the dielectric layer 40, the projection of the first conductive layer 60 on the first surface 11 is also within the projection of the doped region 30 on the first surface 11. An electric field distribution can be generated between the third conductive layer 80 and the first and second conductive layers 60 and 70. When the projections of the first and second conductive layers 60 and 70 on the first surface 11 are both within the projection of the doped region 30 on the first surface 11, the electric field distribution is not affected, thereby improving the withstand voltage stability of the semiconductor device 100.

[0083] It is understood that the overlapping area between the second conductive layer 70 and the dielectric layer 40 may refer to the area where the projection area of ​​the second conductive layer 70 on the first surface 11 overlaps with the projection area of ​​the dielectric layer 40 on the first surface 11. Similarly, the overlapping area between the first conductive layer 60 and the dielectric layer 40 may refer to the area where the projection area of ​​the first conductive layer 60 on the first surface 11 overlaps with the projection area of ​​the dielectric layer 40 on the first surface 11.

[0084] Furthermore, as shown in FIG2a , along the X-direction, a third distance d3 is defined between the second conductive layer 70 and the first passivation layer 50. The third distance d3 is smaller than the first distance d1. Furthermore, the difference between the first distance d1 and the third distance d3 is greater than 0.5 μm. For example, the difference between the first distance d1 and the third distance d3 can be 1 μm, 3 μm, or 5 μm. It is understood that the third distance d3 can be the minimum distance between the second conductive layer 70 and the first passivation layer 50. For example, when the first passivation layer 50 includes a single sub-passivation layer 51, the third distance d3 can be the distance between the second conductive layer 70 and the sub-passivation layer 51. When the first passivation layer 50 includes multiple sub-passivation layers 51, and the dimensions of the multiple sub-passivation layers 51 along the X-direction are not identical, the third distance d3 can be the minimum distance between the second conductive layer 70 and each sub-passivation layer 51. In this way, the surface of the second conductive layer 70 facing the first passivation layer 50 is closer to the first passivation layer 50 than the first conductive layer 60 , thereby increasing the overlapping area between the second conductive layer 70 and the dielectric layer 40 , thereby improving the moisture resistance of the semiconductor device 100 .

[0085] Furthermore, as shown in FIG2 a , the thickness of the first passivation layer 50 is greater than that of the second conductive layer 70 and less than that of the first conductive layer 60. The overlap area between the second conductive layer 70 and the dielectric layer 40 is relatively large, that is, the overlap area between the thin metal layer and the dielectric layer 40 is relatively large. Furthermore, because the thickness of the second conductive layer 70 is less than that of the first passivation layer 50, the cross-section of contact between the second conductive layer 70 and the first passivation layer 50 is relatively small, thereby preventing significant shear stress and preventing cracking of the first passivation layer 50 at the contact area with the second conductive layer 70.

[0086] The material of the first conductive layer 60 may include metal. Specifically, the material of the first conductive layer 60 may be pure metal or metal compound. Exemplarily, the material of the first conductive layer 60 may include aluminum, copper, nickel, titanium, silver, gold, and related metal compounds. These metal materials have good electrical conductivity.

[0087] As shown in FIG2a , the semiconductor device 100 may further include a second passivation layer 140. The second passivation layer 140 covers the side surfaces of the first conductive layer 60. Along the X-direction, a second spacing d2 is defined between the second passivation layer 140 and the first passivation layer 50. The second spacing d2 is the same as or slightly different from the first spacing d1, and the second spacing d2 is greater than the third spacing d3 between the second conductive layer 70 and the first passivation layer 50. During the fabrication of the semiconductor device 100, a dielectric layer 40, a first conductive layer 60, and a second conductive layer 70 may be fabricated on the substrate 10. A passivation layer may then be deposited on the first conductive layer 60, the second conductive layer 70, and the dielectric layer 40. The passivation layer located on the top surface of the first conductive layer 60 and the passivation layer within a certain distance from the side surfaces of the first conductive layer 60 may be etched away to form the first passivation layer 50. Because the side surfaces of the first conductive layer 60 are inclined, the passivation layer covering the side surfaces of the first conductive layer 60 is larger in the Z direction. Therefore, within the same timeframe as the passivation layer covering the top surface of the first conductive layer 60 can be completely etched, the passivation layer covering the side surfaces of the first conductive layer 60 cannot be completely etched away. The remaining passivation layer remaining on the side surfaces of the first conductive layer 60 after etching is the second passivation layer 140. This shortens the etching time and reduces costs. Furthermore, because the second passivation layer 140 only covers the side surfaces of the first conductive layer 60 and does not simultaneously cover the top surface, side surfaces, or the corners therebetween, the shear stress generated by the second passivation layer 140 can be reduced.

[0088] It is understood that the second passivation layer 140 and the first passivation layer 50 are manufactured in the same process step. Therefore, the number of layers and the thickness of the second passivation layer 140 can be the same as the number of layers and the thickness of the first passivation layer 50. For example, as shown in FIG2 a , the second passivation layer 140 can also include two sub-passivation layers 51.

[0089] In addition, in this embodiment, the surface of the second passivation layer 140 facing away from the substrate 10 is flush with the surface of the first conductive layer 60 facing away from the substrate 10. In other embodiments, the surface of the second passivation layer 140 facing away from the substrate 10 may be lower than the surface of the first conductive layer 60 facing away from the substrate 10.

[0090] As shown in FIG2a , the protective layer 110 is provided with a groove 111. The groove 111 is located on the first conductive layer 60 to expose a portion of the top surface of the first conductive layer 60. The area on the first conductive layer 60 not covered by the protective layer 110 can be a characteristic area. After the characteristic area is exposed, it is convenient to weld and package with other components or electronic devices. Therefore, as shown in FIG2a , the protective layer 110 can cover a portion of the surface of the first conductive layer 60, the top surface of the second passivation layer 140, the surface of the second passivation layer 140 facing the first passivation layer 50, the portion of the second conductive layer 70 extending beyond the first conductive layer 60, a portion of the dielectric layer 40, and the surface of the first passivation layer 50 facing away from the substrate 10. In other words, a portion of the protective layer 110 can be located within the second distance d2 between the second passivation layer 140 and the first passivation layer 50. The material of protective layer 110 may include polyimide (PI), which has high flexibility and elasticity. This material can alleviate the extrusion of the molding compound during the packaging process and prevent the diffusion of particulate matter in the molding compound, thereby protecting the first conductive layer 60, the second passivation layer 140, the second conductive layer 70, the dielectric layer 40, and the first passivation layer 50. In addition, when the semiconductor device 100 is completed and tested, because a portion of the protective layer 110 is located within the first distance d1 between the first conductive layer 60 and the first passivation layer 50, the protective layer 110 will be subjected to shear stress. However, due to the high flexibility and elasticity of the protective layer 110, it can buffer the shear stress, thereby reducing the possibility of cracking of the first passivation layer 50 and causing failure of the semiconductor device 100.

[0091] In other embodiments of the present application, as shown in FIG6 , the difference from the embodiment shown in FIG2 a lies in the positional relationship between the second conductive layer 70 and the first passivation layer 50. Specifically, in this embodiment, as shown in FIG6 , a third portion of the second conductive layer 70 is stacked between the first passivation layer 50 and the dielectric layer 40. Thus, an overlapping region exists between the second conductive layer 70 and the first passivation layer 50. For example, a fourth distance d4 is defined between the surface of the second conductive layer 70 facing the first passivation layer 50 and the surface of the first passivation layer 50 facing the first conductive layer 60. This fourth distance d4 can be greater than 0.1 μm, for example, 0.5 μm, 1 μm, etc. Furthermore, the first distance d1 between the first conductive layer 60 and the first passivation layer 50 can also be greater than 0.1 μm, for example, 0.5 μm, 1 μm, etc. Along the X-direction, a fifth distance d5 is defined between the surface of the second conductive layer 70 facing the first passivation layer 50 and the side surface of the doped region 30. This fifth distance d5 can also be greater than 0.1 μm, for example, 0.5 μm, 1 μm, etc. Thus, the first passivation layer 50 and the second conductive layer 70 may cover the entire area of ​​the first surface 11 of the substrate 10 . Therefore, the second conductive layer 70 , the first passivation layer 50 and the dielectric layer 40 may work together to improve moisture resistance.

[0092] In this embodiment, the number of sub-passivation layers 51 in the first passivation layer 50 may also be one or more. In one example, as shown in FIG6 , the first passivation layer 50 includes two sub-passivation layers 51. The third portion of the second conductive layer 70 is located between at least one sub-passivation layer 51 and the dielectric layer 40. Exemplarily, as shown in FIG6 , the third portion of the second conductive layer 70 is located between the two sub-passivation layers 51 and the dielectric layer 40. Thus, an overlapping region exists between the second conductive layer 70 and the two sub-passivation layers 51, thereby further improving the moisture resistance of the semiconductor device 100.

[0093] In another example, as shown in FIG7 , the first passivation layer 50 includes a sub-passivation layer 51 , and the third portion of the second conductive layer 70 is located between the sub-passivation layer 51 and the dielectric layer 40 .

[0094] In another example, as shown in FIG8 , the first passivation layer 50 includes three sub-passivation layers 51 , and the third portion of the second conductive layer 70 is located between the three sub-passivation layers 51 and the dielectric layer 40 .

[0095] In other embodiments of the present application, as shown in FIG9a , the difference from the embodiment shown in FIG2a lies in the positional relationship between the second conductive layer 70 and the first passivation layer 50. As shown in FIG9a , the second conductive layer 70 contacts the first passivation layer 50 along the X-direction. Thus, the first passivation layer 50 and the second conductive layer 70 can cover the entire area of ​​the first surface 11 of the substrate 10. Therefore, the second conductive layer 70, the first passivation layer 50, and the dielectric layer 40 can work together to improve moisture resistance.

[0096] In another example, as shown in FIG9 b , the first passivation layer 50 includes a sub-passivation layer 51 , and the second conductive layer 70 contacts the sub-passivation layer 51 .

[0097] In another example, as shown in FIG9 c , the first passivation layer 50 includes three sub-passivation layers 51 , and the second conductive layer 70 contacts the bottommost sub-passivation layer 51 among the three sub-passivation layers 51 .

[0098] In other embodiments of the present application, as shown in FIG10 , the difference between this embodiment and the embodiment shown in FIG2 a is that a third passivation layer 90 is added to the embodiment shown in FIG2 a . Specifically, as shown in FIG10 , the third passivation layer 90 is located on the side of the protective layer 110 facing the substrate 10, and the third passivation layer 90 covers at least a portion of the surface of the first conductive layer 60 facing away from the substrate 10, a surface of the second passivation layer 140 facing away from the substrate 10, a surface of the second passivation layer 140 facing the first passivation layer 50, a portion of the surface of the second conductive layer 70 facing away from the substrate 10, a surface of the second conductive layer 70 facing the first passivation layer 50, a surface of the dielectric layer 40 facing away from the substrate 10 and located between the first passivation layer 50 and the second conductive layer 70, a surface of the first passivation layer 50 facing the first conductive layer 60, and a surface of the first passivation layer 50 facing away from the substrate 10. A portion of the top surface of the first conductive layer 60 is a characteristic region, which is not covered by the third passivation layer 90, thereby facilitating soldering and packaging of the first conductive layer 60 with other components or electronic devices. Thus, the third passivation layer 90 can provide moisture resistance. Furthermore, the thickness of the third passivation layer 90 is less than that of the second conductive layer 70, that is, less than that of the thin metal layer. For example, the thickness of the third passivation layer 90 is less than 1 μm, such as 0.1 μm or 0.2 μm. Therefore, the third passivation layer 90 has a certain degree of flexibility, thereby preventing cracking of the third passivation layer 90 due to thermal deformation.

[0099] The material of the third passivation layer 90 may have similar or identical properties to the material of the first passivation layer 50. For example, the material of the third passivation layer 90 may include common dielectric materials such as silicon dioxide, silicon nitride, and semi-insulating polysilicon, or inorganic dielectric materials containing nitrogen, carbon, oxygen, phosphorus, and boron.

[0100] In other embodiments of the present application, as shown in FIG11 , the difference between this embodiment and the embodiment shown in FIG6 is that a third passivation layer 90 is added to the embodiment shown in FIG6 . Specifically, as shown in FIG11 , the third passivation layer 90 is located on the side of the protective layer 110 facing the substrate 10, and the third passivation layer 90 covers a portion of the surface of the first conductive layer 60 facing away from the substrate 10, a surface of the second passivation layer 140 facing away from the substrate 10, a surface of the second passivation layer 140 facing toward the first passivation layer 50, a surface of the second conductive layer 70 facing away from the substrate 10 and located between the first conductive layer 60 and the first passivation layer 50, a surface of the first passivation layer 50 facing toward the first conductive layer 60, and a surface of the first passivation layer 50 facing away from the substrate 10.

[0101] In other embodiments of the present application, as shown in FIG12 , the difference between this embodiment and the embodiment shown in FIG9 a is that a third passivation layer 90 is added to the embodiment shown in FIG9 a . As shown in FIG12 , the third passivation layer 90 is located on the side of the protective layer 110 facing the substrate 10, and the third passivation layer 90 covers a portion of the surface of the first conductive layer 60 facing away from the substrate 10, a surface of the second passivation layer 140 facing away from the substrate 10, a portion of the surface of the second passivation layer 140 facing toward the first passivation layer 50, a portion of the surface of the second conductive layer 70 facing away from the substrate 10, a surface of the second conductive layer 70 facing toward the first passivation layer 50, a surface of the dielectric layer 40 facing away from the substrate 10 and located between the first passivation layer 50 and the second conductive layer 70, a surface of the first passivation layer 50 facing toward the first conductive layer 60, and a surface of the first passivation layer 50 facing away from the substrate 10.

[0102] In other embodiments of the present application, as shown in FIG13 , the difference from the embodiment shown in FIG2 a is that this embodiment adds an oxide layer 120 and a polysilicon layer 130 to the semiconductor device 100 shown in FIG2 a , and the overlapped regions between the first conductive layer 60, the second conductive layer 70, and the doped region 30 are different in size. Specifically, in this embodiment, the semiconductor device 100 can be a transistor. The first conductive layer 60 can be the source of the transistor, the third conductive layer 80 can be the drain of the transistor, and the polysilicon layer 130 can be the gate of the transistor.

[0103] As shown in FIG13 , the oxide layer 120 and the polysilicon layer 130 are both located within the first conductive layer 60 and the second conductive layer 70, and the oxide layer 120 wraps around the polysilicon layer 130. There may be multiple doped regions 30, and the projection of the polysilicon layer 130 on the substrate 10 overlaps with the projection of at least one doped region 30 on the substrate 10.

[0104] In other embodiments of the present application, as shown in FIG14 , the difference between this embodiment and the embodiment shown in FIG2 a is that, based on the embodiment shown in FIG2 a , the second passivation layer 140 is removed in this embodiment. The protective layer 110 may cover a portion of the surface of the first conductive layer 60 facing away from the substrate 10, a surface of the first conductive layer 60 facing the first passivation layer 50, a portion of the surface of the second conductive layer 70 facing away from the substrate 10 and located between the first conductive layer 60 and the first passivation layer 50, a surface of the second conductive layer 70 facing the first passivation layer 50, a portion of the surface of the dielectric layer 40 facing away from the substrate 10 and located between the second conductive layer 70 and the first passivation layer 50, a surface of the first passivation layer 50 facing the first conductive layer 60, and a surface of the first passivation layer 50 facing away from the substrate 10.

[0105] It is understandable that, in other embodiments, the second passivation layer 140 may be removed based on any of the embodiments shown in FIG. 4 to FIG. 13 .

[0106] The present invention also provides a method for manufacturing a semiconductor device 100, which can be applied to the semiconductor device 100 shown in FIG2a. As shown in FIG15, the manufacturing method includes:

[0107] S131, providing a substrate and an epitaxial layer.

[0108] As shown in FIG16( a ), a substrate 10 has a first surface 11, and an epitaxial layer 20 is provided on the first surface 11. The substrate 10 may be a doped substrate, and the epitaxial layer 20 may be a doped epitaxial layer 20. Furthermore, the substrate 10 and the epitaxial layer 20 may have the same doping type. For example, both may have the first doping type.

[0109] S132, forming a doped region on the epitaxial layer.

[0110] Silicon carbide semiconductor can be doped on the top surface of the epitaxial layer 20 to form a doped region 30 as shown in FIG16( b ). The doped region 30 is smaller in the X direction than the epitaxial layer 20 and is located in the middle of the epitaxial layer 20 .

[0111] S133, forming a dielectric layer on the epitaxial layer and the doped region.

[0112] As shown in FIG16( c ), during the fabrication process, a dielectric layer 40 can be formed by deposition followed by etching. Dielectric layer 40 is provided with through-holes 44. Part of dielectric layer 40 is located on epitaxial layer 20, and part of dielectric layer 40 is located on doped regions 30. In other words, dielectric layer 40 covers a portion of the top surface of epitaxial layer 20 and a portion of the top surface of doped regions 30. Doped regions 30 correspond to through-holes 44 in dielectric layer 40 and are exposed through through-holes 44.

[0113] S134, forming a second conductive layer on the doped region and the dielectric layer.

[0114] As shown in FIG. 16( d ), a second conductive layer 70 may be formed on a portion of the top surface of the doped region 30 located between the dielectric layer 40 and on the top surfaces of the dielectric layer 40 located on both sides of the region.

[0115] S135 , forming a first conductive layer on the second conductive layer.

[0116] As shown in FIG16( e ), a first conductive layer 60 is formed on top of the second conductive layer 70, and the first conductive layer 60 covers a portion of the top surface of the second conductive layer 70. The thickness of the second conductive layer 70 is less than that of the first conductive layer 60. The first conductive layer 60 and the dielectric layer 40 have an overlapping area.

[0117] S136 , forming a first passivation layer and a second passivation layer on the dielectric layer.

[0118] A passivation layer can be formed on the first conductive layer 60, the second conductive layer 70, and the dielectric layer 40. The passivation layer located on the top surface of the first conductive layer 60 and the passivation layer within a certain distance from the side surface of the first conductive layer 60 are etched away to form a first passivation layer 50 and a second passivation layer 140 as shown in FIG16(f). In this embodiment, there are two first passivation layers 50, and the two first passivation layers 50 are arranged opposite to each other and spaced apart. Each first passivation layer 50 includes two sub-passivation layers 51. Therefore, the two sub-passivation layers 51 close to the dielectric layer 40 can be formed first, and then the two sub-passivation layers 51 away from the dielectric layer 40 can be formed.

[0119] Furthermore, in this embodiment, the second conductive layer 70 and the first passivation layer 50 have no overlapping area and are spaced apart by a third distance d3. Furthermore, along the X-axis, a first distance d1 is spaced apart from the first conductive layer 60 and the first passivation layer 50. The second passivation layer 140 covers the side surfaces of the first conductive layer 60 and, along the X-axis, a second distance d2 is spaced apart from the first passivation layer 50. This second distance d2 is greater than the third distance d3 between the second conductive layer 70 and the first passivation layer 50. Therefore, after the first passivation layer 50 and the first conductive layer 60 are deformed due to heat, they can be deformed to within the first distance d1. Compared with the related technology shown in Figure 1, in which the first conductive layer 60 and the passivation layer 102 are in direct contact and the passivation layer 102 covers the top surface and side surfaces of the first conductive layer 60, which causes the passivation layer 102 to generate shear stress at the position where it contacts the corner of the first conductive layer 60, the technical solution of this embodiment can reduce the generation of shear stress, thereby reducing the cracking of the first passivation layer 50 and the failure of the semiconductor device 100, thereby improving the reliability of the semiconductor device 100.

[0120] It can be understood that in this embodiment, during the process of manufacturing the semiconductor device 100, the second conductive layer 70 and the first conductive layer 60 are manufactured first, and then the first passivation layer 50 is manufactured. In other embodiments, the first passivation layer 50 can also be manufactured first, and then the second conductive layer 70 and the first conductive layer 60 are manufactured.

[0121] S137, making a protective layer.

[0122] A protective layer is formed on the top surface of the semiconductor device 100 obtained in step S136, and a hole is opened in the middle of the protective layer to obtain the protective layer 110 shown in FIG16(g). Moreover, the opening can expose a portion of the surface of the first conductive layer 60, thereby facilitating soldering of the first conductive layer 60 to other components.

[0123] S138, forming a third conductive layer on a side of the substrate facing away from the epitaxial layer.

[0124] A third conductive layer 80 is formed on the side of the substrate 10 facing away from the epitaxial layer 20 , that is, the third conductive layer 80 is formed on the bottom surface of the substrate 10 , to obtain the semiconductor device 100 shown in FIG. 2 a .

[0125] The present invention also provides a method for manufacturing a semiconductor device 100, which can be applied to the semiconductor device 100 shown in FIG10. As shown in FIG17, the manufacturing method includes:

[0126] S151, providing a substrate and an epitaxial layer.

[0127] Refer to step S131 shown in FIG. 15 and (a) in FIG. 16 .

[0128] S152, forming a doped region on the epitaxial layer.

[0129] Refer to step S132 shown in FIG. 15 and (b) in FIG. 16 .

[0130] S153, forming a dielectric layer on the epitaxial layer and the doped region.

[0131] Refer to step S133 shown in FIG. 15 and (c) in FIG. 16 .

[0132] S154, forming a second conductive layer on the doped region and the dielectric layer.

[0133] Refer to step S134 shown in FIG. 15 and (d) in FIG. 16 .

[0134] S155 , forming a first conductive layer on the second conductive layer.

[0135] Refer to step S135 shown in FIG. 15 and (e) in FIG. 16 .

[0136] S156 , forming a first passivation layer and a second passivation layer on the dielectric layer.

[0137] Refer to step S136 shown in FIG. 15 and (f) in FIG. 16 .

[0138] S157, forming a third passivation layer.

[0139] As shown in FIG18( a ), a third passivation layer 90 is formed on the top surface of the semiconductor device 100 obtained in step S156. The third passivation layer 90 can be obtained by first depositing and then etching. The third passivation layer 90 covers a portion of the surface of the first conductive layer 60 facing away from the substrate 10, a surface of the second passivation layer 140 facing away from the substrate 10, a portion of the surface of the second passivation layer 140 facing toward the first passivation layer 50, a portion of the surface of the second conductive layer 70 facing away from the substrate 10, a surface of the second conductive layer 70 facing toward the first passivation layer 50, a surface of the dielectric layer 40 facing away from the substrate 10 and located between the first passivation layer 50 and the second conductive layer 70, a surface of the first passivation layer 50 facing toward the first conductive layer 60, and a surface of the first passivation layer 50 facing away from the substrate 10. Moreover, the thickness of the third passivation layer 90 is less than the thickness of the second conductive layer 70. Thus, the third passivation layer 90 can provide moisture resistance. Furthermore, since the thickness of the third passivation layer 90 is less than that of the second conductive layer 70, that is, the thickness of the third passivation layer 90 is less than that of the thin metal layer. For example, the thickness of the third passivation layer 90 is less than 1 μm, such as 0.1 μm or 0.2 μm. Therefore, the third passivation layer 90 has a certain degree of flexibility, thereby preventing cracking of the third passivation layer 90 due to thermal deformation.

[0140] S158, making a protective layer.

[0141] As shown in FIG18(a), a protective layer 110 is formed on the top surface of the semiconductor device 100 obtained in step S136, and a hole is opened in the middle of the protective layer 110, thereby obtaining the protective layer 110 shown in FIG18(a). Moreover, the provision of the hole can expose a portion of the surface of the first conductive layer 60, thereby facilitating soldering of the first conductive layer 60 to other components.

[0142] S159, forming a third conductive layer on a side of the substrate facing away from the epitaxial layer.

[0143] As shown in FIG18( c ), a third conductive layer 80 is formed on the side of the substrate 10 away from the epitaxial layer 20 , that is, a third conductive layer 80 is formed on the bottom surface of the substrate 10 , to obtain the semiconductor device 100 shown in FIG10 .

[0144] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A semiconductor device, characterized in that: include: substrate; a dielectric layer, the dielectric layer being disposed on the substrate; a first passivation layer, the first passivation layer being provided on a side of the dielectric layer facing away from the substrate; A first conductive layer, wherein the first conductive layer and the first passivation layer are arranged on the same side of the substrate, and a portion of the first conductive layer is stacked on a side of the dielectric layer facing away from the substrate, and along a first direction, there is a first distance between the first conductive layer and the first passivation layer, and the first direction is perpendicular to the thickness direction of the semiconductor device.

2. The semiconductor device according to claim 1, wherein The semiconductor device further includes a second passivation layer, the second passivation layer covers side surfaces of the first conductive layer, and along the first direction, a second distance exists between the second passivation layer and the first passivation layer.

3. The semiconductor device according to claim 2, wherein The semiconductor device further includes a protection layer, a portion of which covers the first conductive layer, the second passivation layer, and the first passivation layer, and a portion of which is located within the second distance.

4. The semiconductor device according to claim 2 or 3, characterized in that The semiconductor device also includes a second conductive layer, which is located between the first conductive layer and the substrate, and a second portion of the second conductive layer is located between the first conductive layer and the dielectric layer. The thickness of the second conductive layer is less than the thickness of the first conductive layer, and the overlapping area between the second conductive layer and the dielectric layer is greater than the overlapping area between the first conductive layer and the dielectric layer.

5. The semiconductor device according to claim 4, wherein Along the first direction, a third distance exists between the second conductive layer and the first passivation layer, and the third distance is smaller than the first distance.

6. The semiconductor device according to claim 4, wherein The second conductive layer contacts the first passivation layer along the first direction.

7. The semiconductor device according to claim 4, wherein: The third portion of the second conductive layer is stacked between the first passivation layer and the dielectric layer.

8. The semiconductor device according to claim 7, wherein: The first passivation layer includes at least two stacked sub-passivation layers, and the third portion of the second conductive layer is stacked between at least one of the sub-passivation layers and the dielectric layer.

9. The semiconductor device according to any one of claims 4 to 7, wherein: The semiconductor device further includes a doped region, part of which is located between the substrate and the second conductive layer, part of which is located between the substrate and the dielectric layer, and a projection of the second conductive layer on the substrate is located within the projection range of the doped region on the substrate.

10. The semiconductor device according to any one of claims 4 to 9, wherein: The semiconductor device also includes a third passivation layer, which covers at least a portion of the surface of the first conductive layer facing away from the substrate, the second passivation layer, a portion of the surface of the second conductive layer facing away from the substrate, a portion of the surface of the first passivation layer facing the first conductive layer, and a portion of the surface of the first passivation layer facing away from the substrate, and the thickness of the third passivation layer is less than the thickness of the second conductive layer.

11. The semiconductor device according to any one of claims 4 to 10, characterized in that: The dielectric layer has a second surface facing the substrate, a third surface facing away from the substrate, and an inclined surface connected between the second surface and the third surface and facing the second conductive layer. Part of the second conductive layer is disposed on the inclined surface.

12. The semiconductor device according to claim 11, wherein The dielectric layer has at least two inclined surfaces, a partial projection of the first conductive layer on the dielectric layer is located between the at least two inclined surfaces, and a projection of an end surface of the first conductive layer facing the first passivation layer on the dielectric layer is located on the inclined surface.

13. A chip, characterized in that: The invention comprises a passive device and the semiconductor device according to any one of claims 1 to 12, wherein the passive device is electrically connected to the semiconductor device.

14. An electronic device, characterized in that: The device comprises a circuit board and the chip according to claim 13, wherein the circuit board is electrically connected to the chip.

15. A vehicle, characterized in that: The vehicle comprises a vehicle body and the electronic device according to claim 14, wherein the electronic device is fixed inside the vehicle body.

16. A method for manufacturing a semiconductor device, characterized in that: The production method comprises: providing a substrate; forming a dielectric layer on the substrate; forming a first conductive layer; A first passivation layer is fabricated on the dielectric layer. The first conductive layer and the first passivation layer are disposed on the same side of the substrate. A portion of the first conductive layer is stacked on a side of the dielectric layer facing away from the substrate. A first distance is provided between the first conductive layer and the first passivation layer along a first direction. The first direction is perpendicular to a thickness direction of the semiconductor device.

17. The manufacturing method according to claim 16, characterized in that: After the step of forming a dielectric layer on the substrate, the manufacturing method further includes: forming a second conductive layer on the substrate and the dielectric layer; The step of making the first conductive layer includes: A first conductive layer is formed on the second conductive layer, wherein the thickness of the second conductive layer is smaller than that of the first conductive layer, and the overlapping area between the second conductive layer and the dielectric layer is larger than the overlapping area between the first conductive layer and the dielectric layer.

18. The manufacturing method according to claim 17, characterized in that: After the step of forming the first conductive layer on the second conductive layer, the manufacturing method further includes: A third passivation layer is produced, wherein the third passivation layer covers at least a portion of the surface of the first conductive layer facing away from the substrate, a portion of the surface of the first conductive layer facing the first passivation layer, a portion of the surface of the second conductive layer facing away from the substrate, a portion of the surface of the first passivation layer facing the first conductive layer, and a portion of the surface of the first passivation layer facing away from the substrate, and the thickness of the third passivation layer is less than the thickness of the second conductive layer.

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