Display substrate and manufacturing method therefor, and display apparatus

Abstract

A display substrate and a manufacturing method therefor, and a display apparatus. The display substrate comprises a plurality of first regions and a plurality of second regions which are alternately arranged; in the direction perpendicular to the display substrate, a display region comprises a driving structure layer and a light-emitting structure layer; a driving structure layer of each first region comprises a plurality of pixel driving circuits, a driving structure layer of each second region comprises at least one gate driving apparatus and / or at least one signal wire, a light-emitting structure layer of each first region comprises a plurality of first light-emitting devices, and a light-emitting structure layer of each second region comprises a plurality of second light-emitting devices; and at least one first light-emitting device in each first region is connected to at least one pixel driving circuit in the first region, and at least one second light-emitting device in each second region is connected to at least one pixel driving circuit in the first region.

Description

Display substrate and manufacturing method thereof, and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on January 31, 2024, with application number 202410139402.3 and invention name “Display substrate, preparation method thereof, and display device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to but is not limited to the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field. Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, the present disclosure provides a display substrate, comprising a plurality of first areas and a plurality of second areas, wherein the first areas and the second areas are in the shape of strips extending along a second direction, the plurality of first areas and the plurality of second areas are alternately arranged along the first direction, and the first direction and the second direction intersect; in a direction perpendicular to the display substrate, the display area comprises a driving structure layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving structure layer away from the substrate; the driving structure layer in the first area comprises a plurality of pixel driving circuits, the driving structure layer in the second area comprises at least one gate driving device and / or at least one signal line, the light-emitting structure layer in the first area comprises a plurality of first light-emitting devices, and the light-emitting structure layer in the second area comprises a plurality of second light-emitting devices; at least one first light-emitting device in the first area is connected to at least one pixel driving circuit in the first area, and at least one second light-emitting device in the second area is connected to at least one pixel driving circuit in the first area.

[0006] In an exemplary embodiment, the driving structure layer of the first area includes a plurality of circuit repetition units, and the orthographic projection of at least one circuit repetition unit on the substrate has a first area. The light-emitting structure layer of the first area includes a plurality of light-emitting repetition units, and the orthographic projection of at least one light-emitting repetition unit on the substrate has a second area. The ratio of the first area to the second area is 0.95 to 1.05; at least one circuit repetition unit includes M+m pixel driving circuits, and at least one light-emitting repetition unit includes M first light-emitting devices; M is an integer multiple of 2 or an integer multiple of 3, and m is a positive integer greater than or equal to 1.

[0007] In an exemplary embodiment, the pixel driving circuit in at least one circuit repetition unit includes at least a first pixel driving circuit and a second pixel driving circuit, at least one first pixel driving circuit is connected to at least one first light-emitting unit, and the orthographic projection of at least one first pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of at least one first light-emitting device on the substrate; at least one second pixel driving circuit is connected to at least one second light-emitting device through an anode connecting line, and the orthographic projection of at least one second pixel driving circuit on the substrate does not overlap with the orthographic projection of at least one second light-emitting device on the substrate.

[0008] In an exemplary embodiment, the second region has a first center line, which is a straight line that bisects the second region in the first direction and extends along the second direction; the second region includes at least a first side repeating unit located on the opposite side of the first center line in the first direction and a second side repeating unit located on the side of the first center line in the first direction, and the first side repeating unit and the second side repeating unit each include N second light-emitting devices, where N is an integer multiple of 3 or an integer multiple of 4.

[0009] In an exemplary embodiment, the first region includes at least a first side region located on a side opposite to the first direction of the second region and a second side region located on a side of the first direction of the second region; at least one second light-emitting device in the first side repeating unit is connected to at least one second pixel driving circuit in the first side region through an anode connecting line, and at least one second light-emitting device in the second side repeating unit is connected to at least one second pixel driving circuit in the second side region through an anode connecting line.

[0010] In an exemplary embodiment, the first side region includes at least a first circuit repeating unit and a second circuit repeating unit, the first circuit repeating unit is located on the side of the second region opposite to the first direction, and the second circuit repeating unit is located on the side of the first circuit repeating unit away from the second region; the second side region includes at least an eleventh circuit repeating unit and a twelfth circuit repeating unit, the eleventh circuit repeating unit is located on the side of the second region in the first direction, and the twelfth circuit repeating unit is located on the side of the eleventh circuit repeating unit away from the second region; the first side repeating unit includes a first light-emitting device group and a second light-emitting device group sequentially arranged along the first direction, and the second side repeating unit includes a first light-emitting device group and a second light-emitting device group sequentially arranged along the first direction. Towards the third light-emitting device group and the fourth light-emitting device group arranged in sequence; at least one second light-emitting device in the first light-emitting device group is connected to at least one second pixel driving circuit in the first circuit repetition unit through a first anode connecting line, at least one second light-emitting device in the second light-emitting device group is connected to at least one second pixel driving circuit in the second circuit repetition unit through a second anode connecting line, at least one second light-emitting device in the third light-emitting device group is connected to at least one second pixel driving circuit in the eleventh circuit repetition unit through an eleventh anode connecting line, and at least one second light-emitting device in the fourth light-emitting device group is connected to at least one second pixel driving circuit in the twelfth circuit repetition unit through a twelfth anode connecting line.

[0011] In an exemplary embodiment, the second length of at least one second anode connecting wire is greater than the first length of at least one first anode connecting wire, the fourth length of at least one twelfth anode connecting wire is greater than the third length of at least one eleventh anode connecting wire, and the first length, the second length, the third length and the fourth length are dimensions in the first direction.

[0012] In an exemplary embodiment, a third length of the at least one eleventh anode connecting line is greater than a first length of the at least one first anode connecting line, and a fourth length of the at least one twelfth anode connecting line is greater than a second length of the at least one second anode connecting line.

[0013] In an exemplary embodiment, the material of the anode connecting line is a metal material, or the material of the anode connecting line is a transparent conductive material.

[0014] In an exemplary embodiment, the first light-emitting device and the second light-emitting device each include an anode, the anode of at least one second light-emitting device is connected to at least one second pixel driving circuit through the anode connecting line, the shape of at least one anode connecting line is a straight line or a broken line extending along the first direction, and the orthographic projection of at least one anode connecting line on the substrate at least partially overlaps with the orthographic projection of the anode of at least one first light-emitting device on the substrate.

[0015] In an exemplary embodiment, the first region further includes at least one dummy connecting line, the at least one dummy connecting line being in the shape of a straight line or a broken line extending along the first direction, and the orthographic projection of the at least one dummy connecting line on the substrate at least partially overlaps with the orthographic projection of the anode of at least one first light-emitting device on the substrate.

[0016] In an exemplary embodiment, the first area includes at least a normal area and a connecting line area, the normal area is an area where the anode connecting line is not provided, and the connecting line area is an area where the anode connecting line is provided; the orthographic projection of at least one anode in the normal area on the substrate at least partially overlaps with the orthographic projection of K1 dummy connecting lines on the substrate, and the orthographic projection of at least one anode in the connecting line area on the substrate at least partially overlaps with the orthographic projections of K2 dummy connecting lines and K3 anode connecting lines on the substrate, K1=K2+K3, and K1, K2 and K3 are all positive integers greater than or equal to 1.

[0017] In an exemplary embodiment, the arrangement of the dummy connecting lines in the normal area is the same as the arrangement of the dummy connecting lines and the anode connecting lines in the connecting line area, and the arrangement is any one or more of the following: the position of the connecting lines in the second direction, the width of the connecting lines, and the spacing between adjacent connecting lines, and the width and the spacing are the dimensions of the second direction.

[0018] In an exemplary embodiment, the routing density of the dummy connection lines in the normal area is the same as the routing density of the dummy connection lines and the anode connection lines in the connection line area, where the routing density is the area of ​​the connection lines per unit area.

[0019] In an exemplary embodiment, at least one dummy connection line is connected to at least one signal connection line through at least one routing connection line, the routing connection line is in the shape of a straight line or a broken line extending along the second direction, the routing connection line is arranged between two adjacent anodes in the first direction, and the orthographic projection of the routing connection line on the substrate does not overlap with the orthographic projection of the anode on the substrate.

[0020] In an exemplary embodiment, the shape of the signal connection line is a straight line or a broken line extending along the first direction; at least one signal connection line is connected to the first power line serving as the signal routing line and the main part of which extends along the second direction to form a mesh connectivity structure for transmitting the first power signal, and / or, at least one signal connection line is connected to the second power line serving as the signal routing line and the main part of which extends along the second direction to form a mesh connectivity structure for transmitting the second power signal, and / or, at least one signal connection line is connected to the initial signal line serving as the signal routing line and the main part of which extends along the second direction to form a mesh connectivity structure for transmitting the initial signal.

[0021] In an exemplary embodiment, at least one gate driving device includes a plurality of gate driving circuits sequentially arranged and cascaded along the second direction, at least one gate driving circuit is connected to a first clock signal line and a second clock signal line, and the first clock signal line and the second clock signal line are in the shape of a straight line or a broken line extending along the second direction; in at least one second area, the orthographic projection of the first power line on the substrate at least partially overlaps with the orthographic projection of the first clock signal line and the second clock signal line on the substrate, and / or, the orthographic projection of the second power line on the substrate at least partially overlaps with the orthographic projection of the first clock signal line and the second clock signal line on the substrate, and / or, the orthographic projection of the initial signal line on the substrate at least partially overlaps with the orthographic projection of the first clock signal line and the second clock signal line on the substrate.

[0022] In an exemplary embodiment, in the second direction, at least one signal connection line is disposed between two gate driving circuits in cascade connection.

[0023] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0024] In yet another aspect, the present disclosure further provides a method for manufacturing a display substrate, the display substrate comprising a plurality of first regions and a plurality of second regions, the first regions and the second regions being strip-shaped and extending along a second direction, the plurality of first regions and the plurality of second regions being alternately arranged along the first direction, and the first direction and the second direction intersecting; the manufacturing method comprising:

[0025] A driving structure layer is formed on the substrate; the driving structure layer in the first area includes a plurality of pixel driving circuits, and the driving structure layer in the second area includes at least one gate driving device and / or at least one signal line;

[0026] A light-emitting structure layer is formed on the side of the driving structure layer away from the substrate; the light-emitting structure layer in the first area includes a plurality of first light-emitting devices, and the light-emitting structure layer in the second area includes a plurality of second light-emitting devices, at least one first light-emitting device in the first area is connected to at least one pixel driving circuit in the first area, and at least one second light-emitting device in the second area is connected to at least one pixel driving circuit in the first area.

[0027] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0029] FIG1 is a schematic structural diagram of a display device;

[0030] FIG2 is a schematic structural diagram of a display substrate;

[0031] FIG3A is a schematic diagram of a planar structure of a display area in a display substrate;

[0032] FIG3B is a schematic diagram of a planar structure of a display area in another display substrate;

[0033] FIG4 is a schematic diagram of a cross-sectional structure of a display area in a display substrate;

[0034] FIG5 is an equivalent circuit diagram of a pixel driving circuit;

[0035] FIG6 is a schematic structural diagram of a scan drive device;

[0036] FIG7 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0037] Figures 8 and 9 are enlarged views of area A in Figure 7;

[0038] FIG10 is a schematic diagram showing the connection between a pixel driving circuit and a light-emitting device according to an embodiment of the present disclosure;

[0039] FIG11 is a schematic diagram showing the connection between another pixel driving circuit and a light-emitting device according to an embodiment of the present disclosure;

[0040] FIG12 is a schematic diagram of a virtual driving circuit according to an exemplary embodiment of the present disclosure;

[0041] FIG13 is a schematic diagram of an anode connecting wire according to an exemplary embodiment of the present disclosure;

[0042] FIG14 is a schematic diagram of a second area arrangement according to an exemplary embodiment of the present disclosure;

[0043] FIG15 is an enlarged view of area D in FIG14 ;

[0044] FIG16 is an enlarged view of area E in FIG14 ;

[0045] 17 and 18 are schematic diagrams of a gate lead according to an exemplary embodiment of the present disclosure.

[0046] DESCRIPTION OF NUMERALS: 10—first region; 10A—first side region; 10B—second side region; 10-1—normal region; 10-2—connection line region; 20—second region; 20A—first side repeating unit; 20B—second side repeating unit; 30—anode connection line; 31—first anode connection line; 32—second anode connection line; 33—third anode connection line; 34—fourth anode connection line; 40—anode; 41—dummy connection line; 42—routing connection line; 50—signal connection line; 60—signal routing line; 61—first power line; 62—second power line; 63—initial signal line; 64—data signal line; 80—integrated circuit; 81—gate lead line; 100—display region; 101—substrate; 102—driving structure layer; 103—light-emitting structure layer; 104—Packaging structure layer; 200—Binding area; 300—Border area. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0048] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0049] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0050] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0051] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0052] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0053] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0054] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0055] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0056] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0057] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They may be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, and may have some minor deformations due to tolerances, such as chamfers, rounded edges, and deformation. The term "approximately" in this disclosure does not strictly define the boundaries, but allows for values ​​within the range of process and measurement errors.

[0058] FIG1 is a schematic diagram of the structure of a display device. As shown in FIG1 , the display device may include a timing controller, a data driver, a scan driver, and a pixel array. The timing controller is connected to the data driver and the scan driver, respectively. The data driver is connected to a plurality of data signal lines (D1 to Dn), respectively. The scan driver is connected to a plurality of scan signal lines (S1 to Sm) and a plurality of emission signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driver circuit, which is connected to the scan signal lines, the emission signal lines, and the data signal lines, respectively. The light-emitting unit may include a light-emitting device, which is connected to the pixel driver circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, and may provide a clock signal, a scan start signal, an emission stop signal, etc. suitable for the specifications of the scan driver to the scan driver. The data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a per-pixel basis, where n can be a natural number. The scan driver can include at least one scan signal driver and at least one light-emitting signal driver. The scan signal driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller. For example, the scan signal driver can sequentially provide scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan signal driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next-level circuit under the control of a clock signal. m can be a natural number. The light emitting signal driver can generate an emission signal to be provided to the light emitting signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the light emitting signal driver can sequentially provide an emission signal having an off-level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting signal driver can be configured in the form of a shift register and can generate an emission signal in a manner that sequentially transmits the emission stop signal provided in the form of an off-level pulse to the next stage circuit under the control of a clock signal. o can be a natural number. In an exemplary embodiment, the pixel array can be provided on a display substrate.

[0059] Figure 2 is a schematic diagram of the structure of a display substrate. As shown in Figure 2, the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a border area 300 located on the other side of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area including a plurality of sub-pixels Pxij that form a pixel array. The plurality of sub-pixels Pxij are configured to display dynamic images or still images. The display area 100 may be referred to as an active area (AA). In an exemplary embodiment, the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as being curled, bent, folded, or rolled up.

[0060] In an exemplary embodiment, the binding area 200 may include a lead area, a bending area, a driver chip area, and a binding pin area arranged in sequence along a direction away from the display area. The lead area is connected to the display area 100 and includes at least a data lead. The bending area is connected to the lead area and may include at least a composite insulating layer provided with a groove, and the groove is configured to bend the binding area to the back of the display area. The driver chip area may include an integrated circuit (IC), which is configured to be connected to a plurality of data lead lines. The binding pin area may include a bonding pad, which is configured to be bonded and connected to an external flexible printed circuit (FPC).

[0061] In an exemplary embodiment, the frame area 300 may include a circuit area, a power line area, a crack dam area, and a cutting area, which are sequentially arranged in a direction away from the display area 100. The circuit area is connected to the display area 100 and may include at least a gate drive device, which is connected to the scanning signal line and the light-emitting signal line in the display area 100. The power line area is connected to the region and may include at least a frame power lead, which extends in a direction parallel to the edge of the display area and is connected to the cathode in the display area 100. The crack dam area is connected to the power line area and may include at least a plurality of cracks provided on the composite insulating layer. The cutting area is connected to the crack dam area and may include at least a cutting groove provided on the composite insulating layer. The cutting groove is configured so that after all the film layers of the display substrate are prepared, the cutting equipment performs cutting along the cutting groove respectively.

[0062] In an exemplary embodiment, the lead line area in the binding area 200 and the power line area in the border area 300 can be provided with an isolation dam, and the isolation dam can extend in a direction parallel to the edge of the display area to form an annular structure surrounding the display area 100. The edge of the display area is the edge of one side of the display area binding area or the border area.

[0063] FIG3A is a schematic diagram of a planar structure of a display area in a display substrate. As shown in FIG3A , the display area may include a plurality of pixel units F arranged in a matrix, and at least one pixel unit F may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a light-emitting signal line, and a data signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit may include a light-emitting device connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0064] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 and the fourth subpixel P4 may be green subpixels (G) that emit green light, and the third subpixel P3 may be a blue subpixel (B) that emits blue light. In an exemplary embodiment, the subpixels may be rectangular, diamond, pentagonal, or hexagonal in shape, and the four subpixels may be arranged in an RGBG pattern.

[0065] Figure 3B is a schematic diagram of the planar structure of the display area in another display substrate. As shown in Figure 3B , the pixel unit F may include three sub-pixels: the first sub-pixel P1 may be a red sub-pixel emitting red light, the second sub-pixel P2 may be a green sub-pixel emitting green light, and the third sub-pixel P3 may be a blue sub-pixel emitting blue light. The three sub-pixels may be arranged in a Real RGB manner.

[0066] In other exemplary embodiments, three sub-pixels or four sub-pixels may be arranged in parallel horizontally or vertically, and the present disclosure does not limit this.

[0067] Figure 4 is a schematic cross-sectional view of the display region within a display substrate, illustrating the structure of four sub-pixels within the display region. As shown in Figure 4, in a plane perpendicular to the display substrate, the display region may include a drive structure layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on a side of the drive structure layer 102 facing away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light-emitting structure layer 103 facing away from the substrate 101. In some possible implementations, the display region may include other film layers, such as a touch-sensitive structure layer, which is not limited in this disclosure.

[0068] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving structure layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit. The light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include a light-emitting device, which may include at least an anode, an organic light-emitting layer and a cathode, the anode being connected to the pixel driving circuit, the organic light-emitting layer being connected to the anode, and the cathode being connected to the organic light-emitting layer, and the organic light-emitting layer emitting light of corresponding colors under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0069] Figure 5 is an equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in Figure 5, the pixel driving circuit can adopt a 7T2C structure, including 7 transistors (first transistor T1 to seventh transistor T7) and 2 capacitors (first capacitor C1 and second capacitor C2), and the pixel driving circuit is respectively connected to 9 signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, light emitting signal line EM, reference signal line REF, initial signal line INIT, data signal line DATA, and first power line VDD).

[0070] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the second electrode of the first transistor T1, the first electrode of the sixth transistor T6, and the gate electrode of the third transistor T3, respectively; the second node N2 is connected to the second electrode of the fourth transistor T4, the second electrode of the sixth transistor T6, and the second end of the second capacitor C2, respectively; the third node N3 is connected to the second electrode of the third transistor T3, the second electrode of the seventh transistor T7, and the second end of the first capacitor C1, respectively; and the fourth node N4 is connected to the second electrode of the second transistor T2, the first end of the first capacitor C1, and the first end of the second capacitor C2, respectively.

[0071] In an exemplary embodiment, the first transistor T1 may be referred to as a first reset transistor, a gate electrode of the first transistor T1 is connected to the first scan signal line S1, a first electrode of the first transistor T1 is connected to the reference signal line REF, and a second electrode of the first transistor T1 is connected to the first node N1.

[0072] In an exemplary embodiment, the second transistor T2 may be referred to as a second reset transistor, a gate electrode of the second transistor T2 is connected to the first scan signal line S1 , a first electrode of the second transistor T2 is connected to the reference signal line REF, and a second electrode of the second transistor T2 is connected to the fourth node N4 .

[0073] In an exemplary embodiment, the third transistor T3 may be referred to as a driving transistor, a gate electrode of the third transistor T3 is connected to the first node N1, a first electrode of the third transistor T3 is connected to the second electrode of the fifth transistor T5, and a second electrode of the third transistor T3 is connected to the third node N3.

[0074] In an exemplary embodiment, the fourth transistor T4 may be referred to as a data writing transistor, a gate electrode of the fourth transistor T4 is connected to the third scan signal line S3 , a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the second node N2 .

[0075] In an exemplary embodiment, the fifth transistor T5 can be referred to as a light emitting control transistor, a gate electrode of the fifth transistor T5 is connected to the light emitting signal line EM, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the first electrode of the third transistor T3.

[0076] In an exemplary embodiment, the sixth transistor T6 may be referred to as a data control transistor, a gate electrode of the sixth transistor T6 is connected to the fourth scan signal line S4 , a first electrode of the sixth transistor T6 is connected to the first node N1 , and a second electrode of the sixth transistor T6 is connected to the second node N2 .

[0077] In an exemplary embodiment, the seventh transistor T7 may be referred to as a third reset transistor, a gate electrode of the seventh transistor T7 is connected to the second scan signal line S2 , a first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and a second electrode of the seventh transistor T7 is connected to the third node N3 .

[0078] In an exemplary embodiment, a first electrode of the light-emitting device EL is connected to the third node N3, and a second electrode of the light-emitting device EL is connected to the second power supply line VSS. The light-emitting device EL may be an OLED including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0079] In an exemplary embodiment, the first power line VDD is configured to provide a constant first voltage signal to the pixel driving circuit, and the second power line VSS is configured to provide a constant second voltage signal to the light-emitting device, wherein the first voltage signal is a high-level signal and the second voltage signal is a low-level signal. The reference signal line and the initial voltage signal may be constant voltage signals, which are not limited in this disclosure.

[0080] In an exemplary embodiment, the seven transistors of the pixel driving circuit may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the seven transistors of the pixel driving circuit may include P-type transistors and N-type transistors.

[0081] In an exemplary embodiment, the seven transistors of the pixel driving circuit may be low-temperature polysilicon thin-film transistors, or may be oxide thin-film transistors, or may be low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, while oxide thin-film transistors have the advantages of high electron mobility, low operating voltage, and low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate to form an LTPO (Low Temperature Polycrystalline + Oxide) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0082] FIG6 is a schematic diagram of the structure of a scan drive device. In an exemplary embodiment, the scan drive device may include a gate drive device (scan signal driver) that provides a scan signal and a gate drive device (luminous signal driver) that provides a light-emitting control signal. The gate drive device may include multiple cascaded gate drive circuits (GOA circuits), the GOA circuits convert clock signals into on / off voltages and output them to the display area respectively. The multi-level GOA circuits are connected to the scan signal lines or light-emitting signal lines in multiple unit rows, and the turn-on voltages are output in sequence by each GOA circuit to achieve row-by-row scanning of multiple unit rows in the display area. As shown in FIG6 , the gate drive device may include a first-level GOA circuit, a second-level GOA circuit, a third-level GOA circuit, ..., and the first-level GOA circuit may generate a scan signal OUT1 based on the initial signal provided by the initial signal line STV, the clock signal provided by the clock signal line CLK / CLKB, and the signal provided by the high-level signal line VGH / low-level signal line VGL, and provide it to the pixel drive circuit of the first unit row in the display area. The i-th level GOA circuit can generate a scanning signal OUTi based on the scanning signal OUTi-1 generated by the i-1-th level GOA circuit, the first clock signal provided by the first clock signal line CLK, the second clock signal provided by the second clock signal line CLKB, the high-level signal provided by the high-level signal line VGH, and the low-level signal provided by the low-level signal line VGL, and provide it to the pixel driving circuit of the i-th unit row in the display area, where i is a positive integer greater than 1.

[0083] At present, as the resolution of display devices gradually increases, and in order to ensure the reliability and functionality of the border area, the border width of existing display devices is about 1.5mm or more. Resolution (Pixels Per Inch, abbreviated as PPI) refers to the number of pixel units per unit area, which can be called pixel density. The higher the PPI value, the higher the density at which the display device can display the picture, and the richer the details of the picture. Since the resolution increase not only requires an increase in the number of gate drive circuits in the border area, thereby increasing the occupied area of ​​the gate drive circuit, but also requires an increase in the width of the power lead in the border area to reduce the impedance and voltage drop of the power lead and ensure the uniformity of the display brightness. Therefore, for the structure of setting the gate drive circuit in the border area, it is more difficult to reduce the border width.

[0084] In order to effectively reduce the border width of the display device and achieve a narrow border of the display device, an exemplary embodiment of the present disclosure provides a display substrate in which a gate driver is arranged in a display area (Gate Driver In AA, abbreviated as GIA). In an exemplary embodiment, the display substrate may include at least a display area and a border area located on at least one side of the display area. The display area may include a plurality of first areas and a plurality of second areas. The shapes of the first and second areas may be strips extending along the second direction. The plurality of first areas and the plurality of second areas may be alternately arranged along the first direction, and the first and second directions intersect. In a direction perpendicular to the display substrate, the display area may include a driving structure layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving structure layer away from the substrate. The driving structure layer in the first area may include a plurality of pixel driving circuits, the driving structure layer in the second area may include at least one gate driver and / or at least one signal trace, and the light-emitting structure layers in the first and second areas may include a plurality of light-emitting devices; at least one light-emitting device in the first area is connected to at least one pixel driving circuit in the first area, and at least one light-emitting device in the second area is connected to at least one pixel driving circuit in the first area.

[0085] In an exemplary embodiment, the driving structure layer of the first area may include a plurality of circuit repetition units, the orthographic projection of the circuit repetition unit on the substrate having a first area, the light-emitting structure layer of the first area may include a plurality of light-emitting repetition units, the orthographic projection of the light-emitting repetition unit on the substrate having a second area, and the ratio of the first area to the second area is 0.95 to 1.05; at least one circuit repetition unit may include M+m pixel driving circuits, and at least one light-emitting repetition unit may include M first light-emitting devices; M is an integer multiple of 2 or an integer multiple of 3, and m is a positive integer greater than or equal to 1.

[0086] In an exemplary embodiment, the light emitting structure layer of the second region may include a first side repeating unit and a second side repeating unit, each of the first side repeating unit and the second side repeating unit including N light emitting devices, where N is an integer multiple of 3 or an integer multiple of 4.

[0087] In an exemplary embodiment, the pixel driving circuit in at least one circuit repetition unit may include at least a first pixel driving circuit and a second pixel driving circuit, the light-emitting device in at least one light-emitting repetition unit may include a first light-emitting device, and the light-emitting device in at least one second repetition unit may include a second light-emitting device; at least one first pixel driving circuit is connected to at least one first light-emitting unit, and the orthographic projection of at least one first pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of at least one first light-emitting device on the substrate; at least one second pixel driving circuit is connected to at least one second light-emitting device through an anode connection line, and the orthographic projection of at least one second pixel driving circuit on the substrate does not overlap with the orthographic projection of at least one second light-emitting device on the substrate.

[0088] In an exemplary embodiment, the first light-emitting device and the second light-emitting device each include an anode, the anode of at least one second light-emitting device is connected to at least one second pixel driving circuit through the anode connecting line, the shape of at least one anode connecting line is a straight line or a broken line extending along the first direction, and the orthographic projection of at least one anode connecting line on the substrate at least partially overlaps with the orthographic projection of the anode of at least one first light-emitting device on the substrate.

[0089] In an exemplary embodiment, the driving structure layer of the first area further includes at least one dummy connecting line, the at least one dummy connecting line is in the shape of a straight line or a broken line extending along the first direction, and the orthographic projection of the at least one dummy connecting line on the substrate at least partially overlaps with the orthographic projection of the anode of at least one first light-emitting device on the substrate.

[0090] In an exemplary embodiment, the first area includes at least a normal area and a connecting line area, the normal area is an area where the anode connecting line is not provided, and the connecting line area is an area where the anode connecting line is provided; the orthographic projection of at least one anode in the normal area on the substrate at least partially overlaps with the orthographic projection of K1 dummy connecting lines on the substrate, and the orthographic projection of at least one anode in the connecting line area on the substrate at least partially overlaps with the orthographic projections of K2 dummy connecting lines and K3 anode connecting lines on the substrate, K1=K2+K3, and K1, K2 and K3 are all positive integers greater than or equal to 1.

[0091] Figure 7 is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure. As shown in Figure 7, the display substrate may include at least a display area and a frame area located on at least one side of the display area, in a plane parallel to the display substrate. The display area may include a plurality of first regions 10 and a plurality of second regions 20. Each of the first regions 10 and the second regions 20 may be in the form of strips extending along a second direction Y. The plurality of first regions 10 and the plurality of second regions 20 may be arranged alternately along a first direction X, forming a GIA structure, with the first direction X and the second direction Y intersecting.

[0092] In an exemplary embodiment, the widths of the plurality of first regions 10 may be substantially the same, the widths of the plurality of second regions 20 may be substantially the same, the widths of the first regions 10 and the widths of the second regions 20 may be different, and the widths may be dimensions in the first direction X. For example, the width of at least one first region 10 may be greater than the width of at least one second region 20.

[0093] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display area may include a driving structure layer disposed on the substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate. The driving structure layer of the first area 10 may include a plurality of circuit units, each of which may include at least a pixel driving circuit, and the driving structure layer of the second area 20 may include a gate driving device and / or a signal trace. The light-emitting structure layer of the first area 10 may include a plurality of first light-emitting units, each of which may include at least a first light-emitting device, and the light-emitting structure layer of the second area 20 may include a plurality of second light-emitting units, each of which may include at least a second light-emitting device. The pixel driving circuit of the first area 10 is configured to provide a driving signal to the first light-emitting device in the first area 10 and the second light-emitting device in the second area 20 to drive the corresponding first light-emitting device and the second light-emitting device to emit light.

[0094] In the exemplary embodiment, the circuit unit referred to in this disclosure refers to an area divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to an area divided according to the light-emitting device. In the exemplary embodiment, the positions of the light-emitting unit and the circuit unit may correspond, or the positions of the light-emitting unit and the circuit unit may not correspond, and this disclosure is not limited here. In the following description, the position, shape, and size of the pixel driving circuit are equivalent to the position, shape, and size of the circuit unit, and the position, shape, and size of the light-emitting device are equivalent to the position, shape, and size of the light-emitting unit.

[0095] In an exemplary embodiment, the driving structure layer of at least one first region 10 may include a plurality of circuit repeating units. The circuit repeating unit is a basic unit constituting the driving structure layer of the first region 10, and the driving structure layer of the first region 10 may be constituted by repeating and continuously arranging the circuit repeating units along the first direction X and the second direction Y.

[0096] In an exemplary embodiment, the light emitting structure layer of at least one first region 10 may include a plurality of light emitting repeating units. The light emitting repeating unit is a basic unit constituting the light emitting structure layer of the first region 10, and the light emitting structure layer of the first region 10 may be constituted by repeating and continuously arranging the light emitting repeating unit along the first direction X and the second direction Y.

[0097] In an exemplary embodiment, in at least one first region 10, the positions of the plurality of circuit repeating units and the plurality of light-emitting repeating units may correspond one to one, the orthographic projection of at least one circuit repeating unit on the substrate may have a first area, the orthographic projection of at least one light-emitting repeating unit on the substrate may have a second area, and the ratio of the first area to the second area may be approximately 0.95 to 1.05, that is, the area of ​​the orthographic projection of the circuit repeating unit on the substrate and the area of ​​the orthographic projection of the light-emitting repeating unit on the substrate may be substantially the same.

[0098] In an exemplary embodiment, the size of at least one circuit repeating unit in the first direction X and the size of at least one light emitting repeating unit in the first direction X may be substantially the same, and the size of at least one circuit repeating unit in the second direction Y and the size of at least one light emitting repeating unit in the second direction Y may be substantially the same.

[0099] In an exemplary embodiment, at least one circuit repetition unit may include M+m pixel driving circuits arranged in sequence along the first direction X, and at least one light-emitting repetition unit may include M first light-emitting devices arranged in sequence along the first direction X, that is, the area of ​​the M+m pixel driving circuits projected on the substrate is substantially the same as the area of ​​the M first light-emitting devices projected on the substrate.

[0100] In an exemplary embodiment, in at least one circuit repeating unit, the sizes of the multiple pixel driving circuits may be substantially the same. In the present disclosure, the size of the pixel driving circuit refers to the size of the orthographic projection of the pixel driving circuit on the substrate. When the orthographic projection of the pixel driving circuit on the substrate is rectangular, the size may include any one or more of the following: the length of the orthographic projection in the first direction X, the length of the orthographic projection in the second direction Y, and the area of ​​the orthographic projection. When the orthographic projection of the pixel driving circuit on the substrate is circular or elliptical, the size may include any one or more of the following: the radius of the orthographic projection, the major axis and minor axis of the orthographic projection, and the area of ​​the orthographic projection.

[0101] In an exemplary embodiment, the dimensions of the multiple first light-emitting devices in at least one light-emitting repeating unit may be substantially the same. In this disclosure, the dimensions of a light-emitting device refer to the dimensions of the orthographic projection of the light-emitting device on the substrate. When the orthographic projection of the light-emitting device on the substrate is rectangular, the dimensions may include any one or more of the following: the length of the orthographic projection in the first direction X, the length of the orthographic projection in the second direction Y, and the area of ​​the orthographic projection. When the orthographic projection of the light-emitting device on the substrate is circular or elliptical, the dimensions may include any one or more of the following: the radius of the orthographic projection, the major and minor axes of the orthographic projection, and the area of ​​the orthographic projection.

[0102] In an exemplary embodiment, in at least one first region 10, the driving structure layer may be arranged in a compressed manner to provide a pixel driving circuit, while the light-emitting structure layer may be arranged in a normal (non-compressed) manner to provide a first light-emitting device. For example, in a normal manner, one circuit repeating unit may be provided with M pixel driving circuits, and one light-emitting repeating unit may be provided with M first light-emitting devices. In a compressed manner, the number of pixel driving circuits provided in the circuit repeating unit may be increased by adopting lateral compression. On the basis of the previously provided M pixel driving circuits, m pixel driving circuits are added, so that M+m pixel driving circuits may be provided in one circuit repeating unit. Since the light-emitting structure layer adopts a normal manner, M first light-emitting devices are still provided in the light-emitting repeating unit, and the area occupied by the M+m pixel driving circuits is substantially the same as the area occupied by the M first light-emitting devices.

[0103] In an exemplary embodiment, for a pixel arrangement of Real RGB, M may be an integer multiple of 3, such as 3, 6, 9, 12, 15, or 18, and m may be a positive integer greater than or equal to 1, such as 1, 2, or 3.

[0104] In an exemplary embodiment, for the pixel arrangement being an RGGB arrangement, M may be an integer multiple of 2, such as 2, 4, 6, 8, 10, or 12, and m may be a positive integer greater than or equal to 1, such as 1, 2, or 3.

[0105] In an exemplary embodiment, a light emitting repetition unit may include 18 first light emitting devices sequentially arranged along the first direction X, and a circuit repetition unit may include 21 pixel driving circuits sequentially arranged along the first direction X, that is, M=18, m=3.

[0106] In another exemplary embodiment, a light emitting repetition unit may include 6 first light emitting devices sequentially arranged along the first direction X, and a circuit repetition unit may include 7 pixel driving circuits sequentially arranged along the first direction X, that is, M=6, m=1.

[0107] In an exemplary embodiment, the light emitting structure layer of the at least one second region 20 may include a first side repeating unit and a second side repeating unit, each of which may include N second light emitting devices sequentially arranged along the first direction X.

[0108] In an exemplary embodiment, for a pixel arrangement of Real RGB, N may be an integer multiple of 3, such as 3, 6, 9, or 12.

[0109] In an exemplary embodiment, for the pixel arrangement being an RGGB arrangement, N may be an integer multiple of 4, such as 4, 8, 12, or 16.

[0110] In an exemplary embodiment, the size of the second light-emitting device in the second area 20 can be substantially the same as the size of the first light-emitting device in the first area 10, and the arrangement of the plurality of second light-emitting devices in the second area 20 can be substantially the same as the arrangement of the plurality of first light-emitting devices in the first area 10.

[0111] In an exemplary embodiment, in at least one second region 20, the first side repeating unit and the second side repeating unit may each include 6 second light-emitting devices arranged in sequence along the first direction X, that is, the light-emitting structure layer of the second region 20 includes 12 second light-emitting devices arranged in sequence along the first direction X.

[0112] In an exemplary embodiment, the driving structure layer of the second area 20 is provided with a gate driving device and / or signal routing, but no pixel driving circuit is provided. The second light-emitting device of the second area 20 needs to be connected to the pixel driving circuit in the first area 10 through an anode connecting line.

[0113] Figures 8 and 9 are enlarged views of region A in Figure 7 . Figure 8 illustrates the structure of the driving structure layer in region A, and Figure 9 illustrates the structure of the light-emitting structure layer in region A. As shown in Figures 8 and 9 , the multiple pixel driving circuits in the first region 10 may include a first pixel driving circuit Q1 and a second pixel driving circuit Q2. The first region 10 includes a plurality of first light-emitting devices F1, and the second region 20 includes a plurality of second light-emitting devices F2.

[0114] In an exemplary embodiment, at least one first pixel driving circuit Q1 in the first area 10 is connected to at least one first light-emitting unit F1 in the first area 10, and the orthographic projection of the at least one first pixel driving circuit Q1 on the substrate at least partially overlaps with the orthographic projection of the at least one first light-emitting device F1 on the substrate. The first pixel driving circuit Q1 is configured to provide a driving signal to the connected first light-emitting device F1 to drive the corresponding first light-emitting device F1 to emit light. In some examples, the relationship between the multiple first pixel driving circuits Q1 and the multiple first light-emitting devices F1 can be one-to-one, that is, one first pixel driving circuit Q1 can be connected to one first light-emitting device F1 and configured to drive the connected first light-emitting device F1 to emit light; or, the relationship between the multiple first pixel driving circuits Q1 and the multiple first light-emitting devices F1 can be one-to-many, that is, one first pixel driving circuit Q1 can be connected to multiple first light-emitting devices F1 and configured to drive the connected multiple first light-emitting devices F1 to emit light; or, the relationship between the multiple first pixel driving circuits Q1 and the multiple first light-emitting devices F1 can be many-to-one, that is, multiple first pixel driving circuits Q1 can be connected to one first light-emitting device F1 and configured to drive the first light-emitting device F1 to emit light.

[0115] In an exemplary embodiment, at least one second pixel driving circuit Q2 in the first area 10 is connected to at least one second light-emitting device F2 in the second area 20 through an anode connecting line, and the orthographic projection of the at least one second pixel driving circuit Q2 on the substrate does not overlap with the orthographic projection of the at least one second light-emitting device F2 on the substrate. The second pixel driving circuit Q2 is configured to provide a driving signal to the connected second light-emitting device F2 to drive the corresponding second light-emitting device F2 to emit light. In some examples, the relationship between the multiple second pixel driving circuits Q2 and the multiple second light-emitting devices F2 can be one-to-one, that is, one second pixel driving circuit Q2 can be connected to one second light-emitting device F2 and configured to drive the connected second light-emitting device F2 to emit light; or, the relationship between the multiple second pixel driving circuits Q2 and the multiple second light-emitting devices F2 can be one-to-many, that is, one second pixel driving circuit Q2 can be connected to multiple second light-emitting devices F2 and configured to drive the connected multiple second light-emitting devices F2 to emit light; or, the relationship between the multiple second pixel driving circuits Q2 and the multiple second light-emitting devices F2 can be many-to-one, that is, multiple second pixel driving circuits Q2 can be connected to one second light-emitting device F2 and configured to drive the second light-emitting device F2 to emit light.

[0116] In an exemplary embodiment, the sizes of the first and second pixel driving circuits Q1 and Q2 may be substantially the same, and the sizes of the first and second light emitting devices F1 and F2 may be substantially the same.

[0117] In an exemplary embodiment, the driving structure layer of the second region 20 may include at least one gate driving device, or may include at least one signal trace, or may include at least one gate driving device and at least one signal trace.

[0118] In an exemplary embodiment, the at least one gate driver may include any one or more of the following: a first gate driver that outputs a first scan signal line S1, a second gate driver that outputs a second scan signal line S2, a third gate driver that outputs a third scan signal line S3, a fourth gate driver that outputs a fourth scan signal line S4, and a fifth gate driver that outputs an emission signal line EM. The at least one signal trace may include any one or more of the following: a first power line, a second power line, and an initial signal line.

[0119] Figure 10 is a schematic diagram illustrating the connection between a pixel driving circuit and a light-emitting device according to an exemplary embodiment of the present disclosure, and is an enlarged view of region B in Figure 7 . As shown in Figure 10 , a second region 20 may be located between two first regions 10. The two first regions 10 may include a first side region 10A located on the opposite side of the second region 20 in the first direction X, and a second side region 10B located on the opposite side of the second region 20 in the first direction X. The second region 20 may have a first centerline O1, which may be a straight line bisecting the second region 20 in the first direction X and extending along the second direction Y. The second region 20 may include at least a first side repeating unit 20A located on the opposite side of the first centerline O1 in the first direction X, and a second side repeating unit 20B located on the opposite side of the first centerline O1 in the first direction X. At least one second light-emitting device F2 in the first side repeating unit 20A can be connected to at least one second pixel driving circuit Q2 in the first side area 10A through an anode connecting line, and at least one second light-emitting device F2 in the second side repeating unit 20B can be connected to at least one second pixel driving circuit Q2 in the second side area 10B through an anode connecting line. That is, the second light-emitting devices F2 and the second pixel driving circuit Q2 located on the same side of the first center line O1 are correspondingly connected.

[0120] In an exemplary embodiment, the driving structure layer of the first region 10 is provided with a plurality of circuit repetition units, the light-emitting structure layer of the first region 10 is provided with a plurality of light-emitting repetition units, the driving structure layer of the second region 20 is provided with a gate driving device and / or signal routing (not shown), and the light-emitting structure layer of the second region 20 is provided with a first side repetition unit 20A and a second side repetition unit 20B.

[0121] In an exemplary embodiment, the driving structure layer of the first side region 10A may include at least a first circuit repeating unit 201 and a second circuit repeating unit 202. The first circuit repeating unit 201 may be located on a side of the second region 20 opposite to the first direction X, and the second circuit repeating unit 202 may be located on a side of the first circuit repeating unit 201 away from the second region 20. The driving structure layer of the second side region 10B may include at least an eleventh circuit repeating unit 211 and a twelfth circuit repeating unit 212. The eleventh circuit repeating unit 211 may be located on a side of the second region 20 in the first direction X, and the twelfth circuit repeating unit 212 may be located on a side of the eleventh circuit repeating unit 211 away from the second region 20.

[0122] In an exemplary embodiment, the first circuit repetition unit 201, the second circuit repetition unit 202, the eleventh circuit repetition unit 211, and the twelfth circuit repetition unit 212 may each include 18 first pixel driving circuits Q1 and 3 second pixel driving circuits Q2. In at least one circuit repetition unit, the 18 first pixel driving circuits Q1 may be arranged sequentially along the first direction X, and the 3 second pixel driving circuits Q2 may be arranged on one side of the first pixel driving circuit Q1 in the first direction X.

[0123] In an exemplary embodiment, since the second pixel driving circuit Q2 in the circuit repetition unit is located on one side of the first pixel driving circuit Q1 in the first direction X, the position of the second pixel driving circuit Q2 in the first circuit repetition unit 201 and the position of the second pixel driving circuit Q2 in the eleventh circuit repetition unit 211 are asymmetric relative to the first center line O1, and the position of the second pixel driving circuit Q2 in the second circuit repetition unit 202 and the position of the second pixel driving circuit Q2 in the twelfth circuit repetition unit 212 are asymmetric relative to the first center line O1.

[0124] In an exemplary embodiment, the light-emitting structure layer of the first side region 10A may include at least a first light-emitting repeating unit 301 and a second light-emitting repeating unit 302, the first light-emitting repeating unit 301 may be located on the side of the second region 20 opposite to the first direction X, and the second light-emitting repeating unit 302 may be located on the side of the first light-emitting repeating unit 301 away from the second region 20. The light-emitting structure layer of the second side region 10B may include at least an eleventh light-emitting repeating unit 311 and a twelfth light-emitting repeating unit 312, the eleventh light-emitting repeating unit 311 may be located on the side of the second region 20 in the first direction X, and the twelfth light-emitting repeating unit 312 may be located on the side of the eleventh light-emitting repeating unit 311 away from the second region 20.

[0125] In an exemplary embodiment, the first light-emitting repeating unit 301, the second light-emitting repeating unit 302, the eleventh light-emitting repeating unit 311, and the twelfth light-emitting repeating unit 312 may each include 18 first light-emitting devices F1. The first light-emitting devices F1 may include red light-emitting devices, green light-emitting devices, and blue light-emitting devices, and the red light-emitting devices, green light-emitting devices, and blue light-emitting devices may be periodically arranged along the first direction X.

[0126] In an exemplary embodiment, the first side repeating unit 20A and the second side repeating unit 20B in the second region 20 may each include six second light-emitting devices F2. The second light-emitting devices F2 may include red, green, and blue light-emitting devices, and the red, green, and blue light-emitting devices may be periodically arranged along the first direction X.

[0127] In an exemplary embodiment, in at least one first region 10, the position of a circuit repetition unit corresponds one-to-one to the position of a light-emitting repetition unit, and the size of the circuit repetition unit is substantially the same as the size of the light-emitting repetition unit, which is equivalent to the area occupied by 21 pixel driving circuits being substantially the same as the area occupied by 18 light-emitting devices.

[0128] In an exemplary embodiment, the position of the first circuit repetition unit 201 may correspond to the position of the first light-emitting repetition unit 301, the position of the second circuit repetition unit 202 may correspond to the position of the second light-emitting repetition unit 302, the position of the eleventh circuit repetition unit 211 may correspond to the position of the eleventh light-emitting repetition unit 311, and the position of the twelfth circuit repetition unit 212 may correspond to the position of the twelfth light-emitting repetition unit 312.

[0129] In an exemplary embodiment, in the corresponding circuit repetition unit and the light-emitting repetition unit, at least one first light-emitting device F1 is directly connected to at least one first pixel driving circuit Q1, and the orthographic projection of the at least one first light-emitting device F1 on the substrate at least partially overlaps with the orthographic projection of the at least one first pixel driving circuit Q1 on the substrate, and the first pixel driving circuit Q1 is configured to provide a driving signal to the connected first light-emitting device F1 to drive the corresponding first light-emitting device F1 to emit light.

[0130] In an exemplary embodiment, at least one second light-emitting device F2 in the second area 20 is connected to at least one second pixel driving circuit Q2 in the first area 10 via an anode connecting line, the orthographic projection of the at least one second light-emitting device F2 on the substrate does not overlap with the orthographic projection of the at least one second pixel driving circuit Q2 on the substrate, and the second pixel driving circuit Q2 is configured to provide a driving signal to the connected second light-emitting device F2 to drive the corresponding second light-emitting device F2 to emit light.

[0131] In an exemplary embodiment, the first side repeating unit 20A may include at least a first light-emitting device group and a second light-emitting device group sequentially arranged along the first direction X, and the second side repeating unit 20B may include at least a third light-emitting device group and a fourth light-emitting device group sequentially arranged along the first direction X. Each light-emitting device group may include three second light-emitting devices F2. The six second light-emitting devices F2 in the first and second light-emitting device groups may be connected to the six second pixel driving circuits Q2 in the first side region 10A, and the six second light-emitting devices F2 in the third and fourth light-emitting device groups may be connected to the six second pixel driving circuits Q2 in the second side region 10B.

[0132] In an exemplary embodiment, the position of the first light-emitting device group in the first side repeat unit 20A and the position of the fourth light-emitting device group in the second side repeat unit 20B may be mirror-symmetrical with respect to the first center line O1, and the position of the second light-emitting device group in the first side repeat unit 20A and the position of the third light-emitting device group in the second side repeat unit 20B may be mirror-symmetrical with respect to the first center line O1.

[0133] In an exemplary embodiment, the three second light-emitting devices F2 of the first light-emitting device group in the first side repetition unit 20A can be connected to the three second pixel driving circuits Q2 in the first circuit repetition unit 201 through the first anode connecting line 31, and the three second light-emitting devices F2 of the second light-emitting device group in the first side repetition unit 20A can be connected to the three second pixel driving circuits Q2 in the second circuit repetition unit 202 through the second anode connecting line 32.

[0134] In an exemplary embodiment, the three second light-emitting devices F2 of the third light-emitting device group in the second side repetition unit 20B can be connected to the three second pixel driving circuits Q2 in the eleventh circuit repetition unit 211 through the third anode connection line 33, and the three second light-emitting devices F2 of the fourth light-emitting device group in the second side repetition unit 20B can be connected to the three second pixel driving circuits Q2 in the twelfth circuit repetition unit 212 through the fourth anode connection line 34.

[0135] In an exemplary embodiment, since the second circuit repetition unit 202 is located on a side of the first circuit repetition unit 201 away from the second region 20, the distance between the second pixel driving circuit Q2 in the second circuit repetition unit 202 and the first center line O1 is greater than the distance between the second pixel driving circuit Q2 in the first circuit repetition unit 201 and the first center line O1, so that the second length of at least one second anode connecting line 32 is greater than the first length of at least one first anode connecting line 31, and the first length and the second length can be dimensions in the first direction X.

[0136] In an exemplary embodiment, since the twelfth circuit repetition unit 212 is located on a side of the eleventh circuit repetition unit 211 away from the second region 20, the distance between the second pixel driving circuit Q2 in the twelfth circuit repetition unit 212 and the first center line O1 is greater than the distance between the second pixel driving circuit Q2 in the eleventh circuit repetition unit 211 and the first center line O1, so that the fourth length of the at least one fourth anode connecting line 34 is greater than the third length of the at least one third anode connecting line 33. The third length and the fourth length may be dimensions in the first direction X.

[0137] In an exemplary embodiment, because the second pixel driving circuit Q2 in the circuit repetition unit is located on one side of the first pixel driving circuit Q1 in the first direction X, the distance between the second pixel driving circuit Q2 in the eleventh circuit repetition unit 211 and the first center line O1 is greater than the distance between the second pixel driving circuit Q2 in the first circuit repetition unit 201 and the first center line O1, and the distance between the second pixel driving circuit Q2 in the twelfth circuit repetition unit 212 and the first center line O1 is greater than the distance between the second pixel driving circuit Q2 in the second circuit repetition unit 202 and the first center line O1, resulting in a certain difference in the lengths of the anode connection lines on both sides of the second region 20, the third length of the at least one third anode connection line 33 is greater than the first length of the at least one first anode connection line 31, and the fourth length of the at least one fourth anode connection line 34 is greater than the second length of the at least one second anode connection line 32.

[0138] In an exemplary embodiment, the distance between the second pixel driving circuit Q2 in the second circuit repetition unit 202 and the first center line O1 can be greater than the distance between the second pixel driving circuit Q2 in the eleventh circuit repetition unit 211 and the first center line O1, and thus the second length of the at least one second anode connecting line 32 can be greater than the third length of the at least one third anode connecting line 33.

[0139] Figure 11 is a schematic diagram illustrating the connection between another pixel driver circuit and a light-emitting device according to an exemplary embodiment of the present disclosure, and is an enlarged view of region B in Figure 7 . The connection structure between the pixel driver circuit and the light-emitting device in this embodiment is substantially the same as that described in Figure 10 , except that the circuit repetition unit in this embodiment includes six first pixel driver circuits Q1 and one second pixel driver circuit Q2, and the light-emitting repetition unit includes six first light-emitting devices F1.

[0140] As shown in FIG11 , the driving structure layer of the first side region 10A may include at least a twenty-first circuit repeating unit 221, a twenty-second circuit repeating unit 222, a twenty-third circuit repeating unit 223, and a twenty-fourth circuit repeating unit 224, which are sequentially arranged in a direction away from the second region 202. The driving structure layer of the second side region 10B may include at least a thirty-first circuit repeating unit 231, a thirty-second circuit repeating unit 232, a thirty-third circuit repeating unit 233, a thirty-fourth circuit repeating unit 234, a thirty-fifth circuit repeating unit 235, and a thirty-sixth circuit repeating unit 236, which are sequentially arranged in a direction away from the second region 202.

[0141] In an exemplary embodiment, the twenty-first circuit repetition unit 221 to the twenty-fourth circuit repetition unit 224 and the thirty-first circuit repetition unit 231 to the thirty-sixth circuit repetition unit 236 may each include six first pixel driving circuits Q1 and one second pixel driving circuit Q2. In at least one circuit repetition unit, the six first pixel driving circuits Q1 may be arranged sequentially along the first direction X, and the one second pixel driving circuit Q2 may be arranged on one side of the first pixel driving circuit Q1 in the first direction X.

[0142] In this exemplary embodiment, because the second pixel driving circuit Q2 in the circuit repetition unit is located to one side of the first pixel driving circuit Q1 in the first direction X, the positions of the second pixel driving circuits Q2 in the circuit repetition units at corresponding positions on both sides of the second region are asymmetric relative to the first center line O1. For example, the position of the second pixel driving circuit Q2 in the twenty-first circuit repetition unit 221 and the position of the second pixel driving circuit Q2 in the thirty-first circuit repetition unit 231 are asymmetric relative to the first center line O1.

[0143] In an exemplary embodiment, the light emitting structure layer of the first side region 10A may include at least a twenty-first light emitting repeating unit 321, a twenty-second light emitting repeating unit 322, a twenty-third light emitting repeating unit 323, and a twenty-fourth light emitting repeating unit 324, which are sequentially arranged in a direction away from the second region 202. The light emitting structure layer of the second side region 10B may include at least a thirty-first light emitting repeating unit 331, a thirty-second light emitting repeating unit 332, a thirty-third light emitting repeating unit 333, a thirty-fourth light emitting repeating unit 334, a thirty-fifth light emitting repeating unit 335, and a thirty-sixth light emitting repeating unit 336, which are sequentially arranged in a direction away from the second region 202.

[0144] In an exemplary embodiment, the twenty-first to twenty-fourth light-emitting repeating units 321 to 324 and the thirty-first to thirty-sixth light-emitting repeating units 331 to 336 may each include six first light-emitting devices F1, and the first and second side repeating units 20A and 20B may each include six second light-emitting devices F2.

[0145] In an exemplary embodiment, the three second light-emitting devices F2 of the first light-emitting device group in the first side repetition unit 20A can be connected to the second pixel driving circuit Q2 in the twenty-first circuit repetition unit 221 to the twenty-third circuit repetition unit 223 through the first anode connection line 31, and the three second light-emitting devices F2 of the second light-emitting device group in the first side repetition unit 20A can be connected to the second pixel driving circuit Q2 in the twenty-fourth circuit repetition unit 224 to the twenty-sixth circuit repetition unit 2 through the second anode connection line 32.

[0146] In an exemplary embodiment, the three second light-emitting devices F2 of the third light-emitting device group in the second side repetition unit 20B can be connected to the second pixel driving circuit Q2 in the thirty-first circuit repetition unit 231 to the thirty-third circuit repetition unit 233 through the third anode connection line 33, and the three second light-emitting devices F2 of the fourth light-emitting device group in the second side repetition unit 20B can be connected to the second pixel driving circuit Q2 in the thirty-fourth circuit repetition unit 234 to the thirty-sixth circuit repetition unit 236 through the fourth anode connection line 34.

[0147] In an exemplary embodiment, the second length of the at least one second anode connecting wire 32 is greater than the first length of the at least one first anode connecting wire 31 , and the fourth length of the at least one fourth anode connecting wire 34 is greater than the third length of the at least one third anode connecting wire 33 .

[0148] In an exemplary embodiment, the third length of the at least one third anode connecting wire 33 is greater than the first length of the at least one first anode connecting wire 31 , and the fourth length of the at least one fourth anode connecting wire 34 is greater than the second length of the at least one second anode connecting wire 32 .

[0149] In an exemplary embodiment, the first anode connecting wire 31, the second anode connecting wire 32, the third anode connecting wire 33 and the fourth anode connecting wire 34 can be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) or molybdenum (Mo), etc., or can be made of alloy materials composed of metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), etc., and can be a single-layer structure, or can be a multi-layer composite structure, such as Ti / Al / Ti, etc.

[0150] In another exemplary embodiment, the first anode connection line 31, the second anode connection line 32, the third anode connection line 33, and the fourth anode connection line 34 can be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO). Because the ITO or IZO film is thin and transparent, it can improve anode flatness and reduce defects such as off-screen watermarks (mura).

[0151] In yet another exemplary embodiment, the plurality of anode connection lines may be provided in one conductive layer, or may be provided in two or more conductive layers, which is not limited in the present disclosure.

[0152] In an exemplary embodiment, the aforementioned light emitting device is connected to the pixel driving circuit through the anode connecting line, which means that the anode of the light emitting device is connected to the pixel driving circuit through the anode connecting line.

[0153] FIG12 is a schematic diagram of a dummy driving circuit according to an exemplary embodiment of the present disclosure, and is an enlarged view of region C in FIG7 . As shown in FIG12 , in at least one first region 10, the driving structure layer may include a plurality of first circuit units, a plurality of second circuit units, and at least one dummy circuit unit. The first circuit unit may include at least a first pixel driving circuit Q1, the second circuit unit may include at least a second pixel driving circuit Q2, and the dummy circuit unit may include at least a dummy driving circuit Q3.

[0154] In an exemplary embodiment, in at least one first region 10, the positions and structures of the first pixel driving circuit Q1 and the second pixel driving circuit Q2 are substantially the same as those in the aforementioned embodiment, and the structure, arrangement, and size of the virtual driving circuit Q3 may be substantially the same as those of the second pixel driving circuit Q2, except that the virtual driving circuit Q3 is not connected to any light-emitting device.

[0155] In an exemplary embodiment, among the multiple circuit repetition units in the first area, the second pixel driving circuit in a portion of the circuit repetition units is connected to the second light-emitting device in the second area located on the side opposite to the first direction X of the first area, and the second pixel driving circuit in another portion of the circuit repetition units is connected to the second light-emitting device in the second area located on the side of the first direction X of the first area, and in the remaining circuit repetition units, M pixel driving circuits are connected to the first light-emitting device in the corresponding light-emitting repeating units, and m pixel driving circuits serve as virtual driving circuits, which are neither connected to the first light-emitting device nor the second light-emitting device.

[0156] In an exemplary embodiment, in the first direction X, the dummy driving circuit Q3 may be disposed in a central position of the first region, on a side of the second pixel driving circuit Q2 away from the second region 20 .

[0157] FIG13 is a schematic diagram of an anode connection line according to an exemplary embodiment of the present disclosure. As shown in FIG13 , the first light-emitting device and the second light-emitting device may each include an anode. The aforementioned connection of the first light-emitting device to the first pixel driving circuit means that the anode of the first light-emitting device is connected to the first pixel driving circuit, and the aforementioned connection of the second light-emitting device to the second pixel driving circuit via the anode connection line means that the anode of the second light-emitting device is connected to the second pixel driving circuit via the anode connection line.

[0158] In an exemplary embodiment, the anodes of the light emitting structure layers in the first region 10 and the second region 20 may be arranged in a real RGB manner, or may be arranged in an RGBG manner, which is not limited in the present disclosure.

[0159] In an exemplary embodiment, the shape of the anode connection line 30 can be a straight line or a broken line with the main portion extending along the first direction X. The positive projection of the anode connection line 30 on the substrate at least partially overlaps with the positive projection of at least one anode 40 in the first region 10 on the substrate. The anode connection line 30 can serve as a horizontal connection line.

[0160] In this disclosure, "A extends along direction B" means that A can include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In the following description, "A extends along direction B" means "the main portion of A extends along direction B."

[0161] In an exemplary embodiment, the anode connection wires 30 may be arranged to be distributed as symmetrically as possible with respect to the anode 40 to ensure the flatness of the anode.

[0162] In an exemplary embodiment, at least one first region 10 may be provided with at least one dummy connecting line 41. The shape of the dummy connecting line 41 may be a straight line or a broken line with the main portion extending along the first direction X. The positive projection of the dummy connecting line 41 on the substrate at least partially overlaps with the positive projection of at least one anode 40 on the substrate. The dummy connecting line 41 is configured to improve the flatness of the anode. The dummy connecting line 41 can serve as another type of lateral connecting line.

[0163] In an exemplary embodiment, since the anode connecting wire 30 is provided in a portion of the first region 10, the first region 10 can be divided into a normal region 10-1 and a connecting wire region 10-2 in the first direction X according to the presence or absence of the anode connecting wire 30. The normal region 10-1 may be a region where the anode connecting wire 30 is not provided, and the connecting wire region 10-2 may be a region where the anode connecting wire 30 is provided.

[0164] In an exemplary embodiment, the orthographic projection of at least one anode 40 in the normal region 10 - 1 at least partially overlaps with the orthographic projections of K1 dummy connection lines 41 on the substrate, that is, the number of overlaps between one anode 40 in the normal region 10 - 1 and the transverse connection lines is K1.

[0165] In an exemplary embodiment, the orthographic projection of at least one anode 40 in the connecting line area 10-2 on the substrate at least partially overlaps with the orthographic projections of K2 dummy connecting lines 41 on the substrate, and the orthographic projection of the anode 40 on the substrate at least partially overlaps with the orthographic projections of K3 anode connecting lines 30 on the substrate, that is, the number of overlaps between one anode 40 in the connecting line area 10-2 and the lateral connecting lines is K2+K3.

[0166] In an exemplary embodiment, the number of overlaps between at least one anode 40 and the transverse connecting line in the normal area 10-1 and the number of overlaps between at least one anode 40 and the transverse connecting line in the connecting line area 10-2 may be substantially the same, i.e., K1=K2+K3, where K1, K2, and K3 are all positive integers greater than or equal to 1.

[0167] In an exemplary embodiment, the arrangement of the transverse connecting lines (dummy connecting lines) in the normal region 10-1 and the arrangement of the transverse connecting lines (dummy connecting lines and anode connecting lines) in the connecting line region 10-2 can be substantially the same. The arrangement can be any one or more of the following: the position of the transverse connecting lines in the second direction Y, the width of the transverse connecting lines, and the spacing between adjacent transverse connecting lines. In an exemplary embodiment, the width and spacing can be the dimensions in the second direction Y.

[0168] In an exemplary embodiment, the routing density of the horizontal connecting lines in the normal area 10-1 can be substantially the same as the routing density of the horizontal connecting lines in the connecting line area 10-2, and the routing density can be any one or more of the following: the area of ​​the horizontal connecting lines per unit area, the sum of the widths of multiple horizontal connecting lines per unit area, and the sum of the lengths of multiple horizontal connecting lines per unit area, where the length can be the dimension in the first direction X and the width can be the dimension in the second direction Y.

[0169] In an exemplary embodiment, since no anode connecting wires are provided in the normal area, while anode connecting wires are provided in the connecting wire area, there is a problem of uneven horizontal connecting wires under the anodes in the first area. The present disclosure provides dummy connecting wires in the first area so that the number of overlaps between multiple anodes and horizontal connecting wires in the normal area and the connecting wire area is substantially the same, which not only effectively improves the uniformity of the horizontal connecting wires under the anodes, but also effectively improves the flatness of the anodes, effectively improves color deviation, and improves display quality. In addition, by setting the arrangement of the horizontal connecting wires in the normal area and the connecting wire area to be substantially the same or similar, the routing density of the horizontal connecting wires in the normal area and the connecting wire area is substantially the same or similar, and it is less likely to have defects such as off-screen watermarks (Mura), thereby improving display quality.

[0170] In an exemplary embodiment, the dummy connection line 41 may be connected to the signal connection line 50 via a routing connection line 42. The shape of the signal connection line 50 may be a straight line or a broken line with a main portion extending along the first direction X, and the shape of the routing connection line 42 may be a straight line or a broken line with a main portion extending along the second direction Y. A first end of the routing connection line 42 is connected to the signal connection line 50, and a second end of the routing connection line 42 is connected to one or more dummy connection lines 41.

[0171] In an exemplary embodiment, in the first direction X, the routing connection line 42 may be disposed between adjacent anodes 40 , and the orthographic projection of the routing connection line 42 on the substrate does not overlap with the orthographic projection of the anode 40 on the substrate, thereby not affecting the flatness of the anode.

[0172] In an exemplary embodiment, the signal connection lines 50 transmitting the same signal may be arranged at intervals of one or more cell rows in the second direction Y. For example, the signal connection lines 50 transmitting the same signal may be arranged in odd-numbered cell rows. For another example, the signal connection lines 50 transmitting the same signal may be arranged in even-numbered cell rows.

[0173] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include a plurality of conductive layers sequentially arranged on a base. In one embodiment, the dummy connection line 41, the routing connection line 42, and the signal connection line 50 may be arranged in the same conductive layer, and the dummy connection line 41, the routing connection line 42, and the signal connection line 50 may be an integrated structure connected to each other. In another embodiment, the dummy connection line 41, the routing connection line 42, and the signal connection line 50 may be arranged in different conductive layers, and the dummy connection line 41, the routing connection line 42, and the signal connection line 50 may be connected to each other through vias. In yet another embodiment, two of the dummy connection line 41, the routing connection line 42, and the signal connection line 50 are arranged in one conductive layer, and the other one is arranged in another conductive layer, which is not limited in the present disclosure.

[0174] In an exemplary embodiment, the multiple conductive layers may include at least a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer, which are arranged in sequence along a direction away from the substrate, and at least one of the dummy connection line 41, the routing connection line 42, and the signal connection line 50 may be arranged in the third source-drain metal layer.

[0175] In an exemplary embodiment, the multiple conductive layers may include at least a blocking layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer, which are arranged in sequence along a direction away from the substrate, and at least one of the dummy connection line 41, the routing connection line 42, and the signal connection line 50 may be arranged in the blocking layer.

[0176] In an exemplary embodiment, the signal connection line 50 extending from the main body along the first direction X can be connected to the first power line extending from the main body along the second direction Y, thereby forming a mesh connection structure for transmitting the first power signal and effectively increasing the routing density of the first power line, thereby further reducing the resistance of the first power line, reducing the voltage drop of the first power signal, reducing power consumption, and improving display uniformity.

[0177] In another exemplary embodiment, the signal connection line 50 extending from the main body along the first direction X can be connected to the second power line extending from the main body along the second direction Y, thereby forming a mesh connection structure for transmitting the second power signal and effectively increasing the routing density of the second power line, thereby further reducing the resistance of the second power line, reducing the voltage drop of the second power signal, and improving display uniformity.

[0178] In another exemplary embodiment, the signal connection line 50 extending from the main body along the first direction X can be connected to the initial signal line extending from the main body along the second direction Y, which not only forms a mesh connection structure for transmitting the initial signal, but also effectively increases the routing density of the initial signal line, further reduces the resistance of the initial signal line, reduces the voltage drop of the initial signal, enhances the driving capability of the initial signal, and improves defects such as horizontal stripes and watermarks caused by insufficient driving capability of the initial signal.

[0179] In an exemplary embodiment, the light-emitting structure layer may include at least an anode conductive layer disposed on a side of the drive structure layer away from the substrate, a pixel definition layer disposed on a side of the anode conductive layer away from the substrate, an organic light-emitting layer disposed on a side of the pixel definition layer away from the substrate, and a cathode disposed on a side of the organic light-emitting layer away from the substrate. The anode conductive layer may include a plurality of anodes, the pixel definition layer may include a plurality of pixel openings, the pixel openings exposing the anodes, and the organic light-emitting layer may be connected to the anodes through the pixel openings.

[0180] In an exemplary embodiment, the light-emitting structure layer may further include at least one auxiliary cathode, which may be arranged in the same layer as the anode, and the orthographic projection of the auxiliary cathode on the substrate at least partially overlaps with the orthographic projection of the second power line (the signal connection line connected to the second power line) on the substrate, and the auxiliary cathode is connected to the second power line (the signal connection line connected to the second power line) through an auxiliary via, and the auxiliary cathode is configured to be connected to a cathode formed subsequently.

[0181] In an exemplary embodiment, after forming the organic light emitting layer, a connection hole exposing the auxiliary cathode may be formed by laser drilling, so that the cathode is connected to the auxiliary cathode through the connection hole.

[0182] In an exemplary embodiment, a plurality of auxiliary cathodes may be periodically arranged along the first direction X and the second direction Y to form a mesh-connected structure of auxiliary cathodes on the display substrate, which may further improve the uniformity of the second power signal in the display substrate, improve display uniformity, and enhance display quality.

[0183] In some other embodiments, the auxiliary cathode may not be provided in the light emitting structure layer, and the cathode in the light emitting structure layer is directly connected to the second power line (the signal connection line 50 connected to the second power line) through the connection hole, which is not limited in the present disclosure.

[0184] In an exemplary embodiment, the pixel definition layer can be made of a black organic material, such as black polyimide or acrylic, or black polyethylene terephthalate. Because the pixel definition layer can cover traces such as anode connection lines and dummy connection lines, it can reduce the reflectivity of signal traces and effectively improve defects such as off-screen watermarks.

[0185] Figure 14 is a schematic diagram of a second region arrangement according to an exemplary embodiment of the present disclosure. As shown in Figure 14, the plurality of second regions 20 may include a first sub-region 20-1, a second sub-region 20-2, a third sub-region 20-3, a fourth sub-region 20-4, a fifth sub-region 20-5, a sixth sub-region 20-6, ..., the (n-5)th sub-region 20-(n-5), the (n-4)th sub-region 20-(n-4), the (n-3)th sub-region 20-(n-3), the (n-2)th sub-region 20-(n-2), the (n-1)th sub-region 20-(n-1), and the nth sub-region 20-n, arranged sequentially along the first direction X.

[0186] In an exemplary embodiment, the scan driving device includes five groups of gate driving devices. The first sub-area 20-1 and the n-th sub-area 20-n can be provided with a first gate driving device 121 that outputs the first scan signal line S1, the second sub-area 20-2 and the (n-1)-th sub-area 20-(n-1) can be provided with a second gate driving device 122 that outputs the second scan signal line S2, the third sub-area 20-3 and the (n-2)-th sub-area 20-(n-2) can be provided with a third gate driving device 123 that outputs the third scan signal line S3, the fourth sub-area 20-4 and the (n-3)-th sub-area 20-(n-3) can be provided with a fourth gate driving device 124 that outputs the fourth scan signal line S4, and the fifth sub-area 20-5 and the (n-4)-th sub-area 20-(n-4) can be provided with a fifth gate driving device 125 that outputs the light emitting signal line EM, forming a bilateral driving structure with five groups of gate driving devices.

[0187] In an exemplary embodiment, each group of gate driving devices may include a plurality of cascaded gate driving circuits, and each level of gate driving circuits is connected to a plurality of pixel driving circuits in a unit row through a scanning signal line or a light-emitting signal line, providing a scanning signal or a light-emitting control signal to the plurality of pixel driving circuits in the unit row.

[0188] In an exemplary embodiment, the multiple pixel driver circuits in the first region and the multiple gate driver circuits in the second region can be simultaneously manufactured using the same process, without the need for additional patterning processes. In some possible embodiments, for special display effects (such as light shielding, uniform light transmission, etc.) or display optimization, one or two film layers can be added to the second region, which is not limited in this disclosure.

[0189] In an exemplary embodiment, the scan driving device may not be limited to 5 groups of gate driving devices, nor is it limited to a bilateral driving structure. The scan driving device may include other groups of gate driving devices and a unilateral driving structure, which is not limited in this disclosure.

[0190] In an exemplary embodiment, at least one sub-area among the sixth sub-area 20-6 to the (n-5)th sub-area 20-(n-5) can be provided with at least one signal trace 60, and the signal trace 60 can include any one or more of the following: a first power line 61, a second power line 62, and an initial signal line 63.

[0191] In an exemplary embodiment, each sub-area in the sixth sub-area 20-6 to the (n-5)th sub-area 20-(n-5) can be provided with a first power line 61 to reduce the resistance of the first power line 61, reduce the voltage drop of the first power signal, reduce power consumption, and improve display uniformity.

[0192] In another exemplary embodiment, each sub-region in the sixth sub-region 20-6 to the (n-5)th sub-region 20-(n-5) can be provided with a second power line 62 to reduce the resistance of the second power line 62, reduce the voltage drop of the second power signal, and improve display uniformity.

[0193] In another exemplary embodiment, each sub-region from the sixth sub-region 20-6 to the (n-5)th sub-region 20-(n-5) can be provided with an initial signal line 63 to reduce the resistance of the initial signal line 63, reduce the voltage drop of the initial signal, enhance the driving capability of the initial signal, and improve defects such as horizontal stripes and watermarks caused by insufficient driving capability of the initial signal.

[0194] In another exemplary embodiment, each sub-area in the sixth sub-area 20-6 to the (n-5)th sub-area 20-(n-5) can be respectively provided with a first power line 61 and a second power line 62, or can be respectively provided with a first power line 61 and an initial signal line 63, or can be respectively provided with a second power line 62 and an initial signal line 63, or can be respectively provided with a first power line 61, a second power line 62 and an initial signal line 63, and the present disclosure is not limited here.

[0195] In an exemplary embodiment, since the driving structure layer in the sixth sub-region 20-6 to the (n-5)th sub-region 20-(n-5) is not provided with a gate driving device, the driving structure layer of these sub-regions can be provided with a virtual driving circuit. The structure, arrangement and size of the virtual driving circuit can be basically the same as the pixel driving circuit in the first area. The difference is that the virtual driving circuit is not connected to any light-emitting device.

[0196] In an exemplary embodiment, at least one sub-area among the first sub-area 20-1 to the fifth sub-area 20-5 and the (n-4)th sub-area 20-(n-4) to the nth sub-area 20-n may also be provided with at least one signal trace 60, and the signal trace 60 may include any one or more of the following: a first power line 61, a second power line 62, and an initial signal line 63.

[0197] In an exemplary embodiment, in at least one of the first to fifth sub-areas 20-1 to 20-5 and the (n-4)th to nth sub-areas 20-(n-4)th to 20-nth sub-areas, the gate driver device may be disposed in the middle of the sub-area in the first direction X, and the signal traces 60 may be disposed on one or both sides of the gate driver device in the first direction X. For example, at least one sub-area may be provided with at least one first power line 61 and at least one initial signal line 63, and the first power line 61 and the initial signal line 63 may be disposed on both sides of the gate driver device. For another example, at least one sub-area may be provided with at least one second power line 62 and at least one initial signal line 63, and the second power line 62 and the initial signal line 63 may be disposed on both sides of the gate driver device. For another example, at least one sub-area may be provided with at least one first power line 61, at least one second power line 62, and at least one initial signal line 63, and the first power line 61, the second power line 62, and the initial signal line 63 may be disposed on both sides of the gate driver device.

[0198] In an exemplary embodiment, in a direction perpendicular to the display substrate, the signal trace 60 can be arranged on the side of the clock signal line away from the substrate. The signal trace 60 that transmits the DC signal can shield the clock signal line to avoid coupling between the anode connection line connected to the light-emitting device and the clock signal line, thereby affecting the stability of the anode voltage in the gate drive device and the light-emitting device, and improving the driving performance of the gate drive device.

[0199] In one embodiment, each sub-area 20-1 to the fifth sub-area 20-5 and the (n-4)th sub-area 20-(n-4) to the nth sub-area 20-n can be provided with a first power line 61, and the positive projection of the first power line 61 on the substrate at least partially overlaps with the positive projection of the clock signal line in the gate drive device on the substrate, which can not only shield the clock signal, but also further reduce the resistance of the first power line 61, reduce the voltage drop of the first power signal, reduce power consumption, and improve display uniformity.

[0200] In another embodiment, each sub-area in the first sub-area 20-1 to the fifth sub-area 20-5 and the (n-4)th sub-area 20-(n-4) to the nth sub-area 20-n can be provided with a second power line 62, and the positive projection of the second power line 62 on the substrate at least partially overlaps with the positive projection of the clock signal line in the gate drive device on the substrate, which can not only shield the clock signal, but also further reduce the resistance of the second power line 62, reduce the voltage drop of the second power signal, and improve display uniformity.

[0201] In another embodiment, each sub-area 20-1 to the fifth sub-area 20-5 and the (n-4)th sub-area 20-(n-4) to the nth sub-area 20-n can be provided with an initial signal line 63, and the positive projection of the initial signal line 63 on the substrate at least partially overlaps with the positive projection of the clock signal line in the gate drive device on the substrate, which can not only shield the clock signal, but also further reduce the resistance of the initial signal line 63, reduce the voltage drop of the initial signal, enhance the driving capability of the initial signal, and improve defects such as horizontal stripes and watermarks caused by insufficient driving capability of the initial signal.

[0202] In another exemplary embodiment, each sub-area in the first sub-area 20-1 to the fifth sub-area 20-5 and the (n-4)th sub-area 20-(n-4) to the nth sub-area 20-n can be respectively provided with a first power line 61 and a second power line 62, or can be respectively provided with a first power line 61 and an initial signal line 63, or can be respectively provided with a second power line 62 and an initial signal line 63, or can be respectively provided with a first power line 61, a second power line 62 and an initial signal line 63, and the present disclosure is not limited thereto.

[0203] In an exemplary embodiment, the display area may further be provided with signal connection lines extending along the first direction X, and the laterally extending signal connection lines are interconnected with the vertically extending signal lines to form a mesh-like interconnected structure throughout the display area.

[0204] Figure 15 is an enlarged view of area D in Figure 14, illustrating the structure of the gate drive circuit and signal routing in the second area. As shown in Figure 15, multiple cascaded gate drive circuits GOA can be arranged sequentially along the second direction Y, and at least one gate drive circuit GOA can be connected to the scan start signal line STV, the first clock signal line CLK, the second clock signal line CLKB, the high-level signal line VGH, and the low-level signal line VGL.

[0205] In an exemplary embodiment, the scan start signal line STV, the first clock signal line CLK, the second clock signal line CLKB, the high-level signal line VGH, and the low-level signal line VGL may be in the shape of a straight line or a broken line extending along the second direction Y. The high-level signal line VGH may be arranged on one side of the gate drive circuit GOA in the first direction X, and the other gate signal lines may be arranged on one side of the gate drive circuit GOA in the opposite direction of the first direction X.

[0206] In an exemplary embodiment, at least one or more of the first power line 61 and the initial signal line 63 may be provided on one side of the high-level signal line VGH in the first direction X, and at least one or more of the first power line 61 and the initial signal line 63 may be provided on the side opposite to the first direction X of the scan start signal line STV. The shapes of the first power line 61 and the initial signal line 63 may be straight lines or broken lines extending along the second direction Y.

[0207] In an exemplary embodiment, at least one second power line 62 may be provided in the region where the gate drive circuit GOA and the gate signal lines are located. The second power line 62 may be in the form of a straight line or a zigzag line extending along the second direction Y. There may be multiple second power lines 62, each of which may have the same or different widths, or may be combined into a single, wider line. The orthographic projection of the second power line 62 on the substrate at least partially overlaps with the orthographic projections of the first clock signal line CLK and the second clock signal line CLKB on the substrate. This allows the second power line 62 to shield the clock signal, preventing coupling between the connection lines connecting the light-emitting devices and the clock signal lines, thereby improving the driving performance of the gate drive device.

[0208] In an exemplary embodiment, the signal connection line 50 may be in the shape of a straight line or a broken line extending along the first direction X. In the second direction Y, the signal connection line 50 may be disposed between two cascaded gate drive circuits GOA to complete a horizontal bridge.

[0209] In an exemplary embodiment, at least one laterally extending signal connection line 50 can be connected to the vertically extending first power line 61 to form a mesh-like connectivity structure for transmitting the first power signal throughout the display area, and / or, at least one laterally extending signal connection line 50 can be connected to the vertically extending second power line 62 to form a mesh-like connectivity structure for transmitting the second power signal throughout the display area, and / or, at least one laterally extending signal connection line 50 can be connected to the vertically extending initial signal line 63 to form a mesh-like connectivity structure for transmitting the initial signal throughout the display area. The present disclosure does not limit this.

[0210] FIG16 is an enlarged view of the E region in FIG14 , illustrating the connection structure of the signal lines in the virtual drive circuit. As shown in FIG16 , the pixel drive circuit (the first pixel drive circuit and the second pixel drive circuit) in the first region 10 may include a storage capacitor and a plurality of transistors, and may be connected to the data signal line 64, the first power line 61, and the initial signal line 63, respectively. The structure of the virtual drive circuit in the portion of the second region 20 may be substantially the same as that of the pixel drive circuit in the first region, but the data signal line 64, the first power line 61, and / or the initial signal line 63 connected to the virtual drive circuit may be connected to the signal connection line 50, respectively, through a via K. When the signal connection line 50 is configured to be connected to the second power line 62, the longitudinal signal line originally used to transmit the data signal, the first power signal, and / or the initial signal is short-circuited with the second power line 62 through the signal connection line 50, thereby maximizing the routing density of the second power line 62.

[0211] Figures 17 and 18 are schematic diagrams of a gate lead line according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the display substrate may include at least a display area 100 and a binding area 200 located on one side of the display area 100 in the second direction Y. The display area 100 may include first areas 10 and second areas 20 arranged alternately along the first direction X. The first area 10 may include a plurality of pixel driving circuits, and the second area 20 may include a plurality of gate driving circuits. The binding area 200 may include at least a driver chip area, which may include at least an integrated circuit (IC) 80. The integrated circuit 80 is configured to connect to a plurality of data lead lines (not shown) and a plurality of gate lead lines 81. The plurality of data lead lines are configured to connect to a plurality of data signal lines in the plurality of first areas 10, and the plurality of gate lead lines 81 are configured to connect to a scan start signal line STV, a first clock signal line CLK, a second clock signal line CLKB, a high level signal line VGH, and a low level signal line VGL in the plurality of second areas 20.

[0212] In an exemplary embodiment, for a chip-on-pi (COP) bonding structure, gate lead lines 81 can be connected to pins on both sides of an integrated circuit 80, enabling the integrated circuit 80 to provide gate signals to the gate driver circuits in the plurality of second regions 20, as shown in FIG17 . Alternatively, gate lead lines 81 can be connected to the output pins (pins on the side of the integrated circuit 80 close to the display area) and the input pins (pins on the side of the integrated circuit 80 away from the display area) by routing wires in the area between the output pins (pins on the side of the integrated circuit 80 close to the display area) and the input pins (pins on the side of the integrated circuit 80 away from the display area), with the plurality of gate lead lines 81 having substantially the same spacing, enabling the integrated circuit 80 to provide gate signals to the gate driver circuits in the plurality of second regions 20, as shown in FIG18 . Alternatively, gate signals can be arranged in sequence with data signals, enabling the integrated circuit 80 to provide gate signals to the gate driver circuits in the plurality of second regions 20, which is not limited in this disclosure.

[0213] In an exemplary embodiment, for a chip-on-film (COF) binding structure, gate lead lines may be arranged on a flexible circuit board (FPC) to enable the integrated circuit to provide gate signals to gate drive circuits in multiple second regions, which is not limited in the present disclosure.

[0214] An exemplary embodiment of the present disclosure provides a display substrate, in which a first area and a second area are alternately arranged in a display area, a pixel driving circuit is arranged in the first area, and a gate driving circuit and a signal line are arranged in the second area. The gate driving circuit and the signal line are both arranged in the display area without occupying space in the border area, thereby effectively reducing the border width of the display device to less than 0.5 mm, thereby increasing the screen-to-body ratio and facilitating full-screen display.

[0215] In the embodiment of the present disclosure, a pixel driving circuit is set in a compression manner in the first area, so that the pixel driving circuit in the first area is connected to the light-emitting device in the second area. Both the first area and the second area can achieve normal display, which not only does not affect the display resolution, but also is conducive to achieving high display resolution.

[0216] By providing dummy connecting lines, the disclosed embodiments not only effectively improve the uniformity of the horizontal connecting lines below the anode, but also effectively improve the flatness of the anode, effectively improving color shift and enhancing display quality. By providing substantially identical or similar arrangements of the horizontal connecting lines in the normal area and the connecting line area, and substantially identical or similar routing densities of the horizontal connecting lines in the normal area and the connecting line area, the disclosed embodiments are less likely to exhibit defects such as off-screen watermarks (mura), thereby improving display quality.

[0217] The embodiment of the present disclosure effectively increases the routing density of the signal leads by providing dummy connecting lines to connect with the signal leads, which can further reduce the resistance of the signal leads, reduce the voltage drop of the signal, reduce power consumption, and improve display uniformity.

[0218] The embodiment of the present disclosure forms a full-surface mesh connection structure in the display area by arranging signal connection lines extending along the first direction of the main body and connecting them with signal leads extending along the second direction of the main body. This can not only effectively reduce the resistance of the signal leads and reduce the voltage drop of the signals, but also effectively improve the uniformity of the signals in the display substrate, effectively improve the display uniformity, and improve the display quality.

[0219] In the embodiment of the present disclosure, by arranging the signal lead to overlap the clock signal line, the signal line transmitting the DC signal can shield the clock signal line, thereby effectively improving the driving performance of the gate driving device.

[0220] The embodiment of the present disclosure provides auxiliary cathodes, which form a mesh-like interconnected structure on the display substrate, thereby further improving the uniformity of the second power supply signal in the display substrate, improving display uniformity, and enhancing display quality.

[0221] The embodiment of the present disclosure can reduce the reflectivity of the signal routing by setting a black pixel definition layer, and can effectively improve defects such as off-screen watermarks.

[0222] The preparation process of the embodiment of the present disclosure is well compatible with the existing preparation process, and the process is simple to implement, easy to implement, high in production efficiency, low in production cost, and high in yield rate.

[0223] The structure shown in the present disclosure is merely an exemplary description. In the exemplary implementation, the corresponding structure may be changed according to actual needs, and the present disclosure does not limit it here.

[0224] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0225] The present disclosure also provides a method for manufacturing a display substrate, for producing the display substrate provided in the above embodiment. In an exemplary embodiment, the display substrate includes a plurality of first regions and a plurality of second regions, wherein the first regions and the second regions are shaped like strips extending along a second direction, and the plurality of first regions and the plurality of second regions are alternately arranged along the first direction, with the first direction and the second direction intersecting. The manufacturing method may include:

[0226] A driving structure layer is formed on the substrate; the driving structure layer in the first area includes a plurality of pixel driving circuits, and the driving structure layer in the second area includes at least one gate driving device and / or at least one signal line;

[0227] A light-emitting structure layer is formed on the side of the driving structure layer away from the substrate; the light-emitting structure layer in the first area includes a plurality of first light-emitting devices, and the light-emitting structure layer in the second area includes a plurality of second light-emitting devices, at least one first light-emitting device in the first area is connected to at least one pixel driving circuit in the first area, and at least one second light-emitting device in the second area is connected to at least one pixel driving circuit in the first area.

[0228] The present disclosure also provides a display device comprising the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. The screen can be assembled into a cylindrical, wraparound, or spherical display, or other borderless display, although the embodiments of the present invention are not limited thereto.

[0229] While the embodiments disclosed herein are as described above, it should be noted that the above embodiments are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate, comprising a plurality of first areas and a plurality of second areas, wherein the first areas and the second areas are shaped like strips extending along a second direction, the plurality of first areas and the plurality of second areas are alternately arranged along the first direction, and the first direction and the second direction intersect; in a direction perpendicular to the display substrate, the display area comprises a driving structure layer arranged on a base and a light-emitting structure layer arranged on a side of the driving structure layer away from the base; the driving structure layer in the first area comprises a plurality of pixel driving circuits, the driving structure layer in the second area comprises at least one gate driving device and / or at least one signal trace, the light-emitting structure layer in the first area comprises a plurality of first light-emitting devices, and the light-emitting structure layer in the second area comprises a plurality of second light-emitting devices; at least one first light-emitting device in the first area is connected to at least one pixel driving circuit in the first area, and at least one second light-emitting device in the second area is connected to at least one pixel driving circuit in the first area.

2. The display substrate according to claim 1, wherein The driving structure layer of the first area includes multiple circuit repetition units, and the orthographic projection of at least one circuit repetition unit on the substrate has a first area. The light-emitting structure layer of the first area includes multiple light-emitting repetition units, and the orthographic projection of at least one light-emitting repetition unit on the substrate has a second area. The ratio of the first area to the second area is 0.95 to 1.05; at least one circuit repetition unit includes M+m pixel driving circuits, and at least one light-emitting repetition unit includes M first light-emitting devices; M is an integer multiple of 2 or an integer multiple of 3, and m is a positive integer greater than or equal to 1.

3. The display substrate according to claim 2, wherein: The pixel driving circuit in at least one circuit repeating unit includes at least a first pixel driving circuit and a second pixel driving circuit, the at least one first pixel driving circuit is connected to the at least one first light-emitting unit, and the orthographic projection of the at least one first pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the at least one first light-emitting device on the substrate; At least one second pixel driving circuit is connected to at least one second light emitting device through an anode connection line, and an orthographic projection of the at least one second pixel driving circuit on the substrate does not overlap with an orthographic projection of the at least one second light emitting device on the substrate.

4. The display substrate according to claim 3, wherein: The second region has a first center line, which is a straight line that bisects the second region in the first direction and extends along the second direction; the second region includes at least a first side repeating unit located on the opposite side of the first center line in the first direction and a second side repeating unit located on the side of the first center line in the first direction, and the first side repeating unit and the second side repeating unit each include N second light-emitting devices, where N is an integer multiple of 3 or an integer multiple of 4.

5. The display substrate according to claim 4, wherein: The first region at least includes a first side region located on the opposite side of the first direction of the second region and a second side region located on the side of the first direction of the second region; at least one second light-emitting device in the first side repeating unit is connected to at least one second pixel driving circuit in the first side region through an anode connecting line, and at least one second light-emitting device in the second side repeating unit is connected to at least one second pixel driving circuit in the second side region through an anode connecting line. The display substrate according to claim 5 , wherein: The first side region includes at least a first circuit repeating unit and a second circuit repeating unit, the first circuit repeating unit is located on the side of the second region opposite to the first direction, and the second circuit repeating unit is located on the side of the first circuit repeating unit away from the second region; the second side region includes at least an eleventh circuit repeating unit and a twelfth circuit repeating unit, the eleventh circuit repeating unit is located on the side of the second region in the first direction, and the twelfth circuit repeating unit is located on the side of the eleventh circuit repeating unit away from the second region; the first side repeating unit includes a first light emitting device group and a second light emitting device group sequentially arranged along the first direction, and the second side repeating unit includes a first light emitting device group and a second light emitting device group sequentially arranged along the first direction a third light-emitting device group and a fourth light-emitting device group; at least one second light-emitting device in the first light-emitting device group is connected to at least one second pixel driving circuit in the first circuit repetition unit through a first anode connecting line, at least one second light-emitting device in the second light-emitting device group is connected to at least one second pixel driving circuit in the second circuit repetition unit through a second anode connecting line, at least one second light-emitting device in the third light-emitting device group is connected to at least one second pixel driving circuit in the eleventh circuit repetition unit through an eleventh anode connecting line, and at least one second light-emitting device in the fourth light-emitting device group is connected to at least one second pixel driving circuit in the twelfth circuit repetition unit through a twelfth anode connecting line.

7. The display substrate according to claim 6, wherein: The second length of at least one second anode connecting line is greater than the first length of at least one first anode connecting line, the fourth length of at least one twelfth anode connecting line is greater than the third length of at least one eleventh anode connecting line, and the first length, the second length, the third length and the fourth length are dimensions in the first direction.

8. The display substrate according to claim 7, wherein: The third length of the at least one eleventh anode connecting line is greater than the first length of the at least one first anode connecting line, and the fourth length of the at least one twelfth anode connecting line is greater than the second length of the at least one second anode connecting line.

9. The display substrate according to claim 3, wherein: The material of the anode connecting line is a metal material, or the material of the anode connecting line is a transparent conductive material.

10. The display substrate according to claim 3, wherein: The first light-emitting device and the second light-emitting device both include an anode, the anode of at least one second light-emitting device is connected to at least one second pixel driving circuit through the anode connecting line, the shape of at least one anode connecting line is a straight line or a broken line extending along the first direction, and the orthographic projection of at least one anode connecting line on the substrate at least partially overlaps with the orthographic projection of the anode of at least one first light-emitting device on the substrate.

11. The display substrate according to claim 10, wherein: The first area also includes at least one dummy connecting line, which is in the shape of a straight line or a broken line extending along the first direction, and the orthographic projection of the at least one dummy connecting line on the substrate at least partially overlaps with the orthographic projection of the anode of at least one first light-emitting device on the substrate.

12. The display substrate according to claim 11, wherein: The first area includes at least a normal area and a connection line area, wherein the normal area is an area where the anode connection line is not provided, and the connection line area is an area where the anode connection line is provided; The orthographic projection of at least one anode in the normal area on the substrate at least partially overlaps with the orthographic projection of K1 dummy connecting lines on the substrate, and the orthographic projection of at least one anode in the connecting line area on the substrate at least partially overlaps with the orthographic projections of K2 dummy connecting lines and K3 anode connecting lines on the substrate, K1=K2+K3, K1, K2 and K3 are all positive integers greater than or equal to 1.

13. The display substrate according to claim 12, wherein: The arrangement of the dummy connecting lines in the normal area is the same as the arrangement of the dummy connecting lines and the anode connecting lines in the connecting line area, and the arrangement is any one or more of the following: the position of the connecting lines in the second direction, the width of the connecting lines, and the spacing between adjacent connecting lines, and the width and the spacing are the dimensions of the second direction.

14. The display substrate according to claim 12, wherein: The routing density of the dummy connection lines in the normal area is the same as the routing density of the dummy connection lines and the anode connection lines in the connection line area, where the routing density is the area of the connection lines per unit area.

15. The display substrate according to claim 11, wherein At least one dummy connection line is connected to at least one signal connection line through at least one routing connection line, the routing connection line is in the shape of a straight line or a broken line extending along the second direction, the routing connection line is arranged between two adjacent anodes in the first direction, and the orthographic projection of the routing connection line on the substrate does not overlap with the orthographic projection of the anode on the substrate.

16. The display substrate according to claim 15, wherein: The shape of the signal connection line is a straight line or a broken line extending along the first direction; at least one signal connection line is connected to the first power line serving as the signal routing line and the main part of which extends along the second direction, forming a mesh connectivity structure for transmitting the first power signal, and / or, at least one signal connection line is connected to the second power line serving as the signal routing line and the main part of which extends along the second direction, forming a mesh connectivity structure for transmitting the second power signal, and / or, at least one signal connection line is connected to the initial signal line serving as the signal routing line and the main part of which extends along the second direction, forming a mesh connectivity structure for transmitting the initial signal.

17. The display substrate according to claim 16, wherein: At least one gate driving device includes a plurality of gate driving circuits sequentially arranged and cascaded along the second direction, at least one gate driving circuit is connected to a first clock signal line and a second clock signal line, and the first clock signal line and the second clock signal line are in the shape of a straight line or a broken line extending along the second direction; In at least one second area, the orthographic projection of the first power line on the substrate at least partially overlaps with the orthographic projections of the first clock signal line and the second clock signal line on the substrate, and / or the orthographic projection of the second power line on the substrate at least partially overlaps with the orthographic projections of the first clock signal line and the second clock signal line on the substrate, and / or the orthographic projection of the initial signal line on the substrate at least partially overlaps with the orthographic projections of the first clock signal line and the second clock signal line on the substrate.

18. The display substrate according to claim 17, wherein: In the second direction, at least one signal connection line is arranged between two cascaded gate driving circuits.

19. A display device comprising the display substrate according to any one of claims 1 to 18.

20. A method for manufacturing a display substrate, the display substrate comprising a plurality of first regions and a plurality of second regions, the first regions and the second regions being stripe-shaped and extending along a second direction, the plurality of first regions and the plurality of second regions being alternately arranged along the first direction, and the first direction and the second direction intersecting; the method comprising: forming a driving structure layer on a substrate; The driving structure layer in the first area includes a plurality of pixel driving circuits, and the driving structure layer in the second area includes at least one gate driving device and / or at least one signal trace; A light-emitting structure layer is formed on the side of the driving structure layer away from the substrate; the light-emitting structure layer in the first area includes a plurality of first light-emitting devices, and the light-emitting structure layer in the second area includes a plurality of second light-emitting devices, at least one first light-emitting device in the first area is connected to at least one pixel driving circuit in the first area, and at least one second light-emitting device in the second area is connected to at least one pixel driving circuit in the first area.

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