System and method for determining optimized device parameters of a multi-variable architecture

Abstract

Method and servers for determining optimized device parameters of an electronic circuit. The method includes accessing design information of the electronic circuit, determining a set of device parameters of the electronic circuit based on the design information, receiving information indicative of set of performances-of-interest to be optimized, and a corresponding set of target values, each target value being associated with a corresponding performance-of- interest, defining a multi-objective reward function based on the set of performances-of-interest to be optimized and outputting, using a pre-built Machine Learning (ML) algorithm interacting with an electronic design automation (EDA) environment, an optimized device parameter value for each of the device parameters based on the multi-objective reward function.

Description

[0001] SYSTEM AND METHOD FOR DETERMINING OPTIMIZED DEVICE PARAMETERS OF A MULTI-VARIABLE ARCHITECTURE CROSS-REFERENCE

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 548,757 filed on February 1, 2024, and entitled “SYSTEM AND METHOD FOR DETERMINING OPTIMIZED DEVICE PARAMETERS OF A MULTI-VARIABLE ARCHITECTURE”, which is herein incorporated by reference in its entirety. FIELD

[0002] The present technology relates to the field of computer optimization. In particular, systems and methods for determining optimized device parameters of a multi-variable architecture are disclosed. BACKGROUND

[0003] Automation-assisted simulation-based optimization (SBO) is a relatively efficient way for the design and optimisation of multi-variable architectures such as electronic circuit design. Indeed, efficiency has been a key parameter in recent optimisation problems due to time-to- market restrictions and rapid technology advancements.

[0004] However, automatic layout creation may be an error-prone task and post-layout simulations may be highly time-consuming operations. Therefore, existing approaches mostly concentrate on pre-layout optimization. As a result, in the post-layout optimization stage, designers must still manually adjust the circuit parameters using theoretically determined design relationships between the different adjustable parameters.

[0005] Even though the recent developments identified above may provide benefits, improvements are still desirable to reduce workload of multi-variable architecture designers. SUMMARY

[0006] Implementations of the present technology have been developed based on developers’ appreciation of shortcomings associated with the prior art. 304628991.1 110447 / 3

[0007] In a first broad aspect of the present technology, there is provided a computer- implemented method for determining optimized device parameters of an electronic circuit. The method includes accessing design information of the electronic circuit, determining a set of device parameters of the electronic circuit based on the design information, receiving information indicative of set of performances-of-interest to be optimized, and a corresponding set of target values, each target value being associated with a corresponding performance-of- interest, defining a multi-objective reward function based on the set of performances-of-interest to be optimized and outputting, using a pre-built Machine Learning (ML) algorithm interacting with an electronic design automation (EDA) environment, an optimized device parameter value for each of the device parameters based on the multi-objective reward function.

[0008] In some non-limiting implementations, the ML algorithm is a Reinforcement Learning algorithm.

[0009] In some non-limiting implementations, receiving information indicative of set of performances-of-interest to be optimized includes receiving, from a designer of the electronic circuit, descriptive data of the set of performances-of-interest.

[0010] In some non-limiting implementations, receiving information indicative of set of performances-of-interest to be optimized includes determining, by executing a dedicated algorithm, the set of performances-of-interest based on the design information of the electronic circuit.

[0011] In some non-limiting implementations, the design information includes a circuit netlist indicative of a circuit topology of the electronic circuit, one or more circuit input, and one or more circuit output.

[0012] In some non-limiting implementations, the ML algorithm is a Soft Actor-Critic reinforcement learning algorithm.

[0013] In some non-limiting implementations, the method further includes extracting historical data from the interaction of the ML algorithm with the EDA environment and determining, for each performance-of-interest, a causal function indicative of a relation between the performance-of-interest and the device parameters based on the historical data. 304628991.1 110447 / 3

[0014] In some non-limiting implementations, the method further includes determining a contribution factor for each pair of device parameter – performance-of-interest based on the causal function.

[0015] In some non-limiting implementations, determining a contribution factor, or “causal relationship”, includes identifying potential causal device parameters based on the device parameters, determining, for each device parameter, a relevance score indicative of a causality, or “relationship” of the device parameter to a given performance-of-interest, determining, for each device parameter, a redundancy score indicative of a relationship between the device parameter and determining a relevance factor of the device parameters to the performance-of- interest based on the relevance score and the redundancy scores thereof.

[0016] In some non-limiting implementations, the method further includes determining, for each device parameter, a global contribution score indicative of a first level of influence that the device parameter has on the set of performances-of-interest, determining, for each device parameter and for each performance-of-interest, a local contribution score indicative of a second level of influence that the device parameter has on the performance-of-interest, determining, for each device parameter, an occurrence frequency score indicative of a number of performances-of-interest influenced by the device parameter, and sorting the set of device parameters based on at least one of the global contribution scores, the local contribution scores, and the occurrence frequency scores.

[0017] In some non-limiting implementations, the method further includes determining a complexity value for the electronic circuit, in response to the complexity value being above a given threshold, upon receiving the set of target values, determining one or more sets of sub- target values based on the set of target values, the one or more sets of sub-target values being relatively less constraining than the set of target values, the ML algorithm being configured to incrementally determines sub-optimized device parameter values for each set of sub-target values.

[0018] In some non-limiting implementations, a given device parameter includes at least one of a capacitance of an electronic component of the electronic circuit, a resistance thereof, an inductance thereof, a bias current flowing therein, a voltage value thereof, and a width and / or a length of a transistor thereof. 304628991.1 110447 / 3

[0019] In a third broad aspect of the present technology, there is provided a computer- implemented method for determining optimized device parameters of a multi-variable architecture. The method includes accessing design information of the multi-variable architecture, determining a set of device parameters of the multi-variable architecture based on the design information, receiving information indicative of set of performances-of-interest to be optimized, and a corresponding set of target values, each target value being associated with a corresponding performance-of-interest, defining a multi-objective reward function based on the set of performances-of-interest to be optimized, and outputting, using a pre-built Machine Learning (ML) algorithm interacting with a design automation (DA) environment, a set of optimized device parameters based on the multi-objective reward function.

[0020] In some non-limiting implementations, the multi-variable architecture is a physical architecture.

[0021] In some non-limiting implementations, the multi-variable architecture is a logical architecture.

[0022] In a third broad aspect of the present technology, there is provided a system for determining optimized device parameters of an electronic circuit. The system includes a controller and a memory storing a plurality of executable instructions which, when executed by the controller, cause the system to access design information of the electronic circuit, determine a set of device parameters of the electronic circuit based on the design information, receive information indicative of set of performances-of-interest to be optimized, and a corresponding set of target values, each target value being associated with a corresponding performance-of-interest, define a multi-objective reward function based on the set of performances-of-interest to be optimized and output, using a pre-built Machine Learning (ML) algorithm interacting with an electronic design automation (EDA) environment, an optimized device parameter value for each of the device parameters based on the multi-objective reward function.

[0023] In some non-limiting implementations, the ML algorithm is a Reinforcement Learning algorithm.

[0024] In some non-limiting implementations, receiving information indicative of set of performances-of-interest to be optimized includes receiving, by the controller and from a designer of the electronic circuit, descriptive data of the set of performances-of-interest. 304628991.1 110447 / 3

[0025] In some non-limiting implementations, receiving information indicative of set of performances-of-interest to be optimized includes determining, by the controller executing a dedicated algorithm, the set of performances-of-interest based on the design information of the electronic circuit.

[0026] In some non-limiting implementations, the ML algorithm is a Soft Actor-Critic reinforcement learning algorithm.

[0027] In some non-limiting implementations, the controller is further configured to extract historical data from the interaction of the ML algorithm with the EDA environment and determine, for each performance-of-interest, a causal function indicative of a relation between the performance-of-interest and the device parameters based on the historical data.

[0028] In some non-limiting implementations, the controller is further configured to determine a contribution factor for each pair of device parameter – performance-of-interest based on the causal function.

[0029] In some non-limiting implementations, the controller determines a contribution factor by identifying causal device parameters based on the device parameters, determining, for each causal device parameter, a relevance score indicative of a causality of the causal device parameter on a given performance-of-interest, determining, for each device parameter, a redundancy score indicative of a number of performances-of-interest related to the causal device parameter and determining a contribution factor based on the relevance score and the redundancy scores thereof.

[0030] In some non-limiting implementations, the controller is further configured to determine, for each device parameter, a global contribution score indicative of a first level of influence that the device parameter has on the set of performances-of-interest, determine, for each device parameter and for each performance-of-interest, a local contribution score indicative of a second level of influence that the device parameter has on the performance-of-interest and determine, for each device parameter, an occurrence frequency score indicative of a number of performances-of-interest influenced by the device parameter. The controller is further configured to sort the set of device parameters based on at least one of the global contribution scores, the local contribution scores, and the occurrence frequency scores. 304628991.1 110447 / 3

[0031] In some non-limiting implementations, the controller is further configured to determine a complexity value for the electronic circuit, in response to the complexity value being above a given threshold, upon receiving the set of target values, determine one or more sets of sub- target values based on the set of target values, the one or more sets of sub-target values being relatively less constraining than the set of target values, the ML algorithm being configured to incrementally determines sub-optimized device parameter values for each set of sub-target values.

[0032] In some non-limiting implementations, a given device parameter includes at least one of a capacitance of an electronic component of the electronic circuit, a resistance thereof, an inductance thereof, a bias current flowing therein, a voltage value thereof, and a width and / or a length of a transistor thereof.

[0033] In a fourth broad aspect of the present technology, there is provided a system for determining optimized device parameters of a multi-variable architecture, the system including a controller and a memory storing a plurality of executable instructions which, when executed by the controller, cause the system to access design information of the multi-variable architecture, determine a set of device parameters of the multi-variable architecture based on the design information, receive information indicative of set of performances-of-interest to be optimized, and a corresponding set of target values, each target value being associated with a corresponding performance-of-interest, define a multi-objective reward function based on the set of performances-of-interest to be optimized and output, using a pre-built Machine Learning (ML) algorithm interacting with a design automation (DA) environment, a set of optimized device parameters based on the multi-objective reward function.

[0034] In some non-limiting implementations, the multi-variable architecture is a physical architecture.

[0035] In some non-limiting implementations, the multi-variable architecture is a logical architecture.

[0036] In the context of the present specification, a “server” is a computer program that is running on appropriate hardware and is capable of receiving requests (e.g., from client devices) over a network, and carrying out those requests, or causing those requests to be carried out. The hardware may be one physical computer or one physical computer system, but neither is required to be the case with respect to the present technology. In the present context, the use of 304628991.1 110447 / 3  the expression a “server” is not intended to mean that every task (e.g., received instructions or requests) or any particular task will have been received, carried out, or caused to be carried out, by the same server (i.e., the same software and / or hardware); it is intended to mean that any number of software elements or hardware devices may be involved in receiving / sending, carrying out or causing to be carried out any task or request, or the consequences of any task or request; and all of this software and hardware may be one server or multiple servers, both of which are included within the expression “at least one server”.

[0037] In the context of the present specification, “user device” is any computer hardware that is capable of running software appropriate to the relevant task at hand. Thus, some (non- limiting) examples of user devices include personal computers (desktops, laptops, netbooks, etc.), smartphones, and tablets, as well as network equipment such as routers, switches, and gateways. It should be noted that a device acting as a user device in the present context is not precluded from acting as a server to other user devices. The use of the expression “a user device” does not preclude multiple user devices being used in receiving / sending, carrying out or causing to be carried out any task or request, or the consequences of any task or request, or steps of any method described herein.

[0038] In the context of the present specification, a “database” is any structured collection of data, irrespective of its particular structure, the database management software, or the computer hardware on which the data is stored, implemented or otherwise rendered available for use. A database may reside on the same hardware as the process that stores or makes use of the information stored in the database or it may reside on separate hardware, such as a dedicated server or plurality of servers.

[0039] In the context of the present specification, the expression “information” includes information of any nature or kind whatsoever capable of being stored in a database. Thus information includes, but is not limited to audiovisual works (images, movies, sound records, presentations etc.), data (location data, numerical data, etc.), text (opinions, comments, questions, messages, etc.), documents, spreadsheets, lists of words, etc.

[0040] In the context of the present specification, the expression “component” is meant to include software (appropriate to a particular hardware context) that is both necessary and sufficient to achieve the specific function(s) being referenced. 304628991.1 110447 / 3

[0041] In the context of the present specification, the expression “computer usable information storage medium” is intended to include media of any nature and kind whatsoever, including RAM, ROM, disks (CD-ROMs, DVDs, floppy disks, hard drivers, etc.), USB keys, solid state- drives, tape drives, etc.

[0042] In the context of the present specification, unless expressly provided otherwise, an “indication” of an information element may be the information element itself or a pointer, reference, link, or other indirect mechanism enabling the recipient of the indication to locate a network, memory, database, or other computer-readable medium location from which the information element may be retrieved. For example, an indication of a document could include the document itself (i.e. its contents), or it could be a unique document descriptor identifying a file with respect to a particular file system, or some other means of directing the recipient of the indication to a network location, memory address, database table, or other location where the file may be accessed. As one skilled in the art would recognize, the degree of precision required in such an indication depends on the extent of any prior understanding about the interpretation to be given to information being exchanged as between the sender and the recipient of the indication. For example, if it is understood prior to a communication between a sender and a recipient that an indication of an information element will take the form of a database key for an entry in a particular table of a predetermined database containing the information element, then the sending of the database key is all that is required to effectively convey the information element to the recipient, even though the information element itself was not transmitted as between the sender and the recipient of the indication.

[0043] In the context of the present specification, the words “first”, “second”, “third”, etc. have been used as adjectives only for the purpose of allowing for distinction between the nouns that they modify from one another, and not for the purpose of describing any particular relationship between those nouns. Thus, for example, it should be understood that, the use of the terms “first server” and “third server” is not intended to imply any particular order, type, chronology, hierarchy or ranking (for example) of / between the server, nor is their use (by itself) intended imply that any “second server” must necessarily exist in any given situation. Further, as is discussed herein in other contexts, reference to a “first” element and a “second” element does not preclude the two elements from being the same actual real-world element. Thus, for example, in some instances, a “first” server and a “second” server may be the same software and / or hardware, in other cases they may be different software and / or hardware. 304628991.1 110447 / 3

[0044] Implementations of the present technology each have at least one of the above- mentioned objects and / or aspects, but do not necessarily have all of them. It should be understood that some aspects of the present technology that have resulted from attempting to attain the above-mentioned object may not satisfy this object and / or may satisfy other objects not specifically recited herein.

[0045] Additional and / or alternative features, aspects and advantages of implementations of the present technology will become apparent from the following description, the accompanying drawings and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] For a better understanding of the present technology, as well as other aspects and further features thereof, reference is made to the following description which is to be used in conjunction with the accompanying drawings, where:

[0047] Figure 1 is a schematic representation of an optimization environment in accordance with some non-limiting implementations of the present technology;

[0048] Figure 2 is a schematic block diagram of an electronic device in accordance with some non-limiting implementations of the present technology;

[0049] Figure 3 is a schematic representation of an optimization kernel executed in the optimization environment of Figure 1 in accordance with some non-limiting implementations of the present technology;

[0050] Figure 4 is schematic representation of a machine learning algorithm of the optimization kernel of Figure 3 in accordance with some non-limiting implementations of the present technology;

[0051] Figure 5 is a schematic representation of a pipeline for determining actionable insights of a multi-variable architecture in accordance with some non-limiting implementations of the present technology;

[0052] Figure 6 is a schematic representation of operations of an evolutionary algorithm-based feature selection (EAFS) of the pipeline of Figure 5 in accordance with non-limiting implementations of the present technology; 304628991.1 110447 / 3

[0053] Figure 7 is a schematic representation of operations of a minimum redundancy maximum relevance (mRMR) algorithm of the pipeline of Figure 5 in accordance with non- limiting implementations of the present technology;

[0054] Figure 8 is a schematic representation of operations of an interventional permutation importance algorithm of the pipeline of Figure 5 in accordance with non-limiting implementations of the present technology;

[0055] Figure 9 is a schematic representation of operations of a local explanation generating algorithm of the pipeline of Figure 5 in accordance with non-limiting implementations of the present technology;

[0056] Figure 10 is a schematic representation of operations for determining relative contributions and relations of device parameters and performances-of-interest executed in the pipeline of Figure 5 in accordance with non-limiting implementations of the present technology;

[0057] Figure 11 is a flow-diagram of a Minimum Conflict Relative Contributions & Occurrences algorithm of the pipeline of Figure 5 in accordance with some non-limiting implementations of the present technology;

[0058] Figure 12 is a schematic representation of illustrative conflicts of device parameters;

[0059] Figure 13A is an electric diagram of an illustrative operationnal-amplifier;

[0060] Figure 13B is a weighted graph of device parameters and performances-of-interest determined by the pipeline of Figure 4 in accordance with some non-limiting implementations of the present technology;

[0061] Figure 14 is a table of device parameters sorted in accordance with some non-limiting implementations of the present technology;

[0062] Figure 15 is a flow-diagram showing operations of a method for determining optimized device parameters of an electronic circuit in accordance with some embodiments of the present technology; and

[0063] Figure 16 is a schematic representation of a soft-actor-critic (SAC) algorithm in accordance with some non-limiting implementations of the present technology. 304628991.1 110447 / 3

[0064] It should also be noted that, unless otherwise explicitly specified herein, the drawings are not to scale. DETAILED DESCRIPTION

[0065] The examples and conditional language recited herein are principally intended to aid the reader in understanding the principles of the present technology and not to limit its scope to such specifically recited examples and conditions. It will be appreciated that those skilled in the art may devise various arrangements that, although not explicitly described or shown herein, nonetheless embody the principles of the present technology.

[0066] Furthermore, as an aid to understanding, the following description may describe relatively simplified implementations of the present technology. As persons skilled in the art would understand, various implementations of the present technology may be of a greater complexity.

[0067] In some cases, what are believed to be helpful examples of modifications to the present technology may also be set forth. This is done merely as an aid to understanding, and, again, not to define the scope or set forth the bounds of the present technology. These modifications are not an exhaustive list, and a person skilled in the art may make other modifications while nonetheless remaining within the scope of the present technology. Further, where no examples of modifications have been set forth, it should not be interpreted that no modifications are possible and / or that what is described is the sole manner of implementing that element of the present technology.

[0068] Moreover, all statements herein reciting principles, aspects, and implementations of the present technology, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof, whether they are currently known or developed in the future. Thus, for example, it will be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative circuitry embodying the principles of the present technology. Similarly, it will be appreciated that any flowcharts, flow diagrams, state transition diagrams, pseudo-code, and the like represent various processes that may be substantially represented in non-transitory computer-readable media and so executed by a computer or processor, whether or not such computer or processor is explicitly shown. 304628991.1 110447 / 3

[0069] The functions of the various elements shown in the figures, including any functional block labeled as a "processor", may be provided through the use of dedicated hardware as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which may be shared. In some implementations of the present technology, the processor may be a general- purpose processor, such as a central processing unit (CPU) or a processor dedicated to a specific purpose, such as a digital signal processor (DSP). Moreover, explicit use of the term a "processor" should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, without limitation, application specific integrated circuit (ASIC), field programmable gate array (FPGA), read-only memory (ROM) for storing software, random access memory (RAM), and non-volatile storage. Other hardware, conventional and / or custom, may also be included.

[0070] Software modules, or simply modules which are implied to be software, may be represented herein as any combination of flowchart elements or other elements indicating performance of process steps and / or textual description. Such modules may be executed by hardware that is expressly or implicitly shown. Moreover, it should be understood that module may include for example, but without being limitative, computer program logic, computer program instructions, software, stack, firmware, hardware circuitry or a combination thereof which provides the required capabilities.

[0071] In an aspect, the present technology provides methods for determining optimized device parameters of a multi-variable architecture such as an electronic circuit. Implementations of the present technology thus provide techniques for enabling a user to obtain optimized values of device values, or device “parameters”. In the present disclosure, the main example of a usage of the present technology is related to optimizing electronic circuits. However, it should be noted that the application to electronic circuits is not limitative, and the teachings of the present technology may be applied to different types of multi-variable systems and architectures, such as industrial processes (e.g. for CO2 capture / conversion), aviation systems (e.g. for flying vessel stability) and control systems (e.g. for design and autotuning). Therefore, it can be said that any processes that can be modeled using simulation may be optimized using the proposed technology. 304628991.1 110447 / 3

[0072] With these fundamentals in place, we will now consider some non-limiting examples to illustrate various implementations of aspects of the present technology.

[0073] Referring to Figure 1, there is shown a schematic diagram of an optimization environment 100, the optimization environment 100 being suitable for implementing non- limiting implementations of the present technology. It is to be expressly understood that the optimization environment 100 as depicted is merely an illustrative implementation of the present technology. Thus, the description thereof that follows is intended to be only a description of illustrative examples of the present technology. This description is not intended to define the scope or set forth the bounds of the present technology. In some cases, what are believed to be helpful examples of modifications to the optimization environment 100 may also be set forth below. This is done merely as an aid to understanding, and, again, not to define the scope or set forth the bounds of the present technology. These modifications are not an exhaustive list, and, as a person skilled in the art would understand, other modifications are likely possible. Further, where this has not been done (i.e., where no examples of modifications have been set forth), it should not be interpreted that no modifications are possible and / or that what is described is the sole manner of implementing that element of the present technology. As a person skilled in the art would understand, this is likely not the case. In addition, it is to be understood that the optimization environment 100 may provide in certain instances simple implementations of the present technology, and that where such is the case they have been presented in this manner as an aid to understanding. As persons skilled in the art would understand, various implementations of the present technology may be of a greater complexity.

[0074] Generally speaking, the optimization environment 100 is configured to provide optimized device parameters values and actionable insights to users of the optimization environment 100. As such, any system variation configured to enable optimization of multi- variable architecture and systems can be adapted to execute implementations of the present technology, once the teachings presented herein are appreciated. Furthermore, the optimization environment 100 will be described using an example of the multi-variable architecture being an electronic circuit. However, implementations of the present technology can be equally applied to other types of multi-variable architectures.

[0075] As shown in Figure 1, the optimization environment 100 includes an optimization device 110 configured to receive design specification 102 from a user. Broadly speaking, the optimization device 110 executes an optimization kernel 210 that takes design information 104 304628991.1 110447 / 3  of the multi-variable architecture as an input. For example, the design information 104 may include a topology of an electronic circuit to be optimized.

[0076] The optimization kernel 210 may further determine a set of device parameters of the electronic circuit based on the design information 104. A device parameter may correspond, for example, and without limitation, to a capacitance of an electronic component of the electronic circuit, a resistance thereof, an inductance thereof, a bias current flowing therein, a voltage value thereof, a width and / or a length of a transistor thereof, etc.

[0077] In some implementations, the optimization device 110 transmits an output 106 of the optimization kernel 210 to a causal discovery module 310. As will be described in greater detail hereinafter, the causal discovery module 310 may use historical data of the optimization kernel to determine actionable insights 108 indicative of sorted device parameters. Finally, the optimization device 110 may transmit the outputs of the optimization kernel and / or the causal discovery module 310 to the user.

[0078] Figure 2 is a schematic representation of the optimization device 110 in accordance with an implementation of the present technology. The optimization device 110 includes a computing unit 250. In some implementations, the computing unit 250 may be implemented by any of a conventional personal computer, a controller, and / or an electronic device (e.g., a server, a controller unit, a control device, a monitoring device etc.) and / or any combination thereof appropriate to the relevant task at hand. In some implementations, the computing unit 250 comprises various hardware components including one or more single or multi-core processors collectively represented by a processor 251, a solid-state drive 255, a RAM 253, a dedicated memory 254, and an input / output interface 256. The computing unit 250 may be a generic computer system.

[0079] In some other implementations, the computing unit 250 may be an “off the shelf” generic computer system. In some implementations, the computing unit 250 may also be distributed amongst multiple systems. The computing unit 250 may also be specifically dedicated to the implementation of the present technology. As a person in the art of the present technology may appreciate, multiple variations as to how the computing unit 250 is implemented may be envisioned without departing from the scope of the present technology.

[0080] Communication between the various components of the computing unit 250 may be enabled by one or more internal and / or external buses 257 (e.g. a PCI bus, universal serial bus, 304628991.1 110447 / 3  IEEE 1394 “Firewire” bus, SCSI bus, Serial-ATA bus, ARINC bus, etc.), to which the various hardware components are electronically coupled.

[0081] The input / output interface 256 may provide networking capabilities such as wired or wireless access. As an example, the input / output interface 256 may comprise a networking interface such as, but not limited to, one or more network ports, one or more network sockets, one or more network interface controllers, and the like. Multiple examples of how the networking interface may be implemented will become apparent to the person skilled in the art of the present technology. For example, but without being limitative, the networking interface may implement specific physical layer and data link layer standards such as Ethernet, Fibre Channel, Wi-Fi or Token Ring. The specific physical layer and the data link layer may provide a base for a full network protocol stack, allowing communication among small groups of computers on the same local area network (LAN) and large-scale network communications through routable protocols, such as Internet Protocol (IP).

[0082] According to implementations of the present technology, the solid-state drive 220 stores program instructions suitable for being loaded into the RAM 230 and executed by the processor 251. Although illustrated as a solid-state drive 255, any type of memory may be used in place of the solid-state drive 255, such as a hard disk, optical disk, and / or removable storage media.

[0083] The processor 251 may be a general-purpose processor, such as a central processing unit (CPU) or a processor dedicated to a specific purpose, such as a digital signal processor (DSP). In some implementations, the processor 251 may also rely on an accelerator 252 dedicated to certain given tasks, such as executing the methods set forth in the paragraphs below. In some implementations, the processor 251 or the accelerator 252 may be implemented as one or more field programmable gate arrays (FPGAs). Moreover, explicit use of the term "processor", should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, without limitation, application specific integrated circuit (ASIC), read-only memory (ROM) for storing software, RAM, and non-volatile storage. Other hardware, conventional and / or custom, may also be included.

[0084] Further, the optimization device 110 may include a screen or display 270. In some implementations, display 270 may comprise and / or be housed with a touchscreen to permit users to input data via some combination of virtual keyboards, icons, menus, or other Graphical User Interfaces (GUIs). In some implementations, display 270 may be implemented using a 304628991.1 110447 / 3  Liquid Crystal Display (LCD) display or a Light Emitting Diode (LED) display, such as an Organic LED (OLED) display. The device may be, for example, an iPhone® from Apple or a Galaxy® from Samsung, or any other mobile device whose features are similar or equivalent to the aforementioned features. The device may be, for example and without being limitative, a handheld computer, a personal digital assistant, a cellular phone, a network device, a smartphone, a navigation device, an e-mail device, a game console, or a combination of two or more of these data processing devices or other data processing devices.

[0085] The optimization device 110 may comprise a memory 260 communicably connected to the computing unit 250 and configured to store data, settings, or any other information relevant to executing the optimization processes and methods disclosed herein. The memory 260 may be embedded in the optimization device 110 as in the illustrated implementation of Figure 2 or located in an external physical location. The computing unit 250 may be configured to access the content of the memory 260 via a network (not shown) such as a Local Area Network (LAN) and / or a wireless connection such as a Wireless Local Area Network (WLAN).

[0086] In some alternative implementations, the optimization device 110 may be implemented as a conventional computer server. In an example of an implementation of the present technology, the optimization device 110 may be implemented as a Dell™ PowerEdge™ Server running the Microsoft™ Windows Server™ operating system. Needless to say, the optimization device 110 may be implemented in any other suitable hardware, software, and / or firmware, or a combination thereof. In the depicted non-limiting implementations of the present technology, the optimization device 110 is a single server. In alternative non-limiting implementations of the present technology, the functionality of the optimization device 110 may be distributed and may be implemented via multiple servers. Optimization kernel preparation

[0087] As will be described in greater details herein after, the optimization kernel 210 includes a machine learning algorithm (MLA) 212 interacting with a design automation (DA) environment 214 to perform the optimization (see Figure 4). In this non-limitative implementation, the MLA 212 is a reinforcement learning (RL) algorithm 212 and the DA environment is an electronic design automation (EDA) environment.

[0088] In this implementation, the MLA is an RL algorithm such that continuous device parameter values can be manipulated. More specifically, the RL algorithm 212 implements a 304628991.1 110447 / 3  Soft Actor-Critic (SAC) algorithm 312. The SAC algorithm may be implemented as described in (Haarnoja et al., 2018), an entirety of the content thereof being incorporated by reference. The developers of the present technology selected the SAC algorithm based on its ability to handle a continuous action space and its sample efficiency, compared to other reinforcement learning algorithms such as Proximal Policy Optimization (PPO) algorithms of Deep Deterministic Policy Gradient (DDPG) algorithms.

[0089] As shown on Figure 3, the MLA 212 receives a current state S of the multi-variable architecture (e.g. an electronic circuit) and target design specifications (S*, G). The state is indicative of current values of device parameters and current values of performances-of-interest (POI). S* includes target values POI* for each POI, and G includes indication whether the target value POI* is a maximum value, a minimum value, an exact value to be reached by the corresponding POI, or a certain range of the POI.

[0090] For example, the MLA 212 may receive a set of performances-of-interest to be optimized from a user of the optimization environment 100. In alternative implementations, the MLA 212 may automatically determine the set of POIs based on the design information of the multi-variable architecture. The MLA 212 also receives indications of boundaries for each device parameters. As will be described with respect to Figure 4, the MLA 212 interacts with the design automation (DA) environment 214, or simulator “214” by transmitting actions (A) to be executed within the DA environment 214 to iteratively optimize the multi-variable architecture.

[0091] Broadly speaking, the SAC algorithm 312 seeks to maximize an expected reward while encouraging a stochastic policy. In this implementation, it is achieved by using the maximum entropy framework where the objective is a combination of the expected reward and the entropy of the policy as: ் ^^^^^^ ^ (1) where ^^ is the the states and actions at step t, ℋ^^^^^^௧|^^௧^ is the entropy term denoted by ℋ^^^^^^௧|^^௧^ ൌെ∑^^ ^^^^^௧|^^௧^log ^^^^^௧|^^௧^, and α ∈ ^0,1^ is a temperature parameter which balances the reward. Higher ^^ values allow more exploration while lower values allow more exploitation. 304628991.1 110447 / 3

[0092] The SAC algorithm 312 thereby defines an entropy regularization term: ^^^^^௧,^^௧^ ൌ ^^^^^௧ ,^^௧^ ^ γE^౪శభ ^^^^^௧ା^^  (2) ^^^^^௧^ ൌ ^^^^~గ,^^^^^^௧ ,^^௧^ െ α log ^^^^^௧|^^௧^^  (3) where ^^^^^௧ ,^^௧^ is the soft Q-value function, γ is the discount factor ^γ ∈ ^0,1^^, and ^^^^^௧^,is the soft value function. The added entropy regularization term helps in convergence, preventing the policy from prematurely getting stuck in local optima by encouraging exploration.

[0093] As best shown on Figure 3, the SAC algorithm 312 includes two main neural networks (NNs), a critic NN 316 and an actor NN 314, a reward definition module 314 in addition to a value function NN. The critic NN 316 is a parameterized NN that takes as input the current states (S) and reward (R) and, accordingly, evaluates the actions selected by the actor. Definition of the reward R is described in greater details herein after. The actor NN 314 is another NN that selects the actions based on its current parameters and states. To find the optimal policy, the following objective function is minimized with respect to the network parameters using the gradient descent technique: J^^ϕ^ ൌ E^^౪,ୟ౪^^logπம^a^|s^^ െ ୩ mୀi^n,ଶ Q^ౡ^s^, a^^^ (4)where ^^ represents the parameters of the actor NN 314 and ^^ represents the parameters of the critic NN 316. It should be noted that, in some implementations, the SAC algorithm 312 adopts the experience replay and target network concepts to prevent dependence on correlated consecutive observations, Q-values overestimation and to stabilize training. Therefore, for instance, for the critic NNs, there is another target network where the minimum of the two networks is used for policy calculations as shown in (4). Additional details about implementing such an algorithm according to some implementation of the present technology are also described in Prianto et al., 2020, the entirety of a content thereof being incorporated by reference herein.

[0094] In this illustrative example, the actions provided by the actor NN 314 take values between (-1,1). Therefore, actions provided to the DA environment 214 are rescaled / denormalized to the boundaries of each device parameter. Said rescaling is done by carrying out some interpolation method as disclosed in (Virtanen et al., 2020), the entirety of a content thereof being incorporated by reference herein. 304628991.1 110447 / 3

[0095] It should also be noted that, in this implementation, the inputs to the actor and critic NNs 314, 316 are normalized. Indeed, the values of the POIs in vector S can have different order of magnitudes. As an example in the context of electronic circuit optimization, the Unity Gain Frequency can have values that exceed 1e6, while the Power can be a value of the order of 1e-3. Therefore, in some implementation, each POI is normalized using its specific objective according to the following formula: ^^^^^^^^ ^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^ൌ |^^^^^^^^ | ^ |^^^^^^∗|(5)^ ^

[0096] This update step, as disclosed in (Ioffe and Szegedy, 2015), the entirety of a content thereof being incorporated by reference herein.

[0097] The definition of the aforementioned reward function will now be described. In this implementation, the reward function is a multi-objective reward function due to multiple POIs to optimize and multiple optimized values of the device parameters to optimize said multiple POIs. Broadly speaking, a reward is a feedback quantity that quantifies the immediate benefit of taking a particular action in one state and going to the next state as a result of that action. In this implementation, the final reward provided to the RL algorithm 212 is a single scalar value.

[0098] In this implementation, the optimization kernel 210 defines a reward vector (^^^ெ) using current values of the POIs and corresponding target value (that may be included in the target design specifications). Said definition may be implemented using Canberra Distance as described in Lance and Williams, 1967, the entirety of a content thereof being integrated herein by reference, where each element of the reward vector corresponds to the specific reward value of each POIs.

[0099] Given a state S, the specific reward for each POI is calculated according to its corresponding target value (POI*) in ^^∗and its specific goal in ^^. If the specific goal is a maximum target value (i.e. the POI is to be maximized until it is larger than or equal to its corresponding value POI*) then the reward is calculated according to equation (6) (see below). If the goal is a minimum value (i.e. the POI is to be minimized until it is below or equal to its corresponding target value POI*) then the reward is calculated according to equation (7) (see below). If the goal is an exact value (i.e. the POI is to be equal to its corresponding target value 304628991.1 110447 / 3  POI*) then the reward is calculated according to equation (8) (see below). A vector includingthe specific reward for each POI at each step is obtained as ^^^ெ ൌ ^^^^,^^ଶ,^^ଷ, …^^ெ^.^^^^^^^^^ െ |^^^^^^^∗|

[100] ^^^^^^^^^^^^ெ^௫ൌ|^^^^^^^^(6) ^| ^ |^^^^^^^∗| (7)(8) if the^^^^^^^^^^^^ா௫^^௧ ൌ 0, and using the negative of the absolute value in the proposed expressionimplies that this term is negative except when the desired performance is met. It should be noted that for ^^^^^^^^^^^^ெ^^if ^^^^^^^^^is negative and its absolute value is less than ^^^^^^^∗the output is multiplied by -1.

[0104] A binary reward vector denoted as ^^^^^is further determined from ^^^ெby the optimization kernel 210 according to a pre-determined threshold ^^௧^. The determined threshold ^^௧^may be defined by a user of the optimization environment 100. In other words, if the value of the specific reward ^^^in ^^^ெis larger than ^^௧^, the ^^^^^^ is considered achieved and the corresponding value of the reward in ^^^^^is one, otherwise the value is zero.

[0105] The final value of the reward (^^) may be calculated according to the following equation (9) using the Hamming distance, as described in (Bookstein et al., 2002), the entirety of a content thereof being incorporated by reference herein, between the goal reward vector ^^^∗^^(a vector of ones with a length equal to the number of POIs) and the binarized reward vector ^^^^^. െ^^^, ^^^^ ^^^ ^ 0(9) vectors, ^^^is the ^^௧^element of the reward vector ^^^ெ, and ^^ is equal to the number of POIs. In this implementation, the Deep Reinforcement Learning architecture includes a multi-objective 304628991.1 110447 / 3  reward function that addresses specific objectives for each performance metric, assigning individual rewards and weights to signify the relative importance of each objective.

[0107] Broadly speaking, in Deep Reinforcement Learning (DRL), the actor neural network of the soft-actor-critic (SAC) algorithm is trained to determine a set of optimal design variable values that lead to desired circuit specifications (i.e. performances-of-interest) in each state of the multi-variable architecture. The state of the multi-variable architecture is defined by the current values of the POIs. In use, the actor NN learns to determine these optimal values by adjusting its weights, until reaching an optimal policy. The critic NN which is used in the training of the actor network, outputs the q-values for each state-action pair ^^^^^,^^^, it also uses a supplementary, secondary network called value network ^^^^^^ that outputs the state-value.

[0108] With reference to Figure 16, an architecture of the SAC algorithm 312 is depicted. The actor NN 314 has an input layer adapted according to the number of POIs, while the output layer varies based on the number of design variables. The critic NN 316 has an architecture with an adaptive input layer and a single output. In some implementations, the input layer of the critic NN 316 changes based on the number of performances-of-interest and design variables. The Q-value network employs a double Q-network technique for enhanced learning efficiency. Each network includes additional hidden layers (H hidden layers), with each layer comprising a fixed number of neurons (N neurons) fixed at the start either based on hyper- parameter optimization or based on trial and error which depends on the common practices found in the literature. Other hyperparameters include learning rate, discount (γ), entropy weight, target smoothing coefficient (τ), batch size, buffer size, initial warm up steps, maximum number of episodes (E) maximum number of steps (J), number of training episodes (m) number of sampled objectives (n) can be varied manually or automatically to assess their impact the learning and prediction performance.

[0109] The following table provides illustrative values of the hyper-parameters of the SAC algorithm 312: 304628991.1 110447 / 3  Hyperparameters    Optimizer  Adam Learning rate  1e‐3 Discount(γ)  0.99 Entropy weight  1e‐3 Target smoothing coefficient (τ)  0.005 Batch size  128 Buffer size  10e6 Initial warm up steps  500 Maximum number of episodes (E)  300 Maximum number of steps (J)  1500 No. of training episodes (m)  5,10,20 No. of sampled objectives (n)  4,9 Actor Neural Network Architecture    Type  Multi‐layer perceptron  Input size  Number of states Hidden layer size [N, N]  [256, 256] Output size  2* Number of actions Output Activation  Tanh Critic Neural Network Architecture    Type  Multi‐layer perceptron Input size  Number of states + Number of actions Hidden layer size [N, N]  [256, 256] Output size  1 Output Activation  Identity

[0110] In use, information about the optimal design parameters is stored in the weights and biases of the actor NN 314 and critic NN 316. These networks not only help in achieving current set POIs but may also be used for transfer learning, applying learned information to different sets of POIs. They effectively learn a generalized optimal policy for the provided design space, offering the optimal set of design parameters for any given state. These networks may be stored in a library for each circuit type and may be further recalled for future applications, such as deployment for the same values of POIs or transfer learning for new values of POIs.

[0111] As shown on Figure 4, the MLA 212 iteratively interacts with the DA environment 214 such that the optimization kernel 210 may provide optimized device parameter values 109. More specifically, in the context of electronic circuit optimization, the DA environment 214 304628991.1 110447 / 3  may be an open-source circuit simulator such as LTspice®, or commercial ones such as MATLAB®Simulink®or Cadence®Spectre®simulators. As an example, at the system level design and high-level verification, MATLAB®Simulink®can be utilized, while at the integrated circuits design, Cadence®Spectre®can be utilized. The interaction between the selected simulator 214 and the RL algorithm 212 may be automated. This is to allow the RL algorithm 212 to carry out the repetitive task of sending actions (setting the device parameters) to the simulator and receiving states (POIs) with minimal interaction from the circuit designer or an operator of the environment 100. Optimization kernel execution

[0112] Prior to execution of the optimization kernel on a given multi-variable architecture (an electronic circuit is taken as an example of multi-variable architecture in the following section), a complexity level of the electronic circuit may be determined by the optimization device 110. In some alternative implementations, the user of the optimization environment 100 may prepare a circuit testbench and determine the complexity level of the electronic circuit, and then selects which approach is necessary to optimize such circuit. More specifically, a direct optimization approach is executed for electronic circuit whose complexity level is below a given threshold, and an incremental optimization approach is executed for electronic circuit whose complexity level is above said threshold.

[0113] With reference to Figure 4, the optimization kernel 210 receives design information 402 about the electronic circuit to be optimized. The design information 402 may include, for example and without limitation, a circuit netlist indicative of a circuit topology of the electronic circuit, one or more circuit input, and one or more circuit output.

[0114] In some implementations, ML-ensemble-based surrogate models may be constructed using methods such as Generative Adversarial Networks (GANs) or Deep Neural Networks (DNNs) to represent a given electronic circuit. For example, sampling techniques such as Multi-dimensional Latin-hypercube Sampling (LHS) can be employed to sample a number of representative hyperparameters and may also be used to obtain the training data for these surrogate models. The surrogate models can then be used to perform fast and efficient hyperparameter tuning.

[0115] In use, the design information 402 are instantiated in the EDA environment 214 by defining the circuit inputs, outputs, supply rails, parametrizing the device parameters, defining 304628991.1 110447 / 3  upper and lower bounds for each device parameter (i.e. device parameter boundaries). This is usually limited by the technology-node limits (e.g., transistor minimum length) and the expertise of the designer. Afterwards, the user may run a one-time simulation using random initial values for the device parameters within the defined boundaries, then probes and saves the POIs so that they can be easily extracted later. As an example, this can be done directly inside a circuit simulator such as Cadence through its embedded Calculator. Finally, the EDA environment 214 may export the netlist, device parameters, and POIs as scripts (such as Cadence®OCEAN scripts) that will be accessed by the RL algorithm 212 to optimize the electronic circuit. Direct optimisation approach

[0116] Given the goals vector (^^), device parameter boundaries, and circuit testbench, the direct RL approach allows training the MLA 212 directly to reach a target objective ^^∗ൌ ^^^^^^^^∗,^^^^^^∗ଶ, …^^^^^^ெ∗^ for a set of M POIs.

[0117] The MLA 212 is trained for an arbitrary large number of episodes, where an episode is a sequence of a pre-determined number of steps in which the cycle of taking actions and observing the corresponding states and rewards is carried out upon interacting with the DA environment 214. During each episode, the optimization kernel 210 is invoked for several steps. During each step, the MLA 212 selects the actions (the values of the device parameters) and sends them to the DA environment 214 that provides the MLA 212 with the corresponding states (i.e. the values of the POIs). Actions are selected from distribution with certain parameters (e.g. mean and standard deviation) whose values are calculated using the actor NN 314. The MLA 212 attempts to learn the optimal policy to select the proper distribution from which sampling actions will result in the desired design specifications. An episode terminates in response to the MLA 212 successfully reaching ^^∗, or if a maximum number of steps is reached.

[0118] In this implementation, ^^∗is set to ^^∗At the beginning of the episode and actions are selected randomly at the first step. If this is the initial episode, the MLA 212 keeps selecting actions randomly until the total number of steps is more than a predetermined number of exploration steps. Selecting actions randomly helps the MLA 212 accumulate knowledge about the design space. After the termination of the random exploration steps, the MLA 212 starts the training process. During each training step, a cycle takes place in which the MLA 212 304628991.1 110447 / 3  selects new actions (i.e. new values of device parameters) based on the previous states (i.e. previous POIs values), then the DA environment 214 provides the MLA 212 with the new states (^^).

[0119] A reward is calculated based on the reached POI values in ^^, specific objectives (^^∗^ and specific goals in ^^, then using the SAC algorithm 312, the parameters of the actor and critic NNs 314, 316 are updated. Finally, at the end of each successful episode, the MLA 212 provides the user with the optimized device parameter values 109 of an optimized design (i.e. including the values of the device parameters that satisfy ^^∗). Incremental optimization approach

[0120] For electronic circuit having a relatively high complexity, another approach is provided by the present technology. As will be described in greater detail herein after, the incremental optimization approach includes operations that are similar to operations of the aforementioned direct approach. Additional operations are executed to smoothly learn the optimal policy required to reach the actions distribution that achieve a target complex objective ^^∗ൌ ^^^^^^^^∗,^^^^∗ଶ, …^^^^^^ெ∗^. The incremental optimization approach is inspired by incremental machine learning (IML) in which the input data is continuously updated to augment the knowledge of the trained ML agent, without retraining it from scratch, as described in Mera et al., 2019, the entirety of a content thereof being incorporated herein by reference.

[0121] In some implementations, complexity of an electronic circuit is determined based on the number of design variables the number of design specifications, the desired specifications and their values or a combination of two or more of these criteria.

[0122] In this implementation, the optimization device 110 defines an objective space with respect to less constraining objectives O^(i.e. a vector of relaxed design specifications with values higher or lower than the desired ones). The definition of O^may be based on the specific goals in (G) and / or an input of the user. For example, the POI∗for POIs that need to be maximized, minimized, and kept at an exact value are reduced, increased and unchanged, respectively to define O^.

[0123] To cover the objective space between ^^ாand ^^∗, ^^ objectives are sampled within the objective space. To do so, the Latin Hypercube Sampling (LHS) technique may be executed, as described in Loh, 1996, the entirety of a content thereof is incorporated by reference herein. 304628991.1 110447 / 3  The n sampled objectives are then used to incrementally train and guide the MLA 212 towards the actions distribution that reach the desired objective ^^∗.

[0124] In use, a distance between each sampled objective and ^^ாis determined by the optimization device 110. To differentiate between the complexity of the objectives, the Minkowski Distance (MD) described in (Nielsen, 2019), the entirety of a content thereof is incorporated by reference herein, may be used as a distance metric. The sampled objectives may further be arranged in an ascending order according to the calculated distance. The objectives with lower distance are considered closer in space to the less constraining objective than the objectives with higher distance. In use, the MLA 212 traverses the objective space incrementally, going from an objective (which is an ensemble of target values POI*) to another. The same training steps in the direct optimization approach are followed here, however, the MLA 212 is trained starting by the ^^∗set as ^^ா, then after m episodes, ^^∗is changed to another sampled objective. The agent keeps traversing the objective space until it starts learning the target objective ^^∗after [m*(n+1)] episodes.

[0125] To demonstrate the incremental approach, a numerical example of a generic circuit with two ^^^^^^^^: Gain (in dB) and Power (in mW), is provided. Given a target objective ^^∗= [90dB, 10mW], where the first value in the vector corresponds to the Gain and the second value corresponds to the Power. A relaxed, or “less constraining”, objective ^^ா= [60dB, 30mW] may be defined. Using the LHS technique, 4 objectives are sampled in the form of [Gain (dB), Power (mW)] values: {[80,30], [70,10], [60,23.3], [90,16.67]}. By calculating the Minkowski distance between the sampled objectives and ^^ா, the values (20, 20.8, 6.67, 30.85) are obtained. Using the calculated distance, the objectives may be ranked as ^^^= [60, 23.3], ^^ଶ= [80, 30], ^^ଷ= [70,10], ^^ସ= [90, 16.67]. Finally, the MLA 212 is trained incrementally on the selected objectives, starting by ^^ா, then on the objective with the lowest MD: (^^^) then ^^ଶ, ^^ଷ, ^^ସ, and finally the process is completed with the target objective (^^∗).

[0126] It should also be noted that the direct optimization approach is considered a special case of the proposed incremental optimization approach in which the number of sampled objectives(n) is equal to zero and ^^ா ൌ ^^∗. Another special case of the incremental optimizationapproach is the abrupt learning approach in which the MLA 212 is trained on ^^ாthen it immediately switches to ^^∗after m episodes. The steps for training the agent to optimize the circuit using the direct, abrupt or the incremental optimization approaches are summarized in the following pseudocode: 304628991.1 110447 / 3

[0127] In some implementations, in case the direct optimization approach failed to optimize the circuit under design, the constraints on the performances-of-interest may be relaxed. A failure criterion such as calculating the number of failed consecutive episodes may be used to terminate the optimization using the direct approach and an automatic or manual process can be used to relax the design specifications and then perform the incremental approach. In case the incremental optimization approach failed to optimize the circuit after a predetermined number of steps or episodes, the visualization and tradeoffs analysis module can then be used 304628991.1 110447 / 3  by the designers to help them decide to change the circuit topology or relax the values of the target POIs.

[0128] In another aspect, the present technology provides a causal discovery method that extracts high-level information from low-level historical data collected from the interactions between the MLA 212 and the DA environment 214. More specifically, the proposed method combines feature selection and a data-driven interventional technique to identify influential device parameters, which are then analyzed using an explainable machine learning technique to estimate their contributions and direct or inverse relations to the POIs. This information may further be used to identify the conflicting relationships between the device parameters and shared POIs, to create a sorted set of device parameters and a weighted causal graph. This may provide user and designers of multi-variable architectures with visual and quantifiable illustrations of the causal relationships, enabling them to optimize the circuit based on actionable insights.

[0129] Figure 5 is a schematic representation of a pipeline 500 for determining actionable insights of a multi-variable architecture in accordance with some non-limiting implementations of the present technology. The pipeline may be executed by the optimization device 110 or any other suitable system. As shown on Figure 5, an input of the pipeline 500 includes historical data 502 obtained from the interactions between the MLA 212 and the DA environment 214 within the optimization kernel 210. In this implementation, the historical data 502 includes both the values of the device parameters supplied by the MLA 212 to the DA environment 214 and the corresponding POIs values generated by the simulator which encompass the failed and successful attempts of the trained MLA 212.

[0130] To ease an understanding and description of the pipeline 500, the pipeline 500 is divided into two phases, each phase including several stages. The first phase involves using feature selection techniques to extract the causal device parameters, while the second phase involves extracting the contributions and the relations (directly or inversely proportional) between the causal device parameters and the POIs. From these relations, an abstract causal function denoted ^^^^ி^may be determined in which the arguments of the function represent the causal device parameters and their direct or inverse relationships with respect to the ^^௧^POI. This function enables a direct comparative analysis with a corresponding theoretical design equation denoted ^^^்ி^. The final outcomes from the pipeline 500 may include a directed weighted causal graph and sorted causal device parameters. 304628991.1 110447 / 3  Phase 1

[0131] During the first phase of the pipeline 500, the causal device parameters are extracted using feature selection and a data-driven interventional technique. As previously described, the input of the pipeline 500 is the historical data 502 which includes the values of POIs and the corresponding device parameters. It should be noted that the causal device parameters are device parameters whose influence on the different POIs have been determined.

[0132] In some implementations, the historical data 502 may be preprocessed by performing standardization and removing missing values. Broadly speaking, the potential causal device parameters affecting each POI are the combined outputs from an Evolutionary algorithm-based feature selection (EAFS) operation and a multivariate filtering feature selection technique (mRMR). Finally, the causal device parameters are the ones extracted from an Interventional Permutation Importance (PIM) operation.

[0133] The steps of the EAFS operation are illustrated with reference to Figure 6 with a numerical example with arbitrary values. The first step in the EAFS technique involves initializing a population of binary arrays (i.e. “individuals”) where one represents the presence of a device parameter and zero represents the absence of that device parameter. The second step involves evaluating a fitness of the individuals. This may be done by training a machine learning (ML) regression model using the subset of device parameters, which are present in each individual candidate and measuring the model’s performance. It should be noted that any ML regression model can be used in the feature selection and intervention steps, such as neural network regression, support vector regression, decision trees, random forests, or an ensemble of ML regression methods.

[0134] Metrics such as mean squared error (MSE) or the coefficient of determination (^^ଶ^, as described in greater detail in Nakagawa et al., 2017, the entirety of a content thereof is incorporated be reference herein, can be used to measure the model’s performance. The third step includes selecting the fittest individuals, then performing crossover, and mutation on the selected individuals in the fourth and fifth steps, respectively to generate a new population. In the crossover step, new individuals are created by combining device parameters from two parents (selected individuals), while in the mutation step, the binary value of some device parameters are randomly changed as shown in Figure 6. 304628991.1 110447 / 3

[0135] Afterwards, the initial population is replaced with the new population and the entire procedure is repeated until reaching a pre-determined stopping criterion. The stopping criterion is either reaching a fitness value that does not change (within a threshold) over a specified number of generations or reaching a certain maximum number of generations. Finally, the best- performing subset of device parameters is selected as the most representative device parameters. This process is repeated for each POI to extract its set of potential causal device parameters.

[0136] The steps of the mRMR feature selection technique operation are illustrated with reference to Figure 7. For the sake of illustration, the figure includes arbitrary numerical values that illustrate each step in the mRMR technique, the examples given in the figure assume that one device parameter (^^ଶ) is already selected. In this technique, k device parameters are typically selected as the most representative ones, where k is usually defined by the expert. To automate the process in the pipeline 500, k is selected to be the number of features extracted by the EAFS for the target POI. In the first step of the mRMR technique, the relevance score between each non-selected device parameter and the target POI is computed, then the redundancy scores between each non-selected device parameter and the previously selected device parameters are calculated in the second step (this score is set to be 1 for the first considered device parameter). Afterwards, combined scores are determined in a third step. For example, the combined scores may be determined as described in Mazzanti, 2021, the entirety of a content thereof is incorporated be reference herein. In a fourth step, the device parameter with the highest combined score is appended to the previously selected device parameters. Finally, if the number of extracted device parameters is not equal to k, the steps listed above are repeated, otherwise the process is terminated, and the final k most representative device parameters are selected. ^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^ ^^^|^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^ ^^^^^^^^^^ ^^^^^ൌ ^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^ ^^^^10^ , are statistical measures such as the F-test, correlation, or mutual information. In some implementations, the relevance score is determined using an F-test, and the redundancy score is determined based on correlation, as described in Hanchuan Peng et al., 2005, the entirety of a content thereof is incorporated be reference herein. It can thus be said that the EAFS operation and mRMR technique are used to extract potential causal device parameters. Broadly speaking, 304628991.1 110447 / 3  contribution of a given device parameters on a POI is determined using an explainable ML algorithm. the aforementioned evolutionary algorithm and mRMR technique extract a set of relevant variables for each POI. More specifically, the mRMR technique uses the relevance score (a statistical measure between each not selected device parameter and POI, and a redundancy score (a statistical measure between each non-selected device parameter and each selected device parameter).

[0138] Figure 8 is a schematic representation of operations of an interventional permutation importance (PIM) algorithm of the pipeline 500 in accordance with some implementations of the present technology. The PIM algorithm provides an alternative method to simulate the effect of interventions through data manipulation rather than performing long iterative simulations. To perform interventions using PIM, the following steps are carried out for each POI.

[0139] A first step of the PIM algorithm includes training a machine learning (ML) regression model on a dataset containing only the potential causal device parameters, or “relevant device parameters”. A second step includes measuring the performance of the ML regression model using a performance metric (^^^), such as ^^ଶor MSE. For each potential causal device parameter, an interventional dataset is determined by randomly permuting its values while keeping other device parameters unchanged. The interventional dataset may further be used as input to the trained ML model and compute the same performance metric (^^ଶ). This processis repeated n times and an average of the computed metrics (∑^ ^^^ଶ^ ൌ ^^ଶ^௩^^ may further be computed.

[0140] In some implementations, a permutation score of each potential causal device parameter may further be calculated as the absolute difference between ^^^and ^^ଶ^௩^. In response to the permutation score being above a pre-determined threshold , the device parameter is considered a causal device parameter. Phase 2

[0141] In the second phase of the pipeline 500, two outcomes are extracted, a weighted directed causal graph (see illustrative example of weighted directed causal graph 1320 on Figure 13B) that relates the extracted causal device parameters to the corresponding POIs, and a list of sorted device parameters that enable the user to perform informed design decisions. To obtain 304628991.1 110447 / 3  these outcomes, a contribution of the causal device parameters and their relations (i.e. direct or inverse) to the POIs is determined using an explainable ML technique. For example, the explainable ML technique may be the tree-based TreeSHAP technique, as described in Lundberg et al., 2020, the entirety of a content thereof being incorporated by reference herein. The device parameters may further be sorted based on a number of conflicting relations between the device parameters and POIs and a level of influence of the device parameters on the POIs.

[0142] Figure 9 is a schematic representation of operations of a local explanation generating algorithm of the pipeline 500 in accordance with some implementations of the present technology. The relative contribution and the relation type of the extracted causal device parameter to their respective POIs are determined. To do so, the optimization device 110 may execute the aforementioned TreeSHAP technique. As shown on Figure 9, inputs of the local explanation generating algorithm 910 are a trained model 905, the values of the device parameters and predictions of the model 905. The local explanation generating algorithm 910 takes these inputs and assigns a score, or “local SHAP”, to each device parameter at each data point indicative of a contribution of the device parameter to the prediction of the trained model 905. Additionally, the optimization device 110 determines a global contribution of each device parameter, or “global SHAP” by calculating the average of the absolute of the local SHAP values.

[0143] More specifically, Figure 10 is a schematic representation of operations for determining relative contributions and relations of device parameters and performances-of-interest executed in the pipeline 500 in accordance with some implementations of the present technology. Using the extracted causal device parameters for each POI, the local SHAP values may be determined using the TreeSHAP technique. The relative contributions and relations may further be determined based on the local SHAP values. In some implementations, the global SHAP values are divided by the maximum global SHAP value among all causal device parameters to determine the corresponding relative contributions.

[0144] In the example given in Figure 10, this value corresponds to the value of ^^^(0.45). This allows the user to receive insights relative to the relative impact of the device parameters with respect to each other. The values of the device parameters may be compared against their local SHAP values to obtain the SHAP dependence plots as described in Lundberg et al., 2020 and to determine whether the relation is direct or inverse. This may provide a quantitative and visual 304628991.1 110447 / 3  interpretation to the user. The relative contributions and relations are then used to sort the device parameters as illustrated on Figure 11.

[0145] Figure 11 is a flow-diagram of a Minimum Conflict Relative Contributions & Occurrences (MiCRO) algorithm of the pipeline 500 in accordance with some implementations of the present technology. Broadly speaking, the MiCRO algorithm 1100 is executed to sort device parameters based on the identified causes, their relationships, contributions, frequency of occurrence and target values for each POI. The optimization device 110 may execute the MiCRO algorithm 1100 to further optimize the electronic circuit or fine-tune it in the post- layout verification phase.

[0146] To determine the most effective order to do so, two main criteria are considered. The first criterion relates to the conflicting relationship between the POIs and shared causal device parameters. The second criterion relates to the level of influence that each device parameter has on all the POIs (including occurrence frequency, local contribution to each POI, and global contribution to shared POIs). A first operation of the MiCRO algorithm 1100 includes counting a number of conflicts for all causal device parameters and POIs. To do so, the goal G (maximize, minimize, or exact) for each POI and the relation between each causal device parameter and the shared POIs are extracted. After counting the number of conflicts for each causal device parameter, the device parameters are sorted using two strategies: 1) a local strategy for optimizing a specific POI through pipeline 1110, and 2) a global strategy that considers all device parameters and POIs through pipeline 1120 simultaneously. In some implementations, device parameters with lower conflict counts are prioritize in both strategies.

[0147] In the pipeline 1110, if the number of conflicting relations for two device parameters is n, device parameters with fewer conflicting relations are prioritized, then consider device parameters with lower contribution than other device parameters. Indeed, modifying the values of device parameters with conflicting relations may lead to undesired changes in the shared POIs. By contrast, if the number of conflicting relations for two device parameters is zero, the device parameters with the highest local contribution are prioritized. Indeed, these device parameters will only impact the target POIs.

[0148] Similarly, in the pipeline 1120, if the number of conflicting relations for two device parameters is n, device parameters with fewer conflicting relations are prioritized, then device parameters with lower total contribution. However, if the number of conflicting relations for 304628991.1 110447 / 3  two device parameters is zero, device parameters with higher occurrences are prioritized, as manipulating these device parameters positively impacts the shared POIS. If the number of occurrences is the same, device parameters with the highest total contributions are prioritized, as they may have a higher impact on the shared POIs.

[0149] Figure 12 illustrates example on how the number of conflicts is determined. In this example there are three POIS to be maximized (POIs^ିଷ^ and two POIs to be minimized (POIsସିହ^. For instance, device parameter Vଷhas a direct relation with POI^& POIଶand an inverse relation with POIଷ& POIସ. Increasing Vଷmay increase both POI^& POIଶand decrease both POIଷ& POIସ, however POIs^ିଷare to be maximized and POIସis to be minimized. This isindicative of conflicting relations between ^POI^ , POIଶ^ and POIଷ, and a conflicting relationbetween POIଷand POIସ, with a total of three conflicting relations. Similarly, examining the relation between V^and all POIs, six conflicting relations may be found, while there are no conflicting relations for Vଶ, as increasing Vଶwill increase both POI^& POIଷand decrease POIସ, which is desired in this example. Examining the relationships between device parameters and POIs results in the identification and quantification of conflicting relations. This insight may help the user to make trade-offs between the POIs, enabling them to make better decisions during the optimization process.

[0150] A case study is provided using an electronic circuit 1310 of an operational-amplifier on Figure 13A. Broadly speaking and as described herein above, the causal device parameters are extracted, their contributions and relations between these device parameters and target POIs. From these relations, the abstract causal function (^^^^ி) are obtained for each POI which can be compared against corresponding abstract theoretical function (^^^்ி) obtained from the analytical design equations. Additionally, these relations may be validated by performing quantitative interventional simulations. Finally, the aforementioned MiCRO method may be applied to provide a list of sorted causal device parameters.

[0151] Figure 13B depicts a weighted directed causal graph 1320 for the operational-amplifier circuit of Figure 13A. The weighted directed causal graph provides a visual illustration of the relations between the device parameters W7, W5, W3,4, CC, IBiasand W1,2, and the POIs PM, UGF, Power and Gain. Moreover, the weights on the edges represent the relative contributions of the causal device parameters; a positive weight indicating a direct relation while a negative weight indicating an inverse relation. The graph 1320 is therefore indicative of a number of 304628991.1 110447 / 3  conflicting relations for each device parameter, the number of shared POIs and the local and global contributions of the device parameters.

[0152] Figure 14 shows the sorted causal device parameters for each POI, along with their local contributions and conflicts. The graph 1320 and the table of Figure 14 form actionable insights that may be provided to the user of the optimization environment 100. The user provided with such as table may use it along with the graph 1320 to determine the priority of device parameter optimization when fine-tuning the circuit in a post-layout phase of the optimization of the electronic circuit 1310.

[0153] For instance, if only the Gain requires post-layout fine-tuning, the user can focus on ^^ଷ,ସwhich is more unique and strongly related to the Gain. On the other hand, if both the Gain and the UGF require tuning, the user may focus on ^^^,ଶ, which is shared between them and does not cause conflicts. The table also shows a comparison between ^^^^ிand ^^^்ிfor the op- amp circuit. The comparison along with the following figures illustrate the effectiveness of the proposed method, as it accurately captures the causal device parameters and their proportionality with respect to their POIs.

[0154] It is worth mentioning that, for some POIs, the inferred abstract function completely agrees with the theoretical abstract functions derived from the full analytic functions, as in the case of ^^^்ிభೌfor Gain and ^^^்ிమ್for UGF. For other POIs, such as PM, some device parameters, such as ^^ଷ,ସ, and ^^^,ଶare excluded from the inferred function due to their relatively lower impact.

[0155] Figure 15 is a flow diagram of a method 1500 for determining optimized device parameters of an electronic circuit according to some implementations of the present technology. In one or more aspects, the method 1500 or one or more steps thereof may be performed by a processor or a computer system, such as the optimization device 110. The method 1500 or one or more steps thereof may be embodied in computer-executable instructions that are stored in a computer-readable medium, such as a non-transitory mass storage device, loaded into memory and executed by a CPU. Some steps or portions of steps in the flow diagram may be omitted or changed in order.

[0156] The method 1500 starts with accessing, at operation 1510, design information of the electronic circuit. For example and without limitations, the design information may include a 304628991.1 110447 / 3  circuit netlist indicative of a circuit topology of the electronic circuit, one or more circuit input, and one or more circuit output.

[0157] The method 1500 continues with determining, at operation 1520, a set of device parameters of the electronic circuit based on the design information. For example, a given device parameter may include at least one of a capacitance of an electronic component of the electronic circuit, a resistance thereof, an inductance thereof, a bias current flowing therein, a voltage value thereof, and a width and / or a length of a transistor thereof.

[0158] The method 1500 continues with receiving, at operation 1530, information indicative of set of performances-of-interest to be optimized, and a corresponding set of target values, each target value being associated with a corresponding performance-of-interest.

[0159] In some implementations, receiving information indicative of set of performances-of- interest to be optimized includes receiving, from a designer of the electronic circuit, descriptive data of the set of performances-of-interest. In some alternative implementations, receiving information indicative of set of performances-of-interest to be optimized includes determining, by executing a dedicated algorithm, the set of performances-of-interest based on the design information of the electronic circuit.

[0160] The method 1500 continues with defining, at operation 1540, a multi-objective reward function based on the set of performances-of-interest to be optimized.

[0161] The method 1500 continues with outputting, at operation 1550, using a pre-built Machine Learning (ML) algorithm interacting with an electronic design automation (EDA) environment, an optimized device parameter value for each of the device parameters based on the multi-objective reward function. In some implementations, the ML algorithm is a Reinforcement Learning algorithm. For example, the ML algorithm may include a Soft Actor- Critic reinforcement learning algorithm.

[0162] In some implementations, the method 1500 further includes extracting historical data from the interaction of the ML algorithm with the EDA environment and determining, for each performance-of-interest, a causal function indicative of a relation between the performance-of- interest and the device parameters based on the historical data. For example, a contribution factor for each pair of device parameter – performance-of-interest may be determined based on the causal function. 304628991.1 110447 / 3

[0163] In these implementations, determining a contribution factor may include employing an explainable ML algorithm to determine causal device parameters based on the device parameters, determining, for each device parameter, a relevance score indicative of a causality of the device parameter on a given performance-of-interest, determining, for each device parameter, a redundancy score indicative of a number of performances-of-interest related to the device parameter and determining the contribution factor based on the relevance score and the redundancy scores thereof.

[0164] In these implementations, the method 1500 also includes determining, for each device parameter, a global contribution score indicative of a first level of influence that the device parameter has on the set of performances-of-interest, determining, for each device parameter and for each performance-of-interest, a local contribution score indicative of a second level of influence that the device parameter has on the performance-of-interest and determining, for each device parameter, an occurrence frequency score indicative of a number of performances- of-interest influenced by the device parameter. The method 1500 further includes sorting the set of device parameters based on at least one of the global contribution scores, the local contribution scores, and the occurrence frequency scores.

[0165] In the same or other implementations, the method 1500 includes determining a complexity value for the electronic circuit and, in response to the complexity value being above a given threshold, upon receiving the set of target values, determining one or more sets of sub- target values based on the set of target values, the one or more sets of sub-target values being relatively less constraining than the set of target values, the ML algorithm being configured to incrementally determines sub-optimized device parameter values for each set of sub-target values.

[0166] It will be appreciated that at least some of the operations of the method 1500 may also be performed by computer programs, which may exist in a variety of forms, both active and inactive. Such as, the computer programs may exist as software program(s) comprised of program instructions in source code, object code, executable code or other formats. Any of the above may be embodied on a computer readable medium, which include storage devices and signals, in compressed or uncompressed form. Representative computer readable storage devices include conventional computer system RAM (random access memory), ROM (read only memory), EPROM (erasable, programmable ROM), EEPROM (electrically erasable, programmable ROM), and magnetic or optical disks or tapes. Representative computer 304628991.1 110447 / 3  readable signals, whether modulated using a carrier or not, are signals that a computer system hosting or running the computer program may be configured to access, including signals downloaded through the Internet or other networks. Concrete examples of the foregoing include distribution of the programs on a CD ROM or via Internet download. In a sense, the Internet itself, as an abstract entity, is a computer readable medium. The same is true of computer networks in general.

[0167] While the above-described implementations have been described and shown with reference to particular steps performed in a particular order, it will be understood that these steps may be combined, sub-divided, or re-ordered without departing from the teachings of the present technology. At least some of the steps may be executed in parallel or in series. Accordingly, the order and grouping of the steps is not a limitation of the present technology.

[0168] It can thus be said that the present technology provides a causal discovery method for analog circuit design. The proposed method combines two feature selection techniques and a data-driven interventional technique to analyze historical data, identifying the most influential device parameters that affect the POIs and constructing a directed causal graph that relates these device parameters to the POIs. In the context of electronic circuit optimization, the graph provides circuit designers with a visual representation of the extracted causal relations, alleviating the need for manual complex analysis of the theoretical design equations that relate these device parameters to the POIs.

[0169] The disclosed technology also adopts an explainable machine learning (ML) technique to extract the impact of the device parameters and their relation (direct or inverse) with the POIs. This provides the circuit designer with a quantifiable relation between the device parameters and the POIs, which may often not be obtained from direct theoretical analysis. It also allows the designer to identify the conflicting relations between each device parameter and the shared POIs, enabling them to focus on device parameters with the least conflicting relationships and the highest positive impact.

[0170] The disclosed technology also proposes an approach to sort device parameters according to the extracted causal relations, their relative contribution, the number of conflicting relations and the desired design specifications. The device parameters are sorted locally for each POI and globally considering the collective objectives of all POIs. This enables the circuit designer to fine tune the circuit based on actionable insights. For instance, if one POI is 304628991.1 110447 / 3  significantly degraded by layout parasitic, the designer may focus on the device parameters that have the highest positive impact on that particular POI and the lowest negative effect on the other POIs. Whether device parameters were successfully optimized to reach the target design specifications or not, the extracted aforementioned historical data may be used to extract 2D and 3D graphs, showing the trends and tradeoffs in between the performances-of-interest. Visualizing these graphs can help users (e.g. designers) to analyze the capabilities of the electronic circuit under test and gain more knowledge about the competing nature of the performances-of-interest enabling the identification of potential tradeoffs. The tradeoffs between the POIs may be further related to the device parameters using the developed causal discovery method.

[0171] It should be expressly understood that not all technical effects mentioned herein need to be enjoyed in each and every implementation of the present technology.

[0172] Modifications and improvements to the above-described implementations of the present technology may become apparent to those skilled in the art. The foregoing description is intended to be exemplary rather than limiting. The scope of the present technology is therefore intended to be limited solely by the scope of the appended claims. 304628991.1 110447 / 3

Claims

What is claimed is:

1. A computer-implemented method for determining optimized device parameters of an electronic circuit, the method comprising: accessing design information of the electronic circuit; determining a set of device parameters of the electronic circuit based on the design information; receiving information indicative of set of performances-of-interest to be optimized, and a corresponding set of target values, each target value being associated with a corresponding performance-of-interest; defining a multi-objective reward function based on the set of performances- of-interest to be optimized; and outputting, using a pre-built Machine Learning (ML) algorithm interacting with an electronic design automation (EDA) environment, an optimized device parameter value for each of the device parameters based on the multi-objective reward function.

2. The method of claim 1, wherein the ML algorithm is a Reinforcement Learning algorithm.

3. The method according to any one of claims 1 to 2, wherein receiving information indicative of set of performances-of-interest to be optimized comprises: receiving, from a designer of the electronic circuit, descriptive data of the set of performances-of-interest.

4. The method according to any one of claims 1 to 2, wherein receiving information indicative of set of performances-of-interest to be optimized comprises: determining, by executing a dedicated algorithm, the set of performances-of- interest based on the design information of the electronic circuit.

5. The method according to any one of claims 1 to 4, wherein the design information includes: 304628991.1 110447 / 3 a circuit netlist indicative of a circuit topology of the electronic circuit, one or more circuit input, and one or more circuit output.

6. The method of according to any one of claims 1 to 5, wherein the ML algorithm is a Soft Actor-Critic reinforcement learning algorithm.

7. The method according to any one of claims 1 to 6, further comprising: extracting historical data from the interaction of the ML algorithm with the EDA environment; and determining, for each performance-of-interest, a causal function indicative of a relation between the performance-of-interest and the device parameters based on the historical data.

8. The method of claim 7, further comprising determining a contribution factor for each pair of device parameter – performance-of-interest based on the causal function.

9. The method of claim 8, wherein determining a contribution factor comprises: identifying causal device parameters based on the device parameters; determining, for each causal device parameter, a relevance score indicative of a causality of the causal device parameter on a given performance-of-interest; determining, for each device parameter, a redundancy score indicative of a number of performances-of-interest related to the causal device parameter; and determining a contribution factor based on the relevance score and the redundancy scores thereof.

10. The method of claim 7, further comprising: determining, for each device parameter, a global contribution score indicative of a first level of influence that the device parameter has on the set of performances-of- interest; 304628991.1 110447 / 3 determining, for each device parameter and for each performance-of-interest, a local contribution score indicative of a second level of influence that the device parameter has on the performance-of-interest; and determining, for each device parameter, an occurrence frequency score indicative of a number of performances-of-interest influenced by the device parameter; the method further comprising: sorting the set of device parameters based on at least one of the global contribution scores, the local contribution scores, and the occurrence frequency scores.

11. The method according to any one of claims 1 to 10, further comprising: determining a complexity value for the electronic circuit; in response to the complexity value being above a given threshold, upon receiving the set of target values, determining one or more sets of sub-target values based on the set of target values, the one or more sets of sub-target values being relatively less constraining than the set of target values, the ML algorithm being configured to incrementally determines sub- optimized device parameter values for each set of sub-target values.

12. The method according to any one of claims 1 to 11, wherein a given device parameter comprises at least one of: a capacitance of an electronic component of the electronic circuit; a resistance thereof, an inductance thereof, a bias current flowing therein, a voltage value thereof, and a width and / or a length of a transistor thereof. 304628991.1 110447 / 3 13. A computer-implemented method for determining optimized device parameters of a multi-variable architecture, the method comprising: accessing design information of the multi-variable architecture; determining a set of device parameters of the multi-variable architecture based on the design information; receiving information indicative of set of performances-of-interest to be optimized, and a corresponding set of target values, each target value being associated with a corresponding performance-of-interest; defining a multi-objective reward function based on the set of performances- of-interest to be optimized; outputting, using a pre-built Machine Learning (ML) algorithm interacting with a design automation (DA) environment, a set of optimized device parameters based on the multi-objective reward function.

14. The method of claim 13, wherein the multi-variable architecture is a physical architecture.

15. The method according to any one of claims 13 to 14, wherein the multi-variable architecture is a logical architecture.

16. A system for determining optimized device parameters of an electronic circuit, the system comprising a controller and a memory storing a plurality of executable instructions which, when executed by the controller, cause the system to: access design information of the electronic circuit; determine a set of device parameters of the electronic circuit based on the design information; receive information indicative of set of performances-of-interest to be optimized, and a corresponding set of target values, each target value being associated with a corresponding performance-of-interest; 304628991.1 110447 / 3 define a multi-objective reward function based on the set of performances-of- interest to be optimized; and output, using a pre-built Machine Learning (ML) algorithm interacting with an electronic design automation (EDA) environment, an optimized device parameter value for each of the device parameters based on the multi-objective reward function.

17. The system of claim 16, wherein the ML algorithm is a Reinforcement Learning algorithm.

18. The system according to any one of claims 16 to 17, wherein receiving information indicative of set of performances-of-interest to be optimized comprises: receiving, by the controller and from a designer of the electronic circuit, descriptive data of the set of performances-of-interest.

19. The system according to any one of claims 16 to 17, wherein, receiving information indicative of set of performances-of-interest to be optimized comprises: determining, by the controller executing a dedicated algorithm, the set of performances-of-interest based on the design information of the electronic circuit.

20. The system according to any one of claims 16 to 19, wherein the ML algorithm is a Soft Actor-Critic reinforcement learning algorithm. 304628991.1 110447 / 3

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