Semiconductor device

Abstract

Provided is a semiconductor device (1) comprising a semiconductor substrate (10), an activation region–side electrode (20), an insulating layer (30), and a field plate (40), wherein the semiconductor substrate (10) includes a substrate region (12), a second conductivity-type activation region (14), and a second conductivity-type guard ring (16). The semiconductor substrate (10) further includes: a first surface semiconductor region (15) of a second conductivity type which is formed on a first main surface side so as to be in contact with the outer periphery of the activation region (14) and not be in contact with the guard ring (16) in plan view, and has a smaller total of impurities than the activation region (14); and a second surface semiconductor region (17) which is formed on the first main surface side so as to be in contact with the outer periphery of the guard ring (16) in plan view, and has a smaller total of impurities than the guard ring (16). Compared to semiconductor devices having a conventional guard ring structure, this semiconductor device (1) can be reduced in size while achieving a higher breakdown voltage, and can achieve a higher withstand capability for the device overall.

Description

Semiconductor Devices Cross Reference

[0001] This application claims priority based on Japanese Patent Application No. 2024-013049 filed on January 31, 2024, the entire contents of which are incorporated herein by reference.

[0002] The present invention relates to a semiconductor device.

[0003] Conventionally, semiconductor devices having a guard ring formed in a peripheral region (semiconductor devices having a guard ring structure) have been known (see, for example, Patent Document 1). A semiconductor device 900 (hereinafter referred to as "conventional semiconductor device 900"), which is an example of a conventional semiconductor device, will be briefly described below.

[0004] As shown in FIG. 4 , the conventional semiconductor device 900 includes a semiconductor substrate 910, an active region side electrode 920 disposed on a first main surface of the semiconductor substrate 910, an insulating layer 930 in contact with the outer periphery of the active region side electrode 920 and disposed on the first main surface, a field plate 940 in contact with the outer periphery of the active region side electrode 920 and disposed on the insulating layer 930, a second electrode 950, and a channel stop electrode 960.

[0005] The semiconductor substrate 910 is ＋ type semiconductor regions 912a and n － and a p-type base region 912 having an n-type semiconductor region 912b and a p-type electrode 920 formed on the first main surface side so that at least a portion of the p-type base region 912b overlaps with an active region side electrode 920 when viewed in plan. ＋ The semiconductor device has an active region 914, a plurality of guard rings 916 formed to surround the periphery of the active region 914 at a distance in plan view, and a channel stopper 919. The active region side electrode 920 and the field plate 940 constitute a first electrode.

[0006] In conventional semiconductor device 900, semiconductor substrate 910 has multiple guard rings 916 in the peripheral region, which allows the depletion layer that spreads from the pn junction between activation region 914 and substrate region 912 to spread to the peripheral region when reverse bias is applied, and also makes it possible to reduce the curvature of the depletion layer. Therefore, conventional semiconductor device 900 can increase the breakdown voltage compared to a semiconductor substrate 910 that does not have guard rings 916.

[0007] Japanese Patent Application Publication No. 10-173174

[0008] In order to obtain a high breakdown voltage in a semiconductor device with a conventional guard ring structure such as semiconductor device 900, it is necessary to increase the number of guard rings, but increasing the number of guard rings requires increasing the area of ​​the peripheral region. For this reason, there is a problem in that it is difficult to miniaturize a semiconductor device with a conventional guard ring structure while achieving a high breakdown voltage.

[0009] Furthermore, in semiconductor devices with conventional guard ring structures, the breakdown voltage at the corners is often lower than that at the edges when reverse bias is applied. For example, at the apex of the corner of guard ring 916 in conventional semiconductor device 900, the depletion layer is less likely to extend due to charge balance. Note that, when the outer edge of the corner of the guard ring is an arc with a central angle of 90° in plan view, as in conventional semiconductor device 900, the apex of the corner of the guard ring is a point on the arc at a central angle of 45°.

[0010] In semiconductor devices with a conventional guard ring structure, avalanche breakdown occurs near the apex of the corner of the guard ring before it occurs at the edge of the guard ring, resulting in a high current density at the corner, which results in a problem of low breakdown resistance for the entire device.

[0011] The present invention has been made to solve the above-mentioned problems, and has as its object to provide a semiconductor device that can be made smaller while achieving a higher breakdown voltage than semiconductor devices with a conventional guard ring structure, and that can increase the breakdown resistance of the device as a whole.

[0012] a first surface semiconductor region of the second conductivity type formed on the first main surface in contact with the periphery of the active region but not in contact with the guard ring, and a second surface semiconductor region of the second conductivity type formed on the first main surface in contact with the periphery of the active region but not in contact with the guard ring, and a second surface semiconductor region of the second conductivity type formed on the first main surface in contact with the periphery of the active region but not in contact with the guard ring, and a second surface semiconductor region of the second conductivity type formed on the first main surface in contact with the periphery of the guard ring, and having a smaller total impurity content than the active region; and

[0013] In the semiconductor device of the present invention, the semiconductor substrate has a first surface semiconductor region of a second conductivity type formed on the first main surface side so as to contact the outer periphery of the active region in plan view but not the guard ring, and having a smaller total impurity concentration than the active region. In the semiconductor device of the present invention, both the substrate region and the first surface semiconductor region can be depleted under reverse bias, thereby achieving a high breakdown voltage without increasing the number of guard rings. Therefore, the semiconductor device of the present invention can be made smaller while achieving a higher breakdown voltage than semiconductor devices with conventional guard ring structures.

[0014] In the semiconductor device of the present invention, the semiconductor substrate has a second surface semiconductor region formed on the first principal surface side so as to contact the outer periphery of the guard ring in a plan view, and having a smaller total impurity concentration than the guard ring. In the semiconductor device of the present invention, the second surface semiconductor region can reduce the electric field strength at the outer periphery of the guard ring, particularly at the apexes of the corners of the guard ring, under reverse bias. Therefore, the semiconductor device of the present invention makes it less likely for avalanche breakdown to occur at the corners under reverse bias, thereby increasing the breakdown resistance of the entire device.

[0015] As a result, the semiconductor device of the present invention can be made smaller while achieving a higher breakdown voltage than semiconductor devices with conventional guard ring structures, and can also be made to have a higher breakdown resistance as a whole.

[0016] 1A and 1B are diagrams illustrating a semiconductor device 1 according to a first embodiment. FIG. 1A is a plan view of the semiconductor device 1. FIG. 1B is a cross-sectional view taken along line A1-A1 of FIG. 1A. In this specification, a "plan view" refers to a view of the semiconductor device as seen from the first main surface of the semiconductor substrate. In FIG. 1A, the active region-side electrode 20, insulating layer 30, and field plate 40 are not shown in order to show the shapes of the active region 14, first surface semiconductor region 15, guard ring 16, and second surface semiconductor region 17. The method of showing each component in plan views according to embodiments other than FIG. 1A, which will be described later, is the same as that shown in FIG. 1A. These diagrams are diagrams illustrating a semiconductor device 2 according to a second embodiment. FIG. 2A is a plan view of the semiconductor device 2. FIG. 2B is a cross-sectional view taken along line A2-A2 of FIG. 2A. These diagrams are cross-sectional views illustrating a semiconductor device 3 according to a third embodiment. FIG. 3 is a cross-sectional view corresponding to FIG. 1B. These diagrams are diagrams illustrating a conventional semiconductor device 900. FIG. 4A is a plan view of the semiconductor device 900. Fig. 4(b) is a cross-sectional view taken along line A-A in Fig. 4(a). In Fig. 4(a), the active region side electrode 920, the insulating layer 930, and the field plate 940 are not shown in order to show the shapes of the active region 914 and the guard ring 916.

[0017] The semiconductor device of the present invention will be described below based on the embodiments shown in the drawings. In each embodiment described below, components having the exact same or substantially the same functions will be designated by common reference numerals in each embodiment, even if their shapes are slightly different, and descriptions already given may be omitted. The embodiments described below do not limit the invention according to the claims. Furthermore, not all of the elements and combinations thereof described in each embodiment are necessarily essential to the solution of the present invention.

[0018] [Embodiment 1] A semiconductor device 1 according to embodiment 1 is a planar diode. As shown in FIG. 1, the semiconductor device 1 includes a semiconductor substrate 10, an active region side electrode 20, an insulating layer 30, a field plate 40, and a second electrode 50. The active region side electrode 20 and the field plate 40 form a first electrode. The semiconductor device 1 may include components other than those described above. Note that, among the drawings including FIG. 1, those showing the configuration of the semiconductor device are schematic diagrams, and the sizes of the illustrated components do not necessarily correspond to the sizes of the actual components. Each component will be described below.

[0019] The semiconductor substrate 10 has a substrate region 12, an active region 14, a first surface semiconductor region 15, a guard ring 16, a second surface semiconductor region 17, and a channel stopper 19. The material of the semiconductor substrate 10 is Si.

[0020] The substrate region 12 is n ＋ type semiconductor regions 12a and n － The n-type semiconductor region 12b is a region of the first conductivity type (n-type in the semiconductor device 1). ＋ The surface impurity concentration of the type semiconductor region 12a is, for example, 1×10 ２０ cm －３ In addition, n ＋ The depth (n ＋ The thickness of the n-type semiconductor region 12a can be set to, for example, 5 to 90 μm. － The surface impurity concentration of the n-type semiconductor region 12b is ＋lower than the type semiconductor region 12a, for example, 5.0×10 １３ ~4.0 x 10 １４ cm －３ In addition, n － The thickness of the type semiconductor region 12b can be set to, for example, 40 to 200 μm.

[0021] The activation region 14 is a region of the second conductivity type (p-type in the semiconductor device 1) formed on the first main surface side so that at least a portion of the activation region side electrode 20 overlaps with the activation region side electrode 20 in a plan view. In this specification, the term "plan view" refers to viewing the target component from the first main surface side of the semiconductor substrate (the side on which the activation region side electrode is located).

[0022] The activation region 14 in the semiconductor device 1 is a region having an outer periphery in which four corners and four sides are alternately arranged. The corners of the activation region 14 are arc-shaped with a central angle of 90°. Therefore, the activation region 14 has a substantially rectangular shape with rounded corners when viewed from above. The surface impurity concentration of the activation region 14 is a concentration that allows ohmic contact with the activation region side electrode 20, and is, for example, 1×10 １６ ~1 x 10 ２１ cm －３ The total impurity concentration in the active region 14 can be, for example, 1.25×10 １２ cm －２ The depth of the activation region 14 can be, for example, 0.5 to 6 μm, and preferably 1 to 3 μm. Note that the "depth" of a region of the semiconductor substrate is based on the first main surface unless otherwise specified.

[0023] In this specification, when a specific region is referred to as a "corner portion," it refers to a corner portion of the outer edge of the region, and this portion can also be said to be a portion connecting two sides that are oriented in different directions. Furthermore, when a specific region is referred to as a "side portion" in this specification, it refers to a straight portion of the outer edge of the region. In this specification, the "outer edge" of a region of a semiconductor substrate does not refer to the tip of a side diffusion where the depth of the region decreases abruptly, but rather to the outer edge of a portion where the depth (thickness) of the region is approximately constant.

[0024] The first surface semiconductor region 15 is formed on the first main surface side so as to contact the outer periphery of the active region 14 in plan view but not to contact the guard ring 16, and is a region of a second conductivity type (p-type in the semiconductor device 1) having a smaller total impurity concentration than the active region 14. The outer periphery of the first surface semiconductor region 15 in plan view has a substantially rectangular shape with rounded corners. The total impurity concentration of the first surface semiconductor region 15 is, for example, 0.75×10 １２ ~1.25 x 10 １２ cm －２ The depth of the first surface semiconductor region 15 can be set to, for example, 0.5 to 3 μm.

[0025] In this specification, "sum of impurities" refers to the value obtained by integrating the concentration distribution from the surface to the depth direction. The sum of impurities is also related to the dose (amount of impurities implanted), but there are cases where an appropriate correlation is not necessarily obtained between the breakdown voltage and the dose. This is because the amount of impurities can change due to heat treatment, etc.

[0026] The guard ring 16 is a region of the second conductivity type (p-type in the semiconductor device 1) formed on the first main surface side so as to surround the activation region 14 at a distance in plan view. The guard ring 16 has a generally rectangular shape with rounded corners on the inner and outer peripheries in plan view. In the semiconductor device 1, only one guard ring 16 is formed. The impurity concentration, total impurity concentration, and depth of the guard ring 16 can be the same as those of the activation region 14, for example. Therefore, the total impurity concentration of the guard ring 16 is, for example, 1.25×10 １２ cm －２It can be made larger.

[0027] The second surface semiconductor region 17 is formed on the first main surface side so as to be in contact with the outer periphery of the guard ring 16 in plan view, and is a region having a smaller total impurity concentration than the guard ring 16. The outer periphery of the second surface semiconductor region 17 in plan view has a substantially rectangular shape with rounded corners. The impurity concentration, total impurity concentration, and depth of the second surface semiconductor region 17 can be, for example, the same as those of the first surface semiconductor region 15. Note that the total impurity concentration of the second surface semiconductor region 17 may be smaller than the total impurity concentration of the first surface semiconductor region 15. Taking these factors into consideration, the total impurity concentration of the second surface semiconductor region 17 is, for example, 0.5×10 １２ ~1.25 x 10 １２ cm －２ It can be said that:

[0028] The channel stopper 19 is a region of the first conductivity type (n-type in the semiconductor device 1) formed on the first main surface side so as to surround the second surface semiconductor region 17 at a distance when viewed from above. ＋ This region has a higher impurity concentration than the type semiconductor region 12a.

[0029] The active region side electrode 20 is disposed on the first main surface of the semiconductor substrate 10 .

[0030] The insulating layer 30 is disposed on the first main surface and in contact with the outer periphery of the active region-side electrode 20. The insulating layer 30 in the semiconductor device 1 is disposed so as to cover a part of the active region 14 including the outer periphery, and a part of the first surface semiconductor region 15, the guard ring 16, the second surface semiconductor region 17, and the channel stopper 19 including the inner periphery.

[0031] The field plate 40 is in contact with the outer periphery of the active region side electrode 20 and is disposed on the insulating layer 30. In the semiconductor device 1, the active region side electrode 20 and the field plate 40 are integrated as a first electrode, but in a plan view, the inner side of the inner periphery of the insulating layer 30 is the boundary, and the field plate 40 is the outer side. The field plate 40 in the semiconductor device 1 is disposed so as to overlap with a portion of the active region 14 and the first surface semiconductor region 15 in a plan view.

[0032] The second electrode 50 is disposed on a second major surface of the semiconductor substrate 10 opposite to the first major surface.

[0033] The effects of the semiconductor device 1 according to the first embodiment will be described below.

[0034] In the semiconductor device 1 according to the first embodiment, the semiconductor substrate 10 has a first surface semiconductor region 15 of the second conductivity type formed on the first main surface side so as to contact the outer periphery of the active region 14 in plan view but not contact the guard ring 16, and having a smaller total impurity concentration than the active region 14. In the semiconductor device 1 according to the first embodiment, both the substrate region 12 and the first surface semiconductor region 15 can be depleted under reverse bias, so that a high breakdown voltage can be obtained without increasing the number of guard rings 16. Therefore, the semiconductor device 1 according to the first embodiment can be made smaller while still achieving a higher breakdown voltage than semiconductor devices with a conventional guard ring structure.

[0035] Furthermore, in the semiconductor device 1 according to the first embodiment, the semiconductor substrate 10 has a second surface semiconductor region 17 formed on the first main surface side so as to be in contact with the outer periphery of the guard ring 16 in a plan view, and having a smaller total impurity concentration than the guard ring 16. In the semiconductor device 1 according to the first embodiment, the second surface semiconductor region 17 can reduce the electric field strength at the outer periphery of the guard ring 16, particularly at the apexes of the corners of the guard ring 16, under reverse bias. Therefore, the semiconductor device 1 according to the first embodiment can increase the breakdown resistance of the entire device by making it less likely for avalanche breakdown to occur at the corners under reverse bias.

[0036] Therefore, the semiconductor device 1 according to the first embodiment can be made smaller while achieving a higher breakdown voltage than semiconductor devices with a conventional guard ring structure, and can also increase the breakdown resistance of the entire device.

[0037] [Embodiment 2] A semiconductor device 2 according to embodiment 2 has a configuration basically similar to that of the semiconductor device 1 according to embodiment 1, but the shapes of the regions in the semiconductor substrate differ from those of the semiconductor device 1 according to embodiment 1. That is, in the semiconductor device 2, the outer peripheries of the activation region 64, first surface semiconductor region 65, guard ring 66, and second surface semiconductor region 67 in the semiconductor substrate 60 are rectangular in plan view (see FIG. 2). As a result, the inner peripheries of the first surface semiconductor region 65, guard ring 66, and second surface semiconductor region 67 are also rectangular in plan view. In addition, in the semiconductor device 2, the inner periphery of the channel stopper 69 is rectangular in plan view.

[0038] The configuration of the semiconductor substrate 60 is the same as the configuration of the semiconductor substrate 10 in embodiment 1, except for the shape of each region. Although detailed explanation using drawings will be omitted, due to the shape of each region in the semiconductor substrate 60, the active region side electrode 22 and the insulating layer 32 in the semiconductor device 2 also have a rectangular outer periphery in plan view. On the other hand, from the viewpoint of increasing the breakdown voltage of the corner portions, it is preferable that the corner portions of the field plate 42 have an arc shape with its center point at the apex of the corner portion of the active region 64. The field plate 42 may also have a rectangular outer periphery in plan view.

[0039] In the semiconductor device 2 according to the second embodiment, the shape of each region in the semiconductor substrate 60 differs from that in the semiconductor device 1 according to the first embodiment, but the semiconductor substrate 60 in the semiconductor device 2 has a first surface semiconductor region 65 and a second surface semiconductor region 67. Therefore, like the semiconductor device 1 according to the first embodiment, the semiconductor device 2 according to the second embodiment can be made smaller while achieving a higher breakdown voltage than semiconductor devices with a conventional guard ring structure, and can also be made to have a higher breakdown voltage tolerance as a whole.

[0040] Furthermore, in the semiconductor device 2 according to the second embodiment, the activation region 64, the first surface semiconductor region 65, the guard ring 66, and the second surface semiconductor region 67 each have a rectangular outer periphery in a plan view. Therefore, according to the semiconductor device 2 according to the second embodiment, a depletion layer is more likely to extend from the corner portions of the first surface semiconductor region 65 and the second surface semiconductor region 67 under a reverse bias, and the electric field strength at the apexes of the corner portions of the first surface semiconductor region 65 and the second surface semiconductor region 67 can be alleviated, thereby increasing the breakdown voltage at the corner portions. As a result, according to the semiconductor device 2 according to the second embodiment, avalanche breakdown is more likely to occur at the side portions under a reverse bias, thereby further increasing the breakdown voltage of the entire device.

[0041] Furthermore, in the semiconductor device 2 according to the second embodiment, the semiconductor substrate 60 has a channel stopper 69, and the channel stopper 69 has a rectangular inner periphery in plan view. Therefore, in the semiconductor device 2 according to the second embodiment, the channel stopper 69, which is a high-concentration region of the first conductivity type (n-type) and has a rectangular inner periphery, surrounds the second surface semiconductor region 67, making it easier for a depletion layer to extend from the corners of the second surface semiconductor region 67 under reverse bias. Therefore, the electric field strength at the apexes of the corners of the second surface semiconductor region 67 is alleviated, thereby increasing the breakdown voltage at the corners. As a result, in the semiconductor device 2 according to the second embodiment, avalanche breakdown is more likely to occur at the edges under reverse bias, thereby further increasing the breakdown voltage of the entire device.

[0042] [Embodiment 3] A semiconductor device 3 according to embodiment 3 basically has the same configuration as the semiconductor device 1 according to embodiment 1, but differs from the semiconductor device 1 according to embodiment 1 in that it further includes a guard ring metal. That is, the semiconductor device 3 includes a guard ring metal 70 disposed on the first main surface so as to overlap with the guard ring 16 in plan view (see FIG. 3).

[0043] The semiconductor device 3 according to the third embodiment differs from the semiconductor device 1 according to the first embodiment in that it further includes a guard ring metal, but the semiconductor substrate 10 in the semiconductor device 3 has a first surface semiconductor region 15 and a second surface semiconductor region 17. Therefore, like the semiconductor device 1 according to the first embodiment, the semiconductor device 3 according to the third embodiment can be made smaller while achieving a higher breakdown voltage than semiconductor devices with a conventional guard ring structure, and can also be made to have a higher breakdown voltage tolerance as a whole.

[0044] Furthermore, the semiconductor device 3 according to the third embodiment includes a guard ring metal 70 arranged on the first main surface so as to overlap with the guard ring 16 when viewed in a plane, thereby suppressing the movement of the external electric field, thereby enabling stabilization of the breakdown voltage and improvement of reliability.

[0045] Although the present invention has been described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments. The present invention can be embodied in various forms without departing from the spirit of the present invention, and for example, the following modifications are also possible.

[0046] (1) The positions, sizes, etc. of the components described in the above embodiments are merely examples and may be changed within the scope that does not impair the effects of the present invention.

[0047] (2) The semiconductor device 3 according to the third embodiment has a structure in which a guard ring metal 70 is added to the semiconductor device 1 according to the first embodiment, but the present invention is not limited to this. For example, the semiconductor device of the present invention may have a structure in which a guard ring metal is added to the semiconductor device 2 according to the second embodiment.

[0048] (3) In the above embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is not limited to this. The first conductivity type may be p-type and the second conductivity type may be n-type.

[0049] (4) In the drawings relating to the above embodiments, the depths of the active regions 14, 64 and the guard rings 16, 66 are shown as being deeper than the depths of the first surface semiconductor regions 15, 65 and the second surface semiconductor regions 17, 67, but the present invention is not limited to this. The depth of at least one of the active regions and the guard rings may be shallower than the depth of at least one of the first surface semiconductor regions and the second surface semiconductor regions.

[0050] (5) Although the semiconductor devices 1 to 3 according to the above embodiments are planar diodes, the present invention is not limited to this. The present invention can also be applied to diodes other than planar diodes, transistors (e.g., MOSFETs), thyristors, and the like.

[0051] (6) In the above embodiments, the semiconductor substrate 10, 60 is made of Si, but the present invention is not limited to this. Materials other than Si (e.g., wide bandgap semiconductor materials such as SiC) can also be used as the semiconductor substrate material in the present invention. The impurity concentration, total impurity amount, thickness, depth, etc. of each region exemplified in the first embodiment are for the case where the semiconductor substrate 10 is made of Si. When a material other than Si is used, the impurity concentration, total impurity amount, thickness, depth, etc. can be set to suit the material.

[0052] (7) In the semiconductor devices 1 to 3 according to the above embodiments, only one structure (hereinafter, referred to as a "guard ring resurf structure") consisting of a combination of the guard ring 16, 66 and the second surface semiconductor region 17, 67 is formed on the semiconductor substrate 10, 60. However, the present invention is not limited to this. The number of guard ring resurf structures in the semiconductor device of the present invention may be multiple. In other words, the present invention also includes semiconductor devices such as the semiconductor devices 1 to 3 in which another (additional) guard ring resurf structure is further formed outside the guard ring 16, 66 and the second surface semiconductor region 17, 67. The number of additional guard ring resurf structures can be determined appropriately based on required specifications (e.g., breakdown voltage), and may be one or two or more. This configuration makes it possible to obtain a higher breakdown voltage compared to a device having only one guard ring resurf structure. Furthermore, even when multiple guard ring resurf structures are formed, it is possible to narrow the peripheral area (reducing the device size) compared to a device that attempts to obtain the same breakdown voltage using only guard rings.

[0053] DESCRIPTION OF SYMBOLS 1, 2, 3...Semiconductor device, 10, 60...Semiconductor substrate, 12...Substrate region, 14, 64...Activated region, 15, 65...First surface semiconductor region, 16, 66...Guard ring, 17, 67...Second surface semiconductor region, 19, 69...Channel stopper, 20, 22...Activated region side electrode, 30, 32...Insulating layer, 40, 42...Field plate, 50...Second electrode, 70...Guard ring metal

Claims

1. A semiconductor device comprising: a semiconductor substrate; an active region-side electrode disposed on a first main surface of the semiconductor substrate; an insulating layer in contact with the periphery of the active region-side electrode and disposed on the first main surface; and a field plate in contact with the periphery of the active region-side electrode and disposed on the insulating layer, wherein the semiconductor substrate has a substrate region of a first conductivity type, an active region of a second conductivity type formed on the first main surface side so as to overlap at least a portion with the active region-side electrode in a planar view, and a guard ring of the second conductivity type formed on the first main surface side so as to surround the active region at a distance in a planar view, wherein the semiconductor substrate further comprises: a first surface semiconductor region of the second conductivity type formed on the first main surface side so as to contact the periphery of the active region in a planar view but not to contact the guard ring, and having a smaller total impurity content than the active region; and a second surface semiconductor region formed on the first main surface side so as to contact the periphery of the guard ring in a planar view, and having a smaller total impurity content than the guard ring.

2. The semiconductor device according to claim 1, wherein the active region, the first surface semiconductor region, the guard ring, and the second surface semiconductor region have a rectangular outer periphery when viewed in plan.

3. The semiconductor device described in claim 1, characterized in that the semiconductor substrate further has a channel stopper of the first conductivity type formed on the first main surface side so as to surround the second surface semiconductor region at a distance when viewed in a plane, and the channel stopper has an inner periphery that is rectangular when viewed in a plane.

4. The semiconductor device according to claim 1, further comprising a guard ring metal disposed on said first main surface so as to overlap said guard ring in a plan view.

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