Semiconductor apparatus and method for manufacturing semiconductor apparatus

Abstract

This semiconductor apparatus comprises, on a substrate, a first nanosheet-type semiconductor element, a second nanosheet-type semiconductor element, and a vertical semiconductor element. The first nanosheet-type semiconductor element and the second nanosheet-type semiconductor element are connected by means of a contact. The vertical semiconductor element is disposed between the substrate and the first nanosheet-type semiconductor element.

Description

Semiconductor device and method for manufacturing the same

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002] Static random access memories (SRAMs) are widely used as semiconductor devices. Because of their high read and write speeds, SRAMs are used in applications requiring high-speed processing. Each SRAM cell is composed of six transistors (Tr): two pull-ups (PUs), two pull-downs (PDs), and two pass gates (PGs). Because of the complex device structure, it is difficult to improve integration density (miniaturization and high integration) by miniaturizing the device and reducing the cell area. To meet the demand for high integration of SRAMs, a structure has been proposed in which each transistor is formed using a fin field-effect transistor (FinFET) (see, for example, Patent Document 1). Furthermore, a configuration has been proposed in which the pull-ups and pull-downs are formed using complementary field-effect transistors (CFETs) to reduce the cell area (see, for example, Non-Patent Document 1).

[0003] US Patent Publication No. 2014 / 0131813

[0004] Mohit Kumar Gupta et al., The Complementary FET (CFET) 6T-SRAM, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 68, NO. 12, DECEMBER 2021, 6106-6111

[0005] However, in the SRAM configuration described in Patent Document 1, although the transistors can be miniaturized using FinFETs, the number of transistors arranged in a plane remains unchanged. Therefore, the configuration described in Patent Document 1 has limitations on improving integration density. Furthermore, in the SRAM configuration described in Non-Patent Document 1, two pass gates are arranged in the plane direction of the substrate relative to the pull-up and pull-down circuits configured with CFETs. Therefore, in the planar layout, an area for forming the pass gates is required in excess of the area for forming the pull-up and pull-down circuits. Therefore, even with the configuration described in Non-Patent Document 1, there are limitations on improving integration density.

[0006] In order to solve the above-mentioned problems, the present invention provides a semiconductor device that allows for an improvement in integration density, and a method for manufacturing the semiconductor device.

[0007] The semiconductor device of the present invention comprises a plurality of semiconductor elements on a substrate, the plurality of semiconductor elements including a first nanosheet type semiconductor element, a second nanosheet type semiconductor element, and a vertical semiconductor element, and includes contacts connecting the first nanosheet type semiconductor element and the second nanosheet type semiconductor element, and the vertical semiconductor element is disposed between the substrate and the first nanosheet type semiconductor element.

[0008] The semiconductor device of the present invention comprises a plurality of semiconductor elements on a substrate, the plurality of semiconductor elements including at least a first nanosheet type semiconductor element, a second nanosheet type semiconductor element, and a third nanosheet type semiconductor element, the second nanosheet type semiconductor element being stacked on the first nanosheet type semiconductor element, the first nanosheet type semiconductor element and the third nanosheet type semiconductor element being arranged parallel to the surface of the substrate, a contact connecting the first nanosheet type semiconductor element and the second nanosheet type semiconductor element being provided in an element isolation region between the first nanosheet type semiconductor element and the second nanosheet type semiconductor element, and a gate of the first nanosheet type semiconductor element and a gate of the third nanosheet type semiconductor element being separated from the contact.

[0009] The present invention also provides a method for manufacturing a semiconductor device comprising a first nanosheet type semiconductor element, a second nanosheet type semiconductor element, and a vertical semiconductor element on a substrate, the method comprising the steps of: forming a channel region and one of source / drain regions constituting the vertical semiconductor element on the substrate; forming a stack of a first semiconductor layer and a sacrificial layer on the channel region of the vertical semiconductor element; forming a stack of a second semiconductor layer and the sacrificial layer; removing the sacrificial layer and embedding a metal layer to form a gate electrode covering the periphery of the first semiconductor layer and the second semiconductor layer in a cross section in the gate width direction; forming source / drain regions on side surfaces of the first semiconductor layer and the second semiconductor layer; and forming contacts connecting the source / drain regions formed on the side surfaces of the first semiconductor layer and the second semiconductor layer.

[0010] According to the present invention, it is possible to provide a semiconductor device and a method for manufacturing a semiconductor memory element that can improve stacking density.

[0011] 1 is an equivalent circuit diagram of a semiconductor device; 2 is a plan layout diagram (top view) of a semiconductor device of a first embodiment; 3 is a cross-sectional view of the semiconductor device shown in FIG. 2 taken along line A-A; 4 is a cross-sectional view of the semiconductor device shown in FIG. 2 taken along line B-B; 5 is a cross-sectional view of the semiconductor device shown in FIG. 2 taken along line C-C; 6 is a manufacturing process diagram (top view) of a semiconductor device of a first embodiment; 7 is a manufacturing process diagram (cross-sectional view along line A-A) of a semiconductor device of a first embodiment; 8 is a manufacturing process diagram (cross-sectional view along line B-B) of a semiconductor device of a first embodiment; 9 is a manufacturing process diagram (cross-sectional view along line C-C) of a semiconductor device of a first embodiment; 10 is a manufacturing process diagram (cross-sectional view along line A-A) of a semiconductor device of a first embodiment; 11 is a manufacturing process diagram (cross-sectional view along line B-B) of a semiconductor device of a first embodiment; 12 is a manufacturing process diagram (cross-sectional view along line C-C) of a semiconductor device of a first embodiment; 1 is a manufacturing process diagram (cross-sectional view along line C-C) of the semiconductor device of the first embodiment; FIG. 2 is a manufacturing process diagram (top view) of the semiconductor device of the first embodiment; FIG. 3 is a manufacturing process diagram (cross-sectional view along line A-A) of the semiconductor device of the first embodiment; FIG. 4 is a manufacturing process diagram (cross-sectional view along line B-B) of the semiconductor device of the first embodiment; FIG. 5 is a manufacturing process diagram (cross-sectional view along line C-C) of the semiconductor device of the first embodiment; FIG. 6 is a manufacturing process diagram (cross-sectional view along line A-A) of the semiconductor device of the first embodiment; FIG. 7 is a manufacturing process diagram (cross-sectional view along line B-B) of the semiconductor device of the first embodiment; FIG. 8 is a manufacturing process diagram (cross-sectional view along line C-C) of the semiconductor device of the first embodiment; FIG. 9 is a manufacturing process diagram (cross-sectional view along line A-A) of the semiconductor device of the first embodiment; FIG. 10 is a manufacturing process diagram (cross-sectional view along line B-B) of the semiconductor device of the first embodiment; FIG. 11 is a manufacturing process diagram (cross-sectional view along line C-C) of the semiconductor device of the first embodiment; 1 is a manufacturing process diagram (cross-sectional view along line A-A) of the semiconductor device of the first embodiment; FIG. 2 is a manufacturing process diagram (cross-sectional view along line B-B) of the semiconductor device of the first embodiment; FIG. 3 is a manufacturing process diagram (cross-sectional view along line C-C) of the semiconductor device of the first embodiment; and FIG. 4 is a manufacturing process diagram (top view) of the semiconductor device of the first embodiment.1 is a manufacturing process diagram (cross-sectional view along line A-A) of the semiconductor device of the first embodiment; FIG. 2 is a manufacturing process diagram (cross-sectional view along line B-B) of the semiconductor device of the first embodiment; FIG. 3 is a manufacturing process diagram (cross-sectional view along line C-C) of the semiconductor device of the first embodiment; FIG. 4 is a manufacturing process diagram (top view) of the semiconductor device of the first embodiment; FIG. 5 is a manufacturing process diagram (cross-sectional view along line A-A) of the semiconductor device of the first embodiment; FIG. 6 is a manufacturing process diagram (cross-sectional view along line B-B) of the semiconductor device of the first embodiment; FIG. 7 is a manufacturing process diagram (cross-sectional view along line C-C) of the semiconductor device of the first embodiment; FIG. 8 is a manufacturing process diagram (cross-sectional view along line A-A) of the semiconductor device of the first embodiment; FIG. 9 is a manufacturing process diagram (cross-sectional view along line B-B) of the semiconductor device of the first embodiment; FIG. 10 is a manufacturing process diagram (cross-sectional view along line C-C) of the semiconductor device of the first embodiment; FIG. 11 is a manufacturing process diagram (cross-sectional view along line A-A) of the semiconductor device of the first embodiment; 56. A manufacturing process diagram (cross-sectional view along line C-C) of the semiconductor device of the first embodiment. A plan layout diagram (top view) of the semiconductor device of the second embodiment. A cross-sectional view along line A-A of the semiconductor device shown in FIG. 50. A cross-sectional view along line B-B of the semiconductor device shown in FIG. 50. A cross-sectional view along line C-C of the semiconductor device shown in FIG. 50. A manufacturing process diagram (cross-sectional view along line C-C) of the semiconductor device of the second embodiment. A manufacturing process diagram (cross-sectional view along line C-C) of the semiconductor device of the second embodiment. A plan layout diagram (top view) of the semiconductor device of the third embodiment. A cross-sectional view along line A-A of the semiconductor device shown in FIG. 56. A cross-sectional view along line B-B of the semiconductor device shown in FIG. 56. A cross-sectional view along line C-C of the semiconductor device shown in FIG. 56. A manufacturing process diagram (top view) of the semiconductor device of the third embodiment. A cross-sectional view along line A-A of the semiconductor device of the third embodiment. A cross-sectional view along line B-B of the semiconductor device of the third embodiment. A cross-sectional view along line C-C ... C-C of the semiconductor device of the third embodiment. A cross-sectional view along line C-C of the semiconductor device of the third embodiment. A cross-sectional view along line A-A of the semiconductor device of the third embodiment. A cross-sectional view along line B-C of the semiconductor device of the third embodiment. A cross-sectional view along line C-C of the semiconductor device of the third embodiment. A cross-sectional view along line C-C of the semiconductor device of the third embodiment. A top view of the manufacturing process diagram of the semiconductor device of the third embodiment. 10A to 10C are diagrams illustrating the manufacturing process of a semiconductor device according to a third embodiment (cross-sectional views taken along line A-A); FIG. 10B is a diagram illustrating the manufacturing process of a semiconductor device according to a third embodiment (cross-sectional views taken along line B-B); FIG. 10C is a diagram illustrating the manufacturing process of a semiconductor device according to a third embodiment (cross-sectional views taken along line C-C); and FIG. 10D is a diagram illustrating the manufacturing process of a semiconductor device according to a third embodiment (top views).1 is a manufacturing process diagram (cross-sectional view along line A-A) of a semiconductor device according to a third embodiment; FIG. 2 is a manufacturing process diagram (cross-sectional view along line B-B) of a semiconductor device according to a third embodiment; FIG. 3 is a manufacturing process diagram (cross-sectional view along line C-C) of a semiconductor device according to a third embodiment; FIG. 4 is a manufacturing process diagram (cross-sectional view along line A-A) of a semiconductor device according to a third embodiment; FIG. 5 is a manufacturing process diagram (cross-sectional view along line B-B) of a semiconductor device according to a third embodiment; FIG. 6 is a manufacturing process diagram (cross-sectional view along line C-C) of a semiconductor device according to a third embodiment; FIG. 7 is a manufacturing process diagram (cross-sectional view along line A-A) of a semiconductor device according to a third embodiment; FIG. 8 is a manufacturing process diagram (cross-sectional view along line B-B) of a semiconductor device according to a third embodiment;

[0012] Hereinafter, embodiments of a semiconductor device and a method for manufacturing a semiconductor device will be described with reference to the drawings, but the present invention is not limited to the following examples. In the following description, the drawings only show the configuration of the main parts of the semiconductor device, and other configurations such as insulating layers will be omitted. The description will be given in the following order: 1. Semiconductor device of first embodiment 2. Method for manufacturing a semiconductor device of first embodiment 3. Semiconductor device of second embodiment 4. Method for manufacturing a semiconductor device of second embodiment 5. Semiconductor device of third embodiment 6. Method for manufacturing a semiconductor device of third embodiment

[0013] 1. First Embodiment of Semiconductor Device A specific embodiment of the semiconductor device of the present invention will be described below. Figures 1 to 5 show schematic configuration diagrams of a semiconductor memory element as an example of a semiconductor device of the first embodiment.

[0014] FIG. 1 is an equivalent circuit diagram of a semiconductor memory element. FIG. 2 is a plan layout diagram (top view) of the semiconductor memory element. FIG. 3 is a cross-sectional view of the semiconductor memory element shown in FIG. 2 taken along line A-A. FIG. 4 is a cross-sectional view of the semiconductor memory element shown in FIG. 2 taken along line B-B. FIG. 5 is a cross-sectional view of the semiconductor memory element shown in FIG. 2 taken along line C-C. Note that in FIGS. 3, 4, and 5, the top surface side of the semiconductor memory element shown in FIG. 2 is shown at the bottom of the drawings.

[0015] FIG. 1 shows a circuit diagram of a static random access memory (SRAM) cell consisting of six transistors (6Tr) as an example of a semiconductor memory element. The SRAM cell 100 has four transistors M1, M2, M3, and M4 that form two cross-coupled inverters. The SRAM cell 100 includes a first inverter formed by a pull-up p-type metal oxide semiconductor (PMOS) transistor M3 (PU1) and a pull-down n-type metal oxide semiconductor (NMOS) transistor M1 (PD1). The SRAM cell 100 also includes a second inverter formed by a pull-up PMOS transistor M4 (PU2) and a pull-down NMOS transistor M2 (PD2). In the SRAM cell 100, both the first and second inverters are coupled between a power supply voltage Vdd and ground.

[0016] The SRAM cell 100 further comprises a first pass gate (PG) transistor (Tr) M5 (PG1) connected between the bit line BL1 and the output of the first inverter. The SRAM cell 100 further comprises a second pass gate (PG) transistor (Tr) M6 (PG2) connected between the second bit line BL2 and the output of the second inverter. The gates of the first pass gate transistor M5 and the second pass gate transistor M6 are connected to a word line (WL) connecting the SRAM cells 100 in a row of the SRAM array. The two pass gate transistors M5 and M6 control the input and output to the SRAM cell 100.

[0017] As shown in FIG. 1, the first inverter and the second inverter are cross-connected. That is, the first inverter has an input connected to the output of the second inverter. Similarly, the second inverter has an input connected to the output of the first inverter. In an SRAM array (not shown) using 6Tr SRAM cells, cells are arranged in rows and columns in plan view. A column of the SRAM array is formed by a pair of bit lines, each of which is a first bit line BL1 and a second bit line BL2. One cell of the SRAM array is arranged between each pair of bit lines. Therefore, as shown in FIG. 1, an SRAM cell 100 is arranged between a first bit line BL1 and a second bit line BL2.

[0018] Next, Fig. 2 shows a plan view of the SRAM cell 100. The plan view shown in Fig. 2 shows two SRAM cells 100 arranged side by side. In Fig. 2, each area indicated by a dashed line corresponds to one SRAM cell 100. The two SRAM cells 100 share a power supply voltage (VDD) 101 and a ground (GND) 102.

[0019] As shown in FIG. 2 , one SRAM cell 100 has a word line (WL) 190 on VDD 101. A first bit line (BL1) 140 and a second bit line (BL2) 180 are provided on the word line 190. Semiconductor layers 110 and 150 are provided on the first bit line 140 and the second bit line 180. The semiconductor layers 110 and 150 are diffusion layers for forming six transistors M1 (first transistor), M2 (second transistor), M3 (third transistor), M4 (fourth transistor), M5 (fifth transistor), and M6 (sixth transistor). The semiconductor layers 110 and 150 form the channels, sources, drains, etc. of each of the transistors M1, M2, M3, M4, M5, and M6. Gate electrodes 120 and 160 of transistors M1, M2, M3, and M4 are formed on the semiconductor layers 110 and 150. The gate electrode 120 (first gate electrode) forms the transistors M1 and M3, and the gate electrode 160 (second gate electrode) forms the transistors M2 and M4. FET junction contacts 130 and 170 of transistors M1, M2, M3, M4, M5, and M6 are also formed on the semiconductor layers 110 and 150. That is, the gate electrode 120 and the semiconductor layer 110 form transistor M1 (PD1) and transistor M3 (PU1). The gate electrode 160 and the semiconductor layer 150 form transistor M2 (PD2) and transistor M4 (PU2). The semiconductor layer 110 and a gate electrode connected to word line 190 (FIG. 3) form transistor M5 (PG1). The semiconductor layer 150 and the gate electrode (FIG. 3) connected to the word line 190 form a transistor M6 (PG2). The transistors M1 (PD1), M3 (PU1), and M5 (PG1) form a first inverter. The transistors M2 (PD2), M4 (PU2), and M5 (PG2) form a second inverter. Wirings 103 and 104 for connecting the first inverter and the second inverter are provided on the gate electrodes 120 and 160 and the FET junction contacts 130 and 170.

[0020] 3, in the cross-sectional view taken along line A-A in FIG. 2, a first bit line 140 is disposed on the word line 190. A semiconductor layer 110 is formed on the first bit line 140. The semiconductor layer 110 is formed in contact with the first bit line 140. The semiconductor layer 110 has, from the first bit line 140 side, a P-type semiconductor layer 114 (fourth semiconductor layer) and an N-type semiconductor layer 113 (third semiconductor layer). Furthermore, on the N-type semiconductor layer 113, a P-type semiconductor layer 112 (eighth semiconductor layer) and an N-type semiconductor layer 111 (ninth semiconductor layer) are provided. A PN junction contact 131 is also provided between the P-type semiconductor layer 112 and the N-type semiconductor layer 111.

[0021] The P-type semiconductor layer 114 and the N-type semiconductor layer 113 are formed in areas narrower than the P-type semiconductor layer 112 and the N-type semiconductor layer 111. A PN junction contact 131 is formed between the P-type semiconductor layer 112 and the N-type semiconductor layer 111. The P-type semiconductor layer 114, the N-type semiconductor layer 113, and the P-type semiconductor layer 112 are the channel region and source / drain regions that constitute the transistor M5, which becomes PG1. The P-type semiconductor layer 114 and the P-type semiconductor layer 112 are the source / drain regions, and the N-type semiconductor layer 113 is the channel region. Therefore, the transistor M5 is a P-channel MOS.

[0022] The P-type semiconductor layer 112 is the source / drain region of the transistor M1 that will become PD1. The N-type semiconductor layer 111 is the source / drain region of the transistor M3 that will become PU1. An FET junction contact 130 is provided between the N-type semiconductor layer 111, which is the source / drain region of the transistor M3, and the wiring 103. An wiring 104 is provided adjacent to the wiring 103. The N-type semiconductor layer 111, which is the source / drain region of the transistor M3 that will become PU1, is connected by the wiring 103 via the FET junction contact 130 to the gate electrodes 160 of the transistors M2 that will become PD2 and M4 that will become PU2. Therefore, the transistor M5 that will become PG1 is connected to the gate electrodes 160 of the transistors M2 and M4 by the wiring 103 via the PN junction contact 131 and the N-type semiconductor layer 111.

[0023] As shown in FIG. 4 , the cross-sectional view taken along line B-B in FIG. 2 includes three N-type semiconductor layers 116 (first semiconductor layers), three P-type semiconductor layers 115 (second semiconductor layers), and a gate electrode 120 formed around and between these semiconductor layers. The three N-type semiconductor layers 116 form the channel region of transistor M1, which becomes PD1. The three P-type semiconductor layers 115 form the channel region of transistor M3, which becomes PU1. The three N-type semiconductor layers 116 and the three P-type semiconductor layers 115, which form the channel region, are composed of nanosheet layers. The three N-type semiconductor layers 116 and the three P-type semiconductor layers 115, which form the channel region composed of nanosheet layers, are surrounded by the gate electrode 120 on the entire periphery of their cross sections in the gate width direction via a gate insulating film (not shown). Note that in the semiconductor device, the nanosheets also include nanowires. That is, the transistor M1 (first nanosheet type semiconductor element) that becomes PD1 and the transistor M3 (second nanosheet type semiconductor element) that becomes PU1 are GAA (Gate All Around)-FETs with a nanosheet structure. The transistor M2 (third nanosheet type semiconductor element) that becomes PD2 and the transistor M4 (fourth nanosheet type semiconductor element) that becomes PU2 are also GAA (Gate All Around)-FETs having the same configuration as the transistors M1 and M3 shown in Figure 4. In addition, a word line 190, a word contact 191, and a gate electrode 192 are formed below the gate electrode 120.

[0024] In addition, a wiring 104 is connected above the gate electrode 120. The wiring 104 is connected to the gate electrodes 120 of the transistor M3 that becomes PD1 and the transistor M1 that becomes PU1, and to a FET junction contact 170. The FET junction contact 170 is connected to the wiring 104 and to an N-type semiconductor layer 151 ( FIG. 5 ), which is the source / drain region of the transistor M4 that becomes PU2, similar to the FET junction contact 130 shown in FIG. 3. Therefore, the gate electrodes 120 of the transistors M3 and M1 are connected to the transistor M6 that becomes PG2 via the wiring 104, the FET junction contact 170, the N-type semiconductor layer 151, and the PN junction contact 171 ( FIG. 5 ).

[0025] As shown in FIG. 5, in the cross section taken along line CC in FIG. 2, a gate electrode 192 is connected to a word line 190 via a word contact 191. Semiconductor layers 110 and 150 are formed on the side surfaces of the gate electrode 192, with a gate insulating film (not shown) or the like interposed therebetween. In the cross section taken along line CC, the semiconductor layers 110 and 150 have a recessed shape at the center of their lower portions. The gate electrode 192 is disposed within this recessed recess. A first bit line 140 and a VDD 101 are formed below the semiconductor layer 110. A second bit line 180 and a VDD 101 are formed below the semiconductor layer 150. The gate electrode 192 is formed below the first bit line 140, the second bit line 180, and the VDD 101. The semiconductor layer 110 also has a P-type semiconductor layer 114 and an N-type semiconductor layer 113 above the first bit line 140 on the side surfaces of the recess. The semiconductor layer 110 also has a P-type semiconductor layer 114 above the VDD 101 on the side surface of the recess.

[0026] The semiconductor layer 110 has a gate electrode 120 and an N-type semiconductor layer 116 stacked above the bottom surface of the recess. The semiconductor layer 110 also has a P-type semiconductor layer 115 and a gate electrode 120 stacked thereon, with the gate electrode 120 and a PN junction contact 131 provided on top of the lowermost N-type semiconductor layer 116. In FIG. 5 , three N-type semiconductor layers 116 and three P-type semiconductor layers 115 are formed. Between the N-type semiconductor layer 116 and the P-type semiconductor layer 115, the gate electrode 120 is formed in the channel region, and the PN junction contact 131 is formed in one of the source / drain regions. The uppermost and lowermost surfaces of the stack of the N-type semiconductor layer 116, the N-type semiconductor layer 115, and the gate electrode 120 are formed by the gate electrode 120.

[0027] Furthermore, the semiconductor layer 110 has a P-type semiconductor layer 112 on the side surface of the stack of the N-type semiconductor layer 116 and the gate electrode 120, and above the N-type semiconductor layer 113 and the P-type semiconductor layer 114. The semiconductor layer 110 has an N-type semiconductor layer 111 on the side surface of the stack of the P-type semiconductor layer 115 and the gate electrode 120. The N-type semiconductor layer 111 and the P-type semiconductor layer 112 are connected via an insulating layer (not shown) or a PN junction contact 131.

[0028] In the semiconductor layer 110, the P-type semiconductor layer 114, the N-type semiconductor layer 113, and the P-type semiconductor layer 112 above the first bit line 140, and the gate electrode 192 form a transistor M5 that becomes PG1. As shown in FIG. 5 , the transistor M5 (first vertical semiconductor element) that becomes PG1 is a vertical metal-oxide-semiconductor field-effect transistor (MOSFET). In addition, in the semiconductor layer 110, the gate electrode 120, the three N-type semiconductor layers 116, and the P-type semiconductor layer 112 form a transistor M1 that becomes PD1. The three N-type semiconductor layers 116 form a channel region, and the P-type semiconductor layers 112 formed on both side surfaces of the three N-type semiconductor layers 116 form source / drain regions. In addition, in the semiconductor layer 110, the gate electrode 120, the three P-type semiconductor layers 115, and the N-type semiconductor layer 111 form a transistor M3 that becomes PU1. The three P-type semiconductor layers 115 form a channel region, and the N-type semiconductor layers 111 formed on both side surfaces of the three P-type semiconductor layers 115 form source / drain regions.

[0029] A P-type semiconductor layer 112, which is the source / drain region of transistor M1 that becomes PD1, and an N-type semiconductor layer 111, which is the source / drain region of transistor M3 that becomes PU1, are connected by a PN junction contact 131. An FET junction contact 130 is provided above one side of the N-type semiconductor layer 111, which is the source / drain region of transistor M3 that becomes PU1, for connecting transistor M3 to wiring 103 (FIGS. 2 and 3). A ground (GND) 102 is connected above the other side of the N-type semiconductor layer 111, which is the source / drain region of transistor M3 that becomes PU1.

[0030] The semiconductor layer 150 also has a P-type semiconductor layer 154 (twelfth semiconductor layer) and an N-type semiconductor layer 153 (seventh semiconductor layer) above the second bit line 180 on the side surface of the recess. The semiconductor layer 150 also has a P-type semiconductor layer 154 above VDD 101 on the side surface of the recess. The semiconductor layer 150 has a gate electrode 160 and an N-type semiconductor layer 156 (fifth semiconductor layer) stacked above the bottom surface of the recess. The semiconductor layer 150 also has a P-type semiconductor layer 155 (sixth semiconductor layer) and a gate electrode 160 stacked thereon, with the gate electrode 160 provided on top of the bottom N-type semiconductor layer 156. In FIG. 5 , three N-type semiconductor layers 156 and three P-type semiconductor layers 155 are formed. A gate electrode 160 is formed between the N-type semiconductor layer 156 and the P-type semiconductor layer 155 in the channel region, and a PN junction contact 171 is formed between one of the source and drain regions. The top and bottom surfaces of the stack of the N-type semiconductor layer 156, the P-type semiconductor layer 155, and the gate electrode 160 are formed by the gate electrode 160.

[0031] Furthermore, the semiconductor layer 150 has a P-type semiconductor layer 152 (tenth semiconductor layer) on the side surface of the stack of the N-type semiconductor layer 156 and the gate electrode 160, and above the N-type semiconductor layer 153 and the P-type semiconductor layer 154. The semiconductor layer 150 also has an N-type semiconductor layer 151 (eleventh semiconductor layer) on the side surface of the stack of the P-type semiconductor layer 155 and the gate electrode 160. The N-type semiconductor layer 151 is formed above the P-type semiconductor layer 152 via an insulating layer (not shown) or a PN junction contact 171.

[0032] In the semiconductor layer 150, the P-type semiconductor layer 154, the N-type semiconductor layer 153, and the P-type semiconductor layer 152 above the second bit line 180, and the gate electrode 192 form a transistor M6 that becomes PG2. As shown in FIG. 5 , the transistor M6 (second vertical semiconductor element) that becomes PG2 is a vertical MOSFET. In addition, in the semiconductor layer 150, the gate electrode 160, the three N-type semiconductor layers 156, and the P-type semiconductor layer 152 form a transistor M2 that becomes PD2. The three N-type semiconductor layers 156 form a channel region, and the P-type semiconductor layers 152 formed on both side surfaces of the three N-type semiconductor layers 156 form source / drain regions. In addition, in the semiconductor layer 150, the gate electrode 160, the three P-type semiconductor layers 155, and the N-type semiconductor layer 151 form a transistor M4 that becomes PU2. The three P-type semiconductor layers 155 form a channel region, and the N-type semiconductor layers 151 formed on both sides of the three P-type semiconductor layers 155 form source / drain regions.

[0033] A P-type semiconductor layer 152, which is the source / drain region of transistor M2 that becomes PD2, and an N-type semiconductor layer 151, which is the source / drain region of transistor M4 that becomes PU2, are connected by a PN junction contact 171. A contact 170 for connecting transistor M4 to wiring 104 (FIGS. 2 and 4) is provided above one side of the N-type semiconductor layer 151, which is the source / drain region of transistor M4 that becomes PU2. A ground 102 is connected above the other side of the N-type semiconductor layer 151, which is the source / drain region of transistor M4 that becomes PU2.

[0034] In the SRAM cell 100 shown in FIGS. 2 to 5, a transistor M1 (PD1) having a GAA-FET structure and a transistor M3 (PU1) similarly having a GAA-FET structure are stacked in the same stacking direction as the gate electrode 120. Furthermore, a transistor M2 (PD2) having a GAA-FET structure and a transistor M4 (PU2) similarly having a GAA-FET structure are stacked in the same stacking direction as the gate electrode 160. That is, the SRAM cell 100 shown in FIGS. 2 to 5 has a CFET (Complementary Field Effect Transistor) structure in which a transistor M1 (PD1) and a transistor M3 (PU1) each having a GAA-FET structure are stacked vertically. Furthermore, the SRAM cell 100 has a CFET structure in which a transistor M2 (PD2) and a transistor M4 (PU2) each having a GAA-FET structure are stacked vertically. That is, the SRAM cell 100 has two CFETs, one of which constitutes PD1 and PU1, and the other of which constitutes PD2 and PU2.

[0035] The SRAM cell 100 shown in Figures 2-5 also includes a transistor M5 (PG1) with a vertical MOS structure below a CFET in which transistors M1 (PD1) and M3 (PU1) are vertically stacked. Transistor M5 is formed below the source-drain region (P-type semiconductor layer 112) of transistor M1, which is PD1. Therefore, the SRAM cell 100 includes a first inverter consisting of transistors M5 (PG1), M1 (PD1), and M3 (PU1), stacked vertically. Furthermore, the SRAM cell 100 includes a transistor M6 (PG2) with a vertical MOS structure below a CFET in which transistors M2 (PD2) and M4 (PU2) are vertically stacked. Transistor M6 is formed below the source-drain region (P-type semiconductor layer 152) of transistor M2, which is PD2. Therefore, the SRAM cell 100 has a configuration in which a second inverter consisting of a transistor M6 (PG2), a transistor M2 (PD2), and a transistor M4 (PU2) is stacked in the vertical direction. Therefore, the SRAM cell 100 is configured with two semiconductor layers: a semiconductor layer 110 in which three transistors M1, M3, and M5 are stacked in the vertical direction, and a semiconductor layer 150 in which three transistors M2, M4, and M5 are stacked in the vertical direction.

[0036] In the SRAM cell 100, the semiconductor layers 110 and 150 are formed of, for example, Si, Ge, etc. The gate electrodes 120 and 160, the FET junction contacts 130 and 170, and the PN junction contacts 131 and 171 are formed of, for example, tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), niobium, etc. The word line (WL) 190, the word contact 191, the bit line (BL) 140 and 180, the wiring 103 and 104, the power supply voltage (VDD) 101, and the ground (GND) 102 are formed of, for example, copper (Cu).

[0037] 2. Manufacturing Method of Semiconductor Device of First Embodiment Next, a method for manufacturing the above-mentioned SRAM cell 100 will be described. Figures 6 to 49 show manufacturing process diagrams for the SRAM cell 100. In the manufacturing process of the SRAM cell 100 shown in Figures 6 to 49, as with Figures 2 to 5 described above, four drawings are shown for each process: a plan view, and cross-sectional views of the plan view taken along lines A-A, B-B, and C-C. Note that in the description of the manufacturing method of the SRAM cell 100, components similar to those in Figures 2 to 5 described above are designated by the same reference numerals, and detailed description thereof will be omitted.

[0038] First, as shown in Figures 6 to 9, using a known method, semiconductor layers 110 and 150 having a CFET structure in which two nanosheet transistors having a GAA-FET structure are stacked vertically, and dummy gates 105, 121, and 161 are formed.

[0039] For example, first, N-type or P-type impurities are implanted into regions of the substrate 106 that will become transistors M5 and M6, forming P-type semiconductor layers 114 and 154 and N-type semiconductor layers 113 and 153. Then, a stack of SiGe layers (sacrificial layers) and Si layers (semiconductor layers) is formed on the substrate 106 by epitaxial growth. In the configurations of FIGS. 7 to 9 , six SiGe layers and six Si layers are stacked. Ge layers may be used instead of the Si layers. In this case, N-type or P-type impurities are implanted into the Si layers, respectively, to form P-type semiconductor layers 115 and 155 and N-type semiconductor layers 116 and 156 that will become channel regions. Even when Ge layers are used instead of Si layers, N-type or P-type impurities are implanted into the Si layers, respectively, to form P-type semiconductor layers 115 and 155 and N-type semiconductor layers 116 and 156 that will become channel regions. Next, a patterned hard mask and dummy gates 105, 121, 161, etc. are formed on the SiGe / Si stack, and the SiGe / Si stack is etched to form SiGe / Si pillars. Furthermore, element isolation such as shallow trench isolators (STI) is formed in the substrate 106 in regions other than the P-type semiconductor layers 114, 154 and N-type semiconductor layers 113, 153 that will become transistors M5, M6. Si layers are formed on the side surfaces of the SiGe / Si stack by epitaxial growth. At this time, N-type or P-type impurities are implanted into the Si layers to form N-type semiconductor layers 111, 151 and P-type semiconductor layers 112, 152 that will become the source and drain regions of transistors M1-M4. After selectively removing the SiGe layers, polysilicon or the like is embedded in the regions where the SiGe layers were removed to form the dummy gates 105, 121, 161.

[0040] Next, as shown in FIGS. 10 to 13 , an insulating layer 108 is formed over the entire surface of the substrate 106, and then one column of dummy gates 105 and the semiconductor layer between the dummy gates 105 are removed and carved to form element isolation between the semiconductor layer 110 and the semiconductor layer 150. At this time, the insulating layer 108 formed between the N-type semiconductor layer 111 and the P-type semiconductor layer 112 and between the N-type semiconductor layer 151 and the P-type semiconductor layer 152 is partially removed. Furthermore, the insulating layer 108 on the STI 107 below the semiconductor layer 110 and the semiconductor layer 150 is partially removed. Then, a Ti / TiN layer 132 is formed over the entire surface. As a result, the Ti / TiN layer 132 is formed on the side and bottom surfaces of the element isolation region between the semiconductor layer 110 and the semiconductor layer 150. 11 and 13, the Ti / TiN layer 132 penetrates into a portion of the space between the P-type semiconductor layers 112, 152 and the N-type semiconductor layers 111, 151, and a contact is formed by the Ti / TiN layer 132 between the P-type semiconductor layers 112, 152 and the N-type semiconductor layers 111, 151. Furthermore, a contact is formed by the Ti / TiN layer 132 in a portion of the upper part of the STI 107. For the sake of explanation, FIGS. 11 to 13 show the STI 107 formed in the substrate and the insulating layer 108 formed on the semiconductor layer 110 and the semiconductor layer 150.

[0041] 14 to 17, the Ti / TiN layer 132 is etched back to leave PN junction contacts 131, 171 made of the Ti / TiN layer between the P-type semiconductor layers 112, 152 and the N-type semiconductor layers 111, 151. In addition, the Ti / TiN layer 132 remains on the STI 107 below the N-type semiconductor layers 111, 151.

[0042] 18 to 21, after removing the dummy gates 121 and 161, a TiN layer is formed in the region where the dummy gates 121 and 161 have been removed. As a result, the gate electrode 120 is formed in the semiconductor layer 110, and the gate electrode 160 is formed in the semiconductor layer 150.

[0043] 22 to 25, the gate electrodes 120, 160 are removed from the regions between the elements of adjacent SRAM cells 100. This separates the gate electrodes 120, 160 that are continuously formed between the elements of adjacent SRAM cells 100. At this time, as shown in FIG. 23, the Ti / TiN layer 132 remaining on the STI 107 below the N-type semiconductor layer 111 is also removed from the regions between the elements of the SRAM cells 100.

[0044] 26 to 29, FET junction contacts 130 and 170 are formed on the N-type semiconductor layers 111 and 151. The FET junction contact 130 is formed on the N-type semiconductor layer 111, which is the source / drain region of transistor M3. The FET junction contact 170 is formed on the N-type semiconductor layer 151, which is the source / drain region of transistor M4.

[0045] Next, as shown in Figures 30 to 33, wirings 103 and 104 for connecting the first inverter and the second inverter are formed. The wirings 103 and 104 are formed on the FET junction contacts 130 and 170, the N-type semiconductor layer 111 which is the source / drain region of transistor M3, and the N-type semiconductor layer 151 which is the source / drain region of transistor M4. The wiring 103 is formed to connect the FET junction contact 130 and the N-type semiconductor layer 151 which is the source / drain region of transistor M4. The wiring 104 is formed to connect the FET junction contact 170 and the N-type semiconductor layer 111 which is the source / drain region of transistor M3.

[0046] Next, as shown in FIGS. 34-37, the substrate 106 is turned upside down and then removed. This exposes the P-type semiconductor layers 114 and 154, as shown in FIGS. 35-37. Then, as shown in FIGS. 38-41, a gate electrode 192 is formed on the gate electrodes 120 and 160 from the surface (back surface) from which the substrate 106 has been removed. To form the gate electrode 192, first, the semiconductor layer (P-type semiconductor layer 114) on the gate electrodes 120 and 160 and the semiconductor layer below the element isolation region between the semiconductor layer 110 and the semiconductor layer 150 formed in the process shown in FIGS. 22-25 are removed to a height that exposes the gate electrodes 120 and 160. Then, after forming a gate insulating film, a dielectric layer, etc. in the recess formed by removing the semiconductor layer, a metal layer such as TiN is embedded. This forms the gate electrode 192 on the side surfaces of the N-type semiconductor layer 113 and the P-type semiconductor layer 114. At the same time, a gate electrode 192 is formed on the side surfaces of the N-type semiconductor layer 153 and the P-type semiconductor layer 154. At this time, the gate electrode 192 is also formed in the region between the N-type semiconductor layer 113 and the P-type semiconductor layer 114 and the region between the N-type semiconductor layer 153 and the P-type semiconductor layer 154, i.e., on the element isolation between the semiconductor layer 110 and the semiconductor layer 150.

[0047] Next, as shown in FIGS. 42 to 45, the first bit line 140, the second bit line 180, and the VDD 101 are formed. The first bit line 140 is formed on the P-type semiconductor layer 114 with the N-type semiconductor layer 113 formed thereunder. The second bit line 180 is formed on the P-type semiconductor layer 154 with the N-type semiconductor layer 151 formed thereunder. The VDD 101 is formed on the P-type semiconductor layers 114, 154 without the N-type semiconductor layers 113, 153 formed thereunder. The first bit line 140, the second bit line 180, and the VDD 101 are formed continuously in the adjacent SRAM cells 100.

[0048] Next, as shown in FIGS. 46-49, word contacts 191 and word lines 190 are formed on the gate electrodes 192. The word lines 190 are formed above the gate electrodes 120, the first bit lines 140, the second bit lines 180, and VDD 101. As shown in FIG. 49, the gate electrodes 192 are formed on the side surfaces of the N-type semiconductor layers 113 and 153 that serve as the channels of the transistors M5 and M6. These multiple gate electrodes 192 are connected by a single word line 190. For this reason, word contacts 191 are formed vertically from the word line 190 to the gate electrodes 192, and each gate electrode 192 is connected to the word line 190. Through the above steps, a semiconductor memory element (SRAM cell) having a CFET structure in which two nanosheet transistors having a GAA-FET structure are stacked vertically, as shown in FIGS. 2-5, can be manufactured.

[0049] 3. Semiconductor Device of Second Embodiment Next, a second embodiment of the semiconductor device will be described. The semiconductor device of the second embodiment described below has a configuration similar to that of the semiconductor device of the first embodiment described above. Therefore, a description of the configuration similar to that of the semiconductor device of the first embodiment described above will be omitted. FIGS. 50 to 53 show the configuration of a semiconductor memory device (SRAM cell) consisting of six transistors (6Tr) as an example of a semiconductor device. FIG. 50 is a planar layout diagram (top view) of a semiconductor memory element. FIG. 51 is a cross-sectional view of the semiconductor memory element shown in FIG. 50 taken along line A-A. FIG. 52 is a cross-sectional view of the semiconductor memory element shown in FIG. 50 taken along line B-B. FIG. 53 is a cross-sectional view of the semiconductor memory element shown in FIG. 50 taken along line C-C.

[0050] 2 to 5, the SRAM cell 200 shown in Figures 50 to 53 differs from the SRAM cell 100 shown in Figures 2 to 5 described above in the positions of the FET junction contacts 130, 170 and the distance from the semiconductor layer 110 to the semiconductor layer 150. The shapes of the wirings 103, 104 for connecting the first inverter and the second inverter are also different. Other than the above configuration, the SRAM cell 200 shown in Figures 50 to 53 can be configured similarly to the SRAM cell 100 shown in Figures 2 to 5.

[0051] As shown in the plan view of FIG. 50 , the FET junction contacts 130 and 170 are formed not on the semiconductor layers 110 and 150 but to the sides of the semiconductor layers 110 and 150. Furthermore, the regions of the FET junction contacts 130 and 170 are expanded laterally (in the gate width direction of the transistors M1-M4). Therefore, the wirings 103 and 104 are formed in a layer higher than the SRAM cell 100 shown in FIGS. 2 to 5 and are connected to the gate electrodes 120 and 160 and the N-type semiconductor layers 111 and 151 via contacts (vias) or the like. As shown in FIG. 51 , in the cross-sectional view taken along line A-A in FIG. 50 , no PN junction contact is formed between the N-type semiconductor layer 111 and the P-type semiconductor layer 112. Furthermore, no FET junction contact 130 is formed above the N-type semiconductor layer 111. As shown in FIG. 52, in the cross section taken along line BB in FIG. 50, the contacts (vias) formed in the gate electrode 120 for connection to the wirings 103 and 104 are omitted.

[0052] 53, in the cross-sectional view taken along line CC in FIG. 50, FET junction contacts 130 and 170 are formed in the region between the semiconductor layer 110 and the semiconductor layer 150. The FET junction contact 130 is formed continuously on the side surface of the semiconductor layer 110, from the side surface of the N-type semiconductor layer 111 to the side surface of the P-type semiconductor layer 112. Therefore, the FET junction contact 130 connects the N-type semiconductor layer 111 and the P-type semiconductor layer 112 only in the lateral direction of the N-type semiconductor layer 111 and the P-type semiconductor layer 112. Furthermore, no PN junction contact 131 (FIG. 5) is provided between the N-type semiconductor layer 111 and the P-type semiconductor layer 112 in the stacking direction. The FET junction contact 170 is formed continuously on the side surface of the semiconductor layer 150, from the side surface of the N-type semiconductor layer 151 to the side surface of the P-type semiconductor layer 152. Therefore, the FET junction contact 170 connects the N-type semiconductor layer 151 and the P-type semiconductor layer 152 only in the lateral direction of the N-type semiconductor layer 151 and the P-type semiconductor layer 152. Furthermore, no PN junction contact 171 (FIG. 5) is provided between the N-type semiconductor layer 151 and the P-type semiconductor layer 152 in the stacking direction.

[0053] 4. Manufacturing Method of Semiconductor Device of Second Embodiment Next, a method for manufacturing the above-described SRAM cell 200 will be described. Note that the manufacturing method of the SRAM cell 200 can apply the same processes as those for the SRAM cell 100 of the first embodiment, with some exceptions. Therefore, in the manufacturing method of the SRAM cell 200, only the processes that are different from those for the SRAM cell 100 of the first embodiment will be described.

[0054] 54 and 55 show manufacturing process diagrams of the SRAM cell 200. FIG. 54 is a cross-sectional view of the SRAM cell 200 shown in FIG. 50 taken along line CC, and corresponds to FIG. 9 showing the manufacturing process of the SRAM cell 100 of the first embodiment. FIG. 55 is a cross-sectional view of the SRAM cell 200 shown in FIG. 50 taken along line CC, and corresponds to FIG. 13 showing the manufacturing process of the SRAM cell 100 of the first embodiment. In the processes shown in FIGS. 54 and 55, the cross-sectional views of the SRAM cell 200 taken along line A-A and line B-B are the same as those shown in FIGS. 7 and 8.

[0055] 54, a known method is used to form semiconductor layers 110 and 150 having a CFET structure in which two nanosheet transistors having a GAA-FET structure are stacked vertically, and dummy gates 105, 121, and 161. At this time, two columns of dummy gates 105 are formed between the semiconductor layer 110 and the semiconductor layer 150, i.e., between the dummy gate 121 and the dummy gate 161.

[0056] 55 , after forming the insulating layer 108, two columns of dummy gates 105 and the semiconductor layer between the dummy gates 105 are removed and recessed to form an isolation between the semiconductor layer 110 and the semiconductor layer 150. Then, a Ti / TiN layer 132 is formed on the entire surface. This forms the Ti / TiN layer 132 on the top surface of the insulating layer 108 and on the side and bottom surfaces of the isolation region between the semiconductor layer 110 and the semiconductor layer 150. By removing two columns of dummy gates 105 and the semiconductor layer between the dummy gates 105, the isolation region between the semiconductor layer 110 and the semiconductor layer 150 is expanded. Therefore, FET contacts 130 and 170 for connecting the P-type semiconductor layers 112 and 152 to the N-type semiconductor layers 111 and 151 can be formed on the side surfaces of the semiconductor layer 110 and the semiconductor layer 150. As a result, it is not necessary to form PN junction contacts between the P-type semiconductor layers 112, 152 and the N-type semiconductor layers 111, 151. Thereafter, the SRAM cell 200 can be manufactured by performing the same steps as in the first embodiment described above.

[0057] 5. Semiconductor Device of Third Embodiment Next, a third embodiment of the semiconductor device will be described. The semiconductor device of the third embodiment described below has a configuration similar to that of the semiconductor device of the first embodiment described above. Therefore, a description of the configuration similar to that of the semiconductor device of the first embodiment described above will be omitted. FIGS. 56 to 59 show the configuration of a semiconductor memory element (SRAM cell) consisting of six transistors (6Tr) as an example of a semiconductor device. FIG. 56 is a planar layout diagram (top view) of the semiconductor memory element. FIG. 57 is a cross-sectional view of the semiconductor memory element shown in FIG. 56 taken along line A-A. FIG. 58 is a cross-sectional view of the semiconductor memory element shown in FIG. 57 taken along line B-B. FIG. 59 is a cross-sectional view of the semiconductor memory element shown in FIG. 56 taken along line C-C.

[0058] The SRAM cells 100 and 200 illustrated in the first and second embodiments have a CFET structure in which two nanosheet transistors having a GAA-FET structure are stacked vertically. In contrast, the SRAM cell 300, which is an example of a semiconductor memory element according to the third embodiment shown in Figures 56 to 59, does not have stacked nanosheet transistors having a GAA-FET structure, and transistors M1 to M4 are all formed in a planar arrangement.

[0059] The plan layout diagram shown in Fig. 56 shows four SRAM cells 300 arranged in two columns and two rows. In Fig. 56, each area indicated by a dashed line corresponds to one SRAM cell 300. Note that in Fig. 56, the PN junction contacts 330 and 370 and wirings 308 and 309 formed on the semiconductor layers 350, 351, 353, and 354 of the two SRAM cells 300 shown on the upper side are not shown.

[0060] As shown in FIG. 56 , one SRAM cell 300 has word lines 391 and 392 on VDD 301, and a bit line (BL1) 340 and a bit line (BL2) 380 on the word lines 391 and 392. Semiconductor layers 310, 311, 350, and 351 are provided on the bit lines (BL1, BL2) 340 and 380. The semiconductor layers 310, 311, 350, and 351 are diffusion layers for forming six transistors M1, M2, M3, M4, M5, and M6, and the channels, sources, drains, etc. of each transistor are formed therein. The semiconductor layer 310 is a diffusion layer for forming transistors M1 and M5. The semiconductor layer 311 is a diffusion layer for forming transistor M3. The semiconductor layer 350 is a diffusion layer for forming transistors M2 and M6. The semiconductor layer 351 is a diffusion layer for forming transistor M4.

[0061] Gate electrodes 320 and 360 of transistors M1, M2, M3, and M4 are formed on the semiconductor layers 310, 311, 350, and 351. The gate electrode 320 forms the transistors M1 and M3, and the gate electrode 360 ​​forms the transistors M2 and M4. PN junction contacts 330 and 370 of transistors M1, M2, M3, M4, M5, and M6 are also formed on the semiconductor layers 310, 311, 350, and 351. That is, the gate electrode 320 and the semiconductor layer 310 form the transistor M1 (PD1). The gate electrode 320 and the semiconductor layer 311 form the transistor M3 (PU1). The gate electrode 360 ​​and the semiconductor layer 350 form the transistor M2 (PD2). The gate electrode 360 ​​and the semiconductor layer 351 form the transistor M4 (PU2). Wirings 308 and 309 for connecting the first inverter and the second inverter are provided on the gate electrodes 320 and 360 and the PN junction contacts 330 and 370 .

[0062] 57, in the cross-sectional view taken along line A-A in FIG. 56, semiconductor layers 310 and 311 are formed on the first bit line 340. The semiconductor layer 310 has, from the first bit line 340 side, an N-type semiconductor layer 314, a P-type semiconductor layer 313, and an N-type semiconductor layer 312. The N-type semiconductor layer 314 and the P-type semiconductor layer 313 are formed in narrower regions than the N-type semiconductor layer 312. The semiconductor layer 311 also has a P-type semiconductor layer 315. The P-type semiconductor layer 315 is formed with the same width as the N-type semiconductor layer 312 of the semiconductor layer 310. The P-type semiconductor layer 315 is spaced apart from the first bit line 340.

[0063] Furthermore, word lines 391 and 392 are arranged on the side surfaces of the N-type semiconductor layer 314 and the P-type semiconductor layer 313 of the semiconductor layer 310. Therefore, the N-type semiconductor layer 314, the P-type semiconductor layer 313, the N-type semiconductor layer 312, and the word lines 391 and 392 form a transistor M5 (PG1). That is, the word lines 391 and 392 function as the gate electrodes of the transistor M5.

[0064] As shown in Figure 57, transistor M5, which becomes PG1, is a vertical MOSFET. N-type semiconductor layer 314 and N-type semiconductor layer 312 are source / drain regions, and P-type semiconductor layer 313 is a channel region. Therefore, transistor M5 is an N-channel MOS. Transistor M6, which becomes PG2, also has a vertical N-channel MOS structure similar to transistor M5 shown in Figure 57.

[0065] The N-type semiconductor layer 312 is a source / drain region that constitutes the transistor M1 that becomes the PD1. The P-type semiconductor layer 315 is a source / drain region that constitutes the transistor M3 that becomes the PU1. A PN junction contact 330 is provided between the N-type semiconductor layer 312 that is the source / drain region of the transistor M1 and the P-type semiconductor layer 315 that is the source / drain region of the transistor M3.

[0066] As shown in FIG. 58 , the cross-sectional view taken along line B-B in FIG. 56 includes three P-type semiconductor layers 316, three N-type semiconductor layers 317, and a gate electrode 320 formed around and between these semiconductor layers. The three P-type semiconductor layers 316 form the channel region of transistor M1, which will become PD1. The three N-type semiconductor layers 317 form the channel region of transistor M3, which will become PU1. The three P-type semiconductor layers 316 and the three N-type semiconductor layers 317, which form the channel regions, are composed of nanosheet layers. The three P-type semiconductor layers 316 and the three N-type semiconductor layers 317, which form the channel regions composed of nanosheet layers, are surrounded on all sides in the gate width direction by gate electrodes 320 via gate insulating films (not shown). In other words, transistor M1, which will become PD1, and transistor M3, which will become PU1, are GAA-FETs. The transistor M2 that becomes PD2 and the transistor M4 that becomes PU2 are also GAA-FETs having the same configuration as the transistors M1 and M3 shown in Fig. 58. Moreover, above the gate electrode 320, word lines 391 and 392 are arranged.

[0067] 59, in the cross-sectional view taken along line CC in FIG. 56, a first bit line 340 and VDD 301 are formed below the semiconductor layer 310. A second bit line 380 and VDD 301 are formed below the semiconductor layer 350. A PN junction contact 330 is formed on the semiconductor layer 310. A PN junction contact 370 is formed on the semiconductor layer 150.

[0068] The semiconductor layer 310 also has an N-type semiconductor layer 314, a P-type semiconductor layer 313, and an N-type semiconductor layer 312 above the first bit line 340. The semiconductor layer 310 also has an N-type semiconductor layer 314 above the VDD 301. The semiconductor layer 310 has a gate electrode 320 and a P-type semiconductor layer 316 stacked therein. In FIG. 59 , three P-type semiconductor layers 316 and four gate electrodes 320 are formed. The top and bottom surfaces of the stack of the P-type semiconductor layers 316 and the gate electrodes 320 are formed by the gate electrodes 320.

[0069] Furthermore, the semiconductor layer 310 has an N-type semiconductor layer 312 on a side surface of a stack of the P-type semiconductor layer 316 and the gate electrode 320, and above the N-type semiconductor layer 314 and the P-type semiconductor layer 313. In the semiconductor layer 310, the gate electrode 320, the three P-type semiconductor layers 316, and the N-type semiconductor layer 312 form a transistor M1 that becomes PD1. The three P-type semiconductor layers 316 form a channel region, and the N-type semiconductor layers 312 formed on both side surfaces of the three P-type semiconductor layers 316 form source / drain regions. In addition, a PN junction contact 330 is provided on one side of the N-type semiconductor layer 312 that forms the source / drain region of the transistor M1 that becomes PD1.

[0070] The semiconductor layer 350 includes an N-type semiconductor layer 354, a P-type semiconductor layer 353, and an N-type semiconductor layer 352 above the second bit line 380. The semiconductor layer 350 also includes a stack of a gate electrode 360 ​​and a P-type semiconductor layer 356. In FIG. 59 , three P-type semiconductor layers 356 are formed, and four gate electrodes 360 are formed. The top and bottom surfaces of the stack of the P-type semiconductor layers 356 and the gate electrodes 360 are formed by the gate electrodes 360. The semiconductor layer 350 also includes an N-type semiconductor layer 352 on the side surfaces of the stack of the P-type semiconductor layers 356 and the gate electrodes 360, above the P-type semiconductor layer 353 and the N-type semiconductor layer 354. In the semiconductor layer 350, the gate electrode 360, the three P-type semiconductor layers 356, and the N-type semiconductor layer 352 form a transistor M2 that serves as PD2. The three P-type semiconductor layers 356 form a channel region, and the N-type semiconductor layers 352 formed on both side surfaces of the three P-type semiconductor layers 356 form source / drain regions. The N-type semiconductor layer 352, which is the source / drain region of the transistor M2 that becomes PD2, and the P-type semiconductor layer (not shown), which is the source / drain region of the transistor M4 that becomes PU2, are connected by a PN junction contact 370.

[0071] 6. Manufacturing Method of Semiconductor Device of Third Embodiment Next, a method for manufacturing the SRAM cell 300 described above will be described. Figures 60-79 show manufacturing process diagrams for the SRAM cell 100. In the manufacturing process for the SRAM cell 100 shown in Figures 60-79, as in Figures 2-5 described above, four diagrams are shown for each step: a plan view and cross-sectional views of the plan view taken along lines A-A, B-B, and C-C. Note that the manufacturing method for the SRAM cell 300 can be similar to the manufacturing method for the SRAM cell 100 of the first embodiment, with some exceptions. Therefore, only the steps different from those of the SRAM cell 100 of the first embodiment will be described. Furthermore, in the description of the manufacturing method for the SRAM cell 300, components similar to those in Figures 56-59 described above will be designated by the same reference numerals, and detailed description thereof will be omitted.

[0072] First, as shown in Figures 60-63, known techniques are used to form semiconductor layers 310, 311, 350, and 351 of a nanosheet transistor having a GAA-FET structure, as well as gate electrodes 320 and 360. For example, first, N-type or P-type impurities are implanted into the regions of substrate 306 that will become transistors M5 and M6, forming P-type semiconductor layers 313 and 353 and N-type semiconductor layers 314 and 354. Then, a stack of SiGe layers and Si layers is formed on substrate 306 by epitaxial growth. In the configurations shown in Figures 60-79, three SiGe layers and three Si layers are stacked. At this time, N-type or P-type impurities are implanted into the Si layers, respectively, to form P-type semiconductor layers 316 and 356, which will become channel regions, and an N-type semiconductor layer 317. As in the first embodiment, Ge layers may be used instead of the Si layers.

[0073] Next, a patterned hard mask and dummy gates are formed on the SiGe / Si stack, and the SiGe / Si stack is etched to form SiGe / Si pillars. Furthermore, element isolation such as shallow trench isolators (STI) is formed in the substrate 306 in areas other than the P-type semiconductor layers 313 and 353 that will become transistors M5 and M6 and the N-type semiconductor layers 314 and 354. Si layers are formed on the side surfaces of the SiGe / Si stack by epitaxial growth. At this time, N-type or P-type impurities are implanted into the Si layers to form N-type semiconductor layers 312 and 352 and a P-type semiconductor layer 315 that will become the source and drain regions of transistors M1-M4. After selectively removing the SiGe layer, TiN or the like is embedded in the areas where the SiGe layer was removed to form gate electrodes 320 and 360. Then, an insulating layer is formed over the entire surface of the substrate 106, and then the gate electrode and the semiconductor layer formed between the gate electrodes 320 and 360 are removed and recessed to separate the semiconductor layers 310 and 350. Furthermore, PN junction contacts 330 and 370 are formed on the semiconductor layers 310 and 350. Furthermore, VDD 302 is formed on the gate electrodes 320 and 360.

[0074] Next, as shown in FIGS. 64 to 67, the substrate 306 is turned upside down and then removed. This exposes the N-type semiconductor layers 314 and 354. Next, as shown in FIGS. 68 to 71, the semiconductor layers above the gate electrodes 320 and 360 are removed from the surface (back side) from which the substrate 306 has been removed, in areas excluding the P-type semiconductor layers 313 and 353 and the N-type semiconductor layers 314 and 354 that will become transistors M5 and M6. This removes the N-type semiconductor layer 314 on the P-type semiconductor layer 315, as shown in FIG. 69. Furthermore, as shown in FIG. 70, the P-type semiconductor layer 313 and the N-type semiconductor layer 314 on the gate electrode 320 are removed. Furthermore, as shown in FIG. 71, the surfaces of the uppermost gate electrodes 320 and 360 are exposed.

[0075] Next, as shown in FIGS. 72-75, word lines 391 and 392 are formed on the side surfaces of the P-type semiconductor layers 313 and 353 and the N-type semiconductor layers 314 and 354 that will become transistors M5 and M6. The word lines 391 and 392 form the gate electrodes of transistors M5 and M6. Next, as shown in FIGS. 76-79, a first bit line 340, a second bit line 380, and VDD 301 are formed. The first bit line 340 is formed on the N-type semiconductor layer 314 with the P-type semiconductor layer 313 formed underneath. The second bit line 380 is formed on the N-type semiconductor layer 354 with the P-type semiconductor layer 353 formed underneath. VDD 301 is formed on the N-type semiconductor layers 314 and 354 that do not have the P-type semiconductor layers 313 and 353 formed underneath. The first bit line 340, the second bit line 380, and the VDD 301 are formed continuously in the adjacent SRAM cell 300. By the above steps, a semiconductor device (SRAM cell) can be manufactured in which nanosheet transistors having a GAA-FET structure are arranged in a plane, as shown in Figures 56 to 59.

[0076] According to the semiconductor devices of the first to third embodiments described above, the transistors M1-M4 are configured as GAA-FETs. This allows for a reduction in the cell size of the semiconductor device and an improvement in the integration density of the semiconductor device. In particular, the semiconductor devices of the first and second embodiments have a CFET structure in which transistors M1 and M3, and transistors M2 and M4 are stacked, and vertical transistors M5 and M6 are formed on the CFET. Therefore, the formation area of ​​transistors M5 and M6 is not added to the formation area of ​​transistors M1-M4. As a result, the reduction in the formation area of ​​transistors M1-M4 allows for a reduction in the element area of ​​the SRAM cell. This allows for a reduction in the cell size of the semiconductor device and an improvement in the integration density of the semiconductor device.

[0077] The present invention is not limited to the configurations described in the above embodiments, and various modifications and changes are possible without departing from the scope of the present invention.

[0078] 100, 200, 300... SRAM cell, 101, 301, 302... power supply voltage (VDD), 102... ground (GND), 102, 120, 160, 192, 320, 360... gate electrode, 103, 104, 308... wiring, 105, 121, 161... dummy gate, 106, 306... substrate, 107... STI, 108... insulating layer, 110, 150, 310, 311, 350, 351... semiconductor layer, 111, 113, 116, 141, 151 , 153, 156, 312, 314, 317, 352, 354... N-type semiconductor layer, 112, 114, 115, 152, 154, 155, 313, 315, 316, 353, 356... P-type semiconductor layer, 130, 170... FET junction contact, 131, 171, 330, 370... PN junction contact, 132... Ti / TiN layer, 140, 340... first bit line, 180, 380... second bit line, 190, 391... word line, 191... word contact

Claims

1. A semiconductor device comprising a plurality of semiconductor elements on a substrate, wherein the plurality of semiconductor elements include a first nanosheet type semiconductor element, a second nanosheet type semiconductor element, and a vertical semiconductor element, and the semiconductor device comprises contacts connecting the first nanosheet type semiconductor element and the second nanosheet type semiconductor element, and the vertical semiconductor element is disposed between the substrate and the first nanosheet type semiconductor element.

2. The semiconductor device according to claim 1, wherein the second nanosheet type semiconductor element is stacked on the first nanosheet type semiconductor element, and the contact is formed between the layers of the first nanosheet type semiconductor element and the second nanosheet type semiconductor element.

3. The semiconductor device according to claim 1, wherein the second nanosheet type semiconductor element is stacked on the first nanosheet type semiconductor element, and the contact is formed continuously on the side surface of the first nanosheet type semiconductor element and the side surface of the second nanosheet type semiconductor element.

4. The semiconductor device according to claim 1, wherein the channel region of the vertical semiconductor element is formed adjacent to the source / drain regions of the first nanosheet type semiconductor element.

5. The semiconductor device according to claim 4, wherein the first nanosheet type semiconductor element and the vertical semiconductor element share one of the source / drain regions.

6. A semiconductor device comprising a plurality of semiconductor elements on a substrate, wherein the plurality of semiconductor elements include at least a first nanosheet type semiconductor element, a second nanosheet type semiconductor element, and a third nanosheet type semiconductor element, wherein the second nanosheet type semiconductor element is stacked on the first nanosheet type semiconductor element, wherein the first nanosheet type semiconductor element and the third nanosheet type semiconductor element are arranged parallel to the surface of the substrate, wherein an element isolation region between the first nanosheet type semiconductor element and the second nanosheet type semiconductor element has a contact connecting the first nanosheet type semiconductor element and the second nanosheet type semiconductor element, and wherein the gate of the first nanosheet type semiconductor element, the gate of the third nanosheet type semiconductor element, and the contact are separated.

7. A method for manufacturing a semiconductor device comprising a first nanosheet type semiconductor element, a second nanosheet type semiconductor element, and a vertical semiconductor element on a substrate, the method comprising the steps of: forming a channel region and one of the source / drain regions constituting the vertical semiconductor element on the substrate; forming a stack of a first semiconductor layer and a sacrificial layer on the channel region of the vertical semiconductor element; forming a stack of a second semiconductor layer and a sacrificial layer; removing the sacrificial layer and embedding a metal layer to form a gate electrode that covers the periphery of the first semiconductor layer and the second semiconductor layer in a cross section in the gate width direction; forming source / drain regions on side surfaces of the first semiconductor layer and the second semiconductor layer; and forming contacts that connect the source / drain regions formed on the side surfaces of the first semiconductor layer and the second semiconductor layer.

8. A method for manufacturing a semiconductor device according to claim 7, wherein in the step of forming the gate electrodes, a plurality of rows of the gate electrodes are formed sandwiching one row of dummy gates therebetween; a step of removing and digging in the semiconductor layer between the dummy gates to form element isolation; and in the step of forming the contacts, the contacts are formed between the first semiconductor layer and the second semiconductor layer from the element isolation region.

9. A method for manufacturing a semiconductor device according to claim 7, wherein in the step of forming the gate electrodes, a plurality of rows of the gate electrodes are formed sandwiching two rows of dummy gates, and a step of removing and digging in the two rows of the dummy gates and the semiconductor layer between the layers of the dummy gates to form element isolation; and in the step of forming the contacts, the contacts are formed on side surfaces of the first semiconductor layer and the second semiconductor layer within the element isolation region.

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