Multilayer ceramic electronic component

Abstract

The present invention provides a multilayer ceramic electronic component such as a multilayer ceramic capacitor regarding which an amount of solder used for mounting can be reduced, and occurrence of squealing can be suppressed.　A multilayer ceramic electronic component 1 includes: a laminate 2 having two principal faces A which faces each other in a lamination direction T and in which a dielectric layer 14 and an internal electrode layer 15 are laminated, and two end faces C which faces each other in a length direction L; two external electrodes 3 provided respectively at the two end faces C so as to cover the end face C and further a part of each of the two principal faces A; and two spacers 4 disposed on one of the two principal faces A. Each of the spacers 4 includes a first region 41 in contact with the external electrode 3 and a second region 42 not in contact with the external electrode 3, the regions being arrayed in the lamination direction T. The second region 42 has a higher Sn content and / or a resin content than that of the first region 41.

Description

Multilayer ceramic electronic components

[0001] The present invention relates to a multilayer ceramic electronic component such as a multilayer ceramic capacitor.

[0002] Multilayer ceramic electronic components such as multilayer ceramic capacitors are widely used in various electronic devices, such as mobile terminal devices such as mobile phones and personal computers. A multilayer ceramic capacitor comprises a rectangular parallelepiped laminate in which dielectric layers and internal electrode layers are alternately stacked, and external electrodes formed on both opposing ends of the laminate.

[0003] A multilayer ceramic capacitor has an inner layer portion in which dielectric layers and internal electrodes are alternately stacked, and dielectric layers are disposed on the top and bottom of the inner layer portion as outer layers to form a rectangular parallelepiped laminate, and external electrodes are provided on both longitudinal end faces of the laminate to form a capacitor body.

[0004] Furthermore, in order to suppress the occurrence of so-called "squeak noise," a multilayer ceramic capacitor is known that includes a spacer (metal frame) formed on the side of the capacitor body that is mounted on a substrate so as to cover part of the external electrodes (Patent Document 1).

[0005] U.S. Patent No. 9,799,453

[0006] However, if the heated and melted solder during mounting runs along the surface of the spacer and rises high in the height direction of the multilayer ceramic capacitor, the expansion and contraction vibrations of the inner layer are transmitted to the mounting board, making it difficult to suppress the occurrence of acoustic noise.

[0007] An object of the present invention is to provide a multilayer ceramic electronic component, such as a multilayer ceramic capacitor, which can reduce the amount of solder used during mounting and suppress the generation of acoustic noise.

[0008] The inventors discovered that by dividing the spacer into a first region that is placed on the capacitor body side and a second region that is placed on the mounting board side, and by making the Sn content and / or resin content higher in the second region than in the first region, it is possible to reduce the amount of solder used during mounting and suppress the occurrence of squealing, and thus completed the present invention.

[0009] That is, the present invention provides a multilayer ceramic electronic component comprising: a laminate including an inner layer portion in which dielectric layers and internal electrode layers are alternately stacked, and having two main surfaces opposing each other in a stacking direction, two end faces opposing each other in a length direction intersecting the stacking direction, and two side surfaces opposing each other in a width direction intersecting the stacking direction and the length direction; two external electrodes connected to the internal electrode layers on each of the two end faces, and covering the end faces and parts of the two main surfaces adjacent to the end faces; and two spacers arranged on one of the two main surfaces of the laminate, wherein the spacers include a first region in contact with the external electrodes and a second region not in contact with the external electrodes, which are aligned in the stacking direction, and the second region has a higher Sn content and / or a higher resin content than the first region.

[0010] According to the present invention, it is possible to provide a multilayer ceramic electronic component such as a multilayer ceramic capacitor that can reduce the amount of solder used during mounting and suppress the generation of acoustic noise.

[0011] 1 is a diagram showing the appearance of a multilayer ceramic capacitor 1. FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line II-II in FIG. 1. FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line III-III in FIG. 1. FIG. 4 is a cross-sectional view of a spacer 4 when mounted (first embodiment). FIG. 5 is a cross-sectional view of a spacer 4 when mounted (second embodiment). FIG. 6 is a cross-sectional view of a spacer 4 when mounted (third embodiment). FIG. 7 is a cross-sectional view of a spacer 4 when mounted (fourth embodiment). FIG. 8 is an enlarged cross-sectional view of a portion of a first region 41 when a phenolic resin is used. FIG. 9 is an enlarged cross-sectional view of a portion of a first region 41 when an epoxy resin is used. FIG. 10 is a flowchart showing a manufacturing method of a multilayer ceramic capacitor 1. FIG. 11 is a diagram illustrating a laminate manufacturing step S1, a base electrode layer forming step S2, and a plating layer forming step S3. FIG. 12 is a cross-sectional view of a multilayer ceramic capacitor 1 on which an insulating material 50 is arranged.

[0012] Hereinafter, a multilayer ceramic capacitor 1 will be described as an embodiment of the multilayer ceramic electronic component of the present invention, but the present invention is not limited thereto. Furthermore, the drawings may be drawn in a simplified schematic form to explain the contents of the invention, and the dimensional ratios of the depicted components or between the components may not match the dimensional ratios of those components described in the specification. Furthermore, components described in the specification may be omitted in the drawings, or the number of components may be omitted.

[0013] (Multilayer ceramic capacitor 1) Fig. 1 is a schematic perspective view of a multilayer ceramic capacitor 1 according to an embodiment. Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 according to an embodiment taken along line II-II in Fig. 1. Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 according to an embodiment taken along line III-III in Fig. 1. Note that Fig. 2 is a cross-section parallel to the length direction L and the stacking direction T, and is also referred to as an LT cross-section. Fig. 3 is a cross-section parallel to the width direction W and the stacking direction T, and is also referred to as a WT cross-section.

[0014] The multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape and includes a capacitor body 1A including a laminate 2 and a pair of external electrodes 3 provided on both ends of the laminate 2, and a spacer 4 attached to the capacitor body 1A. The laminate 2 also includes an inner layer portion 11 in which dielectric layers 14 and internal electrode layers 15 are laminated.

[0015] In the following description, the terms used to represent the orientation of the multilayer ceramic capacitor 1 are: a length direction L, which is the direction in which a pair of external electrodes 3 are provided in the multilayer ceramic capacitor 1; a stacking direction T, which is the direction in which the dielectric layers 14 and the internal electrode layers 15 are stacked; and a width direction W, which is the direction intersecting both the length direction L and the stacking direction T. In the embodiment, the width direction W is perpendicular to both the length direction L and the stacking direction T.

[0016] (Outer Surfaces of Laminate 2) Of the six outer surfaces of the laminate 2, a pair of outer surfaces facing each other in the stacking direction T will be referred to as the first main surface A1 and the second main surface A2, a pair of outer surfaces facing each other in the width direction W will be referred to as the first side surface B1 and the second side surface B2, and a pair of outer surfaces facing each other in the length direction L will be referred to as the first end surface C1 and the second end surface C2. Note that when there is no need to particularly distinguish between the first main surface A1 and the second main surface A2, they will be collectively referred to as the main surface A; when there is no need to particularly distinguish between the first side surface B1 and the second side surface B2, they will be collectively referred to as the side surface B; and when there is no need to particularly distinguish between the first end surface C1 and the second end surface C2, they will be collectively referred to as the end surface C.

[0017] The laminate 2 preferably has rounded ridges R1 including corners. The ridges R1 are the portions where two surfaces of the laminate 2, i.e., the main surface A and the side surface B, the main surface A and the end surface C, or the side surface B and the end surface C, intersect.

[0018] (Laminate 2) The laminate 2 includes an inner layer portion 11 that forms capacitance, an outer layer portion 12 that is arranged to sandwich the inner layer portion 11 in the stacking direction T, and a side margin portion 16 that is arranged to sandwich the inner layer portion 11 and the outer layer portion 12 in the width direction W.

[0019] (Inner Layer Portion 11) The inner layer portion 11 includes dielectric layers 14 and internal electrode layers 15 alternately stacked along the stacking direction T.

[0020] (Dielectric Layer 14) The dielectric layer 14 is made of a ceramic material, such as BaTiO ３ A dielectric ceramic containing the above as its main component is used.

[0021] (Internal Electrode Layer 15) The internal electrode layer 15 includes a plurality of first internal electrode layers 15a and a plurality of second internal electrode layers 15b. The first internal electrode layers 15a and the second internal electrode layers 15b are alternately arranged. The first internal electrode layer 15a includes a first opposing portion 152a opposing the second internal electrode layer 15b and a first lead portion 151a extending from the first opposing portion 152a toward the first end face C1. An end of the first lead portion 151a is exposed at the first end face C1 and electrically connected to the first external electrode 3a described below. The second internal electrode layer 15b includes a second opposing portion 152b opposing the first internal electrode layer 15a and a second lead portion 151b extending from the second opposing portion 152b to the second end face C2. An end of the second lead portion 151b is electrically connected to the second external electrode 3b described below.

[0022] The internal electrode layers 15 are preferably formed from a metal material such as Ni, Cu, Ag, Pd, an Ag—Pd alloy, Au, or Sn.

[0023] (Outer Layer Portion 12) The outer layer portion 12 can be formed from the same material as the dielectric layer 14 of the inner layer portion 11.

[0024] (Side Margins 16) The side margins 16 are arranged to sandwich the inner layer portions 11 and the outer layer portions 12 in the width direction W, and include a first side margin 16a that forms the first side surface B1 of the multilayer ceramic capacitor 1, and a second side margin 16b that forms the second side surface B2 of the multilayer ceramic capacitor 1. The side margins 16 can be made of the same material as the dielectric layers 14.

[0025] (External electrode 3) The external electrode 3 includes a first external electrode 3a provided on the first end face C1 and a second external electrode 3b provided on the second end face C2. The external electrode 3 covers not only the end face C but also a part of the main face A and the side face B that are continuous with the end face C.

[0026] As described above, the end of the first lead portion 151a of the first internal electrode layer 15a is exposed at the first end face C1 and is electrically connected to the first external electrode 3a. Also, the end of the second lead portion 151b of the second internal electrode layer 15b is exposed at the second end face C2 and is electrically connected to the second external electrode 3b. This results in a structure in which multiple capacitor elements are electrically connected in parallel between the first external electrode 3a and the second external electrode 3b.

[0027] The external electrodes 3 include, for example, a base electrode layer 30 and a plating layer 31. However, it is not essential that the external electrodes 3 have such a layered structure. In addition, the external electrodes 3 may include a resin electrode layer to relieve stress applied to the multilayer ceramic capacitor 1.

[0028] The base electrode layer 30 is formed, for example, by applying and baking a conductive paste containing Cu as a main component. The base electrode layer 30 may also contain metal components other than Cu, glass components, and / or ceramic materials. Examples of metal components other than Cu include Mg, Cr, Sr, Al, Na, and Fe. Examples of glass components include oxides of Ba, Sr, Si, Ca, Zn, Al, or B. The ceramic component may contain, as a main component, a component contained in the dielectric layer 14 that forms the inner layer portion 11.

[0029] The base electrode layer can be formed in a two-layer structure. When the base electrode layer has a two-layer structure, the first layer may contain a metal component and a glass component, and the second layer may contain a metal component and a resin. By including a resin in the base electrode layer, the flexural strength can be improved. Note that the second layer does not need to completely cover the first layer, and may cover only a portion of the first layer.

[0030] The plating layer contains, for example, at least one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, and Zn, or an alloy containing such a metal. The proportion of metal per unit volume of the plating layer is preferably 99% by volume or more. The plating layer preferably does not contain a glass component.

[0031] The plating layer 31 can be formed to have a two-layer structure. The two-layer structure can be formed, for example, by a Ni plating layer disposed on the surface of the base electrode layer 30 and a Sn plating layer disposed on the surface of the Ni plating layer. However, the configuration of the plating layer 31 is not limited to this.

[0032] The plating layer 31 can be formed in a three-layer structure. The three-layer structure can be formed, for example, by sequentially arranging a Sn plating layer, a Ni plating layer, and a Sn plating layer on the surface of the base electrode layer 30, or by sequentially arranging a Ni plating layer and a Au plating layer. The Ni plating layer can prevent the base electrode layer from being eroded by solder, and the Sn plating layer can improve mountability.

[0033] (Spacer 4) The spacer 4 includes a pair of first and second spacers 4a and 4b. The first spacer 4a is disposed on the first end face C1 side in the longitudinal direction L of the second main surface A2, which is the substrate mounting surface of the capacitor body 1A, and the second spacer 4b is disposed on the second end face C2 side. When the substrate mounting surface of the capacitor body 1A is the first side face B1, the first spacer 4a is disposed on the first end face C1 side in the longitudinal direction L of the first side face B1, which is the substrate mounting surface of the capacitor body 1A, and the second spacer 4b is disposed on the second end face C2 side.

[0034] The spacer 4 is disposed on the external electrode 3 of the capacitor body 1A and on the subsequent second main surface A2 of the laminate 2 on which no external electrode 3 is disposed. When the substrate mounting surface of the capacitor body 1A is the first side surface B1, the spacer 4 is disposed on the external electrode 3 of the capacitor body 1A and on the subsequent first side surface B1 of the laminate 2 on which no external electrode 3 is disposed.

[0035] In the embodiment, the external electrode 3 is composed of a base electrode layer 30 and a plating layer 31 covering it, and the spacer 4 is placed on the surface of the plating layer 31. However, the plating layer 31 is not necessarily required, and for example, the spacer 4 may be placed on the surface of the base electrode layer 30.

[0036] 2 , the spacer 4 includes a first region 41 that is in contact with the external electrode 3 and a second region 42 that is not in contact with the external electrode 3, which are aligned in the stacking direction T. When the substrate mounting surface of the capacitor body 1A is the first side surface B1, the first region 41 and the second region 42 are aligned in the width direction W, with the first region 41 in contact with the external electrode 3 and the second region 42 not in contact with the external electrode 3. In this way, of the first region 41 and the second region 42 aligned in the stacking direction T or the width direction W, the first region 41 is positioned in contact with the capacitor body 1A, and the second region 42 is positioned away from the capacitor body 1A.

[0037] (First Region 41) The first region 41 can contain various components such as metal components and resin components, but for example, if the first region 41 contains a large amount of metal components, the ratio of the volume to the surface area of ​​the metal components increases, thereby reducing the ESR of the multilayer ceramic electronic component. On the other hand, if the first region 41 contains more resin components than metal powder, the resin components can buffer the vibrations of the multilayer ceramic capacitor, thereby reducing the vibrations transmitted to the mounting board.

[0038] The resin component that forms the first region 41 may be, for example, a resin such as a phenol resin or an epoxy resin.

[0039] An example of the structure of the first region 41 when the first region 41 is formed using a phenol resin is shown in Fig. 8. Fig. 8 is a partially enlarged cross-sectional view of the internal region of the first region 41.

[0040] The first region 41 shown in Figure 8 contains either Cu or Ni and Sn as metal powder. The Cu and Ni may be coated with Ag. The intermetallic compound formed by adding Sn to either Cu or Ni is less likely to deform due to heat, even when soldering is performed when mounting the multilayer ceramic capacitor 1 on a mounting substrate, and the shape of the first region 41 can be reliably maintained. In particular, the intermetallic compound formed by adding Sn to an alloy of Cu and Ni is preferable as a component for forming the first region 41.

[0041] The metal region MP formed by the metal powder contains a phenolic resin. The phenolic resin coats the particles of the intermetallic compound and is scattered so as to fill the gaps between the particles. The phenolic resin may not completely coat the particles of the intermetallic compound. Furthermore, by using the phenolic resin, the amount of gas generated during the heat treatment for forming the first region 41 can be reduced, thereby reducing the voids P within the first region 41. The phenolic resin may be exposed on the surface of the first region 41 and cover at least a portion of the surface of the first region 41. By coating the surface of the first region 41 with the phenolic resin, the smoothness of the surface of the first region 41 is improved, and the mechanical strength of the spacer 4 can be increased.

[0042] Examples of phenolic resins include novolac-type phenolic resins such as phenol novolac resin, phenol aralkyl resin, cresol novolac resin, tert-butylphenol novolac resin, and nonylphenol novolac resin, resol-type phenolic resin, and polyoxystyrene such as polyparaoxystyrene. The first region 41 may contain epoxy resin or rosin in addition to the phenolic resin. Furthermore, the first region 41 may contain epoxy resin or the like in addition to the phenolic resin.

[0043] 8, metal powder MF may be contained in the resin region RP formed by the phenolic resin. The metal powder MF inhibits the shrinkage of the phenolic resin, and the shrinkage stress caused by the phenolic resin can be alleviated.

[0044] An example of the structure of the first region 41 when the first region 41 is formed using epoxy resin is shown in Fig. 9. Fig. 9 is a partially enlarged cross-sectional view of the internal region of the first region 41.

[0045] The first region 41 shown in FIG. 9 includes a Sn region, a resin region RP, a metal region MP containing Cu or Cu and Ni, and an Ag region. The metal region MP is represented as Cu in the figure, but contains either Cu or a metal containing Cu and Ni. The metal region MP may also contain Sn. Note that the metal containing Cu and Ni may be an alloy of Cu and Ni, or may further contain Sn to form an intermetallic compound. Note that Sn may be contained within the Ag region. These regions containing Sn can be detected by WDX or EDX analysis.

[0046] The resin region RP also includes a metal region MP containing Cu or Cu and Ni surrounded by Sn or Ag. When the metal region MP contains Cu and Ni, the Cu and Ni may be alloyed or may further contain Sn to form an intermetallic compound. In particular, within the resin region RP, the composition of the material incorporated is detected as is.

[0047] (Second Region 42) The second region 42 has a higher Sn content than the first region 41. By increasing the Sn content in the second region 42, the Sn contained in the second region 42 melts when heated during mounting, contributing to bonding to the mounting substrate. This allows for a reduction in the amount of solder used when mounting the multilayer ceramic capacitor 1 to the mounting substrate, thereby suppressing the occurrence of squeal caused by solder wetting.

[0048] The average particle size D50 of the Sn particles contained in the first region 41 and the second region 42 is preferably 5 μm or more. If the average particle size D50 of the Sn particles is less than 5 μm, the reactivity between the metals decreases, many voids are generated inside the first region 41 and the second region 42, and the strength of the first region 41 and the second region 42 decreases.

[0049] The second region 42 has a higher resin content than the first region 41. By increasing the resin content of the second region 42, the bond between the second region 42 and the first region 41 can be stably maintained. Furthermore, the resin softens and flows due to the heat of reflow when mounting the multilayer ceramic capacitor 1. This causes the Sn particles to flow, increasing the probability of contact between the Sn particles and each other or between the Sn particles and the solder used during mounting. This facilitates the formation of a metal network, thereby strengthening the electrical and physical bond. Furthermore, because the resin exerts a reducing effect, increasing the amount of resin can also improve the effectiveness of removing metal oxide films.

[0050] 2 , the thickness of the first region 41 and the second region 42 aligned in the stacking direction T is greater than that of the second region 42. When the substrate mounting surface of the capacitor body 1A is the first side surface B1, the first region 41 and the second region 42 are aligned in the width direction W, and the thickness of the first region 41 in the width direction W is greater than that of the second region 42.

[0051] When the first region 41 and the second region 42 are aligned in the stacking direction T, the thickness of the first region 41 in the stacking direction T is 50 μm or more and 250 μm or less, and the thickness of the second region 42 in the stacking direction T is 15 μm or more and 200 μm or less before mounting the multilayer ceramic capacitor 1. If the thickness of the first region 41 in the stacking direction T is less than 50 μm, the distance between the mounting substrate and the multilayer ceramic capacitor 1 becomes short, making it difficult to resolve the acoustic noise problem. On the other hand, if the thickness of the first region 41 in the stacking direction T is greater than 250 μm, the first region 41 becomes more likely to come off from the capacitor body 1A due to external stress. Furthermore, if the thickness of the second region 42 in the stacking direction T is less than 15 μm, the volume of the second region 42 becomes smaller, thereby reducing the bonding strength after reflow. On the other hand, if the thickness of the second region 42 in the stacking direction T is greater than 200 μm, the second region 42 becomes more likely to come off due to external stress. In addition, when the substrate mounting surface of the capacitor body 1A is the first side surface B1, the thickness in the width direction W of the first region 41 is 50 μm or more and 250 μm or less, and the thickness in the width direction W of the second region 42 is 15 μm or more and 200 μm or less.

[0052] (Dimensions after mounting) After mounting the multilayer ceramic capacitor 1, in which the first region 41 and the second region 42 are aligned in the stacking direction T, i.e., in a mounting structure in which the second region 42 is connected to the mounting substrate 51, the thickness of the second region 42 in the stacking direction T after connection is 0.1 μm or more and 200 μm or less.

[0053] 4 , after mounting, the maximum length in the length direction L of the second region 42 is longer than the maximum length in the length direction L of the first region 41. Furthermore, the maximum length in the width direction W of the second region 42 is longer than the maximum length in the width direction W of the first region 41. Due to this difference in size between the first region 41 and the second region 42, a recessed portion D is formed on the side surface of the spacer 4. When solder is used during mounting, the spacer 4 having the recessed portion D formed on the side surface is more effective at suppressing squeal than a spacer without the recessed portion D, because excess molten solder is trapped in the recessed portion D.

[0054] When the substrate mounting surface of capacitor body 1A is on the first side face B1 side and first region 41 and second region 42 are aligned in width direction W, the thickness of the second region in width direction W after being connected to mounting substrate 51 and mounted is 0.1 μm to 200 μm. The maximum length in length direction L of second region 42 is longer than the maximum length in length direction L of first region 41, and the maximum length in stacking direction T of second region 42 is longer than the maximum length in stacking direction T of first region 41.

[0055] Furthermore, after the multilayer ceramic capacitor 1 is connected and mounted on the mounting substrate 51, a resin Ra containing the same components as the resin R contained in the second region 42 may be present on the surface of the second region 42 and on the surface of the mounting substrate 51, as shown in Fig. 5, and the resin Ra may also be present on the surface of the capacitor body 1A. The resin eluted from the second region 42 contributes to the connection between the spacer 4 and the mounting substrate 51. This allows the amount of solder used for connection to be reduced, thereby suppressing acoustic noise.

[0056] Furthermore, the structure of the spacer 4 after mounting can be adjusted by the type and amount of resin used to form the first region 41 and the second region 42. For example, if the second region 42 is formed using a thermosetting resin containing a mixture of phenolic resin and epoxy resin, Sn in the second region 42 melts during mounting on a mounting substrate, and some of it is absorbed by the first region 41. Furthermore, most of the resin in the second region 42 is expelled to the periphery of the second region 42, resulting in the spacer 4 after mounting having a structure as shown in FIG. 6. Using a thermosetting resin can not only bond the solder used during mounting to the metal, but also generate bonding by the thermosetting resin. In this case, if the resin component of the first region 41 contains only phenolic resin, the shape of the first region 41 can be more easily maintained.

[0057] On the other hand, if the first region 41 and the second region 42 are formed using a non-thermosetting resin made of, for example, only phenolic resin, only epoxy resin, or only rosin, the Sn in the second region 42 will melt out and most of it will be absorbed into the first region 41. Furthermore, most of the resin in the second region 42 will be discharged to the periphery of the second region, and the spacer 4 after mounting will have a structure as shown in FIG.

[0058] (Method for Manufacturing Multilayer Ceramic Capacitor 1) Fig. 10 is a flowchart illustrating a method for manufacturing the multilayer ceramic capacitor 1. The method for manufacturing the multilayer ceramic capacitor 1 includes a laminate manufacturing step S1, a base electrode layer forming step S2, a plating layer forming step S3, and a spacer arranging step S4. Fig. 11 is a diagram illustrating the laminate manufacturing step S1, the base electrode layer forming step S2, and the plating layer forming step S3.

[0059] (Laminate manufacturing process S1) A ceramic slurry containing ceramic powder, a binder, and a solvent is formed into a sheet on the surface of a carrier film using a die coater, gravure coater, microgravure coater, or the like to prepare a ceramic green sheet 101 for lamination that will become the dielectric layer 14. Next, a conductive paste is printed in strips on the ceramic green sheet 101 for lamination by screen printing, inkjet printing, gravure printing, or the like, and a conductive pattern 102 that will become the internal electrode layer 15 is printed on the surface of the ceramic green sheet 101 for lamination to prepare a material sheet 103.

[0060] 11( a), a plurality of material sheets 103 are stacked such that the conductive patterns 102 face in the same direction and are offset, for example, by half a pitch, in the longitudinal direction between adjacent material sheets 103. Furthermore, outer layer ceramic green sheets 112 that will become the outer layer portions 12 are stacked on both sides of the plurality of stacked material sheets 103.

[0061] The stacked material sheets 103 and the outer layer ceramic green sheets 112 are pressed together by a hydrostatic press or the like to form a mother block 110 shown in FIG. 11(b).

[0062] Next, the mother block 110 is cut along cutting lines X and Y intersecting with cutting line X shown in FIG. 11(b), and fired to produce a plurality of laminates 2 shown in FIG. 11(c).

[0063] (Base electrode layer forming step S2) Subsequently, a conductive paste containing Cu is applied to and baked on the end face C of the laminate 2 to form the base electrode layer 30. The base electrode layer 30 is formed so as to cover not only the end faces C on both sides of the laminate 2, but also the main face A and side face B of the laminate 2, and to cover a part of the end face C side of the main face A. However, the present invention is not limited to this, and the base electrode layer may contain other metals or other components, and two base electrode layers may be provided.

[0064] (Plating layer forming step S3) Next, a plating layer 31 is formed on the surface of the base electrode layer 30 to produce the capacitor body 1A shown in Fig. 11(d). The plating layer 31 can be composed of a Ni plating layer and a Sn plating layer disposed on the surface of the Ni plating layer, but is not limited to this.

[0065] (Spacer Arranging Step S4) The spacer arranging step S4 includes the following first region forming step and second region forming step.

[0066] (First Region Forming Step) Prepare a first region paste to be used for forming the first region 41. Examples of the first region paste include the following phenol resin-based and epoxy resin-based pastes.

[0067] (Phenol Resin-Based) The paste for the first region contains metals made of Cu, Ni, Sn, and Ag, a phenol resin, a solvent, and an additive.

[0068] Examples of the phenol resin include novolac-type phenol resins such as phenol novolac resin, phenol aralkyl resin, cresol novolac resin, tert-butylphenol novolac resin, and nonylphenol novolac resin; resol-type phenol resin; and polyoxystyrene such as polyparaoxystyrene.

[0069] The first region paste is applied to a first end face C1 side in the length direction L on the second main surface A2 side, which is the substrate mounting surface of the capacitor body 1A, where the first spacers 4a are arranged, and to a second end face C2 side in the length direction L on the other side, where the second spacers 4b are arranged. Furthermore, when the substrate mounting surface of the capacitor body 1A is the first side surface B1, the first region paste is applied to a first end face C1 side in the length direction L on the first side surface B1 side, which is the substrate mounting surface of the capacitor body 1A, where the first spacers 4a are arranged, and to a second end face C2 side in the length direction L on the other side, where the second spacers 4b are arranged. Screen printing, dispensing, or the like can be used to apply the first region paste.

[0070] After the first region paste is applied, a heating step is performed, in which at least a portion of the metal in the paste forms an intermetallic compound to form the metal region MP. As the phenolic resin hardens, some of the phenolic resin is absorbed into the metal region MP and some of the phenolic resin is expelled from the metal region MP, thereby forming the first region 41 of the spacer 4 bonded to the capacitor body 1A.

[0071] (Epoxy Resin-Based) The paste for the first region contains a metal consisting of Cu coated with Sn or Ag, or Cu and Ni coated with silver (Ag) instead of Cu, an epoxy resin, and a solvent.

[0072] The epoxy resin is a bisphenol A epoxy resin. The solvent is, for example, diethylene glycol monobutyl ether, diethylene glycol monoethyl ether, or diethylene glycol monomethyl ether. The paste for the first region does not contain a hardener such as a phenol resin or imidazole.

[0073] The volume ratio of Sn to the total volume of the metal is 70% to 90%. The volume ratio of the metal to the resin is 70% to 90%.

[0074] The epoxy resin-based forming process can be the same as that for the phenolic resin-based forming process described above.

[0075] (Second Region Formation Process) A metal paste for forming the second region 42 is placed on the surface of the first region 41 by a dispensing method or mask printing. The metal paste for the second region 42 may contain an epoxy resin or a phenolic resin, to which a catalyst such as imidazole may be added.

[0076] The resin contained can be an epoxy resin or a phenol resin. By mixing these resins and adding a catalyst such as imidazole, the adhesive strength of the resin can be used to connect the mounting substrate and the multilayer ceramic electronic component during mounting, rather than just using solder, thereby improving the adhesive strength and enabling a stronger connection.

[0077] The second region 42 can be formed by placing a metal paste for forming the second region 42 on the first region 41, and then performing a heat treatment at 100 to 200°C for about 5 to 20 minutes, for example.

[0078] As described above, the heat treatment for forming the first region 41 or the second region 42 can be carried out in each of the first region formation process and the second region formation process, but depending on the components of the first region paste and the second region paste, the heat treatment may be carried out simultaneously.

[0079] Although the embodiment of the present invention has been described above, the present invention is not limited to this and can be embodied in various forms.

[0080] 12 , an insulating material 50 can be disposed between the first spacer 4 a and the second spacer 4 b so as to cover at least a portion of at least one of the first spacer 4 a and the second spacer 4 b and at least a portion of the second main surface A2 or the first side surface B1 of the laminate 2. In addition to this, the insulating material 50 may be disposed so as to fill the gap between the first region 41 and the second main surface A2 or the first side surface B1 of the laminate 2. By disposing the insulating material 50, it is possible to improve the adhesive strength between the spacer 4 and the external electrode 3 and between the spacer 4 and the laminate 2.

[0081] Figure 12 shows an embodiment in which an insulating material 50 is arranged continuously between the inner region 41 of the first spacer 4a and the inner side surface 41 of the second spacer 4b. In such an embodiment, the insulating material 50 can be shaped so that the length in the width direction W of the central part in the longitudinal direction L is shorter than the length in the width direction W of both ends in the longitudinal direction L.

[0082] The insulating material 50 can be arranged continuously between the first spacer 4a and the second spacer 4b, but does not necessarily have to be arranged continuously. For example, the insulating material 50 may be arranged in two parts: one covering a portion of the first spacer 4a and a portion of the second main surface A2 or the first side surface B1 of the laminate 2, and the other covering a portion of the second spacer 4b and a portion of the second main surface A2 or the first side surface B1 of the laminate 2.

[0083] The insulating material 50 can cover the entire capacitor body 1A. When the insulating material 50 covers the entire capacitor body 1A, the cushioning properties of the insulating material 50 are enhanced, and the impact resistance when an impact is applied to the multilayer ceramic capacitor 1 can be improved.

[0084] The insulating material 50 can be formed from an insulating resin. The surface of the insulating resin may be coated with an insulating water-repellent agent. By forming the insulating material from an insulating resin, the flexural strength is improved, and by further coating with an insulating water-repellent agent, the moisture resistance is improved. The insulating resin may contain ceramics, glass, etc., or may be formed only from a water-repellent agent.

[0085] The insulating material 50 may be made primarily of epoxy resin, combined with phenolic resin as a curing agent. Other curing agents that can be used include acid anhydride-based, amine-based, and ester-based curing agents. A curing accelerator may also be added to the epoxy resin. The insulating material 50 may also contain, for example, carbon, Co, Al, Cu, N, or Cr. Since the color of the insulating material 50 can be made different from the color of the capacitor body 1A, it is easier to select the orientation when mounting the insulating material 50 on a substrate.

[0086] The present invention can be embodied in various forms without departing from the spirit and scope of the present invention.

[0087] <1> A multilayer ceramic electronic component comprising: a laminate including an inner layer portion in which dielectric layers and internal electrode layers are alternately stacked, the laminate having two main surfaces opposing each other in a stacking direction, two end faces opposing each other in a length direction intersecting the stacking direction, and two side surfaces opposing each other in a width direction intersecting the stacking direction and the length direction; a capacitor body including two external electrodes connected to the internal electrode layers on each of the two end faces and covering the end faces and parts of the two opposing main surfaces or parts of the two side surfaces; and two spacers arranged on one side of the two main surfaces of the laminate, the spacers including a first region in contact with the external electrodes and a second region not in contact with the external electrodes, which are aligned in the stacking direction or the width direction, and the second region having a higher Sn content and / or a higher resin content than the first region. <2> The multilayer ceramic electronic component according to <1>, wherein the first region and the second region, which are aligned in the stacking direction or the width direction, have a thickness in the stacking direction or the width direction that is greater than that of the second region. <3> The multilayer ceramic electronic component according to <2>, wherein the thickness of the first region is 50 μm or more and 250 μm or less, and the thickness of the second region is 15 μm or more and 200 μm or less. <4> The multilayer ceramic electronic component according to any one of <1> to <3>, wherein the second region contains a thermosetting resin. <5> A mounting structure in which the multilayer ceramic electronic component according to any one of <1> to <4> is connected to a mounting substrate, wherein when the first region and the second region are aligned in the stacking direction or the width direction, the thickness of the second region in the stacking direction or the width direction after connection is 0.1 μm to 200 μm, the maximum length in the length direction is longer than that of the first region, and the maximum length in the width direction or the stacking direction is longer than that of the first region. <6> The mounting structure of a ceramic electronic component according to <5>, in which a resin containing the same components as the resin contained in the second region is present on a surface of the second region and on a surface of the mounting substrate.<7> The ceramic electronic component mounting structure according to <5>, wherein a resin containing the same components as the resin contained in the second region is present on the surface of the second region and on the surface of the capacitor body.

[0088] A Principal surface A1 First principal surface A2 Second principal surface B Side surface C End surface MF Metal powder MP Metal region P Gap R Resin RP Resin region 1 Multilayer ceramic capacitor (multilayer ceramic electronic component) 1A Capacitor body 2 Laminate 3 External electrode 4 Spacer 4a First spacer 4b Second spacer 11 Inner layer portion 12 Outer layer portion 14 Dielectric layer 15 Internal electrode layer 16 Side margin portion 30 Base electrode layer 31 Plating layer 41 First region 42 Second region 50 Insulating material 51 Mounting substrate

Claims

1. A multilayer ceramic electronic component comprising: a laminate including an inner layer portion in which dielectric layers and internal electrode layers are alternately stacked, the laminate having two main surfaces opposing each other in the stacking direction, two end faces opposing each other in a length direction intersecting the stacking direction, and two side surfaces opposing each other in a width direction intersecting both the stacking direction and the length direction; a capacitor body including two external electrodes connected to the internal electrode layers on each of the two end faces and covering the end faces and portions of the two adjacent opposing main faces; and two spacers arranged on one side of the two main faces of the laminate, the spacers including a first region in contact with the external electrodes and a second region not in contact with the external electrodes, aligned in the stacking direction, the second region having a higher Sn content and / or a higher resin content than the first region.

2. The multilayer ceramic electronic component according to claim 1, wherein the thickness of the first region in the stacking direction is greater than that of the second region in the stacking direction.

3. The multilayer ceramic electronic component according to claim 2, wherein the thickness of said first region is 50 μm or more and 250 μm or less, and the thickness of said second region is 15 μm or more and 200 μm or less.

4. The multilayer ceramic electronic component according to any one of claims 1 to 3, wherein the second region contains a thermosetting resin.

5. A mounting structure in which a multilayer ceramic electronic component according to any one of claims 1 to 4 is connected to a mounting substrate, wherein when the first region and the second region are aligned in the stacking direction, the thickness of the second region in the stacking direction after connection is 0.1 μm or more and 200 μm or less, the maximum length in the length direction is longer for the second region than for the first region, and the maximum length in the width direction is longer for the second region than for the first region.

6. The ceramic electronic component mounting structure according to claim 5, wherein a resin containing the same components as the resin contained in the second region is present on the surface of the second region and on the surface of the mounting substrate.

7. The ceramic electronic component mounting structure according to claim 5, wherein a resin containing the same components as the resin contained in the second region is present on the surface of the second region and on the surface of the capacitor body.

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