Reception device and transmission / reception system

Abstract

This reception device RX comprise: a first A / D converter 1 connected to an input terminal; a second A / D converter 2 connected to the input terminal; a phase detector 3 having input terminals connected to a first output terminal of the first A / D converter 1 and a second output terminal of the second A / D converter 2; a loop filter 5 connected to an output terminal of the phase detector 3; and a voltage-controlled oscillator 6 having an input terminal connected to an output terminal of the loop filter 5. A first sampling clock signal of the first A / D converter 1 and a second sampling clock signal of the second A / D converter 2 are generated from an output signal of the voltage-controlled oscillator 6 and have the phase difference of π / 2.

Description

Receiving device and transmitting / receiving system

[0001] The present disclosure relates to a receiving device and a transmitting / receiving system.

[0002] In telecommunications technology, a transmitting device is equipped with a modulation circuit. In digital communications, a high-frequency carrier signal and a low-frequency baseband signal containing the digital information (0, 1) to be transmitted are input to the modulation circuit. The modulation circuit modulates the carrier signal using the baseband signal. The frequency band of the carrier signal is higher than that of the baseband signal and is suitable for propagation. The baseband signal is an information signal, such as an audio signal, a video signal, or a bit stream from a computer. A receiving device is equipped with a demodulation circuit that demodulates the signal transmitted from the transmitting device.

[0003] The demodulation circuit of the receiving device described in Patent Document 1 includes a mixer that multiplies a received signal by a local signal. The local signal is output from a voltage-controlled oscillator (VCO). The frequency of the local signal is set to be the same as the frequency of the carrier signal. The output signal of the mixer is split into two, and then input to two A / D converters (analog-to-digital converters (ADCs)) via two filters, where the baseband signal is demodulated. The output signals of the two ADCs are input to a Costas Loop, which adjusts the frequency of the VCO output signal.

[0004] U.S. Patent No. 8,958,504

[0005] However, conventional receivers have a structure that uses a mixer to perform demodulation, which has the problem of large circuit scale and high power consumption. There is a demand for receivers and transmission / reception systems that can reduce power consumption by reducing the circuit scale.

[0006] A receiving device according to the present disclosure includes a first A / D converter connected to an input terminal, a second A / D converter connected to the input terminal, a phase detector having an input terminal connected to a first output terminal of the first A / D converter and a second output terminal of the second A / D converter, a loop filter connected to the output terminal of the phase detector, and a voltage-controlled oscillator having an input terminal connected to the output terminal of the loop filter, wherein a first sampling clock signal of the first A / D converter and a second sampling clock signal of the second A / D converter are generated from an output signal of the voltage-controlled oscillator and have a phase difference of π / 2. This receiving device achieves demodulation using an A / D converter instead of a mixer, thereby enabling a reduction in circuit size and power consumption.

[0007] The receiving device and transmitting / receiving system of the present disclosure can reduce the circuit scale and power consumption.

[0008] FIG. 1 is a block diagram of a transmission / reception system. FIG. 2 is a timing chart showing a received signal (Rx) (FIG. 2(a)), A / D converted data of the I channel (FIG. 2(b)), A / D converted data of the Q channel (FIG. 2(c)), data of the I channel baseband signal (FIG. 2(d)), and data of the Q channel baseband signal (FIG. 2(e)). FIG. 3 is a block diagram of a receiving device. FIG. 4 is a diagram showing the relationship between an input value and a digital value (3 bits) after A / D conversion. FIG. 5 is a block diagram of a receiving device. FIG. 6 is a diagram showing the relationship between an input value and a digital value (5 bits) after A / D conversion. FIG. 7 is a block diagram of a D / A converter and a loop filter in a receiving device. FIG. 8 is a block diagram of a receiving device. FIG. 9 is a block diagram of a transmission / reception system. FIG. 10 is a block diagram of a transmitting device. FIG. 11 is a block diagram of a transmission / reception system. FIG. 12 is a block diagram of a transmission / reception system. FIG. 13 is a circuit diagram of a pattern checker. FIG. 14 is a block diagram of a transmission / reception system. Fig. 15 is a diagram explaining the logic of operation of the mode selection circuit. Fig. 16 is a block diagram of a transmission / reception system. Fig. 17 is a block diagram of a transmission / reception system. Fig. 18 is a block diagram of a transmission / reception system. Fig. 19 is a block diagram of a transmission / reception system. Fig. 20 is a diagram showing a signal space diagram. Fig. 21 is a diagram showing the time structure of a received signal, Fig. 21(a) is a diagram showing the signal structure, and Fig. 21(b) is a diagram showing the frequency structure. Fig. 22 is a block diagram of a transmission / reception system. Fig. 23 is a block diagram of a transmission / reception system. FIG. 24 is a timing chart of various signals (FIGS. 24(a), 24(b), 24(c), 24(d), 24(e), (FIGS. 24(f), 24(g), 24(h)). FIG. 25 is a timing chart of various signals (FIGS. 25(a), 25(b), 25(c), 25(b2), 25(c2), 25(d), 25(e)). FIG. 26 is a timing chart of various signals (FIGS. 26(a), 26(b), 26(c), 26(d), 26(e), 26(f), 26(g), 26(h), 26(i)). FIG. 27 is a diagram showing a decimation filter.

[0009] Various exemplary embodiments will be described in detail below with reference to the drawings. Note that the same or equivalent parts in the drawings will be denoted by the same reference numerals, and redundant explanations will be omitted.

[0010] FIG. 1 is a block diagram of a transmitting and receiving system.

[0011] The transmission / reception system 100 includes a receiving device RX and a transmitting device TX that transmits a signal received by the receiving device RX as a transmission signal.

[0012] The transmitter TX includes a baseband signal generator 21 , a reference clock generator 22 , a modulation circuit 23 , a carrier signal generator 24 , a transmission amplifier 25 , and a transmission antenna 20 .

[0013] The baseband signal generator 21 processes an information signal contained in an input signal and outputs a baseband signal. The input signal is binary data, and when QPSK (quadrature phase shift keying) is performed, the baseband signal generator 21 generates a baseband signal for an I channel and a baseband signal for a Q channel in synchronization with a reference clock signal output from a reference clock generator 22. The I channel and Q channel baseband signals are input to a modulation circuit 23. The baseband signal input to the modulation circuit 23 is modulated at a reference frequency (f Ｓ )

[0014] The baseband signal generator 21 may include an encoder that encodes the input signal, a circuit that adds an error correction code, a signal generator that serializes the input signal and generates I-channel and Q-channel signals, and the like.

[0015] The reference clock generator 22 generates a clock signal for performing processing within the baseband signal generator 21 and supplies it to the baseband signal generator 21. Note that the baseband signal generator 21 may have a built-in clock signal generator.

[0016] The modulation circuit 23 has a first input terminal to which the I-channel baseband signal output from the baseband signal generator 21 is input, a second input terminal to which the Q-channel baseband signal is input, and a carrier signal f ＲＦThe modulation circuit 23 has a third input terminal to which a carrier frequency (f ＲＦ ) a carrier signal f ＲＦ The frequency of the signal f is expressed as (f) for simplicity.

[0017] The components of the transmission signal output from the modulation circuit 23 can be plotted on a constellation diagram. The horizontal axis of the constellation diagram is the in-phase (I) axis, and the vertical axis is the quadrature (Q) axis. The distance from the origin of the constellation diagram indicates amplitude, and the angle indicates phase. That is, a signal at 0° on the I axis and a signal at 90° on the Q axis are out of phase by 90° (=π / 2). For example, in the case of QPSK, on ​​a circle centered on the origin of the constellation diagram, a signal at 45° represents "11," a signal at 135° represents "10," a signal at 225° represents "00," and a signal at 315° represents "01."

[0018] When modulating QPSK, the carrier signal f is modulated by the baseband signal for I channel. ＲＦ is modulated, and the carrier signal f is modulated by the baseband signal for the Q channel. ＲＦ are modulated, and these carrier signals f ＲＦ are added together and input to the subsequent transmission amplifier 25.

[0019] The carrier signal generator 24 generates a carrier signal f ＲＦ Carrier signal f ＲＦ The frequency band of the carrier signal generator 24 is higher than the frequency band of the baseband signal and has excellent signal propagation characteristics. The carrier signal generator 24 may have a built-in oscillator, but may also generate a carrier signal f in synchronization with a reference clock signal from an external oscillator. ＲＦ may occur.

[0020] The transmission amplifier 25 amplifies the transmission signal output from the modulation circuit 23 and transmits it to the transmission antenna 20. The transmission amplifier 25 may have a function as a band-pass filter that passes transmission signals in a designed frequency band, and may also include an equalizer that increases the intensity of high-frequency components that are attenuated during transmission.

[0021] The transmitting antenna 20 transmits a modulated carrier signal (transmission signal). When the transmission / reception system 100 is a wireless communication system, the transmitting device TX includes a transmitting antenna 20, and the receiving device RX includes a receiving antenna 10. When the transmission / reception system 100 performs wired communication using a conductive cable or an optical cable, these devices do not need to include antennas. When performing communication using an optical cable, a light-emitting diode or laser diode that converts the output signal of the transmitting amplifier 25 into an optical signal is used instead of the transmitting antenna 20, and a photodetector is used instead of the receiving antenna 10. More specifically, the receiving device RX includes an antenna (10) that receives a signal transmitted wirelessly from the transmitting device TX and inputs it to an input terminal of the receiving device. Alternatively, the receiving device RX may be configured to receive a signal transmitted via a wired line from the transmitting device TX and input it to an input terminal of the receiving device. Furthermore, when performing wired communication, communication can be performed using a single-ended or differential line, etc.

[0022] Alternatively, QAM (quadrature amplitude modulation) may be employed as the modulation method in the modulation circuit 23. QAM modulates at least two phases and at least two amplitudes of a carrier signal. When the number of amplitude levels to be modulated is four, the modulation circuit may incorporate a four-level amplitude level conversion circuit (digital-to-analog converter). In the case of QAM, not only the phase (angle on the constellation diagram) but also the amplitude (distance on the constellation diagram) is changed, so the state of the modulated carrier signal can be set at multiple coordinate positions on the constellation diagram (e.g., 16QAM, 64QAM).

[0023] It should be noted that other modulation methods involving phase modulation may also be employed as the modulation method in the modulation circuit 23. When BPSK (binary phase shift keying) is employed as the modulation method in the modulation circuit 23, a signal at 0° on the I axis on a circle centered at the origin of the constellation diagram can represent a "1" and a signal at 180° can represent a "0". In the case of BPSK, only one channel of the baseband signal is required to be input to the modulation circuit 23. As modulation methods, in addition to PSK (phase shift keying) which modulates the phase of a carrier signal, FSK (frequency shift keying) which modulates the frequency of a carrier signal, and ASK (amplitude shift keying) which modulates the amplitude of a carrier signal are known.

[0024] The receiver RX includes a first A / D converter 1, a second A / D converter 2, a phase detector 3, a D / A converter 4 (digital-to-analog converter (DAC)), a loop filter 5, a voltage-controlled oscillator 6 (VCO), and a π / 2 phase shifter 7. The receiver RX includes a receive antenna 10 that receives a transmit signal as a receive signal, and a receive amplifier 11 connected to the output terminal of the receive antenna 10. The analog receive signal output from the receive amplifier 11 is branched and input to the first A / D converter 1 and the second A / D converter 2, respectively.

[0025] The first A / D converter 1 has a first input terminal T11 to which an analog signal (received signal) is input. The first A / D converter 1 has a second input terminal T12 to which a first sampling clock signal is input. The first A / D converter 1 converts the input analog signal (voltage value) into a digital signal in synchronization with the timing of the first sampling clock signal. An example of the number of bits of the digital signal after converting one analog value is n bits (3≦n). For example, an analog voltage V whose voltage range is between V1 and V2 is Ａ When this analog voltage is input, a digital value D Ａ These conversions can be realized, for example, by inputting analog voltages to multiple comparators with different decision thresholds and outputting the digital outputs of each comparator as parallel signals. The output timing of the digital signals can be adjusted by a sampling clock signal.

[0026] The second A / D converter 2 has a first input terminal T21 to which an analog signal (received signal) is input. The second A / D converter 2 has a second input terminal T22 to which a second sampling clock signal is input. The second A / D converter 2 converts the input analog signal into a digital signal in synchronization with the timing of the second sampling clock signal. An example of the number of bits of the digital signal after converting one value is n bits (3≦n). The structure and operation of the second A / D converter 2 are the same as those of the first A / D converter 1.

[0027] The first sampling clock signal of the first A / D converter 1 and the second sampling clock signal of the second A / D converter 2 are generated from the output signal of a voltage-controlled oscillator 6. A π / 2 phase shifter 7 is interposed between the output terminal of the voltage-controlled oscillator 6 and the second input terminal T22 of the second A / D converter 2. Therefore, there is a phase difference of π / 2 between the first sampling clock signal and the second sampling clock signal. When QPSK is used as the phase modulation method, the output signal of the first A / D converter 1 corresponds to an I-channel signal, and the output signal of the second A / D converter 2 corresponds to a Q-channel signal. The digital signal after A / D conversion is output from a first output terminal OUT1 for the I-channel connected to the output terminal of the first A / D converter 1 and from a second output terminal OUT2 for the Q-channel connected to the output terminal of the second A / D converter 2. The I-channel digital signal and the Q-channel digital signal can also be converted into serial signals in a subsequent circuit.

[0028] The phase detector 3 is used to correct the timing of the sampling clock signals in the first A / D converter 1 and the second A / D converter 2 to the correct timing. In the case of QPSK modulation, the carrier signal is modulated with four phase shifts (e.g., 45°, 135°, 225°, and 315°) using a baseband signal. The phase detector 3 detects and outputs the phase difference between the output signal of the first A / D converter 1 and the output signal of the second A / D converter 2, smoothes this, and controls the oscillation frequency of the voltage-controlled oscillator 6, which determines the sampling timing, so as to reduce the phase difference. This control enables the A / D converter to demodulate the received signal without the need for a mixer.

[0029] More specifically, the phase and frequency can be synchronized with the modulated signal (received signal) input to the receiving device, and the QPSK modulated signal can be demodulated into a baseband signal.

[0030] Carrier signal f ＲＦ The received signal modulated by can be expressed as received signal RF(t) = I(t) sin(ωt) + Q(t) sin(ω / 4 + ωt), where t is a function of time. I(t) is the I-channel signal generated by the baseband signal generator of the transmitter, Q(t) is the Q-channel signal generated by the baseband signal generator of the transmitter, and ω is the angular frequency. By using the phase detector 3 to adjust the sampling phase of the received signal RF(t) to 45° and 90° with respect to the RF(t) signal, the received signal RF(t) can be discretized as follows: N is a natural number indicating the discretized value such as N1, N2, N3, ... NX, and f Ｓ is the frequency of the baseband signal, where sin(45°)=0.7.

[0031] That is, RF(N / f Ｓ ) = I(N / f Ｓ) × 0.7 + Q(N / fs) × 0.7. The first A / D converter 1 samples I(N / fs), and the second A / D converter 2 samples Q(N / fs), thereby restoring the I-channel and Q-channel baseband signals. I(N / fs) represents a discretized function of I(t), and Q(N / fs) represents a discretized function of Q(t). The discretization is performed with t = N / fs, and N = N1, N2, N3 ... NX (natural numbers).

[0032] Since a digital signal having phase difference information can be smoothed alone to generate a signal indicating the phase difference, it is possible to omit the D / A converter 4, but in this example, a D / A converter 4 is provided after the phase detector 3. In other words, this receiving device further includes a D / A converter 4 provided between the output terminal of the phase detector 3 and the input terminal of the voltage-controlled oscillator 6. The D / A converter 4 converts the digital signal having the phase difference into an analog signal, ensuring stable operation of the voltage-controlled oscillator 6, which receives analog input at the subsequent stage.

[0033] The loop filter 5 smoothes the signal output from the phase detector 3 or the D / A converter 4. The loop filter 5 also functions as a low-pass filter. If the output level of the loop filter 5 increases, the phase difference increases.

[0034] In this example, when the output level of the loop filter 5 increases and the detected phase difference increases, the voltage-controlled oscillator 6 increases the oscillation frequency. ＲＦ ' is the sampling frequency (f ＲＦ ').

[0035] Sampling frequency (f ＲＦ ') is the carrier signal f ＲＦ The carrier frequency (f ＲＦ When the number of A / D converters for the I channel or Q channel is one, the carrier frequency (f ＲＦ ) and sampling frequency (f ＲＦWhen N A / D converters in one channel are connected in parallel, the sampling frequency (f ＲＦ ') to the carrier frequency (f ＲＦ The first A / D converter 1 has a sampling frequency (f ＲＦ The first sampling clock signal f ＲＦ The second A / D converter 2 receives a second sampling clock signal f ′ having a phase difference (delay) of π / 2 with respect to the first sampling clock signal. ＲＦ ' is given.

[0036] As described above, the receiving device RX includes a first A / D converter 1 connected to an input terminal, a second A / D converter 2 connected to an input terminal, a phase detector 3 having an input terminal connected to a first output terminal of the first A / D converter 1 and a second output terminal of the second A / D converter 2, a loop filter 5 connected to the output terminal of the phase detector 3, and a voltage-controlled oscillator 6 having an input terminal connected to the output terminal of the loop filter 5. The first sampling clock signal of the first A / D converter 1 and the second sampling clock signal of the second A / D converter 2 are generated from the output signal of the voltage-controlled oscillator 6 and have a phase difference of π / 2.

[0037] This receiving device achieves demodulation using an A / D converter instead of a mixer, allowing for a smaller circuit size and reduced power consumption. For example, if an A / D converter with a sampling frequency of 100 Gbps is used in this receiving device, a receiving device with a power consumption of 1 W or less can be configured. On the other hand, if a conventional receiving device were to perform the same processing using chips with sampling frequencies of 0.052 Gbps to 3.2 Gbps (such as the AD6676 (manufactured by Analog Devices), AD6688 (manufactured by Analog Devices), or HSP50210 (manufactured by Renesas Electronics)), the number of components, such as a digital signal processor, would increase, requiring a power consumption of 40 W to 500 W. Conversely, the receiving device disclosed herein would require fewer components than conventional devices and allow for a smaller circuit size.

[0038] FIG. 2 is a timing chart showing a received signal (Rx) (FIG. 2(a)), A / D converted data of the I channel (FIG. 2(b)), A / D converted data of the Q channel (FIG. 2(c)), data of the I channel baseband signal (FIG. 2(d)), and data of the Q channel baseband signal (FIG. 2(e)).

[0039] The received signal (Rx) is generated by modulating a carrier signal in the transmitter (Fig. 2(a)), and the modulation method is QPSK. The A / D converter samples each 1-bit baseband signal multiple times (oversampling). The vertical axis of Fig. 2(a) represents amplitude, and the horizontal axis represents time (ps).

[0040] The sampling timing in the first A / D converter 1 (I channel) is at four phase positions SI0, SI1, SI2, and SI3 of the carrier signal within one bit, as shown in Figures 2(a) and 2(b). The oversampled data can be appropriately thinned out before output, allowing the output frequency to be lowered.

[0041] The sampling timing in the second A / D converter 2 (Q channel) is at four phase positions SQ0, SQ1, SQ2, and SQ3 of the carrier signal within one bit, as shown in Figures 2(a) and 2(c). The oversampled data can be appropriately thinned out before output, allowing the output frequency to be lowered.

[0042] For example, when N = 4, four sampling points are set for one UI (unit interval) in each channel. That is, the phases of the sampling timings are SI0 = 45°, SQ0 = 135°, SI1 = 45°, SQ1 = 135°, SI2 = 45°, SQ2 = 135°, SI3 = 45°, and SQ3 = 135°. Figure 2(a) shows these phase relationships. There is a phase difference of 360° (the phase difference of one cycle) between the sampling timing SI0 and the sampling timing SI1. By omitting the data with phases of 225° and 315°, the number of samples can be reduced, thereby reducing power consumption.

[0043] When N=4, after the above sampling, the sampled values ​​are input to a decimation filter (see FIG. 11), and one piece of data I(N / fs) and Q(N / fs) can be extracted from the multiple sampled values ​​in each channel.

[0044] When N = 2, two sampling points are set for one UI in each channel. That is, the phases of the sampling timing are SI0 = 45°, SQ0 = 135°, SI1 = 45°, and SQ1 = 135°. In this case, as in the case of N = 4, after sampling, the sampled values ​​are input to a decimation filter (see FIG. 11), and one piece of data I(N / fs) and Q(N / fs) can be extracted from the multiple sampled values ​​in each channel.

[0045] Similarly, when N = 8, eight sampling points are set for one UI in each channel. The phases of the sampling points in the I channel can be SI0, SI1, SI2, SI3, SI4, SI5, SI6, and SI7, and the phases of the sampling points in the Q channel can be SQ0, SQ1, SQ2, SQ3, SQ4, SQ5, SQ6, and SQ7. The phases of the sampling points in the I channel can be 45°, and the phases of the sampling points in the Q channel can be 135°. In this case, as in the case of N = 4, after sampling, the sampled values ​​are input to a decimation filter (see FIG. 11), and one piece of data I(N / fs) and Q(N / fs) can be extracted from the multiple sampled values ​​in each channel.

[0046] On the other hand, sampling when the phase of the carrier signal is 45°, 135°, 225°, and 315° has the advantage of increasing the number of samples, thereby improving phase control accuracy. This technique can reduce the data error rate and handle inputs with large distortion. In the example of FIG. 2( a), sampling is performed at phases of 45° and 135°, but sampling for A / D conversion can also be performed at 225° and 315°. For example, when N = 4, four sampling points (45°, 135°, 225°, and 315°) are set for one UI in each channel. The phases of the sampling points in the I channel can be SI0, SI1, SI2, SI3, SI4, SI5, SI6, and SI7, and the phases of the sampling points in the Q channel can be SQ0, SQ1, SQ2, SQ3, SQ4, SQ5, SQ6, and SQ7.

[0047] For example, sampling may be performed with SI0 = 45°, SQ0 = 135°, SI1 = 225°, SQ1 = 315°, S2 = 45°, SQ2 = 135°, SI3 = 225°, SQ3 = 315°, SI4 = 45°, SQ4 = 135°, SI5 = 225°, SQ5 = 315°, S6 = 45°, SQ6 = 135°, SI7 = 225°, SQ7 = 315°.

[0048] In this four-point sampling, when N = 8, four sampling points (45°, 135°, 225°, and 315°) are set for one UI in each channel. The phases of the sampling points in the I channel can be SI0, SI1, SI2, SI3, SI4, SI5, SI6, SI7, SI8, SI9, SI10, SI11, SI12, SI13, SI14, and SI15, and the phases of the sampling points in the Q channel can be SQ0, SQ1, SQ2, SQ3, SQ4, SQ5, SQ6, SQ7, SQ8, SQ9, SQ10, SQ11, SQ12, SQ13, SQ14, and SQ15.

[0049] In this four-point sampling, when N = 2, four sampling points (45°, 135°, 225°, 315°) are set for one UI in each channel. The phases of the sampling points in the I channel can be SI0, SI1, SI2, and SI3, and the phases of the sampling points in the Q channel can be SQ0, SQ1, SQ2, and SQ3.

[0050] In either case of sampling, after sampling, the sampled values ​​are input to a decimation filter (see FIG. 11), and one piece of data I(N / fs) and Q(N / fs) can be extracted from the multiple sampled values ​​in each channel.

[0051] The amplitude fluctuates in the positive and negative directions with the 0 point as the reference. If the converted data points furthest from the 0 point are SI2 (or SQ2), the time interval Ts between them in the same bit (FIG. 2(d) and FIG. 2(e)) is expressed as the carrier frequency (f ＲＦ ) period (T ＲＦ ) times (N is a natural number). Ｓ The data of the baseband signal (BB) can be reproduced by the amplitude level in the signal.

[0052] FIG. 3 is a block diagram of the receiving device.

[0053] The receiving device RX uses a 3-bit A / D converter and performs addition and subtraction of digital signal outputs to detect the phase difference between the output signals of the first and second A / D converters. The first A / D converter 1 outputs a 3-bit signal (DOI2, DOI1, DOI0) corresponding to the level of the input signal. Each bit signal (DOI2, DOI1, DOI0) indicates 0 or 1. The most significant bit (DOI2) indicates the sign of a numerical value. The second A / D converter 2 outputs a 3-bit signal (DOQ2, DOQ1, DOQ0) corresponding to the level of the input signal. Each bit signal (DOQ2, DOQ1, DOQ0) indicates 0 or 1. The most significant bit (DOQ2) indicates the sign of a numerical value. A sample and hold circuit may be arranged upstream of the A / D converter.

[0054] The phase detector 3 includes a first XOR circuit 31, a second XOR circuit 32, and a multiplexer 33. XOR stands for exclusive OR. More specifically, the phase detector 3 receives the first digital value output from the first A / D converter 1 and the second digital value output from the second A / D converter 2 as inputs, and includes a multiplexer 33 that outputs a digital value correlated to the phase difference between the signals indicated by the first and second digital values. The multiplexer 33 is a subtractor that receives three bits of an I channel and three bits of a Q channel as inputs. The sign of the I channel input signal to the multiplexer 33 is negative (-), and the sign of the Q channel input signal is positive (+). This configuration has the advantage of being less susceptible to output delays because the comparison is performed using digital processing.

[0055] More specifically, in this example, the most significant bit of the A / D converter is coded to indicate positive or negative, and the phase detector 3 implements a Costas loop operation using digital circuits (two XOR circuits and an adder). The coding of the A / D converter is also simplified. This digital circuit can also be implemented using 50 gate circuits. When implementing a loop including a phase detector using analog circuits, a comparator structure is considered, but in this case, the comparator delay must be compensated. In this example, the phase detector is implemented using a digital circuit, eliminating the need for such a delay compensation mechanism and improving the accuracy of phase comparison. Furthermore, when implemented using analog circuits, the comparator requires high gain and a high frequency bandwidth. The digital circuit in this example can implement a comparator implemented using analog circuits simply by determining whether the most significant bit is 0 or 1. For example, if the most significant bit is "1," it is treated as +1, and if it is "0," it is treated as -1, and input to a subsequent multiplication circuit (inverting the most significant bit). Therefore, a comparator is not required, which reduces the difficulty of design and reduces power consumption.

[0056] FIG. 4 is a diagram showing the relationship between the input value (Val.) to the A / D converter and the digital value (3 bits) after A / D conversion.

[0057] The digital value is determined according to the value (Val.) of the input signal. The unit of the value of the input signal is, for example, volts, and an example is shown in which the input signal has an amplitude of about −3.5 V to +3.5 V.

[0058] For example, in the receiving device of Figure 3, assume that a voltage of 2.5V is input to A / D converter 1 and a voltage of -1.5V is input to second A / D converter 2. In this case, first A / D converter 1 outputs (0,1,0), and second A / D converter 2 outputs (1,0,1). Since (0,1) is input to first XOR circuit 31, it outputs "1", and since (1,0) is input to second XOR circuit 32, it outputs "1". (1,1,0) is input to the negative addition terminal of multiplexer 33, and (1,0,1) is input to the positive addition terminal. The sum of these values ​​is -1.

[0059] Therefore, the D / A converter 4 outputs a voltage equivalent to this added value as the phase difference. If sampling in the A / D conversion can be performed so that the phase difference between the I channel and the Q channel is eliminated, this means that the condition for restoring the modulated baseband signal is met.

[0060] The received signal of the receiving device in FIG. 3 is generated as a transmission signal in the transmitting device, and this received signal is a carrier signal f ＲＦ The baseband signal f Ｓ The baseband signal f can be generated by phase shift keying (PSK) with Ｓ is a non-return-to-zero (NRZ) signal, and the phase detector 3 is a phase detector that corresponds to a received signal that has been phase-shift keyed. That is, the phase detector 3 shown in FIG. 3 can be used to demodulate a received signal that has been QPSK modulated.

[0061] The received signal of the receiver RX is generated as a transmission signal in the transmitter, and this received signal is a carrier signal f ＲＦ The baseband signal f Ｓ The baseband signal f may be generated by quadrature amplitude modulation (QAM). Ｓ Alternatively, the phase detector 3 may be generated by pulse amplitude modulation (PAM) at n levels, where n is an integer greater than or equal to four (PAM4). In this case, the received signal that has been quadrature phase amplitude modulated (QAM) is demodulated using the A / D converter and phase detector described above. In this case, the structure of the phase detector 3 can be adapted to operate in the case of QAM by placing a data selector in the preceding stage (see FIG. 19). In other words, the phase detector 3 can also detect the phase difference between received signals that have been modulated by QAM and PAM4.

[0062] FIG. 5 is a block diagram of a receiving device.

[0063] The receiving device RX uses a 5-bit A / D converter and detects the phase difference between the first and second A / D converters by performing addition and subtraction of digital signal outputs. The first A / D converter 1 outputs a 5-bit signal (DOI4, DOI3, DOI2, DOI1, DOI0) corresponding to the level of the input signal. Each bit signal (DOI4, DOI3, DOI2, DOI1, DOI0) indicates a 0 or a 1. The most significant bit (DOI4) indicates the sign of a numerical value. The second A / D converter 2 outputs a 5-bit signal (DOQ4, DOQ3, DOQ2, DOQ1, DOQ0) corresponding to the level of the input signal. Each bit signal (DOQ4, DOQ3, DOQ2, DOQ1, DOQ0) indicates a 0 or a 1. The most significant bit (DOQ4) indicates the sign of a numerical value. A sample and hold circuit may be placed before the A / D converter. The receiver RX of this example is a 5-bit version of the 3-bit receiver described above, and apart from this, its structure and operation are the same as those described above.

[0064] FIG. 6 is a diagram showing the relationship between the input value (Val.) to the A / D converter and the digital value (5 bits) after A / D conversion.

[0065] The digital value is determined according to the value (Val.) of the input signal. The unit of the input signal value is, for example, volts, and an example is shown in which the input signal has an amplitude of approximately -15.5 V to +15.5 V. The operation of the receiving device in the case of 5 bits is the same as that of the receiving device in the case of 3 bits.

[0066] FIG. 7 is a block diagram of a D / A converter and a loop filter in the receiving device.

[0067] Illustrated is a specific example of a D / A converter 4 and a loop filter 5 arranged downstream of the phase detector 3. The D / A converter 4 includes a decoder 40 to which the output signal of the phase detector 3 is input, and a plurality of first function circuits B1 connected to the decoder 40. Each first function circuit B1 includes a first charge pump 41 and a second charge pump 42 to which the output signal of the decoder 40 is input. These charge pumps are connected in series, and their connection point (node) is connected to the input terminal (node ​​VC) of a voltage-controlled oscillator 6. The input terminal of the first charge pump 41 is connected to the input terminal of the voltage-controlled oscillator 6 via a first amplifier 43 and a third capacitor 53, which provide an inverted output. The input terminal of the second charge pump 42 is connected to the input terminal of the voltage-controlled oscillator 6 via a second amplifier 44 and a fourth capacitor 54.

[0068] The loop filter 5 includes a resistor 55 having a first end (node ​​VC) connected to the output terminal of the D / A converter 4, a first capacitor 51 connected between a second end of the resistor 55 and a fixed potential (such as ground potential), and a second capacitor 52 connected between the first end of the resistor 55 and the fixed potential (such as ground potential). Second function circuits B2 are connected between the node VC of the loop filter 5 and each of the first function circuits B1.

[0069] The second functional circuit B2 includes a third capacitor 53 connected between a first end (node ​​VC) of the resistor 55 and the output terminal of the first amplifier 43 in the first functional circuit B1, and a fourth capacitor 54 connected between the first end (node ​​VC) of the resistor 55 and the output terminal of the second amplifier 44 in the first functional circuit B1. The loop filter 5 having this structure can have wideband characteristics and can be used with both digital and analog circuits.

[0070] More specifically, when processing N bits (N=3), the digital output of the multiplexer 33 in the preceding stage of the D / A converter 4 is a signal indicating +3, +2, +1, 0, -1, -2, and -3. To process these ±3 values, the D / A converter 4 has three first function circuits B1 connected in parallel, and the loop filter 5 has three second function circuits B2 connected in parallel. The D / A converter 4 includes a decoder 40 in the preceding stage of the first function circuit B1.

[0071] When the digital output of the multiplexer 33 indicates 3, the decoder 40 operates to output a control output (e.g., (second charge pump ON, second charge pump ON, second charge pump ON)) that operates the second charge pump 42 and the second amplifier 44 in the first (DAC0) first function circuit B1, the second (DAC1) first function circuit B1, and the third (DAC2) first function circuit B1.

[0072] When the digital output of the multiplexer 33 indicates 2, the decoder 40 operates to operate the second charge pump 42 and the second amplifier 44 in the first (DAC0) first functional circuit B1 and the second (DAC1) first functional circuit B1, and to output a control output (e.g., (second charge pump ON, second charge pump ON, 0)) that does not operate the charge pump and amplifier in the third (DAC2) first functional circuit B1.

[0073] When the digital output of the multiplexer 33 indicates 1, the decoder 40 operates to operate the second charge pump 42 and the second amplifier 44 in the first (DAC0) first function circuit B1, and to output a control output (e.g., (second charge pump ON, 0, 0)) that does not operate the charge pump and amplifier in the second (DAC1) and third (DAC2) first function circuits B1.

[0074] When the digital output of the multiplexer 33 indicates 0, the decoder 40 operates to output a control output (e.g., (0,0,0)) that disables all the charge pumps and amplifiers.

[0075] When the digital output of the multiplexer 33 indicates -1, the decoder 40 operates to operate the first charge pump 41 and the first amplifier 43 in the first (DAC0) first function circuit B1, and to output a control output (e.g., (first charge pump ON, 0, 0)) that does not operate the charge pumps and amplifiers in the second (DAC1) and third (DAC2) first function circuits B1.

[0076] When the digital output of the multiplexer 33 indicates -2, the decoder 40 operates to operate the first charge pump 41 and the first amplifier 43 in the first (DAC0) first function circuit B1 and the second (DAC1) first function circuit B1, and to output a control output (e.g., (first charge pump ON, first charge pump ON, 0)) that does not operate the charge pump and amplifier in the third (DAC2) first function circuit B1.

[0077] When the digital output of the multiplexer 33 indicates 3, the decoder 40 operates to output a control output (e.g., (first charge pump ON, first charge pump ON, first charge pump ON)) that operates the first charge pump 41 and the first amplifier 43 in the first (DAC0) first function circuit B1, the second (DAC1) first function circuit B1, and the third (DAC2) first function circuit B1.

[0078] When processing N bits, the number of first function circuits and the number of second function circuits are N, and these circuits are connected in parallel. The first charge pump 41 draws current in conjunction with the output of the decoder 40, and the second charge pump 42 discharges current in conjunction with the output of the decoder 40. The output current of the first function circuit B1 is input to the loop filter 5. A voltage is generated at the node VC by the resistor 55 in accordance with the charge pump current. As the first (DAC0) to third (DAC2) first function circuits B1 operate, the current flowing into the loop filter 5 increases or decreases, and the voltage across the resistor 55 changes in accordance with the output value of the multiplexer 33.

[0079] The first amplifier 43 is connected to a third capacitor 53, and the second amplifier 44 is connected to a fourth capacitor 54. For example, when the output of the multiplexer 33 is 1, the first function circuit B1 (DAC0) operates, and a voltage corresponding to the capacitance ratio of the fourth capacitor 54 to the second capacitor 52 is generated at the node VC. Note that the first amplifier 43 is an inverting circuit, and the second amplifier 44 is a buffer circuit, and a voltage of (capacity of the fourth capacitor 54 / capacity of the second capacitor 52 × power supply voltage) × number of parallel connections N is applied to the node VC according to the output of the multiplexer 33.

[0080] FIG. 8 is a block diagram of a receiving device.

[0081] The receiving device RX is the receiving device shown in FIG. 7 with the addition of a first phase interpolator 71 and a second phase interpolator 72. The second phase interpolator 72 also functions as a π / 2 phase shifter. A downconverter 73, which reduces the frequency, is connected to the output terminal of the voltage-controlled oscillator 6. The downconverter 73 reduces the input signal frequency by, for example, one-quarter. An example of the output signal frequency of the voltage-controlled oscillator 6 is 20 GHz. An example of the frequency of the output signal of the downconverter 73 is 5 GHz. The output signal of the downconverter 73 is input to the sampling clock signal input terminals of the first A / D converter 1 and the second A / D converter 2 via the first phase interpolator 71 and the second phase interpolator 72, respectively.

[0082] An example of the frequency of the input signal to the A / D converter (the received signal or its intermediate frequency signal) is 20 GHz. The sampling clock signals of the first A / D converter 1 and the second A / D converter 2 can be set to 5 GHz. The number of first A / D converters 1 can be multiple, and the multiple first A / D converters 1 can be connected in parallel. The number of first A / D converters 1 can also be eight, and an eight-phase input signal can be converted. Similarly, the number of second A / D converters 2 can be multiple, and the multiple second A / D converters 2 can be connected in parallel. The number of second A / D converters 2 can also be eight, and an eight-phase input signal can be converted. Note that a power splitter can be placed in front of the A / D converter.

[0083] An aligner can be arranged after each A / D converter. The aligner output can be eight 3-bit outputs. A plurality of (e.g., eight) phase detectors 3 can be arranged for each of the eight parallel paths.

[0084] FIG. 9 is a block diagram of a transmission and reception system.

[0085] The received signal of the receiver RX has a carrier frequency (f ＲＦ ) carrier signal f ＲＦ , the baseband frequency (f Ｓ ) baseband signal f Ｓ where N is a natural number and f ＲＦ = N × f Ｓ There are several clock generation methods that satisfy these relationships. For example, in the transmitter TX, the reference clock generator 22 and the carrier signal generator 24 are supplied with a reference clock signal f ｒｅｆ The reference frequency generated by the reference clock generator 22 is input as a baseband frequency (f Ｓ ), the carrier signal generator 24 generates the reference clock signal f ｒｅｆ (∝f Ｓ ) with a frequency N times higher ＲＦ In this example, the reference frequency (f Ｓ ) is the baseband frequency (f Ｓ ) which is proportional to the data rate of the baseband signal input to the modulation circuit 23.

[0086] When this structure is used, the timing of the sampling clock signal of the first A / D converter 1 of the receiving device RX coincides with the above-mentioned four phases (phases SI0, SI1, SI2, SI3 in FIG. 2). Also, the timing of the sampling clock signal of the second A / D converter 2 coincides with the above-mentioned four phases (phases SQ0, SQ1, SQ2, SQ3 in FIG. 2). ＲＦ The frequency (f ＲＦ ) and the frequency of the sampling clock signal (f ＲＦ ‘In this configuration, demodulation can be performed by transmitting a signal that satisfies the above conditions, even if a circuit such as a CDR (clock and recovery) circuit is not provided after the A / D converter.

[0087] FIG. 10 is a block diagram of a transmitting device.

[0088] In the case of QPSK modulation, an input signal such as a video signal is sampled in a baseband signal generator 21 in synchronization with a baseband signal fs output from a reference clock generator 22, and is output from two channels as NRZ (non-return to zero) digital signals. A first output signal I(t) of the I channel and a second output signal Q(t) of the Q channel are both input to a modulation circuit 23.

[0089] The baseband signal generator 21 may include an encoder that encodes the input signal, a circuit that adds an error correction code, a signal generator that serializes the input signal and generates I-channel and Q-channel signals, and the like.

[0090] The modulation circuit 23 receives the first output signal I(t) and the carrier signal f ＲＦ In the Q channel, the second output signal Q(t) and the carrier signal f ＲＦ is input. Carrier signal f ＲＦ is the reference clock signal f ｒｅｆ A carrier frequency (f ＲＦ ) and outputs the reference clock signal f ｒｅｆ is input to the reference clock generator 22, but the reference clock signal f ｒｅｆ The frequency of the reference clock signal f Ｓ If the frequency of the carrier wave is equal to the frequency of ＲＦ = N × f Ｓ The first output signal I(t) and the carrier signal f ＲＦ is input to the first modulation unit 231 (multiplier). The second output signal Q(t) and the carrier signal f ＲＦ are input to a second modulation section 232 (multiplier). The output signals of the first modulation section 231 and the second modulation section 232 are input to an adder 233, which outputs a composite signal of these.

[0091] The carrier signal f input to the second modulation section 232 ＲＦ The phase of the carrier signal f input to the first modulation unit 231 is shifted by a π / 2 phase shifter 234. ＲＦ The signal is shifted in phase by π / 2 from the phase of the input signal, and is subjected to quadrature modulation in the adder 233. The output signal of the adder 233 is input to the transmitting antenna 20 via the transmitting amplifier 25.

[0092] The baseband signal generator 21 may include, as necessary, a differential encoder for performing data conversion and a filter for limiting the bandwidth of the baseband signal. Alternatively, a differential encoder may be disposed downstream of a serial-to-parallel converter that converts the input signal into a parallel digital signal, and the differential encoder may perform data conversion into the relative phase change between adjacent bits on the receiving device side. In this example, the baseband signal generator 21 outputs a bit pattern of an NRZ signal.

[0093] When performing QAM modulation, an analog signal having n levels is generated in the I channel, and an analog signal having n levels is generated in the Q channel. The first output signal I(t) and the second output signal Q(t) can be PAMn (n is an integer equal to or greater than 4). In this case, n ２ QAM modulation (e.g., 16QAM) is performed.

[0094] FIG. 11 is a block diagram of a transmission and reception system.

[0095] In this example, a decimation filter is arranged after the A / D converter in the receiver RX in the transmission / reception system shown in Fig. 9 etc. That is, the receiver RX includes a first decimation filter DF1 arranged after the first A / D converter 1 and a second decimation filter DF2 arranged after the second A / D converter 2.

[0096] Oversampled digital signals are output from the first A / D converter 1 and the second A / D converter 2. The decimation filters periodically thin out and extract data from the oversampled digital signals. The first decimation filter DF1 periodically samples and outputs the oversampled digital signal output from the first A / D converter 1. The second decimation filter DF2 periodically samples and outputs the oversampled digital signal output from the second A / D converter 2. The first decimation filter DF1 outputs a demodulated I-channel baseband signal, and the second decimation filter DF2 outputs a demodulated Q-channel baseband signal.

[0097] In this structure, there is no need to use a conventional CDR circuit, so the circuit scale can be reduced and power consumption can be reduced.

[0098] FIG. 12 is a block diagram of a transmission and reception system.

[0099] In this example, a pattern checker is placed after the decimation filter in the receiving device RX in the transmitting / receiving system shown in Fig. 11. That is, the receiving device RX includes a first pattern checker PC1 and a second pattern checker PC2.

[0100] The first pattern checker PC1 is provided after the first decimation filter DF1, detects the error rate of the input signal, and instructs the first decimation filter DF1 to perform sampling at the sampling timing that results in the smallest detected error rate. This structure enables demodulation with a reduced error rate.

[0101] The second pattern checker PC2 is provided after the second decimation filter DF2, detects the error rate of the input signal, and instructs the second decimation filter DF2 to perform sampling at the sampling timing that results in the smallest detected error rate. This structure enables demodulation with a reduced error rate.

[0102] FIG. 13 is a circuit diagram of an example of a pattern checker.

[0103] An example pattern checker PC includes a first flip-flop F1, a second flip-flop F2, a third flip-flop F3, a fourth flip-flop F4, a fifth flip-flop F5, a sixth flip-flop F6, and a seventh flip-flop F7 connected in series. An input signal (Input) is input to the D terminal of the first flip-flop F1 and output from the Q terminal. The output of the flip-flop group is output from the seventh flip-flop F7 in the final stage and input to an XOR circuit 81 together with the input signal. The output of the XOR circuit 81 is input to a NOT circuit 82, and an output signal (OUT) is output from the output terminal. A clock signal CLK is also input to each flip-flop. Such a pattern checker can be used when the input signal is a serial signal.

[0104] This pattern checker can output an output signal that detects a specific error pattern when it is input. If an error is detected, the detection result is fed back to the decimation filter, and the sampling timing of the decimation filter is changed to adjust the sampling timing so as to minimize the error occurrence rate. For example, if there are four sampling points in one UI, the sampled data with the lowest error occurrence rate (one of SI0, SI1, SI2, and SI3) and the sampled data with the lowest error occurrence rate (one of SQ0, SQ1, SQ2, and SQ3) are selected. Similarly, if there are eight sampling points in one UI, one of the I-channel sampled data (SI0 to SI7) and one of the Q-channel sampled data (SQ0 to SQ7) are selected.

[0105] FIG. 14 is a block diagram of a transmission and reception system.

[0106] In this example, in the transmission / reception system shown in Fig. 9 etc., a mode selection circuit is arranged after the A / D converter in the receiver RX. That is, the receiver RX includes a first mode selection circuit MS1 and a second mode selection circuit MS2. With this structure, the baseband signal can be demodulated in the same way as when a decimation filter is used.

[0107] The first most frequent value selection circuit MS1 is provided at the subsequent stage of the first A / D converter 1, and selects and outputs the most numerous value among the multiple values ​​represented by n consecutive sampled data within a period corresponding to one bit.

[0108] The second most frequent value selection circuit MS2 is provided at the subsequent stage of the second A / D converter 2, and selects and outputs the most frequent value from among the multiple values ​​represented by n consecutive sampled data within a period equivalent to one bit.

[0109] 15 is a diagram for explaining the logic of the operation of the mode selection circuit. The mode selection circuit is composed of logic circuits that perform the following logical operations:

[0110] Suppose that within one unit interval (UI), for example, the baseband signal values ​​(BBI) sampled in the I channel of the receiving device are (-1, 3, 3, 3) (the leftmost block in FIG. 15(a)). For example, the values ​​oversampled within one bit in FIG. 2 (FIG. 2(b)) correspond to these values. In this case, values ​​greater than 0 are determined as 1, and values ​​less than or equal to 0 are determined as 0, and a set of digital values ​​D(BBI) (0, 1, 1, 1) is created (FIG. 15(b)). Since the most frequently occurring value in this set of digital values ​​is "1," "1" is selected as the mode (mod(BBI)) (FIG. 15(c)).

[0111] Similarly, within one unit interval (UI), for example, suppose the value (BBQ) of the baseband signal sampled in the Q channel of the receiving device is (1, -3, -3, -3) (the leftmost block in FIG. 15(d)). For example, the values ​​oversampled within one bit in FIG. 2 (FIG. 2(c)) correspond to these values. In this case, values ​​greater than 0 are determined to be 1, and values ​​less than or equal to 0 are determined to be 0, and a set of digital values ​​D(BBQ) (1, 0, 0, 0) is created (FIG. 15(e)). Since the most frequently occurring value in this set of digital values ​​is "0," "0" is selected as the mode (mod(BBQ)) (FIG. 15(f)).

[0112] FIG. 16 is a block diagram of a transmission and reception system.

[0113] In this example, in the transmission / reception system shown in Figure 11, a waveform shaping circuit is arranged after the A / D converter in the receiver RX. That is, the receiver RX includes a first waveform shaping circuit WS1 and a second waveform shaping circuit WS2. The first waveform shaping circuit WS1 is arranged between the first A / D converter 1 and the first decimation filter DF1. The second waveform shaping circuit WS2 is arranged between the second A / D converter 2 and the second decimation filter DF2.

[0114] If the waveform of the digital signal output from the A / D converter is attenuated and distorted, it can be corrected by a waveform shaping circuit. For example, a comparator can be used to convert the distorted waveform into a square wave and reshape it. Alternatively, an FIR (finite impulse response) filter and / or an IIR (infinite impulse response) filter can be used to reshape the waveform of the digital signal. Other filters that perform distortion correction can also be used.

[0115] FIG. 17 is a block diagram of a transmission and reception system.

[0116] In this example, in the transmission / reception system shown in Fig. 11, a superheterodyne circuit is arranged in the front stage of the A / D converter in the receiver RX. That is, the receiver RZ is provided with a first superheterodyne circuit including a first mixer MX1 ​​and a first multiplier MP1. The first mixer MX1 ​​of the first superheterodyne circuit is provided in the front stage of the input terminals of the first A / D converter 1 and the second A / D converter 2. The first mixer MX1 ​​mixes a high-frequency signal received by the receiver RX from the receive antenna 10 and a first local signal f output from the first multiplier MP1. １ The first local signal f １ is the output signal (f ＲＦ ') by the first multiplier MP1, and M １ is a natural number, and this output signal (f ＲＦ ') frequency of M １ Double frequency (f １ = M １ ×f ＲＦ ').

[0117] By using the superheterodyne circuit, the receiver RX reduces the frequency of the high frequency signal received from the receiving antenna 10 to a first intermediate frequency (IF １ ) signal is generated and input to the first and second A / D converters. By lowering the frequency, the sampling clock frequency in the A / D converter can be lowered. ＲＦ The frequency of ＲＦ '=N×fs can be satisfied.

[0118] FIG. 18 is a block diagram of a transmission and reception system.

[0119] In this example, in the transmission / reception system shown in Fig. 15, a plurality of superheterodyne circuits are arranged in front of the A / D converter in the receiver RX. That is, in the receiver RX, a high frequency signal received by the receiver RX and a second local signal f are connected in front of a first superheterodyne circuit (first mixer MX1, first multiplier MP1). ２ The second superheterodyne circuit receives the second local signal f２ is the output signal (f ＲＦ ') by the second multiplier MP2, and M ２ is a natural number, and this output signal (f ＲＦ ') frequency of M ２ The second magnification M ２ is the first magnification M １ The second multiplier MP2 can be set to the output frequency (f １ ) to M ２ The receiver RX may be configured to multiply the number n (n is 2 or more) of superheterodyne circuits (an n-th mixer MXn, an n-th multiplier MP ｎ ) can be provided.

[0120] By using a plurality of superheterodyne circuits, the receiver RX can reduce the frequency of the high frequency signal received from the receiving antenna 10 to the nth intermediate frequency (IF ｎ ) signal is generated and input to the first and second A / D converters. By lowering the frequency, the sampling clock frequency in the A / D converter can be lowered. ＲＦ The frequency of ＲＦ '=N×fs can be satisfied.

[0121] FIG. 19 is a block diagram of a transmission and reception system.

[0122] In this example, a selector DS is arranged before the phase detector 3 in the transmission / reception system of Figure 11. This receiving device can be used to decode a QAM-modulated received signal. The selector DS receives the output signals of the first A / D converter 1 and the second A / D converter 2. The selector DS selects and outputs specific components in the constellation diagram from these output signals. I-channel and Q-channel signals having specific components are input to the phase detector 3. This method makes it possible to modulate a QAM-modulated received signal.

[0123] FIG. 20 is a diagram showing a signal space diagram.

[0124] In the signal space diagram of the I and Q channels, if the I channel component varies from IA to IB and the Q channel component varies from QA to QB, the entire region including these components is designated as R0. The selector DS can select and output signal component data within specific regions R11, R12, R21, R22, R31, R32, R41, and R42 in the diagram. Within each specific region, oversampled data is located in a matrix, for example, 8 x 8. When the output of the A / D converter is represented in the signal space diagram of the I and Q axes, each of the specific regions has an area 1 / 16 of the entire region R0, and the total area of ​​the specific regions (8 regions) is 1 / 2 of the entire region. By using the selector DS to input signals within the specific regions to the phase detector, the QPSK phase detector can be used to demodulate received signals modulated with 16QAM. Note that the selector DS can output 0 when data outside the specific regions is input. This signal space diagram is divided into 16 regions, but the regions into which it is divided can be set arbitrarily. The selector DS can be configured using a filter.

[0125] If the received signal is BPSK modulated, it can be demodulated using the same receiver used for demodulating QPSK. The data on the I and Q channels will be the same.

[0126] 21A and 21B are diagrams showing the time structure of a received signal, where FIG. 21A shows the signal structure and FIG. 21B shows the frequency structure.

[0127] Figure 21(a) shows the structure of a baseband signal. The baseband signal transmits a preamble pattern (a signal for frequency learning) between times t1 and t2, and transmits a random (or information-containing) signal between times t2 and t3. After transmission of the random signal ends, the baseband signal transmits a preamble again between times t3 and t4. The frequency A of the carrier signal during the transmission of the preamble pattern (Figure 21(b)) is, for example, a sine wave of 50 GHz, and the frequency B of the carrier signal during transmission of the random signal modulated by QPSK (Figure 21(b)) has a center frequency of 50 GHz and a data rate of 24.9 Gbps.

[0128] In this receiving device, the received signal input to the input terminals of the first A / D converter 1 and the second A / D converter 2 periodically contains a preamble pattern, and when the preamble pattern is received, the phases of the first sampling clock signal and the second sampling clock signal can be corrected based on the received preamble pattern. For example, a preamble pattern detection circuit is disposed inside the receiving device (for example, disposed at a stage subsequent to the A / D converter), and performs a phase synchronization operation during the period when the preamble pattern is input, and restores the transmitted data during the other periods. The frequency (fs) of the baseband signal and the frequency (f) of the local signal (the signal output by the voltage-controlled oscillator) are synchronized. ＲＦ If the baseband signal frequency (fs) and the local signal frequency (fs') are not an integer multiple, the phase will be shifted by the remainder of these frequencies. If the phase shift exceeds half the length of one bit of the baseband signal (0.5 UI), the communication error rate will increase. Before the error rate increases, the phase is resynchronized using the preamble pattern, and then the received signal is restored. This makes communication possible even if the baseband signal frequency (fs) and the local signal frequency are not an integer multiple.

[0129] FIG. 22 is a block diagram of a transmission and reception system.

[0130] The receiver RX in this transmission / reception system is the receiver RX shown in FIG. 9 with the addition of a preamble detector PAD, and is capable of detecting the preamble pattern described above. The preamble detector PAD is disposed after the first A / D converter 1 and the second A / D converter 2. When the preamble detector PAD detects that the output signals of the first A / D converter 1 and the second A / D converter 2 contain a preamble pattern, it turns on the first switch SW1 and the second switch SW2, activating the phase detector 3. The first switch SW1 is connected between the output terminal of the first A / D converter 1 and the first input terminal of the phase detector 3. The second switch SW2 is connected between the output terminal of the second A / D converter 2 and the second input terminal of the phase detector 3.

[0131] The transmitter TX in this transmission / reception system is configured such that the baseband signal generator 21 in the transmitter TX shown in FIG. 10 is a signal generator with a preamble generation function, and a preamble pattern is included in the output signal. To focus on the processing on the receiving side, experimentally, the baseband signal generator 21 of the transmitter TX was configured to include a first baseband signal generator 21A, a second baseband signal generator 21B, and a preamble generator 21C. The first baseband signal generator 21A and the second baseband signal generator 21B can generate random or information signals such as images or digital data. The preamble generator 21C outputs a preamble pattern signal.

[0132] By connecting the third switch SW3 to the first baseband signal generator 21A, the output signal from the first baseband signal generator 21A is input to the I-channel first modulation section 231 (multiplier). By connecting the third switch SW3 to the preamble generator 21C, the output signal from the preamble generator 21C is input to the I-channel first modulation section 231 (multiplier).

[0133] Similarly, by connecting the fourth switch SW4 to the second baseband signal generator 21B, the output signal from the second baseband signal generator 21B is input to the Q-channel second modulation section 232 (multiplier). By connecting the fourth switch SW4 to the preamble generator 21C, the output signal from the preamble generator 21C is input to the Q-channel first modulation section 231 (multiplier).

[0134] That is, by periodically switching the connections of the third switch SW3 and the fourth switch SW4 to the preamble generator 21C, a preamble pattern can be periodically included in the transmission signal. When the receiver RX detects a preamble pattern, it can periodically correct the sampling timing of the A / D conversion by starting the operation of a feedback loop using the phase detector 3. That is, it is possible to switch from the random signal pattern to the preamble pattern before the phase of the sampling timing in the receiver RX shifts from the reference value beyond a threshold value.

[0135] FIG. 23 is a block diagram of a transmission and reception system.

[0136] In this transmission / reception system, the preamble generator 21C of the transmission device TX shown in FIG. 22 is replaced with a first preamble generator 21C1 and a second preamble generator 21C2.

[0137] By connecting the third switch SW3 to the first baseband signal generator 21A, the output signal from the first baseband signal generator 21A is input to the I-channel first modulation section 231 (multiplier). By connecting the third switch SW3 to the first preamble generator 21C1, the output signal from the first preamble generator 21C1 is input to the I-channel first modulation section 231 (multiplier).

[0138] Similarly, by connecting the fourth switch SW4 to the second baseband signal generator 21B, the output signal from the second baseband signal generator 21B is input to the Q-channel second modulation section 232 (multiplier). By connecting the fourth switch SW4 to the second preamble generator 21C2, the output signal from the second preamble generator 21C2 is input to the Q-channel first modulation section 231 (multiplier). The preamble patterns generated by the first and second preamble generators can be the same, or different. For example, a configuration is possible in which one preamble pattern indicates 1 and the other preamble pattern indicates -1.

[0139] 23 , by periodically switching the connections of the third switch SW3 and the fourth switch SW4 to connect to the first preamble generator 21C1 and the second preamble generator 21C2, a preamble pattern can be periodically included in the transmission signal. When the receiver RX detects a preamble pattern, the operation of a feedback loop using the phase detector 3 can be started, thereby periodically correcting the sampling timing of the A / D conversion. In other words, the random signal pattern can be switched to the preamble pattern before the phase of the sampling timing in the receiver RX shifts from the reference value by exceeding a threshold value.

[0140] The transmitting device may detect the phase synchronization state transmitted from the receiving device and transmit data after confirming that synchronization has been completed.

[0141] As explained above, the frequency (f ＲＦ ') is the N-fold (1≦N) baseband signal f Ｓ Frequency (= N × f Ｓ ), the frequency corresponding to the remainder of these frequencies (Δf Ｓ The phases of these frequencies are shifted in a cycle of f Ｓ When the phase is shifted by 1 UI (unit interval) or more from the symbol width (frequency shift fｅｒｒ If the baseband signal f exceeds 1 UI, demodulation will not be possible. Ｓ By periodically including a preamble pattern as information contained in the signal, the sampling timing of the first A / D converter 1 and the second A / D converter 2 can be corrected in synchronization with this preamble pattern signal, thereby enabling data recovery.

[0142] As described above, the above-described receiving device restores the received signal by using an A / D converter without using a mixer. Next, the operation of the A / D converter will be considered.

[0143] 24A and 24B are timing charts of an input signal (FIG. 24A), an I-channel baseband signal (discrete values) (FIG. 24B), a Q-channel baseband signal (discrete values) (FIG. 24C), and restored data (FIG. 24D) when digital processing is performed.

[0144] The input signal (Input) to the receiver RX is sampled at 45° and 90° and A / D converted (FIG. 24(a)). The I-channel and Q-channel baseband signals (BBI, BBQ) sampled by the A / D conversion are discrete values ​​(FIG. 24(b) and FIG. 24(c)). The Q-channel is the I-channel local signal (LO = frequency (f ＲＦ The phase is π / 2 added to the phase of the phase shifter (45° and 90°). The vertical axis of these timing charts indicates the signal level. The values ​​(DATA) at (45° and 90°) can take the values ​​(11), (00), (10), and (01) (Fig. 24(d)). By sampling at these phases, the baseband signal can be restored.

[0145] 24A and 24B are timing charts of an input signal (FIG. 24E), an I-channel baseband signal (continuous values) (FIG. 24F), a Q-channel baseband signal (continuous values) (FIG. 24G), and restored data (FIG. 24H) when analog processing is performed.

[0146] The input signal (Input) to the receiving device RX is input to the mixer together with the local signal (FIG. 24(e)). The I-channel and Q-channel baseband signals (BBI, BBQ) output from the mixer are continuous values ​​(FIG. 24(f) and FIG. 24(g)). The vertical axis of these timing charts indicates the signal level. The output continuous values ​​are sampled by a subsequent circuit and converted into digital values ​​(DATA). In this case, the digital values ​​can take the values ​​(11), (00), (10), and (01) (FIG. 24(h)). As described above, digital processing can restore baseband signals in the same way as analog processing.

[0147] When the input signal (Input) to the receiving device RX is input to a mixer and restored, the I-channel baseband signal (continuous value) (FIG. 24(a)) has values ​​of 1 and 0. The I-channel and Q-channel baseband signals (BBI, BBQ) have discrete values ​​(FIGS. 24(b) and 24(c)). The Q-channel has a phase that is π / 2 added to the I-channel local signal. Note that the vertical axis of these timing charts indicates the signal level. The values ​​(DATA) at (45° and 90°) can take the values ​​(11), (00), (10), and (01) (FIG. 24(d)). The baseband signal can be restored by performing sampling at these phases.

[0148] Next, a supplementary explanation will be given of a case where the received signal is sampled at four phase timings of 45°, 135°, 225°, and 315°.

[0149] 25 is a timing chart showing an input signal (FIG. 25(a)), an I-channel baseband signal (discrete values) (FIG. 25(b)), a Q-channel baseband signal (discrete values) (FIG. 25(c)), sampling data in the I-channel (FIG. 25(b2)), sampling data in the Q-channel (FIG. 25(c2)), restored baseband signal data in the I-channel (FIG. 25(d)), and restored baseband signal data in the Q-channel (FIG. 25(e)).

[0150] The input signal (Input) is sampled by the A / D converter at four phase timings: 45°, 135°, 225°, and 315° (FIG. 25(a)). That is, the I-channel input signal is sampled by the first A / D converter at phases of 45° and 225° (FIG. 25(b)), and the Q-channel input signal is sampled by the second A / D converter at phases of 135° and 315° (FIG. 25(c)). The sampled values ​​at 215° and 315°, indicated by the arrows, are inverted (FIGS. 25(b2) and 25(c2)), yielding sampled data (BBI) corresponding to the I-channel baseband signal and sampled data (BBQ) corresponding to the Q-channel baseband signal. These values ​​are decimated via a decimation filter to obtain the I-channel baseband signal (FIG. 25(d)) and the Q-channel baseband signal (FIG. 25(e)).

[0151] FIG. 26 shows a timing chart of various signals.

[0152] In these timing charts, the horizontal axis represents time and the vertical axis represents signal amplitude. The input signal (Input) to the receiving device RX is a modulated carrier signal, and A / D conversion sampling is performed at each phase of this signal (45°, 135°, 225°, 315°) (FIG. 26(a)). FIG. 26(a) shows the input signal to the receiving device (FIG. 26(a)). FIG. 26(b) shows AD-converted data sampled at phase 45° in the I channel. FIG. 26(c) shows AD-converted data sampled at phase 135° in the Q channel. FIG. 26(d) shows AD-converted data sampled at phase 225° in the I channel. FIG. 26(e) shows AD-converted data sampled at phase 315° in the Q channel. When N=4, 1 UI in the received signal contains data SI0 to SI7 and data SQ0 to SQ7. The number of sampling data contained in 1 UI varies depending on the value of N.

[0153] 26(f) shows the entire data sampled in the I channel, including the 45° and 225° sampled data, with the 225° sampled data having an inverted value.

[0154] 26(g) shows the entire data sampled in the Q channel, including the 135° and 315° sampled data, with the 315° sampled data being inverted.

[0155] Figure 26(h) shows the data of the restored baseband signal in the I channel, and Figure 26(i) shows the data of the restored baseband signal in the Q channel.

[0156] FIG. 27 is a diagram illustrating a decimation filter.

[0157] 26(f) and 26(g) show signals obtained by inverting the signals at phases of 225° and 315°. To invert the values ​​of these signals, an inverter circuit INV is placed before the decimation filter. For example, the receiver RX shown in FIG. 11 and other figures includes a first decimation filter DF1 placed after the first A / D converter 1 and a second decimation filter DF2 placed after the second A / D converter 2. Each decimation filter has input terminals (IN(45), IN(135)) for signals sampled at phases of 45° and 135°, and input terminals (IN(225), IN(315)) for signals sampled at phases of 225° and 315°. An inverter circuit INV is placed between the decimation filter (DF) and the input terminals (IN(225), IN(315)). The decimation filter (DF) can decimate and output the oversampled data.

[0158] Although various exemplary embodiments have been described above, various omissions, substitutions, and modifications may be made without being limited to the above-described exemplary embodiments. Furthermore, elements from different embodiments may be combined to form other embodiments. Furthermore, it will be understood from the above description that various embodiments of the present disclosure have been described herein for illustrative purposes, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the following claims.

[0159] 10...receiving antenna, 11...receiving amplifier, 20...transmitting antenna, 21...baseband signal generator, 23...modulation circuit, 24...carrier signal generator, 25...transmitting amplifier, 100...transmitting / receiving system, RX...receiving device, TX...transmitting device, 1...first A / D converter, 2...second A / D converter, 3...phase detector, 4...D / A converter, 5...loop filter, 6...voltage controlled oscillator, 7...phase shifter, 31...first XOR circuit, 32...second XOR circuit, 33...multiplexer, 41...first charge pump, 42...second charge pump 43...first amplifier, 44...second amplifier, 51...first capacitor, 52...second capacitor, 53...third capacitor, 54...fourth capacitor, 55...resistor, 71...first phase interpolator, 72...second phase interpolator, 73...down converter, DF1...first decimation filter, DF2...second decimation filter, PC1...first pattern checker, PC2...second pattern checker, MS1...first mode selection circuit, MS2...second mode selection circuit, WS1...first waveform shaping circuit, WS2...second waveform shaping circuit.

Claims

1. A receiving device comprising: a first A / D converter connected to an input terminal; a second A / D converter connected to the input terminal; a phase detector having an input terminal connected to a first output terminal of the first A / D converter and a second output terminal of the second A / D converter; a loop filter connected to the output terminal of the phase detector; and a voltage-controlled oscillator having an input terminal connected to the output terminal of the loop filter, wherein a first sampling clock signal of the first A / D converter and a second sampling clock signal of the second A / D converter are generated from the output signal of the voltage-controlled oscillator and have a phase difference of π / 2.

2. The received signal of the receiving device has a carrier frequency f ＲＦ A carrier signal of a reference frequency f Ｓ where N is a natural number and ＲＦ = N × f Ｓ The receiving device according to claim 1 , wherein the following relationship is satisfied:

3. The receiving device according to claim 2, comprising: a first decimation filter provided in a stage subsequent to the first A / D converter; and a second decimation filter provided in a stage subsequent to the second A / D converter.

4. A receiving device as described in claim 3, comprising: a first pattern checker provided downstream of the first decimation filter, which detects an error rate of an input signal and instructs the first decimation filter to perform a sampling operation at the sampling timing at which the detected error rate is smallest; and a second pattern checker provided downstream of the second decimation filter, which detects an error rate of an input signal and instructs the second decimation filter to perform a sampling operation at the sampling timing at which the detected error rate is smallest.

5. A receiving device as described in claim 2, comprising: a first mode selection circuit provided downstream of the first A / D converter, which selects the most numerous value from among multiple values represented by n consecutive data samples taken within a period equivalent to one bit; and a second mode selection circuit provided downstream of the second A / D converter, which selects the most numerous value from among multiple values represented by n consecutive data samples taken within a period equivalent to one bit.

6. The receiving device according to claim 3, comprising: a first waveform shaping circuit provided between the first A / D converter and the first decimation filter; and a second waveform shaping circuit provided between the second A / D converter and the second decimation filter.

7. A first superheterodyne circuit is provided in front of the input terminals of the first A / D converter and the second A / D converter, to which a high frequency signal received by the receiving device and a first local signal are input, and the first local signal is generated from the output signal of the voltage controlled oscillator, and M １ is a natural number, and M of the frequency of this output signal １ 3. The receiving device according to claim 2, having a doubled frequency.

8. A second superheterodyne circuit is provided in front of the first superheterodyne circuit, to which the high frequency signal received by the receiving device and a second local signal are input, and the second local signal is generated from the output signal of the voltage controlled oscillator, and M ２ is a natural number, and M of the frequency of this output signal ２ 8. The receiving device according to claim 7, having a doubled frequency.

9. The receiving device according to claim 2, wherein the received signal of the receiving device is generated by phase shift keying the carrier signal with the baseband signal.

10. The receiving device according to claim 2, wherein the received signal of the receiving device is generated by quadrature amplitude modulation (QAM) of the carrier signal with the baseband signal.

11. The receiving device according to claim 1, wherein the phase detector has a multiplexer that receives the first digital value output from the first A / D converter and the second digital value output from the second A / D converter and outputs a digital value that correlates to the phase difference between the signals indicated by the first digital value and the second digital value.

12. The receiving device according to claim 11, further comprising a D / A converter provided between the output terminal of the phase detector and the input terminal of the voltage-controlled oscillator.

13. The receiving device according to claim 12, wherein the loop filter includes: a resistor having a first end connected to the output terminal of the D / A converter; a first capacitor connected between a second end of the resistor and a fixed potential; a second capacitor connected between the first end of the resistor and the fixed potential; and a third capacitor connected in parallel to a path between the first end of the resistor and the output terminal of the D / A converter.

14. The receiving device according to claim 1, wherein the received signals input to the input terminals of the first A / D converter and the second A / D converter periodically include a preamble pattern, and when the preamble pattern is received, the phases of the first sampling clock signal and the second sampling clock signal are corrected based on the received preamble pattern.

15. The receiving device according to claim 1, further comprising an antenna for receiving a signal wirelessly transmitted from a transmitting device and inputting the signal to said input terminal.

16. The receiving device according to claim 1, which receives a signal transmitted by wire from a transmitting device and inputs it to said input terminal.

17. A transmission / reception system comprising: a receiving device according to any one of claims 1 to 16; and a transmitting device that transmits a signal received by said receiving device as a transmission signal.

Images