Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor that is capable of suppressing reduction in reliability.　A multilayer ceramic capacitor 10 includes: a laminate 12 including an effective area 21 in which a plurality of ceramic layers 14 and a plurality of internal electrode layers 16 are alternately laminated, and an ineffective area 24 in which one or plurality of the ceramic layers 14 are laminated and which covers at least a part of the effective area 21; and an external electrode 30 that is formed on an outer surface of the laminate 12 and is connected to the internal electrode layer 16. The ineffective area 24 includes: an interface region 42 including an interface 41 between the effective area 21 and the ineffective area 24; and an interface outer region 44 that is situated in an outer side direction from the laminate 12 with respect to the interface region 42. Continuity of Si that is present in a direction along the interface 41 in the interface region 42 is greater than continuity of Si that is present in a direction along the interface 41 in the interface outer region 44.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] In recent years, with the trend toward miniaturization of electronic devices, there has been a demand for smaller and larger capacitance multilayer ceramic capacitors to be installed in electronic devices. A typical multilayer ceramic capacitor comprises a laminate having an active portion and an inactive portion, and external electrodes disposed on the outer surface of the laminate. The active portion is formed by laminating multiple ceramic layers and multiple internal electrode layers so as to be capable of accumulating capacitance. The inactive portion covers the active portion and is formed by laminating multiple ceramic layers. The internal electrode layers and external electrode layers of the active portion are connected.

[0003] In the multilayer ceramic capacitor described in Patent Document 1, an effective portion is formed by laminating ceramic sheets for effective portions coated with internal electrode paste. Furthermore, a plurality of ceramic sheets for ineffective portions are integrated into the effective portion before firing to prepare a pre-fired laminate, i.e., a laminated chip. Here, the ceramic sheets for effective portions and the ceramic sheets for ineffective portions contain ceramic particles, a binder, a solvent, and the like. The binder and solvent contain a resin component. The laminated chip then undergoes a degreasing process and a firing process to form the laminate.

[0004] Japanese Patent Application Laid-Open No. 2014-7187

[0005] The inventors have discovered that various laminates, including the laminate of Patent Document 1, may have problems with adhesion between the ineffective and effective portions. When there are problems with adhesion between the ineffective and effective portions, the reliability of the multilayer ceramic capacitor may decrease. Therefore, there is room for improvement in order to stably produce reliable multilayer ceramic capacitors.

[0006] Therefore, a primary object of the present invention is to provide a multilayer ceramic capacitor capable of suppressing a decrease in reliability.

[0007] A multilayer ceramic capacitor according to the present invention comprises a laminate including an effective portion in which a plurality of ceramic layers and a plurality of internal electrode layers are alternately stacked, and an ineffective portion in which one or more ceramic layers are stacked and which covers at least a part of the effective portion, and an external electrode formed on an outer surface of the laminate and connected to the internal electrode layer, The ineffective portion includes an interface region including an interface between the effective portion and the ineffective portion, and an extra-interface region located outward of the laminate from the interface region, and the continuity of Si existing in the interface region in a direction along the interface is greater than the continuity of Si existing in the extra-interface region in a direction along the interface.

[0008] In the multilayer ceramic capacitor according to the present invention, the continuity of Si in the interface region is greater than the continuity of Si in the non-interface region. That is, Si is present more continuously in the interface region between the valid and invalid portions. This more continuous presence of Si in the interface region improves the adhesion between the valid and invalid portions. This makes it possible to prevent the invalid portions from peeling off from the valid portion, thereby providing a multilayer ceramic capacitor that can prevent a decrease in reliability.

[0009] According to the present invention, it is possible to provide a multilayer ceramic capacitor capable of suppressing a decrease in reliability.

[0010] The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

[0011] 1 is a perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. It is a cross-sectional view taken along line II-II in FIG. 1. It is a cross-sectional view taken along line III-III in FIG. 1. It is a cross-sectional view taken along line IV-IV in FIG. 2. It is a cross-sectional view taken along line V-V in FIG. 2. (a) is a partial enlarged view of portion α in FIG. 3, and (b) is a cross-sectional photograph of portion α in FIG. 3 taken with a wavelength dispersive X-ray analyzer (WDX) corresponding to (a). It is a schematic diagram illustrating a method for determining the continuity of SiO2 (or Si). (a) is a partial enlarged view of portion β in FIG. 3, and (b) is a cross-sectional photograph of portion β in FIG. 3 taken with a wavelength dispersive X-ray analyzer (WDX) corresponding to (a). (a) to (e) are diagrams for explaining a method for manufacturing a multilayer ceramic capacitor according to this embodiment. It is a schematic diagram illustrating stacking ceramic sheets for effective portions coated with conductive paste for internal electrode layers.

[0012] EMBODIMENTS 1. Multilayer Ceramic Capacitor A multilayer ceramic capacitor according to an embodiment of the present invention will be described below, taking a two-terminal multilayer ceramic capacitor as an example.

[0013] Fig. 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. Fig. 2 is a cross-sectional view taken along line II-II in Fig. 1. Fig. 3 is a cross-sectional view taken along line III-III in Fig. 1. Fig. 4 is a cross-sectional view taken along line IV-IV in Fig. 2. Fig. 5 is a cross-sectional view taken along line V-V in Fig. 2.

[0014] As shown in FIGS. 1 to 3 , the multilayer ceramic capacitor 10 includes a rectangular parallelepiped laminate 12 and external electrodes 30 disposed on both ends of the laminate 12 .

[0015] (1) Laminate As shown in FIG. 1 , the laminate 12 has a first main surface 12a and a second main surface 12b that face each other in a height direction (stacking direction) x, a first side surface 12c and a second side surface 12d that face each other in a width direction y that is perpendicular to the height direction x, and a first end surface 12e and a second end surface 12f that face each other in a length direction z that is perpendicular to the height direction x and the width direction y. The laminate 12 has rounded corners and ridges. Note that a corner refers to a portion where three adjacent surfaces of the laminate intersect, and a ridge refers to a portion where two adjacent surfaces of the laminate 12 intersect. Furthermore, unevenness or the like may be formed on some or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f.

[0016] 2 to 5, the laminate 12 has a valid portion 21 and an invalid portion 24. The invalid portion 24 includes an outer layer portion 22 and a side margin portion 23. The valid portion 21 and the invalid portion 24 will be described below.

[0017] (1-1) Effective Section The effective section 21 is formed by alternately stacking a plurality of ceramic layers 14 and a plurality of internal electrode layers 16. In the effective section 21, the internal electrode layers 16 face each other via the ceramic layers 14, thereby forming a capacitance. The effective section 21 is a portion where the internal electrode layers 16 are present. Specifically, in the height direction x, the effective section 21 is a portion between the outermost surface of the effective section 21 on the first main surface 12a side and the outermost surface of the effective section 21 on the second main surface 12b side. The outermost surface of the effective section 21 on the first main surface 12a side is the internal electrode surface on the first main surface 12a side of the internal electrode layer 16 (first internal electrode layer 16a in the example of FIGS. 2 and 3 ) located on the outermost surface of the plurality of internal electrode layers 16 on the first main surface 12a side. The outermost surface of the effective portion 21 on the second main surface 12b side is the internal electrode surface on the second main surface 12b side of the internal electrode layer 16 (the second internal electrode layer 16b in the examples of FIGS. 2 and 3 ) that is located on the outermost surface of the multiple internal electrode layers 16 on the second main surface 12b side. In the width direction y, the effective portion 21 is a portion between the outermost surface of the effective portion 21 on the first side surface 12c side and the outermost surface of the effective portion 21 on the second side surface 12d side. The outermost surface of the effective portion 21 on the first side surface 12c side is located at the internal electrode end portions of the first and second internal electrode layers 16a, 16b on the first side surface 12c side. The outermost surface of the effective portion 21 on the second side surface 12d side is located at the internal electrode end portions of the first and second internal electrode layers 16a, 16b on the second side surface 12d side.

[0018] The ceramic layer 14 can be formed, for example, from a dielectric material. Examples of such dielectric materials include dielectric ceramics having a perovskite structure and containing, as a main component, a perovskite-type compound containing, for example, BaTiO3, CaTiO3, SrTiO3, or CaZrO3. When the dielectric material is the main component, a silicon compound may be added as an additive depending on the desired characteristics of the laminate 12. In addition to silicon compounds, additives such as magnesium compounds, bamboo compounds, manganese compounds, iron compounds, chromium compounds, cobalt compounds, and nickel compounds may also be added in smaller amounts than the main component. The compounds may be oxides or carbonates.

[0019] The thickness of the ceramic layers 14 in the effective portion 21 after firing is preferably, but not limited to, 0.3 μm or more and 1.0 μm or less. The number of ceramic layers 14 stacked in the effective portion 21 is preferably, but not limited to, 15 or more and 1,000 or less. More preferably, the thickness of the ceramic layers 14 in the effective portion 21 after firing is preferably, but not limited to, 0.3 μm or more and 0.6 μm or less. This makes it possible to increase the number of stacked layers, which contributes to higher capacity.

[0020] The internal electrode layers 16 include, for example, a plurality of first internal electrode layers 16 a and a plurality of second internal electrode layers 16 b, each having a substantially rectangular shape. The plurality of first internal electrode layers 16 a and the plurality of second internal electrode layers 16 b are embedded so as to be alternately arranged at equal intervals with the ceramic layers 14 sandwiched therebetween along the height direction x of the laminate 12.

[0021] 4, the first internal electrode layer 16a is disposed on the plurality of ceramic layers 14 and is located inside the laminate 12. The first internal electrode layer 16a has a first opposing electrode portion 26a facing the second internal electrode layer 16b, and a first lead electrode portion 28a located on one end side of the first internal electrode layer 16a and extending from the first opposing electrode portion 26a to the first end face 12e of the laminate 12. An end of the first lead electrode portion 28a is led out to the surface of the first end face 12e and exposed from the laminate 12.

[0022] 5 , the second internal electrode layer 16b is disposed on the plurality of ceramic layers 14 and is located inside the laminate 12. The second internal electrode layer 16b has a second opposing electrode portion 26b facing the first internal electrode layer 16a, and a second extraction electrode portion 28b located on one end side of the second internal electrode layer 16b and extending from the second opposing electrode portion 26b to the second end face 12f of the laminate 12. An end of the second extraction electrode portion 28b is extracted to the surface of the second end face 12f and exposed from the laminate 12.

[0023] The shapes of the first opposing electrode portion 26a of the first internal electrode layer 16a and the second opposing electrode portion 26b of the second internal electrode layer 16b are not particularly limited, but are preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the shape may be tapered in plan view, with a slope increasing toward either side.

[0024] The shapes of the first lead electrode portion 28a of the first internal electrode layer 16a and the second lead electrode portion 28b of the second internal electrode layer 16b are not particularly limited, but are preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the shape may be tapered in plan view, with a slope increasing toward either side.

[0025] The width of the first opposing electrode portion 26a and the width of the first lead-out electrode portion 28a may be the same, or one of them may be narrower. Similarly, the width of the second opposing electrode portion 26b and the width of the second lead-out electrode portion 28b may be the same, or one of them may be narrower.

[0026] The first internal electrode layer 16a and the second internal electrode layer 16b can be made of an appropriate conductive material, for example, a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy.

[0027] The thickness of each of the internal electrode layers 16, i.e., the first internal electrode layers 16a and the second internal electrode layers 16b, is preferably, but not limited to, 0.2 μm or more and 2.0 μm or less. Furthermore, although not limited to, it is more preferably, but not limited to, 0.2 μm or more and 0.5 μm or less. Furthermore, it is preferable that the total number of the first internal electrode layers 16a and the second internal electrode layers 16b is 15 or more and 1000 or less.

[0028] In the laminate 12, capacitance is formed by the first opposing electrode portion 26a of the first internal electrode layer 16a and the second opposing electrode portion 26b of the second internal electrode layer 16b facing each other via the ceramic layer 14. Therefore, capacitance can be obtained between the first external electrode 30a connected to the first internal electrode layer 16a and the second external electrode 30b connected to the second internal electrode layer 16b, and the characteristics of a capacitor are exhibited.

[0029] (1-2) Invalid portion The invalid portion 24 is formed by laminating one or more ceramic layers 14. The material components, such as the dielectric material and additives, of the ceramic layers 14 of the invalid portion 24 may be the same as those of the ceramic layers 14 of the valid portion 21. The invalid portion 24 covers at least a portion of the valid portion 21. The invalid portion 24 has an outer layer portion 22 and a side margin portion 23.

[0030] In Fig. 6, (a) is a partially enlarged view of the α portion of Fig. 3, and (b) is a cross-sectional photograph of the α portion of Fig. 3 taken with a wavelength dispersive X-ray analyzer (WDX) corresponding to (a). Fig. 7 is a schematic diagram for explaining a method for determining the continuity of SiO2 (or Si). In Fig. 8, (a) is a partially enlarged view of the β portion of Fig. 3, and (b) is a cross-sectional photograph of the β portion of Fig. 3 taken with a wavelength dispersive X-ray analyzer (WDX) corresponding to (a).

[0031] (a) Outer Layer Portion As shown in FIGS. 2 and 3 , the outer layer portion 22 (part of the ineffective portion 24) includes a first outer layer portion 22a and a second outer layer portion 22b. The first and second outer layer portions 22a and 22b are formed by stacking multiple ceramic layers 14. The effective portion 21 is sandwiched between the first outer layer portion 22a and the second outer layer portion 22b in the height direction (stacking direction) x. The first outer layer portion 22a is adjacent to the internal electrode surface of the first internal electrode layer 16a located at the outermost surface of the first internal electrode layer 16a in the effective portion 21. The internal electrode surface is aligned in the planar direction (LW plane direction). In other words, the first outer layer portion 22a is located on the first main surface 12a side and is formed from multiple ceramic layers 14 located between the first main surface 12a and the outermost surface of the effective portion 21 on the first main surface 12a side, in a straight line (extension of) that outermost surface in the length direction z. The second outer layer portion 22b is adjacent to the internal electrode surface of the second internal electrode layer 16b located at the outermost surface of the second internal electrode layer 16b of the effective portion 21. That is, the second outer layer portion 22b is located on the second main surface 12b side and is formed from a plurality of ceramic layers 14 located between the second main surface 12b and the outermost surface of the effective portion 21 on the second main surface 12b side and a straight line in the longitudinal direction z of that outermost surface. The thickness of the ceramic layers 14 in the first and second outer layer portions 22a, 22b after firing is not limited to, but is preferably, for example, 10 μm to 100 μm. The number of ceramic layers 14 stacked in the first and second outer layer portions 22a, 22b is not limited to, but is preferably, for example, 1 to 50. The first and second outer layer portions 22a, 22b may be formed from a single ceramic layer 14.

[0032] In the first and second outer layer portions 22a, 22b, Si is present continuously at the interface 41 with the effective portion 21. The first and second outer layer portions 22a, 22b include an interface region 42 and an off-interface region 44. The interface region 42 includes the interface 41 between the effective portion 21 and the first and second outer layer portions 22a, 22b. The off-interface region 44 is located toward the outside of the laminate 12 relative to the interface region 42. The continuity of Si present in the interface region 42 in the direction along the interface 41 is greater than the continuity of Si present in the off-interface region 44 in the direction along the interface 41. The outer layer portion 22 in this embodiment will be further described using FIG. 6 . However, since the first and second outer layer portions 22a, 22b have the same configuration, the following description will focus on the first outer layer portion 22a.

[0033] In the example of FIG. 6 , the first outer layer portion 22a includes an interface region 42, an interface-adjacent region 43, and an off-interface region 44. The interface region 42 includes an interface 41 where the effective portion 21 and the first outer layer portion 22a contact each other. The interface-adjacent region 43 is adjacent to the interface region 42 in the outward direction of the laminate 12. The off-interface region 44 is adjacent to the interface-adjacent region 43 in the outward direction of the laminate 12. That is, in the first outer layer portion 22a, the interface region 42, the interface-adjacent region 43, and the off-interface region 44 are located adjacent to each other in this order in the outward direction of the laminate 12. The off-interface region 44 also includes a central portion 47 of the first outer layer portion 22a in the direction from the effective portion 21 toward the first outer layer portion 22a. In other words, the central portion 47 is the center of the first outer layer portion 22a in a direction perpendicular to the direction along the interface 41. The extra-interface region 44 includes an outer surface region 45 and an extra-interface main region 46. The outer surface region 45 includes the outer surface of the laminate 12 and is located on the outer surface side of the laminate 12. The extra-interface main region 46 is the region of the extra-interface region 44 other than the outer surface region 45 and is located more inward of the laminate 12 than the outer surface region 45. The extra-interface main region 46 includes a central portion 47. The average thickness of the interface region 42 of the first outer layer portion 22a is, for example, 1.20 μm or more and 1.25 μm or less. The average thickness of the interface-adjacent region 43 of the first outer layer portion 22a is, for example, 3 μm or more and 5 μm or less.

[0034] The position, range, and Si continuity of each region 42, 43, 45, 46, etc. can be identified using visual inspection or a scale (reference dimensions, ruler, etc.) based on the results of measurement using a wavelength dispersive X-ray analyzer (WDX). For example, in FIG. 6B, the regions 42, 43, 45, 46, etc. and the Si continuity are identified as follows using visual inspection or a scale. In FIG. 6B, the region adjacent to the effective portion 21 in the outward direction of the laminate 12 and having continuous white regions containing Si is identified as the interface region 42. The region adjacent to the interface region 42 in the outward direction of the laminate 12 and having fewer and discontinuous white regions containing Si than the interface region 42 is identified as the interface-adjacent region 43. The region where the white regions containing Si are dispersed and have less Si continuity is identified as the extra-interface main region 46. The region adjacent to the extra-interface main region 46 in the outward direction of the laminate 12 and having more continuous white regions containing Si than the extra-interface main region 46 is identified as the outer surface region 45.

[0035] Here, the position, range, and Si continuity of each region 42, 43, 45, 43, etc. can also be identified by Si intensity. For example, the interface region 42 and the interface-adjacent region 43 can be identified as follows. First, the Si intensity in a portion that can be considered to be the interface region 42 of the first outer layer portion 22a within a predetermined field of view (described below), for example, the ratio of the Si intensity to the Ba intensity (Si intensity / Ba intensity), is measured using WDX. As described below, the Si intensities of multiple sub-division regions (e.g., one pixel) within the portion that can be considered to be the interface region 42 are obtained, and their average is calculated. Whether Si is segregated in the portion that can be considered to be the interface region 42 of the first outer layer portion 22a is determined based on this average. In other words, the average of the ratio of the Si intensity to the Ba intensity (Si intensity / Ba intensity) in the portion that can be considered to be the interface region 42 of the first outer layer portion 22a within the predetermined field of view is calculated. In this embodiment, when the average value of the Si intensity / Ba intensity is, for example, 0.1 or more, it is determined that Si is segregated. The average value is, for example, 0.1 or more and 0.2 or less. In this way, the portion determined to have Si segregated can be identified as the interface region 42. Similarly, the Si intensity / Ba intensity is obtained in at least one sub-division region in a portion of the first outer layer portion 22a that can be considered as the interface-adjacent region 43, and the average is obtained. Based on the result, it is determined whether Si is segregated, and the interface-adjacent region 43 can be identified. Note that the average value of the Si intensity / Ba intensity in the interface-adjacent region 43 is, for example, 0.05 or more and less than 0.10, and this is considered to be the absence of Si segregation in the definition of the present invention. The positions, ranges, and Si continuity of other regions, such as the outer surface region 45 and the extra-interface main region 46, can also be identified by the Si intensity / Ba intensity in the same manner as described above.

[0036] The first outer layer portion 22a contains Si as an additive to the ceramic material. The Si exists as SiO in the first outer layer portion 22a. The Si may be in the form of SiO or a low-viscosity liquid phase component containing SiO. The same applies hereinafter. Hereinafter, Si may be referred to as SiO, and SiO may be referred to as Si. In the interfacial region 42, Si exists substantially continuously along the interface 41. The continuity of Si in the interfacial region 42 along the interface 41 is greater than the continuity of Si in the extra-interface region 44 along the interface 41. In other words, the continuity of Si in the interfacial region 42 along the interface 41 is greater than the continuity of Si in the central portion 47 along the interface 41. In other words, the continuity of Si in the interfacial region 42 along the interface 41 is greater than the continuity of Si in the extra-interface region 46 along the interface 41.

[0037] 6B, the white regions are regions where Si exists. In FIG. 6B, Si exists continuously in the interface region 42, whereas Si exists dispersedly in the out-of-interface main region 46 (the region of the out-of-interface region 44 excluding the outer surface region 45), indicating that the continuity of Si is low.

[0038] The continuity of Si in the interface region 42 is preferably 50% or more to improve the adhesion between the effective portion 21 and the outer layer portion 22. To further improve the adhesion between the effective portion 21 and the outer layer portion 22, the continuity of Si in the interface region 42 is more preferably 80% or more.

[0039] Furthermore, the Si content of the interface-adjacent region 43 may be smaller than the Si content of the interface region 42. As can be seen from (b) of Figure 6, the white area in the interface-adjacent region 43 is smaller and has a lower Si content than the interface region 42. Furthermore, the Si content of the interface-adjacent region 43 may be smaller than the Si content of the extra-interface region 44.

[0040] Here, the content of metal elements including compounds such as Ni and NiO in the extra-interface region 44 is smaller than the content of metal elements including compounds such as Ni and NiO in the interface region 42. In particular, when the main component of the internal electrode layer 16 is Ni, the Ni content in the extra-interface region 44 is smaller than the Ni content in the interface region 42. This is thought to be because the extra-interface region 44 is farther away from the first internal electrode layer 16a of the effective portion 21 than the interface region 42. Similarly, the content of metal elements including compounds such as Ni and NiO in the interface-adjacent region 43 is smaller than the content of metal elements including compounds such as Ni and NiO in the interface region 42. In particular, when the main component of the internal electrode layer 16 is Ni, the Ni content in the interface-adjacent region 43 is smaller than the Ni content in the interface region 42. This is thought to be because the interface-adjacent region 43 is farther away from the first internal electrode layer 16a of the effective portion 21 than the interface region 42.

[0041] The continuity of Si in the first outer layer portion 22a can be determined, for example, as follows. A WT cross section is exposed in the laminate 12, as shown in FIG. 3 . The WT cross section is analyzed for the presence or absence of Si, for example, using a wavelength dispersive X-ray analyzer (WDX). Analysis using WDX detects the intensities of various components for each of multiple divided regions in the WT cross section. Specifically, the WDX divides a predetermined field of view (referred to here as one field of view) into multiple divided regions for intensity analysis. The multiple divided regions are, for example, regions obtained by dividing the first outer layer portion 22a into multiple regions in a direction perpendicular to the interface 41. In this embodiment, the first outer layer portion 22a is divided in a direction perpendicular to the interface 41 and includes multiple divided regions arranged along the interface 41. Based on the Si intensity, it is determined for each divided region whether Si is present in the interface region 42. The continuity of Si is then determined based on the proportion of the interface regions 42 in which Si is present among all the interface regions 42 in the divided regions. Each divided region is a predetermined region of the image obtained using WDX, such as a plurality of pixels.

[0042] An example of how to determine the continuity of Si will be further explained using FIG. 7. FIG. 7 is a schematic representation of the same field of view as FIG. 6(a) and FIG. 8(a) described below. In the example of FIG. 7, the ceramic layer 14 is assumed to be mainly composed of BaTiO3 and to contain Si as an additive. The internal electrode layer 16 is assumed to be mainly composed of Ni.

[0043] A WT cross section is exposed in the first outer layer portion 22a, as shown in FIG. 7 . A wavelength-dispersive X-ray analyzer (WDX) is used to analyze various components in multiple divided regions in the WT cross section. The multiple divided regions are regions obtained by dividing the first outer layer portion 22a into multiple regions perpendicular to the interface 41. In the example shown in FIG. 7 , the first outer layer portion 22a is divided into divided regions C1, C2, C3, C4, ..., Cn. Each divided region C1 to Cn is further divided into, for example, 12 sub-divided regions R1 to R12 from the valid portion 21 toward the invalid portion 24. Here, the interface region 42, the interface-adjacent region 43, etc. can be identified visually or using a scale, as described above. For example, in the example shown in FIG. 7 , groups G1 to G4 are identified as the interface region 42. Group G1 includes sub-division regions R1 to R5 in division region C1, group G2 includes sub-division regions R2 to R6 in division region C2, group G3 includes sub-division regions R1 to R5 in division region C3, and group G4 includes sub-division regions R1 to R5 in division region C4. When visually inspecting FIG. 6B and FIG. 8B (described later), the locations where the white regions containing Si are continuous and where Si is recognized to be segregated generally coincide with the locations of each of groups G1 to G4 in FIG. 7, each of which includes a predetermined number of sub-division regions. Other areas, such as the interface-adjacent region 43, the outer surface region 45, and the outer-interface main region 46, can also be identified using a similar method.

[0044] Here, the interface 41 between the first internal electrode layer 16a, which is the outermost surface on the first main surface 12a side of the effective portion 21, and the first external layer portion 22a (ineffective portion 24) can be identified, for example, as follows: For each of the sub-division regions R1 to R12, a wavelength dispersive X-ray analyzer (WDX) is used to determine the ratio of Ni intensity to Ba intensity (Ni intensity / Ba intensity) as an index of Ni content. Next, from the effective portion 21 side toward the ineffective portion 24 side, a sub-division region is identified where the ratio of Ni intensity to Ba intensity becomes, for example, 0.2 or less. In this embodiment, a Ni intensity / Ba intensity of 0.2 or less is used as the criterion for a region that is not an internal electrode layer 16. Therefore, when the Ni intensity / Ba intensity is, for example, 0.3, the region is determined to be one in which an internal electrode layer 16 is present. In the case of Figure 7, the sub-divided region R1 is identified in the divided region C1, the sub-divided region R2 is identified in the divided region C2, the sub-divided region R1 is identified in the divided region C3, and the sub-divided region R1 is identified in the divided region C4 as the sub-divided region that first satisfies the condition of Ni intensity / Ba intensity ≤ 0.2. Note that the index of the Ni content may be expressed as the ratio of the Ni content to the Ba content (Ni content / Ba content). By using the index of the Ni content in this way, it is possible to identify the interface 41 between the first internal electrode layer 16a, which is the outermost surface on the first main surface 12a side of the effective portion 21, and the first outer layer portion 22a (ineffective portion 24).

[0045] In the case of FIG. 7 , the continuity of the interface region 42 can be determined as follows. First, for each of groups G1 to G4, the ratio of Si intensity to Ba intensity (Si intensity / Ba intensity) is determined using a wavelength dispersive X-ray analyzer (WDX). In group G1 of the interface region 42, the Si intensity / Ba intensity in the sub-division regions R1 to R5 is as shown in FIG. 7 , and the average of these Si intensity / Ba intensity ratios is 0.066. Therefore, the average Si intensity / Ba intensity in group G1 is less than 0.1. Therefore, it is determined that the amount of Si present in group G1 is low, and the continuity of Si is interrupted. Meanwhile, the Si intensity / Ba intensity in groups G2 (sub-division regions R2 to R6), G3 (sub-division regions R1 to R5), and G4 (sub-division regions R1 to R5) are as shown in FIG. 7 . The average Si intensity / Ba intensity ratios for each of groups G2 to G4 are 0.196, 0.19, and 0.188. Therefore, the average Si intensity / Ba intensity ratio for groups G2 to G4 is 0.1 or greater and 0.2 or less. Therefore, it is determined that the amount of Si is large in each of groups G2 to G4, and that Si is present continuously throughout groups G2 to G4. Based on this result, when considering the interface region 42 (groups G1 to G4) as a whole, it is determined that Si is present continuously in the interface region 42, and that Si is segregated.

[0046] 7, the ratio of the number of groups (groups G2 to G4) in which the Si intensity / Ba intensity is 0.1 or more is calculated among the number of groups G1 to G4, thereby determining the continuity of Si in the interface region 42.

[0047] The continuity of Si in the out-of-interface region 44 can also be determined in the same manner as described above. That is, the out-of-interface region 44 is identified by visual inspection or the like. Then, for each of the divided regions C1, C2, ..., etc. of the out-of-interface region 44, the average Si intensity / Ba intensity of the sub-divided region is determined. Then, the ratio of the number of divided regions in which the Si intensity / Ba intensity is 0.05 or more and less than 0.10 is determined among the number of divided regions in the out-of-interface region 44. In this way, the continuity of Si in the out-of-interface region 44 can be determined. The continuity of Si can also be determined in the same manner for the outer surface region 45, the out-of-interface main region 46, etc.

[0048] The continuity of Si may be determined not by the ratio of Si intensity to Ba intensity but by the ratio of Si content to Ba content.

[0049] (b) Side Margin Portion As shown in FIGS. 3 to 5 , the side margin portion 23 (part of the ineffective portion 24) has a first side margin portion 23a and a second side margin portion 23b. The first and second side margin portions 23a, 23b are formed by stacking a plurality of ceramic layers 14. A laminate portion 20 is sandwiched in the width direction y between the first side margin portion 23a and the second side margin portion 23b. Here, the laminate portion 20 is formed by stacking an effective portion 21 and a pair of outer layer portions 22 above and below the effective portion 21 in the height direction x. The first and second side margin portions 23a, 23b are adjacent to the internal electrode ends of the first and second internal electrode layers 16a, 16b. The internal electrode ends are located at both ends in the W direction of the planar direction (LW planar direction) of the first and second internal electrode layers 16a, 16b. In particular, the internal electrode ends are the ends of the first and second internal electrode layers 16a, 16b on the first and second side surfaces 12c, 12d. The first and second side margins 23a, 23b are regions where the first and second internal electrode layers 16a, 16b are not present in a cross section viewed from the height direction (stacking direction) x as shown in FIGS. 4 and 5 . The thickness of the ceramic layers 14 after firing in the first and second side margins 23a, 23b is not limited to this, but is preferably, for example, 10 μm to 100 μm. The number of ceramic layers 14 stacked in the first and second side margins 23a, 23b is not limited to this, but is preferably, for example, 1 to 50. The first and second side margins 23a, 23b may be formed from a single ceramic layer 14.

[0050] In the first and second side margin portions 23a, 23b, Si is present continuously at the interface 41 with the effective portion 21. The first and second side margin portions 23a, 23b include an interface region 42 and an out-of-interface region 44. The interface region 42 includes the interface 41 between the effective portion 21 and the first and second side margin portions 23a, 23b. The out-of-interface region 44 is located outside the stack 12 relative to the interface region 42. The continuity of Si present in the interface region 42 in the direction along the interface 41 is greater than the continuity of Si present in the out-of-interface region 44 in the direction along the interface 41. The side margin portion 23 in this embodiment will be further described using FIG. 8 . However, since the first and second side margin portions 23a, 23b have the same configuration, the following description will focus on the first side margin portion 23a.

[0051] In the example of FIG. 8 , the first side margin 23a includes an interface region 42, an interface-adjacent region 43, and an off-interface region 44. The interface region 42 includes an interface 41 where the effective portion 21 and the first side margin 23a contact each other. The interface-adjacent region 43 is adjacent to the interface region 42 in the outward direction of the laminate 12. The off-interface region 44 is adjacent to the interface-adjacent region 43 in the outward direction of the laminate 12. That is, in the first side margin 23a, the interface region 42, the interface-adjacent region 43, and the off-interface region 44 are located adjacent to each other in this order in the outward direction of the laminate 12. The off-interface region 44 also includes a central portion 47 of the first side margin 23a in the direction from the effective portion 21 toward the first side margin 23a. In other words, the central portion 47 is the center of the first side margin 23a in the direction perpendicular to the direction along the interface 41. The extra-interface region 44 includes an outer surface region 45 and an extra-interface main region 46. The outer surface region 45 includes the outer surface of the laminate 12 and is located on the outer surface side of the laminate 12. The extra-interface main region 46 is the region of the extra-interface region 44 other than the outer surface region 45 and is located more inward of the laminate 12 than the outer surface region 45. The extra-interface main region 46 includes a central portion 47. The average thickness of the interface region 42 of the first side margin portion 23a is, for example, 1.06 μm or more and 1.12 μm or less. The average thickness of the interface-adjacent region 43 of the first side margin portion 23a is, for example, 3 μm or more and 5 μm or less.

[0052] As described above, the position, range, and Si continuity of each region 42, 43, 45, 46, etc. can be identified using visual inspection or a scale (reference dimensions, ruler, etc.) based on the results of measurement using a wavelength dispersive X-ray analyzer (WDX). For example, in FIG. 8B, the regions 42, 43, 45, 46, etc. and the Si continuity are identified as follows using visual inspection or a scale. In FIG. 8B, the region adjacent to the effective portion 21 on the outer side of the stack 12 and having continuous white regions containing Si is identified as the interface region 42. Furthermore, the region adjacent to the interface region 42 on the outer side of the stack 12 and having fewer and discontinuous white regions containing Si than the interface region 42 is identified as the interface-adjacent region 43. Furthermore, the region where the white regions containing Si are dispersed and the Si continuity is low is identified as the extra-interface main region 46. Further, the portion adjacent to the outer-interface main region 46 in the outer direction of the laminate 12 and having a continuous white region containing Si beyond the outer-interface main region 46 is identified as the outer surface region 45 .

[0053] The position, range, and Si continuity of each region 42, 43, 45, 43, etc. can also be identified by Si intensity. For example, the interface region 42 and the interface-adjacent region 43 can be identified as follows: First, the Si intensity in a portion of the first side margin 23a that can be considered the interface region 42 within a predetermined field of view is measured using WDX, for example, the ratio of the Si intensity to the Ba intensity (Si intensity / Ba intensity). The Si intensities of multiple sub-division regions (e.g., one pixel) within the portion that can be considered the interface region 42 are obtained, and their average is calculated. Whether Si is segregated in the portion of the first side margin 23a that can be considered the interface region 42 is determined based on this average. In other words, the average of the ratio of the Si intensity to the Ba intensity (Si intensity / Ba intensity) in the portion of the first side margin 23a that can be considered the interface region 42 within a predetermined field of view is calculated. In this embodiment, when the average value of the Si intensity / Ba intensity is, for example, 0.1 or more, it is determined that Si is segregated. The average value is, for example, 0.1 or more and 0.2 or less. In this way, the portion determined to have Si segregated can be identified as the interface region 42. Similarly, the Si intensity / Ba intensity is obtained in at least one sub-division region in the portion of the first side margin portion 23a that can be considered as the interface-adjacent region 43, and the average is obtained. Based on the result, it is determined whether Si is segregated, and the interface-adjacent region 43 can be identified. Note that the average value of the Si intensity / Ba intensity in the interface-adjacent region 43 is, for example, 0.05 or more and less than 0.10, and this is considered to be the absence of Si segregation in the definition of the present invention. The positions, ranges, and Si continuity of other regions, such as the outer surface region 45 and the outer-interface main region 46, can also be identified by the Si intensity / Ba intensity in the same manner as described above.

[0054] The first side margin portion 23a contains Si as an additive to the ceramic material. The Si exists as SiO in the first side margin portion 23a. The Si may be in the form of SiO or a low-viscosity liquid phase component containing SiO. The same applies hereinafter. Also, Si may be referred to as SiO, and SiO may be referred to as Si. In the interfacial region 42, Si exists substantially continuously along the interface 41. The continuity of Si in the interfacial region 42 along the interface 41 is greater than the continuity of Si in the extra-interface region 44 along the interface 41. In other words, the continuity of Si in the interfacial region 42 along the interface 41 is greater than the continuity of Si in the central portion 47 along the interface 41. In other words, the continuity of Si in the interfacial region 42 along the interface 41 is greater than the continuity of Si in the extra-interface region 46 along the interface 41.

[0055] 8B, the white regions are regions where Si exists. In FIG. 8B, Si exists continuously in the interface region 42, whereas Si exists dispersedly in the out-of-interface main region 46 (the region of the out-of-interface region 44 excluding the outer surface region 45), indicating that the continuity of Si is low.

[0056] In order to improve the adhesion between the effective portion 21 and the side margin portion 23, the continuity of Si in the interface region 42 is preferably 50% or more. In order to further improve the adhesion between the effective portion 21 and the side margin portion 23, the continuity of Si in the interface region 42 is more preferably 80% or more.

[0057] Furthermore, the Si content of the interface-adjacent region 43 may be smaller than the Si content of the interface region 42. As can be seen from (b) of Figure 8, the white area in the interface-adjacent region 43 is smaller and has a lower Si content than the interface region 42. Furthermore, the Si content of the interface-adjacent region 43 may be smaller than the Si content of the extra-interface region 44.

[0058] Here, the content of metal elements including compounds such as Ni and NiO in the extra-interface region 44 is smaller than the content of metal elements including compounds such as Ni and NiO in the interface region 42. In particular, when the main component of the internal electrode layer 16 is Ni, the Ni content in the extra-interface region 44 is smaller than the Ni content in the interface region 42. This is thought to be because the extra-interface region 44 is farther away from the first internal electrode layer 16a of the effective portion 21 than the interface region 42. Similarly, the content of metal elements including compounds such as Ni and NiO in the interface-adjacent region 43 is smaller than the content of metal elements including compounds such as Ni and NiO in the interface region 42. In particular, when the main component of the internal electrode layer 16 is Ni, the Ni content in the interface-adjacent region 43 is smaller than the Ni content in the interface region 42. This is thought to be because the interface-adjacent region 43 is farther away from the first internal electrode layer 16a of the effective portion 21 than the interface region 42.

[0059] The continuity of Si in the first side margin 23a can be determined, for example, as described above, as follows. The WT cross section is analyzed for the presence or absence of Si using, for example, WDX. By analyzing using WDX, the intensities of various components are detected for each of multiple divided regions in the WT cross section. Specifically, a predetermined field of view (here, referred to as one field of view) is divided into multiple divided regions using WDX, and intensity analysis is performed. The multiple divided regions are, for example, regions obtained by dividing the first side margin 23a into multiple regions in a direction perpendicular to the interface 41. In this embodiment, the first side margin 23a is divided in a direction perpendicular to the interface 41 and includes multiple divided regions arranged along the interface 41. Whether Si is present in the interface region 42 for each divided region is determined based on the Si intensity. Then, the continuity of Si is determined based on the proportion of the interface regions 42 containing Si among all the divided regions. Each divided region is a predetermined region of an image obtained using WDX, such as a plurality of pixels.

[0060] The continuity of Si in the first side margin portion 23a can be determined in the same manner as in FIG.

[0061] (2) External Electrodes As shown in FIGS. 1 to 5, external electrodes 30 are disposed on the first end face 12e side and the second end face 12f side of the laminate 12.

[0062] The external electrode 30 includes a first external electrode 30a and a second external electrode 30b.

[0063] The first external electrode 30a is connected to the first internal electrode layer 16a and is disposed on at least the surface of the first end face 12e. In this embodiment, the first external electrode 30a extends from the first end face 12e of the laminate 12 and is disposed on part of the first main surface 12a, part of the second main surface 12b, and part of the first side surface 12c, and part of the second side surface 12d. In this case, the first external electrode 30a is electrically connected to the first extraction electrode portion 28a of the first internal electrode layer 16a.

[0064] The second external electrode 30b is connected to the second internal electrode layer 16b and is disposed on at least the surface of the second end face 12f. In this embodiment, the second external electrode 30b extends from the second end face 12f and is disposed on a part of the first main face 12a, a part of the second main face 12b, and a part of the first side face 12c, and a part of the second side face 12d. In this case, the second external electrode 30b is electrically connected to the second extraction electrode portion 28b of the second internal electrode layer 16b.

[0065] The external electrode 30 includes a base electrode layer 32 containing a metal component and a plating layer 34 disposed on the base electrode layer 32. The first external electrode 30a includes a first base electrode layer 32a containing a metal component and a first plating layer 34a disposed on the first base electrode layer 32a. The second external electrode 30b includes a second base electrode layer 32b containing a metal component and a second plating layer 34b disposed on the second base electrode layer 32b.

[0066] (2-1) Base electrode layer

[0067] The first base electrode layer 32a is connected to the first internal electrode layer 16a and disposed on the surface of the first end face 12e. The first base electrode layer 32a also extends from the first end face 12e and is disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, and a portion of the first side surface 12c and a portion of the second side surface 12d. In this case, the first base electrode layer 32a is electrically connected to the first extraction electrode portion 28a of the first internal electrode layer 16a. The first base electrode layer 32a may be disposed only on the surface of the first end face 12e.

[0068] The second base electrode layer 32b is connected to the second internal electrode layer 16b and is disposed on the surface of the second end face 12f. The second base electrode layer 32b also extends from the second end face 12f and is disposed on part of the first main surface 12a, part of the second main surface 12b, and part of the first side surface 12c, and part of the second side surface 12d. In this case, the second base electrode layer 32b is electrically connected to the second extraction electrode portion 28b of the second internal electrode layer 16b. The second base electrode layer 32b may be disposed only on the surface of the second end face 12f.

[0069] (2-2) Plating Layer Next, the first plating layer 34a and the second plating layer 34b, which are the plating layers 34 disposed on the base electrode layer 32, will be described with reference to FIGS. 2 to 5. FIG.

[0070] The first plating layer 34a is disposed so as to cover the first base electrode layer 32a on the first end face 12e side. Furthermore, the first plating layer 34a may be disposed so as to cover the first base electrode layer 32a on the first main surface 12a, the second main surface 12b, the first side surface 12c, and the second side surface 12d side. However, the first plating layer 34a may be disposed only on the first base electrode layer 32a on the first end face 12e side.

[0071] The second plating layer 34b is disposed so as to cover the second base electrode layer 32b on the second end face 12f side. Furthermore, the second plating layer 34b may be disposed so as to cover the second base electrode layer 32b on the first principal surface 12a, the second principal surface 12b, the first side surface 12c, and the second side surface 12d side. However, the second plating layer 34b may be disposed only on the second base electrode layer 32b on the second end face 12f side.

[0072] The first plating layer 34a and the second plating layer 34b contain at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag--Pd alloy, Au, and the like.

[0073] The plating layer 34 may be formed of multiple layers. For example, the first plating layer 34a has a two-layer structure consisting of a first lower-layer plating layer and a first upper-layer plating layer covering the first lower-layer plating layer, and the second plating layer 34b has a two-layer structure consisting of a second lower-layer plating layer and a second upper-layer plating layer covering the second lower-layer plating layer. It is preferable that the first lower-layer plating layer and the second lower-layer plating layer are Ni plating layers, and the first upper-layer plating layer and the second upper-layer plating layer are Sn plating layers.

[0074] The first and second lower plating layers made of Ni are used to prevent the base electrode layer 32 from being eroded by solder when mounting the multilayer ceramic capacitor 10. The first and second upper plating layers made of Sn are used to improve the wettability of the solder when mounting the multilayer ceramic capacitor 10, thereby facilitating mounting.

[0075] The first and second lower plating layers made of Ni are preferably 1 μm or more and 15 μm or less, and the first and second upper plating layers made of Sn are preferably 1 μm or more and 15 μm or less.

[0076] Each of the first and second external electrodes 30a, 30b may not be provided with a base electrode layer 32, and the plating layer 34 may be formed directly on the surface of the laminate 12. That is, the multilayer ceramic capacitor 10 may have a structure in which the first end face 12e and the second end face 12f are plated to form a plating layer 34 electrically connected to the first internal electrode layer 16a or the second internal electrode layer 16b. In such a case, the plating layer 34 may be formed by plating after a catalyst is disposed on the surface of the laminate 12 as a pretreatment.

[0077] In addition, when the plating layer 34 is formed directly on the laminate 12 without providing the base electrode layer 32, the amount of the reduction in the thickness of the base electrode layer 32 can be converted into a lower profile, i.e., a thinner laminate, or into the thickness of the laminate, i.e., the thickness of the effective portion 21, thereby improving the design freedom of the thickness of the laminate 12.

[0078] (3) Dimensions of the Multilayer Ceramic Capacitor The dimension in the length direction z (L dimension), the dimension in the height direction x (T dimension), and the dimension in the width direction y (W dimension) of the multilayer ceramic capacitor 10 are not particularly limited.

[0079] 2. Manufacturing Method of Multilayer Ceramic Capacitor Next, a manufacturing method of a multilayer ceramic capacitor will be described. In Fig. 9, (a) to (e) are diagrams for explaining the manufacturing method of the multilayer ceramic capacitor of this embodiment. Fig. 10 is a schematic diagram showing the state in which ceramic sheets for effective portions coated with conductive paste for internal electrode layers are stacked.

[0080] (1) Formation of Laminated Chip (Unfired Laminated Chip) First, a perovskite compound containing Ba and Ti is prepared as a dielectric ceramic material. A ceramic paste for the effective portion is prepared by mixing a dielectric powder obtained from this dielectric ceramic material with additives such as Si, an organic binder, an organic solvent, a plasticizer, and a dispersant in a predetermined ratio. The ceramic paste for the effective portion contains, for example, 0.8 mol to 2.0 mol of Si per 100 mol of Ti.

[0081] Ceramic pastes for the invalid portions (ceramic paste for the outer layer, ceramic paste for the side margin, ceramic paste for the interface) are prepared in the same manner as the ceramic paste for the valid portion.

[0082] The ceramic paste for the outer layer and the ceramic paste for the side margin contain, for example, 1.0 mol to 4.0 mol of Si per 100 mol of Ti. The ceramic paste for the interface used at the interface between the valid portion 21 and the invalid portion 24 is adjusted so that the Si content is higher than that of the ceramic paste for the valid portion, the ceramic paste for the outer layer, and the ceramic paste for the side margin. The ceramic paste for the interface contains, for example, 5.0 mol to 10.0 mol of Si per 100 mol of Ti.

[0083] Furthermore, a conductive paste for the internal electrode layers is prepared by mixing a conductive metal for the internal electrode layers, an organic binder, an organic solvent, an additive, and the like in a predetermined ratio.

[0084] Various ceramic pastes are applied to the surfaces of multiple resin films (not shown) to form ceramic sheets 50 (50a, 50b). Specifically, the ceramic paste for the effective portion is applied to the surface of the resin film and dried to form the ceramic sheet for the effective portion 50a. The thickness of the ceramic sheet for the effective portion 50a is, for example, 0.5 μm to 2.0 μm. Furthermore, the ceramic paste for the invalid portion is applied to the surface of the resin film and dried to form the ceramic sheets for the invalid portion 50b (the ceramic sheet for the outer layer 50b1, the ceramic sheet for the side margin 50b2, and the ceramic sheet for the interface 50b3). The thickness of the ceramic sheet for the outer layer 50b1 and the ceramic sheet for the side margin 50b2 is, for example, 20 μm to 30 μm. The thickness of the ceramic sheet for the interface 50b3 is, for example, 5.0 μm to 8.0 μm.

[0085] Next, as shown in Fig. 9(a), a predetermined number of outer layer ceramic sheets 50b1 are stacked while peeled from the resin film. Next, as shown in Fig. 9(b), an interface ceramic sheet 50b3 is stacked on top of the outer layer ceramic sheets 50b1 while peeled from the resin film. These multiple outer layer ceramic sheets 50b1 and interface ceramic sheets 50b3 are stacked and fired to form the second outer layer portion 22b.

[0086] Next, as shown in FIG. 9C , the ceramic sheet 50a for the effective portion 21 is laminated, peeled from the resin film, on the ceramic sheets 50b1 and 50b3 for the outer and interface layers, which will become the second outer layer portion 22b. A conductive paste 51 for the internal electrode layers is applied (printed) to the ceramic sheet 50a for the effective portion. The conductive paste 51 for the internal electrode layers on the ceramic sheet 50a for the effective portion is dried to form a conductive film. At this time, as shown in FIG. 10 , adjacent ceramic sheets 50a for the effective portion, each having a conductive film formed thereon, are laminated in a shifted state relative to each other. This results in the effective portion 21, before firing, having multiple ceramic sheets 50a for the effective portion, each having a conductive film formed thereon, which will become the first and second internal electrode layers 16a and 16b. Various printing methods, such as screen printing, inkjet printing, and gravure printing, can be used.

[0087] Next, as shown in Figure 9(d), the interface ceramic sheet 50b3 is peeled off from the resin film and stacked on top of the uppermost effective ceramic sheet 50a on which the conductive film is formed. Furthermore, a predetermined number of outer layer ceramic sheets 50b1 are stacked on top of that. This results in a laminated sheet. By stacking and firing multiple outer layer ceramic sheets 50b1 and interface ceramic sheets 50b3, the first outer layer portion 22a can be formed.

[0088] Next, the laminated sheets are pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0089] The laminated block is then cut to a predetermined size to cut out the unfired laminated portion 20 (a laminate of the unfired effective portion 21 and the unfired outer layer portion 22). At this time, the corners and ridges of the unfired laminated portion 20 may be rounded by barrel polishing or the like.

[0090] Only the conductive film that will become the first internal electrode layer 16a is exposed on one end face of the unsintered laminated part 20 obtained by the above process.On the other end face, only the conductive film that will become the second internal electrode layer 16b is exposed.Furthermore, on both side faces of the unsintered laminated part 20, the conductive films that will become the first and second internal electrode layers 16a, 16b are exposed, respectively.

[0091] (2) Formation of Side Margins Next, a procedure for forming the first and second side margins 23a and 23b will be described.

[0092] As described above, the interface ceramic paste is applied to the surface of the resin film and dried to form the interface ceramic sheet 50b3, and the side margin ceramic paste is applied to the surface of the resin film and dried to form the side margin ceramic sheet 50b2.

[0093] Next, the interface ceramic sheet 50b3 and the plurality of side margin ceramic sheets 50b2 are peeled off from the resin film.

[0094] Next, as shown in FIG. 9E, an interface ceramic sheet 50b3 is laminated on the side of the unsintered laminate 20 where the conductive film is exposed, and multiple side margin ceramic sheets 50b2 are laminated on top of that. The ceramic sheets 50b3 and 50b2 are pressed against and punched out while facing the side of the unsintered laminate 20 where the conductive film is exposed. The interface ceramic sheet 50b3 and multiple side margin ceramic sheets 50b2 are stacked and fired to form the first side margin 23a. Furthermore, the interface ceramic sheet 50b3 is laminated on the side of the unsintered laminate 20 where the layer that will become the first side margin 23a is not formed, and multiple side margin ceramic sheets 50b2 are further laminated on top of that. The ceramic sheets 50b3 and 50b2 are pressed against and punched out while facing the side of the unsintered laminate 20 where the conductive film is exposed. The interface ceramic sheet 50b3 and the multiple side margin ceramic sheets 50b2 are stacked and fired to form the second side margin portion 23b. At this time, it is preferable to apply an organic solvent to the side surface of the unfired laminate portion 20 in advance as an adhesive.

[0095] Next, the laminated chip 55, on which the layers that will become the first and second side margin portions 23a, 23b have been formed, is subjected to a degreasing process (a degreasing process for laminated chips) and degreased under predetermined conditions. The degreasing process is preferably performed in a mixed atmosphere of N2 / H2 / H2O, for example. The degreasing process is performed, for example, by sequentially performing low-temperature degreasing and high-temperature degreasing. The low-temperature degreasing is performed, for example, at a temperature of 250°C to 300°C, at a heating rate of 0.15°C / min to 0.25°C / min, and for a low-temperature time of 300 minutes, although this is not limited thereto. The high-temperature degreasing is performed, for example, at a temperature of 800°C, at a heating rate of 3.0°C / min to 3.5°C / min, and for a high-temperature time of 200 minutes, although this is not limited thereto.

[0096] Thereafter, the laminated chip 55 is put into a firing process (a firing process for laminated chips) and fired at a predetermined temperature to obtain a sintered laminate 12. The firing temperature depends on the materials of the ceramic layers and the internal electrode layers, but is preferably 1200°C or higher and 1250°C or lower.

[0097] In addition, the portions that can become the first and second side margin portions 23a, 23b may be formed by applying ceramic paste for the interface and ceramic paste for the side margins to both sides of the laminated chip 55 where the conductive film is exposed.

[0098] That is, an interface ceramic paste is applied to both sides of the laminated chip 55 where the conductive film is exposed, and then dried to form an interface ceramic sheet 50b3. Furthermore, a side margin ceramic paste is applied to the surface of the interface ceramic sheet 50b3, and then dried to form a side margin ceramic sheet 50b2.

[0099] Furthermore, the portions that can become the first and second side margin portions 23a, 23b may be formed by masking both end surfaces of the laminate portion 20 with resin or the like, dipping the entire laminate portion 20 in an interface ceramic paste, drying, and then dipping it again in a side margin ceramic paste and drying. In this case, the interface ceramic sheet 50b3 and the side margin ceramic sheet 50b2 are formed in this order on both side surfaces of the laminate portion 20. (3) Formation of External Electrodes

[0100] Next, the external electrodes 30 including the base electrode layer 32 and the plating layer 34 are formed on the laminate 12. First, a conductive paste for the external electrodes, mainly composed of Cu, for example, is applied to both end faces 12e, 12f, etc. of the laminate 12. The laminate 12 is then fired in a firing process for the external electrodes, thereby forming the base electrode layer 32.

[0101] Next, a plating layer 34 is formed. The plating layer 34 may be formed on the surface of the base electrode layer 32, or may be formed directly on the laminate 12. In this embodiment, the plating layer 34 is formed on the surface of the base electrode layer 32. In this case, after the base electrode layer 32 is formed, the plating layer 34 is formed on the surface of the base electrode layer 32. More specifically, a Ni plating layer and a Sn plating layer are formed on the base electrode layer 32. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating. As a plating method, barrel plating is preferably used.

[0102] In this manner, the multilayer ceramic capacitor 10 shown in FIG. 1 is manufactured.

[0103] 3. Effects According to the multilayer ceramic capacitor 10 described above, the continuity of Si (SiO2) in the interface region 42 is greater than the continuity of Si in the extra-interface region 44. That is, Si is present more continuously in the interface region 42 between the valid portion 21 and the invalid portion 24. The more continuous presence of Si in the interface region 42 improves the adhesion between the valid portion 21 and the invalid portion 24. This makes it possible to prevent the invalid portion 24 from peeling off from the valid portion 21, thereby providing a multilayer ceramic capacitor 10 that can prevent a decrease in reliability. Note that in this embodiment, Si is present mainly as SiO2.

[0104] The reason for the improved adhesion between the valid portion 21 and the invalid portion 24 will now be explained. The reason for the improved adhesion is thought to be, but is not limited to, the following phenomenon. The valid portion 21 before firing is formed by laminating ceramic sheets 50a for the valid portion coated with conductive paste 51 for the internal electrode layers. The invalid portion 24 before firing is formed by laminating ceramic sheets 50b for the invalid portion. The invalid portion 24 before firing (ceramic sheets 50b for the invalid portion: ceramic sheets 50b for the outer layer, ceramic sheets 50b1 for the side margin, and ceramic sheets 50b3 for the interface) is integrated with the valid portion 21 before firing so as to cover at least a portion of the valid portion 21 before firing, forming a laminated chip 55 (pre-fired laminate 12). This laminated chip 55 undergoes a degreasing process and a firing process to become the laminate 12 (pre-fired laminate 12). During at least one of the degreasing and firing processes, resin components are removed from the ceramic sheet 50b for the invalid portion, leaving behind the main component BaTiO3 powder and the like. Therefore, gaps may be generated between the BaTiO3 powder and the like due to the removal of the resin components. Therefore, gaps may also be generated at the interface 41 between the valid portion 21 and the invalid portion 24. In the multilayer ceramic capacitor 10 according to this embodiment, such gaps are generally absent in the interface region 42. Instead, Si is continuously present along the interface 41 in the interface region 42. In other words, in the interface region 42 between the internal electrode layer 16 at the outermost surface (or outermost end) of the valid portion 21 and the invalid portion 24, continuous gaps are generally absent along the interface 41, and Si is continuously present along the interface 41. It is believed that Si largely fills the gaps, improving the adhesion between the valid portion 21 and the invalid portion 24 compared to when continuous gaps are present in the interface region 42. This makes it possible to prevent the ineffective portion 24 from peeling off from the effective portion 21, and as a result, it is possible to prevent a decrease in the reliability of the multilayer ceramic capacitor 10.

[0105] Furthermore, when the occurrence of gaps and the presence of Si in the gaps are examined separately for the degreasing process and the firing process, the following behavior may occur during the manufacturing process of the multilayer ceramic capacitor 10, although this is not limited thereto. In the pre-fired laminate 12, the removal of resin components through the degreasing process may result in continuous gaps along the interface 41 between the valid portion 21 and the invalid portion 24. Specifically, the degreasing process removes resin components from the invalid portion ceramic sheets 50b (the invalid portion ceramic sheets 50: the outer layer ceramic sheet 50b1, the side margin ceramic sheet 50b2, and the interface ceramic sheet 50b3), which may result in continuous gaps along the interface 41 between the invalid portion ceramic sheets 50b and the conductive layer for the internal electrode layer on the outermost surface (or outermost edge) of the valid portion 21. By firing this pre-fired laminate 12 in the firing process, the metal powder of the conductive paste 51 for the internal electrode layer and the ceramic powder of the valid portion and invalid portion ceramic sheets 50a, 50b are sintered to form metal particles and ceramic particles. Furthermore, it is believed that during this firing process, Si in the invalid portion ceramic sheet 50b melts and fluidizes, and migrates into the gaps in the interface region 42. In this embodiment, it is believed that Si mainly in the interface ceramic sheet 50b3 melts and fluidizes, and migrates into the gaps in the interface region 42. Therefore, it is believed that through the firing process, the gaps in the interface region 42 are largely filled with Si, improving the adhesion between the valid portion 21 and the invalid portion 24. Note that at least a portion of the Si that was present in the interface-adjacent region 43 migrates into the gaps in the interface region 42 during the firing process, and therefore the Si content in the interface-adjacent region 43 is believed to be lower than that in the interface region 42.

[0106] In the above embodiment, the interface region 42 is located closer to the effective portion 21 than the central portion 47 of the invalid portion 24. Since the continuity of Si is high in the interface region 42 close to the effective portion 21, the adhesion between the effective portion 21 and the invalid portion 24 can be improved.

[0107] Furthermore, the outer surface region 45 is located on the outer surface side of the laminate 12, and Si may also be present continuously in this outer surface region 45. Even in such a case, the continuity of Si in the interface region 42 is greater than the continuity of Si in the extra-interface main region 46 of the extra-interface region 44 excluding the outer surface region 45. In other words, Si is present more continuously in the interface region 42 between the valid portion 21 and the invalid portion 24. Therefore, peeling of the invalid portion 24 from the valid portion 21 can be suppressed.

[0108] 4. Experimental Examples Multilayer ceramic capacitors of examples and comparative examples were fabricated as the multilayer ceramic capacitor 10. Then, the interfacial peeling rate of the ineffective portion 24 from the effective portion 21 was evaluated.

[0109] A. Sample Preparation A laminate 12 was fabricated as a sample of the example by the above-described manufacturing method. In particular, in the example, when forming the first and second outer layer portions 22a, 22b, the outer layer ceramic sheet 50b1 was stacked on the effective portion 21 before firing, with the interface ceramic sheet 50b3 stacked on top of it. Furthermore, when forming the first and second side margin portions 23a, 23b, the side margin ceramic sheet 50b2 was stacked on the laminate portion 20 (effective portion 21 and outer layer portion 22) with the interface ceramic sheet 50b3 stacked on top of it.

[0110] As a comparative example, a laminate 12 was fabricated using the above-described manufacturing method, except that an interface ceramic sheet 50b3 was stacked. In other words, the interface ceramic sheet 50b3 was not used in the comparative example. When forming the first and second outer layer portions 22a, 22b, an outer layer ceramic sheet 50b1 was stacked on the effective portion 21 before firing. Furthermore, when forming the first and second side margin portions 23a, 23b, a side margin ceramic sheet 50b2 was stacked on the laminate portion 20.

[0111] B. Evaluation of Samples One hundred multilayer ceramic capacitors were prepared as an example, and one hundred multilayer ceramic capacitors were prepared as a comparative example. The appearance of the samples was observed to determine whether cracks, peeling, etc. occurred at the interface 41 between the valid portion 21 and the invalid portion 24. Those with cracks, peeling, etc. were counted as the number of peelings, and the interface peeling rate per 100 samples was calculated.

[0112] Table 1 shows the results of the interfacial peeling rate for the examples and comparative examples.

[0113]

[0114] C. Experimental Results In the example, the rate of interface peeling between the effective and ineffective portions was 0%, meaning no peeling occurred. When the example sample was observed with WDX, continuous segregation of Si was observed in the interface region. The continuity of Si was approximately 80%.

[0115] On the other hand, in the comparative example, the peeling rate at the interface between the effective and ineffective portions was 20%, and peeling had occurred. When the comparative example sample was observed with WDX, no continuous segregation of Si was observed in the interface region.

[0116] From the above, it was found that continuous segregation of Si in the interface region can suppress peeling of the ineffective portion from the effective portion.

[0117] As described above, although the embodiments of the present invention have been disclosed in the above description, the present invention is not limited thereto. In other words, various modifications can be made to the above-described embodiments in terms of mechanism, shape, material, quantity, position, arrangement, etc., without departing from the scope of the technical idea and purpose of the present invention, and such modifications are included in the present invention.

[0118] <Modifications> (1) In the above embodiment, the invalid portion 24 includes the interface-adjacent region 43. However, if the continuous presence of Si in the interface region 42 can improve the adhesion between the valid portion 21 and the invalid portion 24, the invalid portion 24 does not need to include the interface-adjacent region 43. Similarly, in the above embodiment, the extra-interface region 44 includes the outer surface region 45. However, if the continuous presence of Si in the interface region 42 can improve the adhesion between the valid portion 21 and the invalid portion 24, the extra-interface region 44 does not need to include the outer surface region 45.

[0119] (2) In the above embodiment, Si is continuously present in the interface region 42 in both the outer layer portion 22 and the side margin portion 23. However, Si may be continuously present in the interface region 42 of either the outer layer portion 22 or the side margin portion 23. For example, the continuity of Si in the interface region 42 of the outer layer portion 22 may be greater than the continuity of Si in the out-of-interface region 44 of the outer layer portion 22. This can improve the adhesion between the effective portion 21 and the outer layer portion 22. Furthermore, for example, the continuity of Si in the interface region 42 of the side margin portion 23 may be greater than the continuity of Si in the out-of-interface region 44 of the side margin portion 23. This can improve the adhesion between the effective portion 21 and the side margin portion 23.

[0120] (3) In the above embodiment, the multilayer ceramic capacitor 10 is formed by disposing the interface ceramic sheet 50b3, which has a higher Si content than the outer layer and side margin ceramic sheets 50b1 and 50b2, in the interface region 42 or nearby the interface region 42 to enhance the Si continuity in the interface region 42. However, a multilayer ceramic capacitor 10 with high Si continuity in the interface region 42 may be formed, for example, by adjusting the atmosphere in at least one of the degreasing process and the firing process for the laminate chip. In this case, the process of preparing the interface ceramic paste and disposing the interface ceramic sheet 50b3 can be omitted from the manufacturing method of the multilayer ceramic capacitor in the above embodiment. Note that the Si content in the effective ceramic paste, the outer layer and side margin ceramic paste, the thickness of the effective ceramic sheet 50a, and the outer layer and side margin ceramic sheets 50b1 and 50b2, and the like can be similar to those in the above embodiment.

[0121] Furthermore, in the manufacturing method of the above embodiment, first, the laminated portion 20 having the effective portion 21 and the outer layer portion 22 is formed, and then the side margin portion 23 is formed on the unfired laminated portion 20 to form the laminate 12. The manufacturing process is not limited as long as Si is continuously present in the interface region 42. For example, the unfired laminated chip 55 may be produced by simultaneously arranging the unfired outer layer portion 22 and the unfired side margin portion 23 on the unfired effective portion 21.

[0122] (4) In the above embodiment, a two-terminal multilayer ceramic capacitor having two terminals, a first external electrode 30a and a second external electrode 30b, has been described as the multilayer ceramic capacitor. However, the scope of application of the present invention is not limited to two-terminal multilayer ceramic capacitors. The present invention is applicable to multilayer ceramic capacitors having a laminate with an active portion and an inactive portion and external electrodes. Therefore, the present invention may also be applied to, for example, a three-terminal multilayer ceramic capacitor. A three-terminal multilayer ceramic capacitor includes a laminate 12 similar to the above embodiment and first to fourth external electrodes. The internal electrode layers 16 include a first internal electrode layer extending to the first end face 12e and the second end face 12f, and a second internal electrode layer extending to the first side face 12c and the second side face 12d. A first external electrode is disposed on the first end face 12e of the laminate 12. The first external electrode is electrically connected to the first internal electrode layer exposed at the first end face 12e of the laminate 12. A second external electrode is disposed on the second end face 12f of the laminate 12. The second external electrode is electrically connected to the first internal electrode layer exposed at the second end face 12f of the laminate 12. A third external electrode is disposed on the first side face 12c of the laminate 12. The third external electrode is electrically connected to the second internal electrode layer exposed at the first side face 12c of the laminate 12. A fourth external electrode is disposed on the second side face 12d of the laminate 12. The fourth external electrode is electrically connected to the second internal electrode layer exposed at the second side face 12d of the laminate 12.

[0123] (5) In the above embodiment, the multilayer ceramic capacitor 10 in which Si is continuously present in the interface region 42 between the active portion 21 and the inactive portion 24 has been described as an example. The present invention is also applicable to the following electronic components. When a piezoelectric ceramic material is used for the ceramic layers 14, the multilayer ceramic capacitor functions as a piezoelectric component. Specific examples of piezoelectric ceramic materials include PZT (lead zirconate titanate) ceramic materials. When a semiconductor ceramic material is used for the ceramic layers 14, the multilayer ceramic capacitor functions as a thermistor. Specific examples of semiconductor ceramic materials include spinel ceramic materials. When a magnetic ceramic material is used for the ceramic layers 14, the multilayer ceramic capacitor functions as an inductor. When functioning as an inductor, the internal electrode layers 16 become coil-shaped conductors. Specific examples of magnetic ceramic materials include ferrite ceramic materials.

[0124] <1> A multilayer ceramic capacitor comprising: a laminate including: an effective portion in which a plurality of ceramic layers and a plurality of internal electrode layers are alternately stacked; and an ineffective portion in which one or a plurality of ceramic layers are stacked and which covers at least a part of the effective portion; and an external electrode formed on an outer surface of the laminate and connected to the internal electrode layer, wherein the ineffective portion includes an interface region including an interface between the effective portion and the ineffective portion, and an extra-interface region located outward of the laminate with respect to the interface region, and the continuity of Si existing in the interface region in a direction along the interface is greater than the continuity of Si existing in the extra-interface region in a direction along the interface.

[0125] <2> The multilayer ceramic capacitor according to <1>, wherein the out-of-interface region includes a central portion of the invalid portion in a direction from the valid portion side toward the invalid portion side, and continuity of Si existing in the direction along the interface in the interface region is greater than continuity of Si existing in the direction along the interface in the central portion.

[0126] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein the ineffective portion further includes an interface-adjacent region adjacent to the interface region in an outer direction of the laminate, and the Si content in the interface-adjacent region is smaller than the Si content in the interface region.

[0127] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein the out-of-interface region includes an outer surface region that includes an outer surface of the laminate and is located on the outer surface side of the laminate, and an out-of-interface main region that is a region other than the outer surface region and is located on the laminate side, and wherein continuity of Si existing in the interface region in a direction along the interface is greater than continuity of Si existing in the out-of-interface main region in a direction along the interface.

[0128] <5> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein the content of the metal element including Ni in the extra-interface region is smaller than the content of the metal element including Ni in the interface region.

[0129] <6> The multilayer ceramic capacitor according to any one of <1> to <5>, wherein the ineffective portion includes a plurality of divided regions that are divided into a plurality of pieces in a direction perpendicular to the interface and that are arranged in a direction along the interface, and the continuity of Si in the interface region is represented by a ratio of the divided regions in which Si is present in the interface region among the plurality of divided regions, and the continuity of Si in the extra-interface region is represented by a ratio of the divided regions in which Si is present in the extra-interface region among the plurality of divided regions.

[0130] <7> The multilayer ceramic capacitor according to <6>, wherein a divided region among the plurality of divided regions in which Si is present in the interface region includes a portion in which an index of Si content, which is indicated by a ratio of Si intensity to Ba intensity or a ratio of Si content to Ba content, is 0.1 or more.

[0131] <8> The multilayer ceramic capacitor according to <6> or <7>, wherein a divided region among the plurality of divided regions in which Si is present in the interface region includes a portion where an index of Ni content, which is indicated by a ratio of Ni intensity to Ba intensity or a ratio of Ni content to Ba content, becomes 0.2 or less for the first time from the effective portion side to the ineffective portion side.

[0132] <9> The multilayer ceramic capacitor according to any one of <1> to <8>, wherein the continuity of Si in the interface region is 80% or more.

[0133] <10> The multilayer ceramic capacitor according to any one of <1> to <9>, wherein the internal electrode layers have internal electrode surfaces along a planar direction and internal electrode ends that are ends in the planar direction, the ineffective portion includes an outer layer portion adjacent to an internal electrode surface of an internal electrode layer located at an outermost surface among the internal electrode layers of the effective portion, and a side margin portion adjacent to the internal electrode end, and in at least one of the outer layer portion and the side margin portion, continuity of Si existing in the direction along the interface in the interface region is greater than continuity of Si existing in the direction along the interface in the out-of-interface region.

[0134] REFERENCE SIGNS LIST 10: Multilayer ceramic capacitor 12: Laminate 12a, 12b: First and second main surfaces 12c, 12d: First and second side surfaces 12e, 12f: First and second end surfaces 14: Ceramic layer 16: Internal electrode layer 16a, 16b: First and second internal electrode layer 20: Laminate portion 21: Effective portion 22: Outer layer portion 22a, 22b: First and second outer layer portion 23: Side margin portion 23a, 23b: First and second side margin portion 24: Ineffective portion 26a, 26b: First and second opposing electrode portions 28a, 28b: First and second extraction electrode portions 30: External electrode 30a, 30b: First and second external electrode 32 : Base electrode layer 32a, 32b: First and second base electrode layer 34: Plating layer 34a, 34b: First and second plating layer 41: Interface 42: Interface region 43: Interface adjacent region 44: Outer interface region 45: Outer surface region 46: Outer interface main region 47: Center portion 50: Ceramic sheet 50a: Ceramic sheet for effective portion 50b: Ceramic sheet for ineffective portion 50b1: Ceramic sheet for outer layer 50b2: Ceramic sheet for side margin 50b3: Ceramic sheet for interface 51: Conductive paste for internal electrode layer 55: Laminated chip C1 to Cn: Divided region G1, G2, G3, G4...: GroupR1 to R12: Sub-divided regions x: Height direction y: Width direction z: Length direction

Claims

1. A multilayer ceramic capacitor comprising: a laminate including an effective portion in which a plurality of ceramic layers and a plurality of internal electrode layers are alternately stacked; and an ineffective portion in which one or more ceramic layers are stacked and which covers at least a part of the effective portion; and external electrodes formed on the outer surface of the laminate and connected to the internal electrode layers, wherein the ineffective portion includes an interface region including the interface between the effective portion and the ineffective portion, and an extra-interface region located outside the laminate with respect to the interface region, and the continuity of Si existing in the interface region in a direction along the interface is greater than the continuity of Si existing in the extra-interface region in a direction along the interface.

2. The multilayer ceramic capacitor according to claim 1, wherein the out-of-interface region includes a central portion of the ineffective portion in a direction from the effective portion side toward the ineffective portion side, and the continuity of Si existing in the direction along the interface in the interfacial region is greater than the continuity of Si existing in the direction along the interface in the central portion.

3. A multilayer ceramic capacitor according to claim 1 or 2, wherein the ineffective portion further includes an interface-adjacent region adjacent to the interface region in an outward direction of the laminate, and the Si content in the interface-adjacent region is smaller than the Si content in the interface region.

4. A multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the extra-interface region includes an outer surface region that includes the outer surface of the laminate and is located on the outer surface side of the laminate, and an extra-interface main region that is a region other than the outer surface region and is located on the laminate side, and the continuity of Si existing in the interface region in a direction along the interface is greater than the continuity of Si existing in the extra-interface main region in a direction along the interface.

5. A multilayer ceramic capacitor according to any one of claims 1 to 4, wherein the content of metal elements including Ni in the extra-interface region is smaller than the content of metal elements including Ni in the interface region.

6. A multilayer ceramic capacitor according to any one of claims 1 to 5, wherein the ineffective portion includes a plurality of divided regions that are divided into a plurality of pieces in a direction perpendicular to the interface and that are arranged in a direction along the interface, the continuity of Si in the interface region is represented by the proportion of divided regions among the plurality of divided regions in which Si exists in the interface region, and the continuity of Si in the extra-interface region is represented by the proportion of divided regions among the plurality of divided regions in which Si exists in the extra-interface region.

7. The multilayer ceramic capacitor according to claim 6, wherein the divided regions among the plurality of divided regions in which Si is present in the interface region include a portion in which an index of Si content, expressed by the ratio of Si intensity to Ba intensity or the ratio of Si content to Ba content, is 0.1 or more.

8. A multilayer ceramic capacitor according to claim 6 or 7, wherein a divided region among the plurality of divided regions in which Si is present in the interface region includes a portion where an index of Ni content, indicated by the ratio of Ni intensity to Ba intensity or the ratio of Ni content to Ba content, becomes 0.2 or less for the first time from the effective portion side to the ineffective portion side.

9. A multilayer ceramic capacitor according to any one of claims 1 to 8, wherein the continuity of Si in the interface region is 80% or more.

10. A multilayer ceramic capacitor according to any one of claims 1 to 9, wherein the internal electrode layers have internal electrode surfaces along a planar direction and internal electrode ends that are ends in the planar direction, the ineffective portion includes an outer layer portion adjacent to the internal electrode surface of the internal electrode layer located on the outermost surface of the internal electrode layers of the effective portion, and a side margin portion adjacent to the internal electrode end, and in at least one of the outer layer portion and the side margin portion, the continuity of Si existing in the direction along the interface in the interface region is greater than the continuity of Si existing in the direction along the interface in the out-of-interface region.

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