Production method for semiconductor device

Abstract

According to the present invention, a production method for a semiconductor device includes a step for preparing a layered wafer that includes a receiver wafer and a donor wafer, a step for forming a bevel part at one or both of a corner part of the receiver wafer and a corner part of the donor wafer, and a step for forming a device structure on the donor wafer side.

Description

Semiconductor device manufacturing method

[0001] This application claims priority from Patent Application No. 2024-014225 filed with the Japan Patent Office on February 1, 2024, the entire contents of which are incorporated herein by reference. The present disclosure relates to a method for manufacturing a semiconductor device.

[0002] Patent Document 1 (US 2019 / 244853 A1) discloses a method for manufacturing a semiconductor component, including a step of providing a wafer composite. The wafer composite includes an auxiliary substrate, a donor substrate, and a sacrificial layer interposed between the auxiliary substrate and the donor substrate. The auxiliary substrate is separated from the donor substrate after a step of forming functional elements on the donor substrate.

[0003] US Patent Application Publication No. 2019 / 244853

[0004] SUMMARY The present disclosure provides a novel method for manufacturing a semiconductor device.

[0005] The present disclosure provides a method for manufacturing a semiconductor device, including a step of preparing a stacked wafer including a receiver wafer and a donor wafer, a step of forming a bevel portion on either or both of a corner of the receiver wafer and a corner of the donor wafer, and a step of forming a device structure on the donor wafer side.

[0006] The present disclosure provides a method for manufacturing a semiconductor device, including a step of preparing a stacked wafer including a receiver wafer having a bevel portion and a donor wafer, and a step of forming a device structure on the donor wafer side.

[0007] The present disclosure provides a semiconductor device including a first semiconductor layer, a second semiconductor layer made of a different material from the first semiconductor layer and stacked on the first semiconductor layer, and a third semiconductor layer made of a different material from the first semiconductor layer and stacked on the second semiconductor layer.

[0008] The above and other objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0009] FIG. 1 is a plan view showing a receiver wafer according to the first embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a plan view showing a base wafer according to the first embodiment. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 3. FIG. 5 is a process diagram showing a method for manufacturing a semiconductor device according to the first embodiment. FIG. 6A is a cross-sectional view related to the process diagram of FIG. 5. FIG. 6B is a cross-sectional view related to the process diagram of FIG. 5. FIG. 6C is a cross-sectional view related to the process diagram of FIG. 5. FIG. 6D is a cross-sectional view related to the process diagram of FIG. 5. FIG. 6E is a cross-sectional view related to the process diagram of FIG. 5. FIG. 6F is a cross-sectional view related to the process diagram of FIG. 5. FIG. 6G is a cross-sectional view related to the process diagram of FIG. 5. FIG. 6H is a cross-sectional view related to the process diagram of FIG. 5. FIG. 6I is a cross-sectional view related to the process diagram of FIG. 5. FIG. 6J is a cross-sectional view related to the process diagram of FIG. 5. FIG. 6K is a cross-sectional view related to the process diagram of FIG. 5. FIG. 6L is a cross-sectional view related to the process diagram of FIG. 5. FIG. 6M is a cross-sectional view related to the process diagram of FIG. 5. 6N is a cross-sectional view related to the process diagram of FIG. 5. FIG. 6O is a cross-sectional view related to the process diagram of FIG. 5. FIG. 7 is a plan view showing a device region. FIG. 8 is an enlarged cross-sectional view of a bevel portion according to a first example. FIG. 9 is an enlarged cross-sectional view showing a stacked wafer and an epitaxial layer. FIG. 10A is an enlarged cross-sectional view of a bevel portion according to a second example. FIG. 10B is an enlarged cross-sectional view of a bevel portion according to a third example. FIG. 10C is an enlarged cross-sectional view of a bevel portion according to a fourth example. FIG. 10D is an enlarged cross-sectional view of a bevel portion according to a fifth example. FIG. 10E is an enlarged cross-sectional view of a bevel portion according to a sixth example. FIG. 11 is a plan view showing a receiver wafer according to a second embodiment. FIG. 12 is a cross-sectional view taken along line XII-XII shown in FIG. 11. FIG. 13 is an enlarged cross-sectional view showing an edge of the receiver wafer shown in FIG. 11. FIG. 14 is a plan view showing a base wafer according to a second embodiment. FIG. 15 is a cross-sectional view taken along line XV-XV shown in FIG. 14. Fig. 16 is a process diagram showing a method for manufacturing a semiconductor device according to the second embodiment. Fig. 17 is a cross-sectional view showing a bonding step according to the second embodiment. Fig. 18 is an enlarged cross-sectional view showing an edge of the laminated wafers according to the second embodiment. Fig. 19 is a cross-sectional view showing a bonding step according to a modified example. Fig. 20 is an enlarged cross-sectional view showing an edge of the laminated wafers according to a modified example.21 is a plan view showing a first semiconductor device. FIG. 22 is a cross-sectional view taken along line XXII-XXII shown in FIG. 21. FIG. 23 is a plan view showing an example of a layout of the device surface. FIG. 24 is a cross-sectional view taken along line XXIV-XXIV shown in FIG. 21. FIG. 25 is a cross-sectional view taken along line XXV-XXV shown in FIG. 21. FIG. 26 is a plan view showing a second semiconductor device. FIG. 27 is a cross-sectional view taken along line XXVII-XXVII shown in FIG. 26.

[0010] [Detailed Description] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0011] In this specification, open language such as "including" and "having" is described as a concept that encompasses closed language such as "consisting of." When the term "substantially" is used in this specification, this term not only includes a numerical value (form) that is equal to the numerical value (form) of the comparison target, but also includes a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target.

[0012] In this specification, terms such as "first," "second," and "third" are used, but these are symbols added to the names of each structure to clarify the order of explanation, and are not added with the intention of limiting the names of each structure.

[0013] In this specification, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type."

[0014] "P-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. Trivalent elements are at least one of boron, aluminum, gallium, and indium. Pentavalent elements are at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0015] Fig. 1 is a plan view showing a receiver wafer 1 according to a first embodiment. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. The receiver wafer 1 is a semiconductor wafer used in a manufacturing method for a semiconductor device SM, and forms a part of the substrate of the semiconductor device SM.

[0016] The receiver wafer 1 is a disk-shaped wafer cut from a semiconductor ingot (semiconductor crystal block) by a slicing method. The receiver wafer 1 includes a polycrystalline semiconductor. The receiver wafer 1 includes polycrystalline silicon (Si) or polycrystalline wide-bandgap semiconductor. A wide-bandgap semiconductor is a semiconductor with a bandgap higher than that of Si.

[0017] Examples of wide bandgap semiconductors include gallium nitride (GaN), silicon carbide (SiC), and diamond (C). In this embodiment, the receiver wafer 1 includes polycrystalline SiC, which is an example of a polycrystalline wide bandgap semiconductor. The receiver wafer 1 may be polycrystalline SiC of a cubic system or polycrystalline SiC of a hexagonal system.

[0018] The receiver wafer 1 has a first polytype. In this embodiment, the receiver wafer 1 includes 3C (Cubic)-SiC polycrystalline as the first polytype. Of course, the receiver wafer 1 may also include at least one of 2H (Hexagonal)-SiC polycrystalline, 4H-SiC polycrystalline, and 6H-SiC polycrystalline.

[0019] Of course, the receiver wafer 1 may include a semiconductor single crystal. In this case, the receiver wafer 1 may include a Si single crystal or a wide bandgap semiconductor single crystal (preferably a SiC single crystal). The receiver wafer 1 may be a cubic SiC single crystal or a hexagonal SiC single crystal. The receiver wafer 1 may include at least one of a 3C—SiC single crystal, a 2H—SiC single crystal, a 4H—SiC single crystal, and a 6H—SiC single crystal.

[0020] The receiver wafer 1 may contain n-type impurities or p-type impurities in a part of or the entire area depending on the specifications of the semiconductor device SM. For example, in the manufacturing method of the semiconductor device SM, an n-type or p-type receiver wafer 1 may be used.

[0021] The receiver wafer 1 has a first plate surface 2 on one side, a second plate surface 3 on the other side, and a first sidewall 4 connecting the first plate surface 2 and the second plate surface 3. The first plate surface 2 may be a ground surface or a polished surface (mirror surface). The second plate surface 3 may be a ground surface or a polished surface (mirror surface). The surface condition of the second plate surface 3 may be the same as or different from the surface condition of the first plate surface 2.

[0022] The receiver wafer 1 includes a first corner 5 and a second corner 6. The first corner 5 connects the first plate surface 2 and the first side wall 4. The first corner 5 is angular and not chamfered. The first corner 5 connects the first plate surface 2 and the first side wall 4 at a substantially right angle. The second corner 6 connects the second plate surface 3 and the first side wall 4. The second corner 6 is angular and not chamfered. The second corner 6 connects the second plate surface 3 and the first side wall 4 at a substantially right angle.

[0023] The receiver wafer 1 has a first mark 7 indicating the crystal orientation of the SiC polycrystal on the first sidewall 4. In this embodiment, the first mark 7 includes an orientation notch formed by a cutout recessed toward the inner portion (center) of the first plate surface 2. The first mark 7 may also include an orientation flat formed by a cutout extending linearly (see the two-dot chain line).

[0024] The receiver wafer 1 has a first size D1. The first size D1 is the diameter (first diameter) of the receiver wafer 1 outside the first mark 7. The first size D1 may be 1 inch or greater and 12 inches or less. The first size D1 may have a value belonging to at least one of the ranges of 1 inch or greater and 2 inches or less, 2 inches or greater and 4 inches or less, 4 inches or greater and 6 inches or less, 6 inches or greater and 8 inches or less, 8 inches or greater and 10 inches or less, and 10 inches or greater and 12 inches or less. The first size D1 is preferably 4 inches or greater.

[0025] The receiver wafer 1 has a first thickness T1. The first thickness T1 may be 50 μm or more and 1000 μm or less. The first thickness T1 may have a value belonging to at least one of the following ranges: 50 μm or more and 100 μm or less, 100 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, 400 μm or more and 500 μm or less, 500 μm or more and 600 μm or less, 600 μm or more and 700 μm or less, 700 μm or more and 800 μm or less, 800 μm or more and 900 μm or less, and 900 μm or more and 1000 μm or less. The first thickness T1 is preferably 200 μm or more and 500 μm or less.

[0026] Fig. 3 is a plan view showing the base wafer 10 according to the first embodiment. Fig. 4 is a cross-sectional view taken along line IV-IV shown in Fig. 3. The base wafer 10 is a semiconductor wafer used in the manufacturing method of the semiconductor device SM, and forms part of the substrate of the semiconductor device SM together with the receiver wafer 1. The base wafer 10 is the target on which devices are formed.

[0027] The base wafer 10 is a disk-shaped wafer cut from a semiconductor ingot (semiconductor crystal block) by a slicing method. The base wafer 10 contains a different material from the receiver wafer 1. The base wafer 10 has different crystal properties from the receiver wafer 1. The base wafer 10 contains a semiconductor single crystal.

[0028] The base wafer 10 includes a single crystal of Si or a single crystal of a wide bandgap semiconductor. In this embodiment, the base wafer 10 includes a single crystal of SiC, which is an example of a single crystal of a wide bandgap semiconductor. The base wafer 10 may be a cubic SiC single crystal or a hexagonal SiC single crystal.

[0029] The base wafer 10 has a second polytype. The second polytype may be the same as or different from the first polytype. In this embodiment, the base wafer 10 includes a 4H—SiC single crystal as the second polytype. Of course, the base wafer 10 may also include at least one of a 3C—SiC single crystal, a 2H—SiC single crystal, and a 6H—SiC single crystal.

[0030] The base wafer 10 may contain n-type or p-type impurities in some or all of its regions depending on the specifications of the semiconductor device SM. In the manufacturing method of the semiconductor device SM, an n-type or p-type base wafer 10 may be used. The conductivity type of the base wafer 10 may be the same as or different from the conductivity type of the receiver wafer 1.

[0031] The base wafer 10 has a third plate surface 11 on one side, a fourth plate surface 12 on the other side, and a second sidewall 13 connecting the third plate surface 11 and the fourth plate surface 12. The third plate surface 11 and the fourth plate surface 12 may be formed by the c-plane of a SiC single crystal.

[0032] In this case, the third plate surface 11 may be formed by the C-face ((000-1) face) of the SiC single crystal, and the fourth plate surface 12 may be formed by the Si-face ((0001) face) of the SiC single crystal. Of course, the third plate surface 11 may be formed by the Si-face ((0001) face), and the fourth plate surface 12 may be formed by the C-face ((000-1) face).

[0033] The third plate surface 11 may be a ground surface or a polished surface (mirror finish). The fourth plate surface 12 may be a ground surface or a polished surface (mirror finish). The surface condition of the fourth plate surface 12 may be the same as or different from the surface condition of the third plate surface 11.

[0034] The base wafer 10 (third plate surface 11 and fourth plate surface 12) has an off-axis angle inclined at a predetermined angle in a predetermined off-axis direction with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined by the off-axis angle from a vertical line with respect to the third plate surface 11 (fourth plate surface 12).

[0035] The off-direction may be the a-axis direction ([11-20] direction) of the SiC single crystal. The off-angle may be 0° or more and 10° or less. The off-angle may have a value belonging to at least one of the ranges of 0° or more and 1° or less, 1° or more and 2° or less, 2° or more and 3° or less, 3° or more and 4° or less, 4° or more and 5° or less, 5° or more and 6° or less, 6° or more and 7° or less, 7° or more and 8° or less, 8° or more and 9° or less, and 9° or more and 10° or less.

[0036] The off angle is preferably 5° or less. The off angle is preferably 2° or more and 4.5° or less. The off angle preferably has a value within the range of 4°±0.1°. Of course, the off angle may be 0°. In other words, the third plate surface 11 and the fourth plate surface 12 may be just planes with respect to the c-plane.

[0037] The base wafer 10 includes a third corner 14 and a fourth corner 15. The third corner 14 connects the third plate surface 11 and the second side wall 13. The third corner 14 is angular and not chamfered. The third corner 14 connects the third plate surface 11 and the second side wall 13 at a substantially right angle. The fourth corner 15 connects the fourth plate surface 12 and the second side wall 13. The fourth corner 15 is angular and not chamfered. The fourth corner 15 connects the fourth plate surface 12 and the second side wall 13 at a substantially right angle.

[0038] The base wafer 10 has a second mark 16 indicating the crystal orientation of the SiC single crystal on the second sidewall 13. In this embodiment, the second mark 16 includes an orientation notch formed by a cutout recessed toward the inner portion (center) of the third plate surface 11. The second mark 16 may also include an orientation flat formed by a cutout extending linearly (see the two-dot chain line).

[0039] The second mark 16 may indicate the a-axis direction ([11-20] direction) or the m-axis direction ([1-100] direction) of the SiC single crystal. The a-axis direction may be referred to as the first direction (first crystal direction), and the m-axis direction may be referred to as the second direction (second crystal direction). Of course, the m-axis direction may be referred to as the first direction (first crystal direction), and the a-axis direction may be referred to as the second direction (second crystal direction).

[0040] The base wafer 10 has a second size D2. The second size D2 is the diameter (second diameter) of the base wafer 10 outside the second mark 16. The second size D2 is preferably equal to or smaller than the first size D1. The second size D2 may be approximately equal to the first size D1. The second size D2 may be smaller than the first size D1. The second size D2 may be larger than the first size D1.

[0041] The second size D2 may be 1 inch or more and 12 inches or less. The first size D1 may have a value belonging to at least one of the ranges of 1 inch or more and 2 inches or less, 2 inches or more and 4 inches or less, 4 inches or more and 6 inches or less, 6 inches or more and 8 inches or less, 8 inches or more and 10 inches or more and 12 inches or less. The first size D1 is preferably 4 inches or more.

[0042] The difference value (D1-D2) between the first size D1 and the second size D2 may be 0 mm or more and 10 mm or less. The difference value (D1-D2) may have a value belonging to at least one of the ranges of 0 mm or more and 1 mm or less, 1 mm or more and 2 mm or less, 2 mm or more and 3 mm or less, 3 mm or more and 4 mm or less, 4 mm or more and 5 mm or less, 5 mm or more and 6 mm or less, 6 mm or more and 7 mm or less, 7 mm or more and 8 mm or less, 8 mm or more and 9 mm or less, and 9 mm or more and 10 mm or less. The difference value is preferably 5 mm or less.

[0043] The base wafer 10 has a second thickness T2. The second thickness T2 is preferably greater than the first thickness T1. The second thickness T2 may be less than the first thickness T1. The second thickness T2 may be approximately equal to the first thickness T1.

[0044] The second thickness T2 may be 50 μm or more and 1500 μm or less. The second thickness T2 may have a value belonging to at least one of the ranges of 50 μm or more and 100 μm or less, 100 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, 400 μm or more and 500 μm or less, 500 μm or more and 600 μm or less, 600 μm or more and 700 μm or less, 700 μm or more and 800 μm or less, 800 μm or more and 900 μm or less, 900 μm or more and 1000 μm or less, 1000 μm or more and 1100 μm or less, 1100 μm or more and 1200 μm or less, 1200 μm or more and 1300 μm or less, 1300 μm or more and 1400 μm or less, and 1400 μm or more and 1500 μm or less.

[0045] Fig. 5 is a process diagram showing a manufacturing method of a semiconductor device SM according to the first embodiment. Figs. 6A to 6O are cross-sectional views related to the process diagram of Fig. 5. Fig. 7 is a plan view showing a device region 28. Fig. 8 is an enlarged cross-sectional view of a bevel portion 21 according to the first example. Fig. 9 is an enlarged cross-sectional view showing a laminated wafer 20 and an epitaxial layer 26.

[0046] 5, the manufacturing method includes a step S1 of preparing the laminated wafers 20 (see FIGS. 6A to 6F). The manufacturing method includes a step S2 of forming the beveled portion 21 (see FIGS. 6G to 6H). The manufacturing method includes a step S3 of forming the device structure 22 (see FIGS. 6I to 6L). The manufacturing method includes a step S4 of dicing the laminated wafers 20 (see FIG. 6M). The manufacturing method includes a step S5 of reusing the base wafer 10 (see FIGS. 6N to 6O). These steps will be described in order below.

[0047] 6A, the step S1 of preparing the laminated wafers 20 includes a step S6 of preparing the receiver wafer 1 (see FIGS. 1 and 2). The step S1 of preparing the laminated wafers 20 includes a step S7 of treating the first surface 2 of the receiver wafer 1. The treatment step S7 includes a step of activating bonds on the first surface 2. The treatment step S7 may include a sputter etching step of the first surface 2. In this case, the treatment step S7 may include a step of irradiating the first surface 2 with an argon beam.

[0048] The etching amount of the first plate surface 2 may be greater than 0 nm and less than or equal to 50 nm. The etching amount may have a value belonging to at least one of the ranges of greater than 0 nm and less than or equal to 5 nm, 5 nm to 10 nm, 10 nm to 15 nm, 15 nm to 20 nm, 20 nm to 25 nm, 25 nm to 30 nm, 30 nm to 35 nm, 35 nm to 40 nm, 40 nm to 45 nm, and 45 nm to 50 nm.

[0049] 6B , the step S1 of preparing the laminated wafers 20 includes the step S8 of preparing the base wafer 10 (see FIGS. 3 and 4 ). The step S8 of preparing the base wafer 10 is performed independently of the step S6 of preparing the receiver wafer 1. The step S8 of preparing the base wafer 10 may also be performed in parallel with the step S6 of preparing the receiver wafer 1.

[0050] The step S8 of preparing the base wafer 10 may be performed before the step S6 of preparing the receiver wafer 1. The step S8 of preparing the base wafer 10 may be performed after the step S6 of preparing the receiver wafer 1. The step S8 of preparing the base wafer 10 may be performed at the same timing as the step S6 of preparing the receiver wafer 1.

[0051] The step S1 of preparing the laminated wafer 20 includes a step S9 of forming a fragile layer 23 on the base wafer 10. The fragile layer 23 may also be referred to as a "fragile region," "altered layer (region)," "modified layer (region)," "defective layer (region)," "damaged layer (region)," etc. The fragile layer 23 is a region in which a part of the base wafer 10 has become embrittled due to modification of the SiC single crystal.

[0052] The fragile layer 23 is formed inside the base wafer 10 at a distance from the third plate surface 11 and the fourth plate surface 12. The fragile layer 23 is formed so as to extend in a layer in the horizontal direction along the third plate surface 11 and the fourth plate surface 12. The fragile layer 23 is formed so as to be unevenly distributed in an area on the third plate surface 11 side relative to the fourth plate surface 12. Specifically, the fragile layer 23 is formed in an area on the third plate surface 11 side relative to a thickness position of the intermediate portion of the base wafer 10.

[0053] The fragile layer 23 is formed at a distance of more than 0 μm and not more than 5 μm from the third plate surface 11. The distance between the fragile layers 23 may be in at least one of the following ranges: more than 0 μm and not more than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm. The distance between the fragile layers 23 is preferably not more than 2.5 μm.

[0054] The step S9 of forming the fragile layer 23 may include either one or both of an ion irradiation step and a laser irradiation step. In the ion irradiation step, ions are irradiated to a focal point set inside the base wafer 10, and the fragile layer 23 is formed as an "ion irradiation mark."

[0055] In the ion irradiation process, at least one of hydrogen ions, helium ions, trivalent element ions, and pentavalent element ions may be irradiated into the interior of the base wafer 10. The trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0056] In the ion irradiation process, ions are irradiated into the interior of the base wafer 10 from the third plate surface 11 side. Ions may also be irradiated into the interior of the base wafer 10 from the fourth plate surface 12 side. The ion irradiation unit for the base wafer 10 is moved in the horizontal direction along the third plate surface 11. This forms a fragile layer 23 extending in layers in the horizontal direction.

[0057] In the laser irradiation step, a laser beam is irradiated onto a focal point set inside the base wafer 10, and a brittle layer 23 is formed as a "laser irradiation mark." In the laser irradiation step, the laser beam is irradiated onto the inside of the base wafer 10 from the third plate surface 11 side. The laser beam may also be irradiated onto the inside of the base wafer 10 from the fourth plate surface 12 side.

[0058] The laser beam may be pulsed. The laser irradiation unit for the base wafer 10 is moved in the horizontal direction along the third plate surface 11. As a result, a fragile layer 23 extending in layers in the horizontal direction is formed.

[0059] 6C , the step S1 of preparing the laminated wafers 20 includes a step S10 of processing the third surface 11 of the base wafer 10. The processing step S10 may be performed prior to the step S9 of forming the fragile layer 23. The processing step S10 of the base wafer 10 may be performed separately from or simultaneously with the processing step S7 of the receiver wafer 1.

[0060] The processing step S10 includes a step of activating bonds on the third plate surface 11. The processing step S10 may include a step of sputter etching the third plate surface 11. In this case, the processing step S10 may include a step of irradiating the third plate surface 11 with an argon beam.

[0061] The etching amount of the third plate surface 11 may be greater than 0 nm and less than or equal to 50 nm. The etching amount may have a value belonging to at least one of the ranges of greater than 0 nm and less than or equal to 5 nm, 5 nm to 10 nm, 10 nm to 15 nm, 15 nm to 20 nm, 20 nm to 25 nm, 25 nm to 30 nm, 30 nm to 35 nm, 35 nm to 40 nm, 40 nm to 45 nm, and 45 nm to 50 nm.

[0062] 6D , the step S1 of preparing the laminated wafers 20 includes a step S11 of bonding the receiver wafer 1 and the base wafer 10. In the bonding step S11, the base wafer 10, which has undergone the step S9 of forming the fragile layer 23 and the processing step S10, is bonded to the receiver wafer 1, which has undergone the processing step S7.

[0063] In this process, the first plate surface 2 of the receiver wafer 1 and the third plate surface 11 of the base wafer 10 are bonded (adhered) together by a direct wafer bonding method. The direct wafer bonding method is performed in a reduced pressure environment. When the receiver wafer 1 and the base wafer 10 are bonded (adhered), the brittle layer 23 is unevenly distributed on the first plate surface 2 side of the receiver wafer 1. The bonded portion (boundary) of the receiver wafer 1 and the base wafer 10 may contain amorphous SiC.

[0064] In this embodiment, the second size D2 of the base wafer 10 is equal to or smaller than the first size D1 of the receiver wafer 1. Therefore, the receiver wafer 1 and the base wafer 10 are attached so that the second side wall 13 does not protrude outward relative to the first side wall 4. The first mark 7 and the second mark 16 may overlap each other or may be offset from each other in the circumferential direction.

[0065] When the second size D2 is approximately equal to the first size D1, the receiver wafer 1 and the base wafer 10 are attached so that the first sidewall 4 and the second sidewall 13 are approximately aligned. These modes prevent the second sidewall 13 from overhanging the first sidewall 4, thereby suppressing cracks in the base wafer 10 caused by stress (external force) on the second sidewall 13.

[0066] 6E , the step S1 of preparing the laminated wafers 20 includes a step S12 of forming the donor wafer 24. The step S12 of forming the donor wafer 24 includes a step of thinning the base wafer 10 in an attached (bonded) state to the receiver wafer 1.

[0067] The thinning step (S12) includes a step of cutting the base wafer 10 in a horizontal direction along the third plate surface 11. Specifically, the base wafer 10 is cut in a horizontal direction starting from the brittle layer 23 (the cutting starting point). The term "cutting" may be read as "cleaving."

[0068] In this process, an external force is applied to the fragile layer 23. The external force may include at least one of mechanical stress (physical stress), thermal stress using heating and cooling, static electricity, and ultrasonic waves. The mechanical stress may be tensile stress caused by a tape, cutting stress caused by a blade, or the like. The external force may be applied to the base wafer 10 immersed in a chemical solution. The chemical solution may be neutral, acidic, or alkaline. The external force applied to the base wafer 10 in the chemical solution is preferably ultrasonic waves.

[0069] 6F , the step S1 of preparing the laminated wafers 20 includes a polishing step S13 of polishing the cut surfaces of the donor wafer 24. The polishing step S13 may be a step of polishing the cut surfaces to a mirror finish. This step includes a step of removing the brittle layer 23 from the cut surfaces. The polishing step S13 may be performed by a chemical mechanical polishing (CMP) method. As a result of this step, the cut surfaces of the donor wafer 24 become the device surfaces 25. In this embodiment, the device surfaces 25 are formed by the Si-face ((0001) plane) of the SiC single crystal.

[0070] When the donor wafer 24 (base wafer 10) has an off-axis angle, the step planes and terrace planes of the SiC single crystal exposed due to the off-axis angle are ground. When the donor wafer 24 (base wafer 10) is an on-axis plane with respect to the c-plane, the exposure of the step planes and terrace planes of the SiC single crystal is suppressed, and the amount of grinding of the donor wafer 24 is reduced.

[0071] In the step S1 of preparing the laminated wafers 20, the laminated wafers 20 having a laminated structure including the receiver wafer 1 and the donor wafer 24 are formed through these steps. The donor wafer 24 has a third thickness T3 that is less than the thickness of the receiver wafer 1.

[0072] The third thickness T3 may be greater than 0 μm and less than or equal to 5 μm. The third thickness T3 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm. The third thickness T3 is preferably less than or equal to 1 μm.

[0073] The donor wafer 24 inherits the second size D2 of the base wafer 10. Therefore, the donor wafer 24 is supported by the base wafer 10 so that the second sidewall 13 does not protrude outward relative to the first sidewall 4. When the second size D2 is approximately equal to the first size D1, the donor wafer 24 is supported by the receiver wafer 10 so that the first sidewall 4 and the second sidewall 13 approximately coincide with each other. According to these modes, overhang of the second sidewall 13 relative to the first sidewall 4 is avoided, thereby suppressing cracks in the thin donor wafer 24.

[0074] 6G and 6H , after the step S1 of preparing the laminated wafers 20, the step S2 of forming the bevel portion 21 is performed. In this embodiment, the step S2 of forming the bevel portion 21 is performed after the polishing step S13. Of course, the step S2 of forming the bevel portion 21 may be performed before the polishing step S13, and the polishing step S13 may be performed after the step S2 of forming the bevel portion 21.

[0075] The bevel portion 21 forming process S2 includes either or both of a process of forming a first bevel portion 21A on the corner (fourth corner 15) of the donor wafer 24 (see Figure 6G) and a process of forming a second bevel portion 21B on the corner (second corner 6) of the receiver wafer 1 (see Figure 6H).

[0076] In this embodiment, the step S2 of forming the bevel portion 21 includes both the step of forming the first bevel portion 21A and the step of forming the second bevel portion 21B. The step of forming the second bevel portion 21B may be performed simultaneously with the step of forming the first bevel portion 21A. Of course, the step of forming the second bevel portion 21B may be performed before the step of forming the first bevel portion 21A or after the step of forming the first bevel portion 21A.

[0077] The step of forming the first bevel portion 21A may be performed by using either or both of an etching method and a grinding method. The etching method may be either or both of a dry etching method and a wet etching method. The grinding method may be a bevel grinding method for the corner portion (fourth corner portion 15) of the donor wafer 24.

[0078] The step of forming the second bevel portion 21B may be performed using either or both of an etching method and a grinding method. The etching method may be either or both of a dry etching method and a wet etching method. The grinding method may be a bevel grinding method for the corner portion (second corner portion 6) of the receiver wafer 1.

[0079] 8, in this embodiment, the first bevel portion 21A is formed on an obliquely inclined surface extending from the device surface 25 of the donor wafer 24 toward the bonding portion. The inclination direction of the first bevel portion 21A is a direction extending from the device surface 25 toward the outside of the stacked wafers 20. In this embodiment, the first bevel portion 21A is formed to extend across the entire donor wafer 24 and reach the receiver wafer 1.

[0080] The proportion of the receiver wafer 1 in the first bevel portion 21A is greater than the proportion of the donor wafer 24 in the first bevel portion 21A. Of course, the proportion of the receiver wafer 1 may be less than the proportion of the donor wafer 24.

[0081] The first bevel portion 21A is formed at a distance from the second plate surface 3 of the receiver wafer 1 toward the first plate surface 2 (adhered portion). In this embodiment, the first bevel portion 21A is formed at a distance from the thickness position of the middle portion of the receiver wafer 1 toward the first plate surface 2. The first bevel portion 21A defines the end of the stacked wafer 20 on the device surface 25 side in a tapered shape in a cross-sectional view. In other words, the wafer size of the stacked wafer 20 gradually increases from the device surface 25 toward the second plate surface 3.

[0082] The first bevel portion 21A has a first inclination angle θ1 with respect to an extension of the device surface 25. The first inclination angle θ1 is the angle formed by a line connecting the base end and tip end of the first bevel portion 21A with an extension of the device surface 25. The base end is the end on the device surface 25 side, and the tip end is the end on the second side wall 13 (first side wall 4) side.

[0083] The first tilt angle θ1 may be greater than 0° and less than or equal to 45°. The first tilt angle θ1 may have a value belonging to at least one of the ranges of greater than 0° and less than or equal to 5°, 5° to 10°, 10° to 15°, 15° to 20°, 20° to 25°, 25° to 30°, 30° to 35°, 35° to 40°, and 40° to 45°.

[0084] In this embodiment, the second bevel portion 21B is formed on an obliquely inclined surface extending from the second plate surface 3 of the receiver wafer 1 toward the first plate surface 2 (adhered portion). The inclination direction of the second bevel portion 21B is a direction extending from the second plate surface 3 toward the outside of the laminated wafers 20. The second bevel portion 21B is formed at a distance from the donor wafer 24 toward the second plate surface 3. In other words, the second bevel portion 21B is formed only on the receiver wafer 1, and not on the donor wafer 24.

[0085] The second bevel portion 21B is formed at a distance from the first bevel portion 21A toward the second plate surface 3, and faces the first bevel portion 21A across the remaining portion of the first sidewall 4. In this embodiment, the second bevel portion 21B is formed at a distance from the thickness position of the intermediate portion of the receiver wafer 1 toward the first plate surface 2. The second bevel portion 21B defines the end of the laminated wafer 20 on the second plate surface 3 side in a reverse tapered shape in a cross-sectional view. In other words, the wafer size of the laminated wafer 20 gradually increases from the second plate surface 3 toward the device surface 25.

[0086] The second bevel portion 21B has a second inclination angle θ2 with respect to an extension of the second plate surface 3. The second inclination angle θ2 is the angle formed by a line connecting the base end and the tip end of the second bevel portion 21B with an extension of the second plate surface 3. The base end is the end on the second plate surface 3 side, and the tip end is the end on the first side wall 4 (second side wall 13) side. The second inclination angle θ2 may be approximately equal to the first inclination angle θ1. The second inclination angle θ2 may be smaller or larger than the first inclination angle θ1.

[0087] The second tilt angle θ2 may be greater than 0° and less than or equal to 45°. The second tilt angle θ2 may have a value belonging to at least one of the following ranges: greater than 0° and less than or equal to 5°, 5° to 10°, 10° to 15°, 15° to 20°, 20° to 25°, 25° to 30°, 30° to 35°, 35° to 40°, and 40° to 45°.

[0088] 6I , the manufacturing method of the semiconductor device SM includes a step S3 of forming a device structure 22 after a step S2 of forming a bevel portion 21. The device structure 22 is formed on the donor wafer 24 side having the first bevel portion 21A. The step S3 of forming the device structure 22 includes a step S14 of forming an epitaxial layer 26 on the donor wafer 24. The epitaxial layer 26 is stacked on the donor wafer 24 by epitaxial growth using the device surface 25 as the crystal growth starting point.

[0089] The epitaxial layer 26 contains a material different from that of the receiver wafer 1. The epitaxial layer 26 has crystal properties different from those of the receiver wafer 1. The epitaxial layer 26 contains a single crystal of a semiconductor. The epitaxial layer 26 contains a single crystal of Si or a single crystal of a wide bandgap semiconductor.

[0090] In this embodiment, the epitaxial layer 26 includes a SiC single crystal, which is an example of a single crystal of a wide bandgap semiconductor. The epitaxial layer 26 may be a cubic SiC single crystal or a hexagonal SiC single crystal.

[0091] The epitaxial layer 26 has a third polytype. The third polytype may be the same as the first polytype or may be different from the first polytype. The third polytype may be the same as the second polytype or may be different from the second polytype. In this embodiment, the third polytype is the same as the second polytype.

[0092] That is, in this embodiment, the epitaxial layer 26 contains a 4H—SiC single crystal as the third polytype. Of course, the epitaxial layer 26 may contain at least one of a 3C—SiC single crystal, a 2H—SiC single crystal, and a 6H—SiC single crystal.

[0093] In this embodiment, the epitaxial layer 26 is deposited while inheriting the crystalline state (crystal axis, crystal direction, and off-angle) of the donor wafer 24. The crystal growth surface of the epitaxial layer 26 after crystal growth becomes the device surface 25 of the laminated wafer 20. In this embodiment, the device surface 25 after crystal growth is formed by the Si-face ((0001) plane) of the SiC single crystal.

[0094] The epitaxial layer 26 may be regarded as one component of the laminated wafer 20. The epitaxial layer 26 may have a portion laminated on the peripheral portion (first bevel portion 21A) of the laminated wafer 20, with the receiver wafer 1 serving as the crystal growth starting point.

[0095] The epitaxial layer 26 may contain n-type impurities or p-type impurities in a part of the region or in the entire region depending on the specifications of the semiconductor device SM. In the manufacturing method of the semiconductor device SM, either or both of the n-type epitaxial layer 26 and the p-type epitaxial layer 26 may be formed.

[0096] 9, the epitaxial layer 26 has a fourth thickness T4. The fourth thickness T4 is less than the first thickness T1 of the receiver wafer 1. The fourth thickness T4 is preferably greater than the third thickness T3 of the donor wafer 24. Of course, the fourth thickness T4 may be less than the third thickness T3.

[0097] The fourth thickness T4 may be 1 μm or more and 50 μm or less. The fourth thickness T4 may have a value belonging to at least one of the ranges of 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or more and 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or more and 45 μm or more and 50 μm or less. The fourth thickness T4 is preferably 5 μm or more and 25 μm or less.

[0098] 6J, the step S3 of forming the device structure 22 includes a step S15 of forming a plurality of functional devices 27 on the device surface 25 of the epitaxial layer 26. Referring to Fig. 7, the step S15 of forming the plurality of functional devices 27 includes a step of setting a plurality of device regions 28 and a plurality of lines to cut 29 on the device surface 25. The device regions 28 are regions corresponding to the semiconductor devices SM.

[0099] The device surface 25 is defined by the plurality of device regions 28 and the plurality of cutting lines 29 using alignment marks or the like. The alignment marks may be marks engraved on the device surface 25 (for example, a trench, a trench electrode structure, a trench insulating structure, or the like), marks attached to the device surface 25 (for example, a metal film or an insulating film, or the like), marks printed on the device surface 25 (for example, ink, or the like), or the like.

[0100] In this embodiment, the plurality of device regions 28 are set in a matrix along the a-axis and m-axis directions of the SiC single crystal, and the plurality of cutting lines 29 are set in a lattice pattern extending along the a-axis and m-axis directions of the SiC single crystal. The plurality of device regions 28 are set at intervals inward from the first bevel portion 21A.

[0101] Each of the device regions 28 is set to have a quadrangular shape (square or rectangular) in a plan view. The device regions 28 may have a first side 28 a and a second side 28 b. The first side 28 a extends in a first direction (e.g., the a-axis direction), and the second side 28 b extends in a second direction (e.g., the m-axis direction) perpendicular to the first direction.

[0102] The first side 28a has a first length L1, and the second side 28b has a second length L2. The first length L1 and the second length L2 correspond to the lengths of the corresponding two sides of the semiconductor device SM. The second length L2 may be approximately equal to the first length L1. The second length L2 may be less than the first length L1. The second length L2 may be greater than the first length L1.

[0103] The first length L1 may be 0.1 mm or more and 20 mm or less. The first length L1 may have a value belonging to at least one of the ranges of 0.1 mm or more and 0.5 mm or less, 0.5 mm or more and 1 mm or less, 1 mm or more and 2.5 mm or less, 2.5 mm or more and 5 mm or less, 5 mm or more and 7.5 mm or less, 7.5 mm or more and 10 mm or less, 10 mm or more and 12.5 mm or less, 12.5 mm or more and 15 mm or less, 15 mm or more and 17.5 mm or less, and 17.5 mm or more and 20 mm or less.

[0104] The second length L2 may be 0.1 mm or more and 20 mm or less. The second length L2 may have a value belonging to at least one of the ranges of 0.1 mm or more and 0.5 mm or less, 0.5 mm or more and 1 mm or less, 1 mm or more and 2.5 mm or less, 2.5 mm or more and 5 mm or less, 5 mm or more and 7.5 mm or less, 7.5 mm or more and 10 mm or less, 10 mm or more and 12.5 mm or less, 12.5 mm or more and 15 mm or less, 15 mm or more and 17.5 mm or less, and 17.5 mm or more and 20 mm or less.

[0105] The functional device 27 is formed using a surface layer portion of the device surface 25 and / or a region above the device surface 25. The functional device 27 may include at least one of a semiconductor switching device, a semiconductor rectifying device, and a passive device. The functional device 27 may also be an LSI (Large Scale Integration) including at least two of a semiconductor switching device, a semiconductor rectifying device, and a passive device.

[0106] The semiconductor switching device may include at least one of a metal insulator semiconductor field effect transistor (MISFET), a bipolar junction transistor (BJT), an insulated gate bipolar junction transistor (IGBT), and a junction field effect transistor (JFET).

[0107] The semiconductor rectifying device may include at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The passive device may include at least one of a resistor, a capacitor, an inductor, and a fuse.

[0108] The step S15 of forming the functional device 27 may include a step of introducing a pentavalent element into the surface layer portion of the device surface 25 by ion implantation. The step S15 of forming the functional device 27 may include a step of introducing a trivalent element into the surface layer portion of the device surface 25 by ion implantation.

[0109] The step S15 of forming the functional device 27 may include a step of forming a plurality of trench electrode structures on the device surface 25. The step of forming the trench electrode structures may include a step of forming trenches on the device surface 25, a step of forming an insulating film that covers the wall surfaces of the trenches, and a step of burying electrodes in the trenches via the insulating film.

[0110] The trench forming step may include an etching method. The etching method may include either or both of a dry etching step and a wet etching step. The insulating film forming step may include either or both of an oxidation treatment method (e.g., a thermal oxidation treatment method) and a CVD (Chemical Vapor Deposition) method.

[0111] The electrode embedding step may include a step of depositing an electrode on the device surface 25 by a CVD method and a step of removing a portion of the electrode covering the device surface 25 by an etching method (etch-back method). The electrode may include conductive polysilicon. The etching method may include either or both of a dry etching step and a wet etching step.

[0112] The step S3 of forming the device structure 22 includes a step S16 of forming an insulating interlayer film 30. The interlayer film 30 is stacked on the device surface 25 so as to collectively cover the multiple device regions 28. The interlayer film 30 may be formed over the entire device surface 25.

[0113] The step S16 of forming the interlayer film 30 may include a step of stacking one or more interlayer films 30 on the device surface 25 by a CVD method. The one or more interlayer films 30 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0114] The step S3 of forming the device structure 22 includes a step S17 of forming a plurality of first electrodes 31. The plurality of first electrodes 31 are respectively formed on the interlayer film 30 in the corresponding device regions 28. The step S17 of forming the plurality of first electrodes 31 may include a step of forming a base electrode that serves as a base for the first electrodes 31, and a step of removing unnecessary portions of the base electrode.

[0115] The base electrode forming step may include either or both of a sputtering method and a CVD method. The base electrode removing step may include an etching method. The etching method may include either or both of a dry etching step and a wet etching step. The base electrode (plurality of first electrodes 31) may have a layered structure including multiple metal films, or may have a single-layer structure made of a single metal film.

[0116] 6K, the step S3 of forming the device structure 22 includes a step S18 of thinning the receiver wafer 1. In this embodiment, the step S18 of thinning the receiver wafer 1 is performed after the step S17 of forming the first electrode 31. The timing of the thinning step S18 is arbitrary, and it may be performed before the step S17 of forming the first electrode 31. Of course, the thinning step S18 may be performed before the step S15 of forming the epitaxial layer 26. The thinning step S18 does not necessarily have to be performed, and may be omitted.

[0117] The thinning step S18 includes a step of removing unnecessary portions of the receiver wafer 1 from the second surface 3 side of the receiver wafer 1. The unnecessary portions of the receiver wafer 1 may be removed by either or both of an etching method and a grinding method. The etching method may include either or both of a dry etching step and a wet etching step. The grinding method may include a CMP method. In the thinning step S18, part or all of the second bevel portion 21B of the receiver wafer 1 may be removed.

[0118] The receiver wafer 1 is thinned from the first thickness T1 to a fifth thickness T5. The fifth thickness T5 after thinning may be greater than or less than the fourth thickness T4. The fifth thickness T5 may be greater than or equal to 10 μm and less than or equal to 350 μm.

[0119] The fifth thickness T5 may have a value belonging to at least one of the ranges of 10 μm to 50 μm, 50 μm to 100 μm, 100 μm to 150 μm, 150 μm to 200 μm, 200 μm to 250 μm, 250 μm to 300 μm, and 300 μm to 350 μm. The fifth thickness T5 is typically 50 μm to 150 μm.

[0120] 6L , the step S3 of forming the device structure 22 includes a step S19 of forming a second electrode 32 on the second plate surface 3 of the receiver wafer 1. In this embodiment, the step S19 of forming the second electrode 32 is performed after the thinning step S18. The step S19 of forming the second electrode 32 may include either or both of a sputtering method and a CVD method.

[0121] The second electrode 32 is formed on the second plate surface 3 so as to face the entire area of ​​the plurality of device regions 28 via the laminated wafer 20. The second electrode 32 may be formed over the entire area of ​​the second plate surface 3, or may be spaced inward from the periphery of the second plate surface 3. The second electrode 32 may have a laminated structure including multiple metal films, or may have a single-layer structure made of a single metal film.

[0122] 6M , the method for manufacturing the semiconductor device SM includes, after the step S3 of forming the device structure 22 (the step S19 of forming the second electrode 32), a step S4 of dicing the laminated wafers 20. In the dicing step S4, the laminated wafers 20 are cut in the stacking direction along a plurality of lines 29 to cut.

[0123] The stacked wafers 20 may be cut with a dicing blade (dicing saw). This cuts out a plurality of semiconductor devices SM from one stacked wafer 20. Each of the plurality of semiconductor devices SM includes a part of the receiver wafer 1, a part of the donor wafer 24, and a part of the epitaxial layer 26 as a base material. Each of the semiconductor devices SM also includes a functional device 27, an interlayer film 30, a first electrode 31, and a second electrode 32.

[0124] 6N , the manufacturing method of the semiconductor device SM may include a recycling step S5 of the base wafer 10. In the recycling step S5, the base wafer 10 that has been subjected to the donor wafer 24 formation step S12 is prepared. The base wafer 10 has a brittle layer 23 remaining on the cut surface.

[0125] The reuse step S5 includes a reuse determination step S20 for the base wafer 10. In the determination step S20, it is determined whether or not a further donor wafer 24 can be formed from the base wafer 10. For example, if the thickness of the base wafer 10 is at least twice the thickness of the donor wafer 24, it may be determined that the base wafer 10 is reusable. If the base wafer 10 is not reusable (S20: NO), the reuse step S5 ends.

[0126] 6O, if the base wafer 10 is reusable (S20: YES), the base wafer 10 is reused as a new base wafer 10. In this case, a polishing step S21 is performed on the cut surface of the base wafer 10. In this step, the brittle layer 23 is removed from the cut surface, and the cut surface of the base wafer 10 becomes a new third plate surface 11. The polishing step S21 may be a mirror polishing step for the cut surface. The polishing step S21 may be performed by a CMP method.

[0127] When the base wafer 10 has an off-axis angle, the step planes and terrace planes of the SiC single crystal exposed due to the off-axis angle are ground. When the base wafer 10 is an on-axis plane with respect to the c-plane, the exposure of the step planes and terrace planes of the SiC single crystal is suppressed, and the amount of grinding of the base wafer 10 is reduced.

[0128] Thereafter, steps S1 to S21 are performed using a new base wafer 10. The determining step S20 is performed at any timing after the forming step S12 of the donor wafer 24. Through the steps including those described above, the semiconductor device SM is manufactured.

[0129] 10A to 10D are enlarged cross-sectional views showing bevel portion 21 according to examples 2 to 6. In the bevel portion 21 forming step S2, bevel portion 21 according to examples 2 to 6 may be formed instead of bevel portion 21 according to example 1.

[0130] 10A , bevel portion 21 according to the second example has first bevel portion 21 A but does not have second bevel portion 21 B. In this case, forming step S2 of bevel portion 21 includes the step of forming first bevel portion 21 A but does not include the step of forming second bevel portion 21 B.

[0131] 10B , bevel portion 21 according to the third example does not have first bevel portion 21 A but has second bevel portion 21 B. In this case, the forming step S2 of bevel portion 21 does not include the step of forming first bevel portion 21 A but includes the step of forming second bevel portion 21 B.

[0132] 10C , bevel portion 21 according to the fourth example has first bevel portion 21A but does not have second bevel portion 21B. In this case, the forming step S2 of bevel portion 21 includes the step of forming first bevel portion 21A but does not include the step of forming second bevel portion 21B.

[0133] The first bevel portion 21A is formed on an obliquely inclined surface extending from the device surface 25 toward the second plate surface 3 so as to reach the second plate surface 3. In other words, the first bevel portion 21A is formed over almost the entire thickness range between the device surface 25 and the second plate surface 3. The inclination direction of the first bevel portion 21A is a direction extending from the device surface 25 toward the outside of the laminated wafer 20.

[0134] The first tilt angle θ1 may be equal to or greater than 30° and less than 90°. The first tilt angle θ1 may have a value belonging to at least one of the ranges of 30° to 35°, 35° to 40°, 40° to 45°, 45° to 50°, 50° to 55°, 55° to 60°, 60° to 65°, 65° to 70°, 70° to 75°, 75° to 80°, 80° to 85°, and 85° to less than 90°. The first tilt angle θ1 is preferably equal to or greater than 45°.

[0135] 10D , bevel portion 21 according to the fifth example does not have first bevel portion 21 A but has second bevel portion 21 B. In this case, the forming step S2 of bevel portion 21 does not include the step of forming first bevel portion 21 A but includes the step of forming second bevel portion 21 B.

[0136] The second bevel portion 21B is formed on an obliquely inclined surface extending from the second plate surface 3 toward the device surface 25 so as to reach the device surface 25. In other words, the second bevel portion 21B is formed over almost the entire thickness range between the device surface 25 and the second plate surface 3. The inclination direction of the second bevel portion 21B is a direction from the second plate surface 3 toward the outside of the laminated wafer 20.

[0137] The second tilt angle θ2 may be equal to or greater than 30° and less than 90°. The second tilt angle θ2 may have a value belonging to at least one of the ranges of 30° to 35°, 35° to 40°, 40° to 45°, 45° to 50°, 50° to 55°, 55° to 60°, 60° to 65°, 65° to 70°, 70° to 75°, 75° to 80°, 80° to 85°, and 85° to less than 90°. The second tilt angle θ2 is preferably equal to or greater than 45°.

[0138] 10E , the bevel portion 21 according to the sixth example includes a first bevel portion 21A that is curved in an arc shape. In this example, the first bevel portion 21A is curved in a direction that protrudes outward from the laminated wafers 20. In a cross-sectional view, the center of curvature of the first bevel portion 21A may be located inside the laminated wafers 20. The first bevel portion 21A has a base end located on the device surface 25 side and a tip end located on the first sidewall 4 side.

[0139] The bevel portion 21 according to the sixth example has a second bevel portion 21B that is curved in an arc shape. In this example, the second bevel portion 21B is curved in a direction that protrudes outward from the laminated wafer 20. In a cross-sectional view, the center of curvature of the second bevel portion 21B may be located inside the laminated wafer 20.

[0140] Second bevel portion 21B has a base end located on the second plate surface 3 side and a tip end located on the first side wall 4 side. The tip end of second bevel portion 21B may be connected to the tip end of first bevel portion 21A at first side wall 4. In other words, second bevel portion 21B may form a single bevel portion 21 curved in an arc shape together with first bevel portion 21A.

[0141] As described above, the manufacturing method for semiconductor device SM includes a step S1 of preparing laminated wafers 20, a step S2 of forming bevel portions 21, and a step S3 of forming device structures 22. In the step S1 of preparing laminated wafers 20, laminated wafers 20 including a receiver wafer 1 and a donor wafer 24 are prepared. In the step S2 of forming bevel portions 21, bevel portions 21 are formed on either or both of the corners of the receiver wafer 1 and the donor wafer 24. In the step S3 of forming device structures 22, the device structures 22 are formed on the donor wafer 24 side.

[0142] This provides a method for manufacturing the semiconductor device SM with a novel process. For example, according to this manufacturing method, cracks in the laminated wafer 20 are suppressed by the bevel portion 21, and the device structure 22 is properly formed on the donor wafer 24 side. As a result, the semiconductor device SM is properly formed from the laminated wafer 20.

[0143] The donor wafer 24 may have a material different from that of the receiver wafer 1. According to this manufacturing method, cracks in the stacked wafers 20 containing different materials are suppressed by the bevel portion 21. The receiver wafer 1 may include a wide bandgap semiconductor. The donor wafer 24 may include a wide bandgap semiconductor. According to this manufacturing method, cracks in the stacked wafers 20 containing a wide bandgap semiconductor are suppressed.

[0144] The receiver wafer 1 may contain SiC. The donor wafer 24 may contain SiC. According to this manufacturing method, cracks are suppressed in the stacked wafers 20 containing SiC. In this case, the receiver wafer 1 may contain SiC, and the donor wafer 24 may contain SiC having crystal properties different from those of the receiver wafer 1. According to this manufacturing method, cracks are suppressed in the stacked wafers 20 containing SiC having different crystal properties.

[0145] The receiver wafer 1 may include a polycrystalline material, and the donor wafer 24 may include a single crystal material. This manufacturing method suppresses cracks in the laminated wafers 20 that include a polycrystalline material and a single crystal material. Furthermore, since the receiver wafer 1 that includes a polycrystalline material is less expensive than the receiver wafer 1 that includes a single crystal material, manufacturing costs are reduced.

[0146] The receiver wafer 1 may have a first polytype (first atomic arrangement), and the donor wafer 24 may have a second polytype (second atomic arrangement) different from the first polytype. This manufacturing method suppresses cracking in the laminated wafers 20 including the first and second polytypes. The receiver wafer 1 may include a tetragonal crystal structure, and the donor wafer 24 may include a hexagonal crystal structure. This manufacturing method suppresses cracking in the laminated wafers 20 including the tetragonal crystal structure and the hexagonal crystal structure.

[0147] The receiver wafer 1 may contain 3C—SiC, and the donor wafer 24 may contain 4H—SiC. This manufacturing method suppresses cracks in the stacked wafers 20 containing 3C—SiC and 4H—SiC.

[0148] The bevel portion 21 may be formed at least on the donor wafer 24. In this case, the device structure 22 may be formed on the donor wafer 24 having the bevel portion 21. According to this manufacturing method, cracks in the donor wafer 24 are appropriately suppressed by the bevel portion 21. This improves the reliability of the device structure 22 (i.e., the semiconductor device SM) on the donor wafer 24 side.

[0149] The stacked wafers 20 may include a donor wafer 24 that is thinner than the receiver wafer 1. In this case, the bevel portion 21 may be formed at a corner of the donor wafer 24 that is thinner than the receiver wafer 1. According to this manufacturing method, cracks in the thin donor wafer 24 are appropriately suppressed by the bevel portion 21.

[0150] The step S1 of preparing the laminated wafers 20 may include a step S6 of preparing the receiver wafer 1, a step S8 of preparing the base wafer 10, a step S11 of bonding the receiver wafer 1 and the base wafer 10, and a step S12 of forming the donor wafer 24. In the step S12 of forming the donor wafer 24, the base wafer 10 may be thinned while being bonded to the receiver wafer 1.

[0151] In this case, the bevel portion 21 forming step S2 may be performed after the thinning step (S12) of the base wafer 10. According to this manufacturing method, the thin donor wafer 24 is supported by the receiver wafer 1, so the donor wafer 24 does not need to be handled separately. This allows the thin donor wafer 24 to be processed appropriately. Furthermore, the bevel portion 21 appropriately suppresses cracks in the thin donor wafer 24.

[0152] The base wafer 10 does not have to have a bevel portion. If the base wafer 10 has a bevel portion, a sharp bevel portion remains in the donor wafer 24 during the thinning step (S12) of the base wafer 10, and this may become a starting point for cracks. In this regard, a base wafer 10 without a bevel portion avoids this risk.

[0153] The base wafer 10 thinning step (S12) may include a step of cutting the base wafer 10 horizontally along the surface of the base wafer 10. According to this manufacturing method, a base wafer 10 recycling step S5 can be performed. In the recycling step S5, the base wafer 10 used in the donor wafer 24 formation step S12 is reused as a new base wafer 10. The recycling step S5 may include a polishing step S21 of the cut surface of the new base wafer 10.

[0154] The base wafer 10 may be cut horizontally from a region on the receiver wafer 1 side relative to a thickness position of the middle portion of the base wafer 10. The base wafer 10 may have a fragile layer 23 therein that extends horizontally, and may be cut horizontally starting from the fragile layer 23. According to this manufacturing method, the fragile layer 23 improves the cutting efficiency of the base wafer 10.

[0155] In this case, the bevel portion 21 may be formed after the thinning step (S12) of the base wafer 10 using the fragile layer 23. If the fragile layer 23 is formed after the bevel portion 21 forming step S2, the fragile layer 23 may not be properly formed on the bevel portion 21, and the base wafer 10 may not be properly cut. On the other hand, if the bevel portion 21 forming step S2 is performed on the base wafer 10 having the fragile layer 23, the base wafer 10 may be improperly fractured starting from the fragile layer 23 due to an external force generated in the bevel portion 21 forming step S2.

[0156] In this regard, if the fragile layer 23 is formed before the bevel portion 21 forming step S2, the formation location of the fragile layer 23 is not obstructed by the bevel portion 21, and the base wafer 10 can be properly cut. This allows the donor wafer 24 to be properly formed. Furthermore, since the bevel portion 21 forming step S2 is performed on the donor wafer 24 that does not have the fragile layer 23 as a cutting starting point, the bevel portion 21 is properly formed on the donor wafer 24.

[0157] The step S1 of preparing the laminated wafers 20 may include a step S9 of forming a fragile layer 23 and a bonding step S11. In the step S9 of forming the fragile layer 23, the fragile layer 23 is formed inside the base wafer 10 before the bonding step S11. In the bonding step S11, the base wafer 10 having the fragile layer 23 is bonded to the receiver wafer 1. According to this manufacturing method, the fragile layer 23 is appropriately formed in the base wafer 10 without being restricted by the receiver wafer 1. This allows the base wafer 10 to be appropriately cut starting from the fragile layer 23.

[0158] The manufacturing method of the semiconductor device SM may include a polishing step S13 of the cut surface of the donor wafer 24 after the cutting step (S12) of the base wafer 10. In this case, the forming step S2 of the bevel portion 21 may be performed after the polishing step S13. This step prevents the bevel portion 21 from disappearing due to the polishing step S13.

[0159] The step S3 of forming the device structure 22 may include a step S14 of forming an epitaxial layer 26 using the donor wafer 24 as a growth starting point. The epitaxial layer 26 may have a material different from that of the receiver wafer 1. The epitaxial layer 26 may include a wide bandgap semiconductor. The epitaxial layer 26 may include SiC.

[0160] The epitaxial layer 26 may have a third polytype that is different from the first polytype of the receiver wafer 1. The epitaxial layer 26 may have a third polytype that is different from the second polytype of the donor wafer 24 (base wafer 10). The epitaxial layer 26 may include hexagonal crystals. The thickness of the epitaxial layer 26 may be less than the thickness of the receiver wafer 1. The thickness of the epitaxial layer 26 may be greater than the thickness of the donor wafer 24.

[0161] The step S3 of forming the device structure 22 may include a step S15 of forming a functional device 27. In the step S15 of forming the functional device 27, a device region 28 may be set on the donor wafer 24 side, and the functional device 27 may be formed in the device region 28.

[0162] The device region 28 may have a first side 28a extending in a first direction and a second side 28b extending in a second direction. The second direction is a direction intersecting (specifically, perpendicular to) the first direction. A first length L1 of the first side 28a may be 0.1 mm or more and 20 mm or less. A second length L2 of the second side 28b may be 0.1 mm or more and 20 mm or less.

[0163] The first length L1 may be 1 mm or more. The first length L1 may be 5 mm or more. The first length L1 may be 10 mm or more. The first length L1 may be 15 mm or more. The second length L2 may be 1 mm or more. The second length L2 may be 5 mm or more. The second length L2 may be 10 mm or more. The second length L2 may be 15 mm or more.

[0164] Increasing the plane area of ​​the device region 28 (semiconductor device SM) increases the resistance to large currents and large voltages. In particular, semiconductor devices SM using wide bandgap semiconductors (SiC) are used in relatively high voltage environments.

[0165] Therefore, it is preferable to set a large flat area device region 28 and manufacture a large-area semiconductor device SM with high breakdown voltage and high efficiency. In this case, the first length L1 and the second length L2 are preferably 5 mm or more. In this case, by using a receiver wafer 1 including a polycrystalline material, the manufacturing cost of the large-area semiconductor device SM is appropriately reduced.

[0166] The manufacturing method of the semiconductor device SM may include a dicing step S4. In the dicing step S4, the laminated wafer 20 may be cut in the thickness direction. According to this manufacturing method, the semiconductor device SM is manufactured, which includes a part of the receiver wafer 1 and a part of the donor wafer 24 as a base material.

[0167] Fig. 11 is a plan view showing a receiver wafer 1 according to the second embodiment. Fig. 12 is a cross-sectional view taken along line XII-XII shown in Fig. 11. Fig. 13 is an enlarged cross-sectional view showing an end of the receiver wafer 1 shown in Fig. 11. The following describes configurations that differ from the receiver wafer 1 according to the first embodiment.

[0168] 11 to 13, the receiver wafer 1 according to the second embodiment has a receiver bevel portion 35 pre-formed on the first sidewall 4. The step of forming the receiver bevel portion 35 is performed after the receiver wafer 1 is cut out from a semiconductor ingot.

[0169] The step of forming the receiver bevel portion 35 may be performed by using either or both of an etching method and a grinding method. The etching method may be either or both of a dry etching method and a wet etching method. The grinding method may be a bevel grinding method for the first sidewall 4 of the receiver wafer 1.

[0170] The receiver bevel portion 35 is formed on an obliquely inclined surface extending from the first plate surface 2 to the second plate surface 3. The inclination direction of the receiver bevel portion 35 is a direction starting from the first plate surface 2 and extending inward of the laminated wafers 20. In this embodiment, the receiver bevel portion 35 is formed over almost the entire thickness range of the first plate surface 2 and the second plate surface 3.

[0171] That is, in this embodiment, the receiver bevel portion 35 forms the first sidewall 4 of the receiver wafer 1. The receiver wafer 1 is formed by the receiver bevel portion 35 into an inverted tapered shape in cross section, in which the wafer size gradually decreases from the first plate surface 2 toward the second plate surface 3.

[0172] 13 , the receiver wafer 1 has a bevel inclination angle θb with respect to the second plate surface 3. The bevel inclination angle θb is the angle formed by a line connecting the base end and tip end of the receiver bevel portion 35 with an extension of the second plate surface 3. The base end is the end on the second plate surface 3 side, and the tip end is the end on the first plate surface 2 side.

[0173] The bevel inclination angle θb may be greater than 0° and less than or equal to 45°. The bevel inclination angle θb may have a value belonging to at least one of the ranges of greater than 0° and less than or equal to 5°, 5° to 10°, 10° to 15°, 15° to 20°, 20° to 25°, 25° to 30°, 30° to 35°, 35° to 40°, and 40° to 45°.

[0174] The receiver wafer 1 includes a first corner 5 and a second corner 6. The first corner 5 connects the first plate surface 2 and the receiver bevel 35. The first corner 5 connects the first plate surface 2 and the receiver bevel 35 in an arc shape. In other words, the first corner 5 forms an arc corner with respect to the first plate surface 2 and the receiver bevel 35. The center of curvature of the first corner 5 may be located within the receiver wafer 1 in a cross-sectional view.

[0175] The second corner 6 connects the second plate surface 3 and the receiver bevel 35. The second corner 6 connects the second plate surface 3 and the receiver bevel 35 in an arc shape. In other words, the second corner 6 forms an arc corner with respect to the second plate surface 3 and the receiver bevel 35. The curvature of the second corner 6 may be larger than the curvature of the first corner 5. The center of curvature of the second corner 6 may be located within the receiver wafer 1 in a cross-sectional view.

[0176] The receiver wafer 1 has a first mark 7 indicating the crystal orientation of the SiC polycrystal on the receiver bevel portion 35 (first sidewall 4). In this embodiment, the first mark 7 includes an orientation notch formed by a cutout recessed toward the inner portion (center) of the first plate surface 2. The first mark 7 may also include an orientation flat formed by a cutout extending linearly (see the two-dot chain line).

[0177] 12 , the first size D1 of the receiver wafer 1 in this embodiment includes a first receiver size D11 (first receiver diameter) and a second receiver size D12 (second receiver diameter). The first receiver size D11 is the diameter outside the first mark 7 of the receiver wafer 1 on the first plate surface 2 side. The second receiver size D12 is the diameter outside the first mark 7 of the receiver wafer 1 on the second plate surface 3 side.

[0178] The first receiver size D11 may be 1 inch or more and 12 inches or less. The first size D1 may have a value belonging to at least one of the ranges of 1 inch or more and 2 inches or less, 2 inches or more and 4 inches or less, 4 inches or more and 6 inches or less, 6 inches or more and 8 inches or less, 8 inches or more and 10 inches or more and 12 inches or less. The first receiver size D11 is preferably 4 inches or more.

[0179] The second receiver size D12 is smaller than the first receiver size D11. The difference (D11-D12) between the second receiver size D12 and the first receiver size D11 may be greater than 0 inch and equal to or less than 1 inch.

[0180] The difference value (D11-D12) may have a value belonging to at least one of the ranges of greater than 0 inches and equal to or less than 0.1 inches, 0.1 inches or more and equal to or less than 0.2 inches, 0.2 inches or more and equal to or less than 0.3 inches, 0.3 inches or more and equal to or less than 0.4 inches, 0.4 inches or more and equal to or less than 0.5 inches, 0.5 inches or more and equal to or less than 0.6 inches, 0.6 inches or more and equal to or less than 0.7 inches, 0.7 inches or more and equal to or less than 0.8 inches, 0.8 inches or more and equal to or less than 0.9 inches, and 0.9 inches or more and equal to or less than 1 inch.

[0181] Fig. 14 is a plan view showing a base wafer 10 according to the second embodiment. Fig. 15 is a cross-sectional view taken along line XV-XV shown in Fig. 14. The base wafer 10 according to the second embodiment is a wafer that is used together with the receiver wafer 1 according to the second embodiment in the manufacturing method of the semiconductor device SM. Below, configurations that are different from (can be compared with) the base wafer 10 according to the first embodiment will be described.

[0182] The base wafer 10 according to the second embodiment has a second size D2 that is smaller than the first size D1 of the receiver wafer 1. Specifically, the second size D2 is smaller than the first receiver size D11. The second size D2 may be smaller than the second receiver size D12. The second size D2 may be larger than the second receiver size D12. The second size D2 may be approximately equal to the second receiver size D12.

[0183] The base wafer 10 includes a third corner 14 and a fourth corner 15. The third corner 14 connects the third plate surface 11 and the second side wall 13. The third corner 14 is angular and not chamfered. The third corner 14 connects the third plate surface 11 and the second side wall 13 at a substantially right angle. The fourth corner 15 connects the fourth plate surface 12 and the second side wall 13. The fourth corner 15 is angular and not chamfered. The fourth corner 15 connects the fourth plate surface 12 and the second side wall 13 at a substantially right angle.

[0184] Fig. 16 is a process diagram showing a manufacturing method of the semiconductor device SM according to the second embodiment. Fig. 17 is a cross-sectional view showing a bonding step S11 according to the second embodiment. Fig. 18 is an enlarged cross-sectional view showing an edge of the laminated wafer 20 according to the second embodiment.

[0185] 16, in the manufacturing method of the semiconductor device SM according to the second embodiment, the receiver bevel portion 35 is formed in advance on the receiver wafer 1, so that the step S2 of forming the bevel portion 21 is omitted, and the step S3 of forming the device structure 22 is performed after the step S1 of preparing the laminated wafers 20. In other words, the manufacturing method according to the second embodiment includes steps S1 to S21, similar to the first embodiment, except for the step S2 of forming the bevel portion 21.

[0186] 17 , the bonding step S11 includes bonding the receiver wafer 1 having the receiver bevel portion 35 to the base wafer 10. As in the first embodiment, in this step, the first plate surface 2 of the receiver wafer 1 and the third plate surface 11 of the base wafer 10 are bonded together by a direct wafer bonding method. In the bonded state (bonded state) of the receiver wafer 1 and the base wafer 10, the brittle layer 23 is unevenly distributed on the first plate surface 2 of the receiver wafer 1 (the third plate surface 11 of the base wafer 10) side.

[0187] In this embodiment, the second size D2 of the base wafer 10 is smaller than the first receiver size D11 of the receiver wafer 1. The base wafer 10 is attached to the receiver wafer 1 with a space inward from the receiver bevel 35. Specifically, the base wafer 10 is attached with a space inward from the first corner 5 of the receiver wafer 1, and does not protrude outward beyond the receiver bevel 35.

[0188] If the second size D2 is less than the second receiver size D12, the base wafer 10 may be attached to the receiver wafer 1 with a space inward from the second corner 6. If the second size D2 is approximately equal to the second receiver size D12, the base wafer 10 may be attached to the receiver wafer 1 with the second sidewall 13 positioned above the second corner 6.

[0189] Referring to FIG. 18, after the step S12 of forming the donor wafer 24, the stacked wafers 20 include the receiver wafer 1 having a cross-sectional shape that is processed into a reverse tapered shape with respect to the donor wafer 24 by the receiver bevel portion 35.

[0190] In this embodiment, the second size D2 of the donor wafer 24 is smaller than the first receiver size D11 of the receiver wafer 1. The donor wafer 24 is bonded to the receiver wafer 1 at a spaced-inward distance from the receiver bevel 35. Specifically, the base wafer 10 is bonded to the receiver wafer 1 at a spaced-inward distance from the first corner 5 of the receiver wafer 1 and does not protrude outward beyond the receiver bevel 35.

[0191] If the second size D2 is less than the second receiver size D12, the donor wafer 24 may be bonded to the receiver wafer 1 so that it is spaced inward from the second corner 6. If the second size D2 is approximately equal to the second receiver size D12, the donor wafer 24 may be bonded to the receiver wafer 1 so that the second sidewall 13 is positioned above the second corner 6.

[0192] Fig. 19 is a cross-sectional view showing a bonding step S11 according to a modified example. Fig. 20 is an enlarged cross-sectional view showing an end portion of a laminated wafer 20 according to a modified example. With reference to Figs. 19 and 20, in the manufacturing method of a semiconductor device SM according to a modified example, the second plate surface 3 of the receiver wafer 1 and the third plate surface 11 of the base wafer 10 are bonded by a direct wafer bonding method. That is, in the manufacturing method according to the modified example, the processing step S7 of the receiver wafer 1 is performed on the second plate surface 3.

[0193] When the receiver wafer 1 and the base wafer 10 are bonded (adhered), the fragile layer 23 is unevenly distributed on the second surface 3 of the receiver wafer 1 (the third surface 11 of the base wafer 10).

[0194] In this example, the second size D2 of the base wafer 10 is set to be smaller than the second receiver size D12 of the receiver wafer 1, and the base wafer 10 is attached to the receiver wafer 1 with a space inward from the receiver bevel 35. Specifically, the base wafer 10 is attached with a space inward from the second corner 6 of the receiver wafer 1, and does not protrude outward beyond the receiver bevel 35.

[0195] 20 , after the donor wafer 24 formation step S12, the stacked wafers 20 include the receiver wafer 1 having a cross-sectional shape that is tapered relative to the donor wafer 24 by the receiver bevel portion 35. The donor wafer 24 is bonded to the receiver wafer 1 at a distance inward from the receiver bevel portion 35 (second corner portion 6) and does not protrude outward beyond the receiver bevel portion 35.

[0196] In the modified example, the second size D2 of the base wafer 10 (donor wafer 24) is limited to be equal to or smaller than the second receiver size D12 (preferably smaller than the second receiver size D12). Therefore, when the alignment margin of the base wafer 10 relative to the receiver wafer 1 is taken into consideration, the manufacturing method of the second embodiment is preferable.

[0197] As described above, the manufacturing method of the semiconductor device SM includes a step S1 of preparing the laminated wafers 20 and a step S3 of forming the device structure 22. In the step S1 of preparing the laminated wafers 20, the laminated wafers 20 are prepared, which include the receiver wafer 1 having the receiver bevel portion 35 and the donor wafer 24. In the step S3 of forming the device structure 22, the device structure 22 is formed on the donor wafer 24 side.

[0198] This provides a method for manufacturing the semiconductor device SM with a novel process. For example, according to this manufacturing method, the receiver bevel portion 35 of the receiver wafer 1 suppresses cracks in the stacked wafers 20. Furthermore, the process S2 of forming the bevel portion 21 on the donor wafer 24 can be omitted. This reduces the process burden on the donor wafer 24, and the device structure 22 is appropriately formed on the donor wafer 24 side.

[0199] In the step S1 of preparing the laminated wafers 20, the laminated wafers 20 may include a donor wafer 24 that does not have a bevel portion. According to this manufacturing method, the process load on the donor wafer 24 is appropriately reduced.

[0200] The donor wafer 24 may have a material different from that of the receiver wafer 1. According to this manufacturing method, cracks in the stacked wafers 20 including different materials are suppressed by the receiver bevel portion 35. The receiver wafer 1 may include a wide bandgap semiconductor. The donor wafer 24 may include a wide bandgap semiconductor. According to this manufacturing method, cracks in the stacked wafers 20 including a wide bandgap semiconductor are suppressed.

[0201] The receiver wafer 1 may contain SiC. The donor wafer 24 may contain SiC. According to this manufacturing method, cracks are suppressed in the stacked wafers 20 containing SiC. In this case, the receiver wafer 1 may contain SiC, and the donor wafer 24 may contain SiC having crystal properties different from those of the receiver wafer 1. According to this manufacturing method, cracks are suppressed in the stacked wafers 20 containing SiC having different crystal properties.

[0202] The receiver wafer 1 may include a polycrystalline material, and the donor wafer 24 may include a single crystal material. This manufacturing method suppresses cracks in the laminated wafers 20 that include a polycrystalline material and a single crystal material. Furthermore, since the receiver wafer 1 that includes a polycrystalline material is less expensive than the receiver wafer 1 that includes a single crystal material, manufacturing costs are reduced.

[0203] The receiver wafer 1 may have a first polytype (first atomic arrangement), and the donor wafer 24 may have a second polytype (second atomic arrangement) different from the first polytype. This manufacturing method suppresses cracking in the laminated wafers 20 including the first and second polytypes. The receiver wafer 1 may include a tetragonal crystal structure, and the donor wafer 24 may include a hexagonal crystal structure. This manufacturing method suppresses cracking in the laminated wafers 20 including the tetragonal crystal structure and the hexagonal crystal structure.

[0204] The receiver wafer 1 may contain 3C—SiC, and the donor wafer 24 may contain 4H—SiC. This manufacturing method suppresses cracks in the stacked wafers 20 containing 3C—SiC and 4H—SiC.

[0205] The receiver wafer 1 may be processed into a reverse tapered shape with respect to the donor wafer 24 by the receiver bevel portion 35. In this case, the alignment margin of the donor wafer 24 with respect to the receiver wafer 1 is ensured while maintaining the protective effect of the receiver bevel portion 35.

[0206] The donor wafer 24 may be smaller in size than the receiver wafer 1. This configuration prevents the donor wafer 24 from overhanging the receiver wafer 1, thereby preventing cracks in the donor wafer 24. The donor wafer 24 may be thinner than the receiver wafer 1. This manufacturing method prevents cracks in the thin donor wafer 24.

[0207] The step S1 of preparing the laminated wafers 20 may include a step S6 of preparing the receiver wafer 1, a step S8 of preparing the base wafer 10, a step S11 of bonding the receiver wafer 1 and the base wafer 10, and a step S12 of forming the donor wafer 24. In the step S12 of forming the donor wafer 24, the base wafer 10 may be thinned while being bonded to the receiver wafer 1.

[0208] According to this manufacturing method, the thin donor wafer 24 is supported by the receiver wafer 1, so that the donor wafer 24 does not need to be handled alone. As a result, cracks in the thin donor wafer 24 are appropriately suppressed by the receiver bevel portion 35, and processing of the thin donor wafer 24 is appropriately performed.

[0209] The base wafer 10 does not have to have a bevel portion. If the base wafer 10 has a bevel portion, a sharp bevel portion remains in the donor wafer 24 during the thinning step (S12) of the base wafer 10, and this may become a starting point for cracks. In this regard, a base wafer 10 without a bevel portion avoids this risk.

[0210] The base wafer 10 thinning step (S12) may include a step of cutting the base wafer 10 horizontally along the surface of the base wafer 10. According to this manufacturing method, a base wafer 10 recycling step S5 can be performed. In the recycling step S5, the base wafer 10 used in the donor wafer 24 formation step S12 is reused as a new base wafer 10. The recycling step S5 may include a polishing step S21 of the cut surface of the new base wafer 10.

[0211] The base wafer 10 may be cut horizontally from a region on the receiver wafer 1 side relative to a thickness position of the middle portion of the base wafer 10. The base wafer 10 may have a fragile layer 23 therein that extends horizontally, and may be cut horizontally starting from the fragile layer 23. According to this manufacturing method, the fragile layer 23 improves the cutting efficiency of the base wafer 10.

[0212] The step S1 of preparing the laminated wafers 20 may include a step S9 of forming a fragile layer 23 and a bonding step S11. In the step S9 of forming the fragile layer 23, the fragile layer 23 is formed inside the base wafer 10 before the bonding step S11. In the bonding step S11, the base wafer 10 having the fragile layer 23 is bonded to the receiver wafer 1. According to this manufacturing method, the fragile layer 23 is appropriately formed in the base wafer 10 without being restricted by the receiver wafer 1. This allows the base wafer 10 to be appropriately cut starting from the fragile layer 23.

[0213] The method for manufacturing the semiconductor device SM may include a polishing step S13 for polishing the cut surface of the donor wafer 24 after the cutting step (S12) of the base wafer 10.

[0214] The step S3 of forming the device structure 22 may include a step S14 of forming an epitaxial layer 26 using the donor wafer 24 as a growth starting point. The epitaxial layer 26 may have a material different from that of the receiver wafer 1. The epitaxial layer 26 may include a wide bandgap semiconductor. The epitaxial layer 26 may include SiC.

[0215] The epitaxial layer 26 may have a third polytype that is different from the first polytype of the receiver wafer 1. The epitaxial layer 26 may have a third polytype that is different from the second polytype of the donor wafer 24 (base wafer 10). The epitaxial layer 26 may include hexagonal crystals. The thickness of the epitaxial layer 26 may be less than the thickness of the receiver wafer 1. The thickness of the epitaxial layer 26 may be greater than the thickness of the donor wafer 24.

[0216] The step S3 of forming the device structure 22 may include a step S15 of forming a functional device 27. In the step S15 of forming the functional device 27, a device region 28 may be set on the donor wafer 24 side, and the functional device 27 may be formed in the device region 28.

[0217] The device region 28 may have a first side 28a extending in a first direction and a second side 28b extending in a second direction. The second direction is a direction intersecting (specifically, perpendicular to) the first direction. A first length L1 of the first side 28a may be 0.1 mm or more and 20 mm or less. A second length L2 of the second side 28b may be 0.1 mm or more and 20 mm or less.

[0218] The first length L1 may be 1 mm or more. The first length L1 may be 5 mm or more. The first length L1 may be 10 mm or more. The first length L1 may be 15 mm or more. The second length L2 may be 1 mm or more. The second length L2 may be 5 mm or more. The second length L2 may be 10 mm or more. The second length L2 may be 15 mm or more.

[0219] Increasing the plane area of ​​the device region 28 (semiconductor device SM) increases the resistance to large currents and large voltages. In particular, semiconductor devices SM using wide bandgap semiconductors (SiC) are used in relatively high voltage environments.

[0220] Therefore, it is preferable to set a large flat area device region 28 and manufacture a large-area semiconductor device SM with high breakdown voltage and high efficiency. In this case, the first length L1 and the second length L2 are preferably 5 mm or more. In this case, by using a receiver wafer 1 including a polycrystalline material, the manufacturing cost of the large-area semiconductor device SM is appropriately reduced.

[0221] The manufacturing method of the semiconductor device SM may include a dicing step S4. In the dicing step S4, the laminated wafer 20 may be cut in the thickness direction. According to this manufacturing method, the semiconductor device SM is manufactured, which includes a part of the receiver wafer 1 and a part of the donor wafer 24 as a base material.

[0222] Fig. 21 is a plan view showing the first semiconductor device SM1. Fig. 22 is a cross-sectional view taken along line XXII-XXII shown in Fig. 21. Fig. 23 is a plan view showing an example layout of the device surface 44. Fig. 24 is a cross-sectional view taken along line XXIV-XXIV shown in Fig. 21. Fig. 25 is a cross-sectional view taken along line XXV-XXV shown in Fig. 21.

[0223] 21 to 25, a first semiconductor device SM1 is an example of a semiconductor device SM manufactured using the manufacturing method according to the first embodiment or the manufacturing method according to the second embodiment (including modifications). The first semiconductor device SM1 is a semiconductor switching device having an insulated gate transistor structure Tr as an example of a functional device 27. The transistor structure Tr has a trench gate vertical structure.

[0224] The first semiconductor device SM1 includes a chip 40 formed in a rectangular parallelepiped shape. The chip 40 may also be referred to as a “semiconductor chip.” The chip 40 has a stacked structure including a first semiconductor layer 41, a second semiconductor layer 42, and a third semiconductor layer 43.

[0225] In this embodiment, the first semiconductor layer 41 is made of a polycrystalline portion and is formed by a portion of the receiver wafer 1. In this embodiment, the second semiconductor layer 42 is made of a single crystal portion and is formed by a portion of the donor wafer 24. In this embodiment, the third semiconductor layer 43 is made of a single crystal portion and is formed by a portion of the epitaxial layer 26.

[0226] The first semiconductor layer 41 has n-type conductivity, the second semiconductor layer 42 has n-type conductivity, and the third semiconductor layer 43 has n-type conductivity. The second semiconductor layer 42 has an n-type impurity concentration that is less than the n-type impurity concentration of the first semiconductor layer 41. The third semiconductor layer 43 has an n-type impurity concentration that is less than the n-type impurity concentration of the second semiconductor layer 42.

[0227] The description of the configurations (materials, thickness, etc.) of the first semiconductor layer 41, the second semiconductor layer 42, and the third semiconductor layer 43 applies to the description of the configurations (materials, thickness, etc.) of the receiver wafer 1, the donor wafer 24, and the epitaxial layer 26.

[0228] The chip 40 has a device surface 44, a non-device surface 45, and four sidewalls 46. The device surface 44 is formed by the third semiconductor layer 43, the non-device surface 45 is formed by the first semiconductor layer 41, and the sidewalls 46 are formed by the first semiconductor layer 41, the second semiconductor layer 42, and the third semiconductor layer 43. The device surface 44 is formed by a portion of the device surface 25 described above, and the non-device surface 45 is formed by a portion of the second plate surface 3 described above.

[0229] The device surface 44 and the non-device surface 45 are formed in a rectangular shape when viewed vertically. The planar shape and area of ​​the device surface 44 (non-device surface 45) correspond to the planar shape and area of ​​the device region 28.

[0230] The first semiconductor device SM1 includes a transistor structure Tr formed on the device surface 44. The configuration of the transistor structure Tr will be described below. The first semiconductor device SM1 includes a p-type body region 47 formed in a surface layer portion of the device surface 44. The body region 47 has a p-type impurity concentration higher than the n-type impurity concentration of the third semiconductor layer 43.

[0231] The body region 47 is formed in the inner portion of the device surface 44 at a distance inward from the periphery (sidewall 46) of the device surface 44. The body region 47 is formed in the surface layer portion of the third semiconductor layer 43 at a distance from the second semiconductor layer 42 toward the device surface 44, and faces the first semiconductor layer 41 and the second semiconductor layer 42 with a part of the third semiconductor layer 43 interposed therebetween.

[0232] The first semiconductor device SM1 includes a plurality of trench-type (trench electrode-type) gate structures 50 formed in the device surface 44. The gate structures 50 may also be referred to as "trench electrode structures." The plurality of gate structures 50 are formed inwardly of the device surface 44 and spaced apart from the periphery (sidewall 46) of the device surface 44.

[0233] The multiple gate structures 50 are arranged at intervals in the m-axis direction and each extend in a strip-like manner in the a-axis direction. That is, the multiple gate structures 50 are arranged in a stripe pattern in the a-axis direction. The extension direction of the multiple gate structures 50 coincides with the off-direction of the SiC single crystal. Of course, the multiple gate structures 50 may also be arranged at intervals in the a-axis direction and each extend in a strip-like manner in the m-axis direction.

[0234] The plurality of gate structures 50 penetrate the body region 47 and are located in the third semiconductor layer 43. The plurality of gate structures 50 are formed at intervals on the device surface 44 side from the second semiconductor layer 42, and face the first semiconductor layer 41 and the second semiconductor layer 42 with a part of the third semiconductor layer 43 interposed therebetween.

[0235] The plurality of gate structures 50 include trenches 51, insulating films 52, buried electrodes 53, and buried insulators 54. The trenches 51 are formed on the device surface 44 and define the wall surfaces of the gate structures 50. The insulating films 52 coat the wall surfaces of the trenches 51 in a film-like manner. The buried electrodes 53 are buried on the bottom wall side of the trenches 51 via the insulating films 52. The buried electrodes 53 are buried at an interval from the device surface 44 to the bottom wall side of the trenches 51.

[0236] The buried insulator 54 is buried on the opening side of the trench 51 via the insulating film 52, and covers the buried electrode 53 inside the trench 51. The buried electrode 53 is buried at a distance from the device surface 44 toward the bottom wall of the trench 51. Of course, the buried electrode 53 may be disposed inside or outside the trench 51 so as to protrude from the device surface 44.

[0237] The first semiconductor device SM1 includes a plurality of p-type well regions 55 formed in the third semiconductor layer 43 in a region below the plurality of gate structures 50. The plurality of well regions 55 have a p-type impurity concentration higher than the n-type impurity concentration of the third semiconductor layer 43. The p-type impurity concentration of the plurality of well regions 55 may be higher or lower than the p-type impurity concentration of the body region 47.

[0238] The multiple well regions 55 are formed in a thickness range between the bottom of the third semiconductor layer 43 and the bottom walls of the multiple gate structures 50, and overlap the multiple gate structures 50 in a one-to-one correspondence in the thickness direction. The multiple well regions 55 each extend in a strip shape following the extension direction of the corresponding gate structure 50 in a plan view. The multiple well regions 55 are formed at intervals from the bottom of the third semiconductor layer 43 toward the bottom wall of the corresponding gate structure 50, and face the first semiconductor layer 41 and the second semiconductor layer 42 with a part of the third semiconductor layer 43 between them.

[0239] The first semiconductor device SM1 includes a plurality of p-type high concentration well regions 56 formed in the plurality of well regions 55. The plurality of high concentration well regions 56 have a p-type impurity concentration higher than the p-type impurity concentration of the plurality of well regions 55.

[0240] The plurality of high concentration well regions 56 are respectively formed in regions along the bottom walls of the corresponding gate structures 50 within the corresponding well regions 55. The plurality of high concentration well regions 56 are formed at intervals from the bottom of the corresponding well region 55 toward the bottom wall of the corresponding gate structure 50, and face the third semiconductor layer 43 across a part of the corresponding well region 55. The plurality of high concentration well regions 56 each extend in a strip shape following the extension direction of the corresponding gate structure 50 in a plan view.

[0241] The first semiconductor device SM1 includes a plurality of n-type source regions 57 formed in the body region 47. The plurality of source regions 57 have a higher n-type impurity concentration than the n-type impurity concentration of the third semiconductor layer 43.

[0242] The n-type impurity concentration of the multiple source regions 57 is higher than the n-type impurity concentration of the second semiconductor layer 42. The n-type impurity concentration of the multiple source regions 57 may be lower than the n-type impurity concentration of the second semiconductor layer 42. The n-type impurity concentration of the multiple source regions 57 may be higher or lower than the n-type impurity concentration of the first semiconductor layer 41.

[0243] The plurality of source regions 57 are formed along the plurality of gate structures 50 in the surface layer portion of the body region 47. In this embodiment, the plurality of source regions 57 are formed in regions between the plurality of gate structures 50 at intervals in the extension direction of the plurality of gate structures 50.

[0244] The plurality of source regions 57 face the buried electrode 53 and the buried insulator 54 with the insulating film 52 interposed therebetween. The plurality of well regions 55 are formed at intervals from the bottom of the body region 47 toward the device surface 44, and face the third semiconductor layer 43 with a portion of the body region 47 interposed therebetween.

[0245] The first semiconductor device SM1 includes a plurality of p-type contact regions 58 formed in the third semiconductor layer 43. The plurality of contact regions 58 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 47. The p-type impurity concentration of the plurality of contact regions 58 is higher than the p-type impurity concentration of the well region 55. The p-type impurity concentration of the plurality of contact regions 58 may be higher or lower than the p-type impurity concentration of the well high-concentration region 56.

[0246] The plurality of contact regions 58 are formed in regions along the plurality of gate structures 50, respectively. The plurality of contact regions 58 are formed in a one-to-many correspondence with the plurality of gate structures 50. The plurality of contact regions 58 are formed at intervals along the extension direction of the corresponding gate structures 50.

[0247] The plurality of contact regions 58 are formed along the sidewalls and bottom wall of the corresponding gate structures 50. The plurality of contact regions 58 electrically connect the plurality of well regions 55 and the plurality of high concentration well regions 56 to the body region 47.

[0248] The first semiconductor device SM1 includes an insulating interlayer film 59 that selectively covers the device surface 44. The interlayer film 59 is formed by a part of the above-mentioned interlayer film 30. The interlayer film 59 includes a source opening 60 that selectively exposes the device surface 44 and the plurality of gate structures 50.

[0249] The first semiconductor device SM1 includes a first electrode 31 disposed on the interlayer film 59 and a second electrode 32 disposed on the non-device surface 45. The first electrode 31 includes a source electrode 61, a gate electrode 62, and a gate finger electrode 63. In this embodiment, the second electrode 32 is a drain electrode 64. A source potential is applied to the source electrode 61, a gate potential is applied to the gate electrode 62, and a drain potential is applied to the drain electrode 64.

[0250] The source electrode 61 collectively covers the region of the interlayer film 59 where the source opening 60 is formed. The source electrode 61 is electrically connected to the plurality of source regions 57 and the plurality of contact regions 58 on the device surface 44, and is electrically insulated from the buried electrode 53 by the buried insulator 54. The source electrode 61 may have a portion that forms a Schottky junction with the third semiconductor layer 43.

[0251] The gate electrode 62 is disposed on the interlayer film 59 at a distance from the source electrode 61. The gate finger electrode 63 is drawn out from the gate electrode 62 onto the interlayer film 59 and extends in a strip shape along the periphery of the source electrode 61. The gate finger electrode 63 is electrically connected to the plurality of gate structures 50 (the plurality of buried electrodes 53) via gate openings (not shown).

[0252] Fig. 26 is a plan view showing a second semiconductor device SM2. Fig. 27 is a cross-sectional view taken along line XXVII-XXVII shown in Fig. 26. The second semiconductor device SM2 is an example of a semiconductor device SM manufactured using the manufacturing method according to the first embodiment or the manufacturing method according to the second embodiment (including modifications). With reference to Figs. 26 and 27, the second semiconductor device SM2 is a semiconductor rectifier having a diode structure Di as an example of a functional device 27.

[0253] Similar to the first semiconductor device SM1, the second semiconductor device SM2 includes a chip 40. Similar to the first semiconductor device SM1, the chip 40 has a stacked structure including an n-type first semiconductor layer 41, an n-type second semiconductor layer 42, and an n-type third semiconductor layer 43, and includes a device surface 44, a non-device surface 45, and four sidewalls 46.

[0254] The second semiconductor device SM2 includes a p-type guard region 65 formed in a surface layer portion of the device surface 44. The guard region 65 has a p-type impurity concentration higher than the n-type impurity concentration of the third semiconductor layer 43. The guard region 65 is formed in an inner portion of the device surface 44 at a distance from the periphery (sidewall 46) of the device surface 44.

[0255] The guard region 65 extends in a band shape along the periphery of the device surface 44. In this embodiment, the guard region 65 is formed in a polygonal ring shape (quadratic ring shape) surrounding the inner part of the device surface 44. The guard region 65 is formed in the surface layer portion of the third semiconductor layer 43 at a distance from the second semiconductor layer 42 toward the device surface 44, and faces the first semiconductor layer 41 and the second semiconductor layer 42 with a part of the third semiconductor layer 43 in between.

[0256] The second semiconductor device SM2 includes an insulating interlayer film 59 that selectively covers the device surface 44. The interlayer film 59 includes a contact opening 66 that selectively exposes the device surface 44 and the guard region 65. The contact opening 66 exposes an inner portion of the device surface 44 and an inner edge portion of the guard region 65.

[0257] The second semiconductor device SM2 includes a first electrode 31 disposed on the interlayer film 59 and a second electrode 32 disposed on the non-device surface 45. In this embodiment, the first electrode 31 is an anode electrode 67 to which an anode potential is applied, and the second electrode 32 is a cathode electrode 68 to which a cathode potential is applied.

[0258] The anode electrode 67 collectively covers the region of the interlayer film 59 where the contact opening 66 is formed. The anode electrode 67 is electrically connected to the third semiconductor layer 43 and the guard region 65 on the device surface 44. The anode electrode 67 forms a Schottky junction with the third semiconductor layer 43. This forms a diode structure Di (Schottky barrier diode structure) in which the anode electrode 67 serves as an anode region and the third semiconductor layer 43 serves as a cathode region.

[0259] Of course, the second semiconductor device SM2 may include a p-type anode region that forms a p-n junction with the third semiconductor layer 43. The anode region may have a p-type impurity concentration higher than the n-type impurity concentration of the third semiconductor layer 43.

[0260] The anode region may be formed in a surface layer portion of the third semiconductor layer 43 at a distance from the second semiconductor layer 42 toward the device surface 44, and may face the first semiconductor layer 41 and the second semiconductor layer 42 with a part of the third semiconductor layer 43 interposed therebetween. In this case, the anode electrode 67 may be electrically connected to the anode region. With this configuration, a diode structure Di is formed as a pn junction diode.

[0261] The above-described embodiments (including modified examples) can be implemented in other embodiments. For example, in the manufacturing method according to the second embodiment, the step S2 of forming the bevel portion 21 is omitted. However, in the manufacturing method according to the second embodiment, the step S2 of forming the bevel portion 21 (the step of forming the first bevel portion 21A) on the donor wafer 24 may be performed. That is, in the manufacturing method according to the second embodiment, the first bevel portion 21A may be formed at the corner of the donor wafer 24 after the step S2 of forming the bevel portion 21.

[0262] In the method for manufacturing the semiconductor device SM described above, a semiconductor device SM may be manufactured that integrally includes the transistor structure Tr of the first semiconductor device SM1 and the diode structure Di of the second semiconductor device SM2 described above. In other words, the semiconductor device SM may include the transistor structure Tr and the diode structure Di formed on the same chip 40.

[0263] In each of the above-described embodiments, a structure may be adopted in which the conductivity type of an “n-type” semiconductor region is inverted to “p-type” and the conductivity type of a “p-type” semiconductor region is inverted to “n-type.” A specific configuration in this case can be obtained by replacing “n-type” with “p-type” and “p-type” with “n-type” in the above description and accompanying drawings.

[0264] Below, examples of features extracted from this specification and drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components of the above-mentioned embodiments, but are not intended to limit the scope of each clause to the above-mentioned embodiments. The "semiconductor device" in the following clauses may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier device," etc., as necessary.

[0265] [A1] A method for manufacturing semiconductor devices (SM, SM1, SM2), comprising: a step (S1) of preparing a laminated wafer (20) including a receiver wafer (1) and a donor wafer (24); a step (S2) of forming bevel portions (21, 21A, 21B) on either or both of a corner portion (6) of the receiver wafer (1) and a corner portion (15) of the donor wafer (24); and a step (S3) of forming a device structure (22) on the donor wafer (24) side.

[0266] [A2] The method for manufacturing a semiconductor device (SM, SM1, SM2) according to A1, wherein the donor wafer (24) has a material different from that of the receiver wafer (1).

[0267] [A3] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to A1 or A2, wherein the receiver wafer (1) includes a wide bandgap semiconductor and the donor wafer (24) includes a wide bandgap semiconductor.

[0268] [A4] The method for manufacturing a semiconductor device (SM, SM1, SM2) according to A3, wherein the receiver wafer (1) comprises SiC and the donor wafer (24) comprises SiC.

[0269] [A5] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to any one of A1 to A4, wherein the receiver wafer (1) comprises a polycrystal and the donor wafer (24) comprises a single crystal.

[0270] [A6] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to any one of A1 to A5, wherein the receiver wafer (1) has a first polytype, and the donor wafer (24) has a second polytype different from the first polytype.

[0271] [A7] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to any one of A1 to A6, wherein the receiver wafer (1) contains a tetragonal crystal and the donor wafer (24) contains a hexagonal crystal.

[0272] [A8] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to any one of A1 to A7, wherein the bevel portion (21, 21A, 21B) is formed on at least the donor wafer (24), and the device structure (22) is formed on the donor wafer (24) having the bevel portion (21, 21A, 21B).

[0273] [A9] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to any one of A1 to A8, wherein the donor wafer (24) is thinner than the receiver wafer (1), and the bevel portion (21, 21A, 21B) is formed at a corner portion (15) of the donor wafer (24) which is thinner than the receiver wafer (1).

[0274] [A10] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to any one of A1 to A9, wherein the step (S1) of preparing the laminated wafer (20) includes steps (S6, S8) of preparing the receiver wafer (1) and the base wafer (10), a step (S11) of bonding the receiver wafer (1) and the base wafer (10), and a step (S12) of thinning the base wafer (10) in a bonded state to form the donor wafer (24), and the bevel portion (21, 21A, 21B) is formed after the step (S12) of forming the donor wafer (24).

[0275] [A11] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to A10, wherein the base wafer (10) does not have a bevel portion (21, 21A, 21B).

[0276] [A12] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to A11, wherein the donor wafer (24) formation process (S12) includes a process of cutting the base wafer (10) in a horizontal direction along the surface of the base wafer (10).

[0277] [A13] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to A12, wherein the base wafer (10) is cut in the horizontal direction from the region on the receiver wafer (1) side relative to the thickness position of the middle part.

[0278] [A14] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to A12 or A13, wherein the base wafer (10) has a fragile layer (23) therein extending along the horizontal direction, is cut in the horizontal direction starting from the fragile layer (23), and the bevel portion (21, 21A, 21B) is formed after a step (S12) of forming the donor wafer (24) using the fragile layer (23).

[0279] [A15] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to A14, wherein the preparation step (S1) of the laminated wafer (20) includes a step (S9) of forming the fragile layer (23) inside the base wafer (10) before the bonding step (S11), and the bonding step (S11) of bonding the base wafer (10) having the fragile layer (23) to the receiver wafer (1).

[0280] [A16] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to any one of A12 to A15, further comprising a polishing step (S13) of the cut surface of the donor wafer (24) after the donor wafer (24) formation step (S12), and the bevel portion (21, 21A, 21B) formation step (S2) is performed after the polishing step (S13).

[0281] [A17] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to any one of A12 to A16, further comprising a reuse step (S5) of the base wafer (10) used in the formation step (S12) of the donor wafer (24).

[0282] [A18] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to any one of A1 to A17, wherein the forming step (S3) of the device structure (22) includes a forming step (S14) of an epitaxial layer (26) having the donor wafer (24) as a growth starting point.

[0283] [A19] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to any one of A1 to A18, wherein the forming process (S3) of the device structure (22) includes a forming process (S15) of a functional device (27) in a device region (28) set on the donor wafer (24) side.

[0284] [A20] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to A19, wherein the device region (28) has a first side (28a) having a first length (L1) of 5 mm or more and a second side (28b) having a second length (L2) of 5 mm or more.

[0285] [A21] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to any one of A1 to A20, further comprising a dicing step (S4) of cutting the laminated wafer (20) in the thickness direction.

[0286] [B1] A method for manufacturing a semiconductor device (SM, SM1, SM2), comprising: a step (S1) of preparing a stacked wafer (20) including a receiver wafer (1) having a bevel portion (35) and a donor wafer (24); and a step (S3) of forming a device structure (22) on the donor wafer (24) side.

[0287] [B2] The method for manufacturing a semiconductor device (SM, SM1, SM2) according to B1, wherein the donor wafer (24) does not have a bevel portion (35).

[0288] [B3] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to B1 or B2, wherein the donor wafer (24) has a material different from that of the receiver wafer (1).

[0289] [B4] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to any one of B1 to B3, wherein the receiver wafer (1) includes a wide bandgap semiconductor and the donor wafer (24) includes a wide bandgap semiconductor.

[0290] [B5] The method for manufacturing a semiconductor device (SM, SM1, SM2) according to B4, wherein the receiver wafer (1) comprises SiC and the donor wafer (24) comprises SiC.

[0291] [B6] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to any one of B1 to B5, wherein the receiver wafer (1) comprises a polycrystal and the donor wafer (24) comprises a single crystal.

[0292] [B7] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to any one of B1 to B6, wherein the receiver wafer (1) has a first polytype and the donor wafer (24) has a second polytype different from the first polytype.

[0293] [B8] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to any one of B1 to B7, wherein the receiver wafer (1) contains a tetragonal crystal and the donor wafer (24) contains a hexagonal crystal.

[0294] [B9] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to any one of B1 to B8, wherein the receiver wafer (1) is processed into an inverse tapered shape relative to the donor wafer (24) by the bevel portion (35).

[0295] [B10] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to any one of B1 to B9, wherein the donor wafer (24) has a size smaller than that of the receiver wafer (1).

[0296] [B11] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to any one of B1 to B10, wherein the donor wafer (24) is thinner than the receiver wafer (1).

[0297] [B12] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to any one of B1 to B11, wherein the step (S1) of preparing the laminated wafer (20) includes steps (S6, S8) of preparing the receiver wafer (1) and the base wafer (10), a step (S11) of bonding the receiver wafer (1) and the base wafer (10), and a step (S12) of thinning the base wafer (10) in a bonded state to form the donor wafer (24).

[0298] [B13] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to B12, wherein the base wafer (10) does not have a bevel portion (35).

[0299] [B14] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to B12 or B13, wherein the donor wafer (24) formation step (S12) includes a step of cutting the base wafer (10) in a horizontal direction along the surface of the base wafer (10).

[0300] [B15] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to B14, wherein the base wafer (10) is cut in the horizontal direction from the region on the receiver wafer (1) side relative to the thickness position of the middle part.

[0301] [B16] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to B14 or B15, wherein the base wafer (10) has a fragile layer (23) therein extending along the horizontal direction, and is cut in the horizontal direction starting from the fragile layer (23).

[0302] [B17] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to B16, wherein the preparation step (S1) of the laminated wafer (20) includes a step (S9) of forming the fragile layer (23) inside the base wafer (10) before the bonding step (S11), and the bonding step (S11) of bonding the base wafer (10) having the fragile layer (23) to the receiver wafer (1).

[0303] [B18] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to any one of B14 to B17, further comprising a polishing step (S13) of the cut surface of the donor wafer (24) after the donor wafer (24) formation step (S12).

[0304] [B19] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to any one of B14 to B18, further comprising a step (S5) of reusing the base wafer (10) used in the step (S12) of forming the donor wafer (24).

[0305] [B20] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to any one of B1 to B19, wherein the forming step (S2) of the device structure (22) includes a forming step (S14) of an epitaxial layer (26) whose growth origin is the donor wafer (24).

[0306] [B21] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to any one of B1 to B20, wherein the forming step (S3) of the device structure (22) includes a step (S15) of forming a functional device (27) in a device region (28) set on the donor wafer (24) side.

[0307] [B22] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to B21, wherein the device region (28) has a first side (28a) having a first length (L1) of 5 mm or more and a second side (28b) having a second length (L2) of 5 mm or more.

[0308] [B23] A method for manufacturing a semiconductor device (SM, SM1, SM2) according to any one of B1 to B22, further comprising a dicing step (S4) of cutting the laminated wafer (20) in the thickness direction.

[0309] [C1] A semiconductor device (SM, SM1, SM2) including a first semiconductor layer (41), a second semiconductor layer (42) made of a material different from that of the first semiconductor layer (41) and stacked on the first semiconductor layer (41), and a third semiconductor layer (43) made of a material different from that of the first semiconductor layer (41) and stacked on the second semiconductor layer (42).

[0310] [C2] A semiconductor device (SM, SM1, SM2) according to C1, wherein the first semiconductor layer (41) includes a wide bandgap semiconductor, the second semiconductor layer (42) includes a wide bandgap semiconductor, and the third semiconductor layer (43) includes a wide bandgap semiconductor.

[0311] [C3] The semiconductor device (SM, SM1, SM2) according to C2, wherein the first semiconductor layer (41) contains SiC, the second semiconductor layer (42) contains SiC, and the third semiconductor layer (43) contains SiC.

[0312] [C4] A semiconductor device (SM, SM1, SM2) according to any one of C1 to C3, wherein the first semiconductor layer (41) comprises polycrystalline, the second semiconductor layer (42) comprises single crystal, and the third semiconductor layer (43) comprises single crystal.

[0313] [C5] A semiconductor device (SM, SM1, SM2) according to any one of C1 to C4, wherein the first semiconductor layer (41) has a first polytype, the second semiconductor layer (42) has a second polytype different from the first polytype, and the third semiconductor layer (43) has a third polytype different from the first polytype.

[0314] [C6] A semiconductor device (SM, SM1, SM2) according to any one of C1 to C5, wherein the first semiconductor layer (41) includes a tetragonal crystal, the second semiconductor layer (42) includes a hexagonal crystal, and the third semiconductor layer (43) includes a hexagonal crystal.

[0315] [C7] A semiconductor device (SM, SM1, SM2) described in any one of C1 to C6, wherein the first semiconductor layer (41) has a first thickness T1, the second semiconductor layer (42) has a second thickness T2 that is less than the first thickness T1, and the third semiconductor layer (43) has a third thickness T3 that is less than the first thickness T1.

[0316] [C8] The semiconductor device (SM, SM1, SM2) according to C7, wherein the third thickness T3 is greater than the second thickness T2.

[0317] [C9] A semiconductor device (SM, SM1, SM2) according to any one of C1 to C8, wherein the first semiconductor layer (41) has a first conductivity type (n-type), the second semiconductor layer (42) has a first conductivity type (n-type), and the third semiconductor layer (43) has the first conductivity type (n-type).

[0318] [C10] A semiconductor device (SM, SM1, SM2) according to any one of C1 to C9, wherein the second semiconductor layer (42) has a lower impurity concentration than the first semiconductor layer (41), and the third semiconductor layer (43) has a lower impurity concentration than the first semiconductor layer (41).

[0319] [C11] The semiconductor device (SM, SM1, SM2) according to any one of C1 to C10, wherein the third semiconductor layer (43) has a lower impurity concentration than the second semiconductor layer (42).

[0320] [C12] A semiconductor device (SM, SM1, SM2) according to any one of C1 to C11, further including a first electrode (31, 61, 62, 63, 67) arranged on the third semiconductor layer (43) and a second electrode (32, 64, 68) arranged on the first semiconductor layer (41).

[0321] [C13] A semiconductor device (SM, SM1, SM2) according to C12, further comprising an insulating interlayer film (59) covering the third semiconductor layer (43), and the first electrode (31, 61, 62, 63, 67) is arranged on the interlayer film (59).

[0322] [C14] The semiconductor device (SM, SM1, SM2) according to any one of C1 to C11, further comprising a functional device (27) formed in the third semiconductor layer (43).

[0323] [C15] The semiconductor device (SM, SM1, SM2) according to C14, wherein the functional device (27) includes a trench electrode structure (50) formed in the third semiconductor layer (43).

[0324] [C16] A semiconductor device (SM, SM1, SM2) according to C15, wherein the trench electrode structure (50) is formed in the third semiconductor layer (43) at a distance from the second semiconductor layer (42) and faces the second semiconductor layer (42) across a portion of the third semiconductor layer (43).

[0325] [C17] A semiconductor device (SM, SM1, SM2) according to C15 or C16, further comprising a body region (47) formed in a surface layer portion of the third semiconductor layer (43), and the trench electrode structure (50) penetrates the body region (47).

[0326] [C18] A semiconductor device (SM, SM1, SM2) according to C17, wherein the body region (47) is formed in the third semiconductor layer (43) at a distance from the second semiconductor layer (42) and faces the second semiconductor layer (42) across a portion of the third semiconductor layer (43).

[0327] [C19] A semiconductor device (SM, SM1, SM2) according to any one of C14 to C18, further including a first electrode (31, 61, 62, 63, 67) arranged on the third semiconductor layer (43) and a second electrode (32, 64, 68) arranged on the first semiconductor layer (41).

[0328] [C20] The semiconductor device (SM, SM1, SM2) according to C19, wherein the first electrode (31, 61, 62, 63, 67) has a portion that forms a Schottky junction with the third semiconductor layer (43).

[0329] Although specific embodiments have been described in detail above, these are merely examples that clarify the technical content. Various technical ideas extracted from this specification can be appropriately combined without being limited by the order of explanation in the specification, the order of the embodiment examples, the order of the modified examples, etc.

[0330] 1 Receiver wafer 6 Second corner 10 Base wafer 15 Fourth corner 20 Stacked wafer 21 Bevel portion 21A First bevel portion 21B Second bevel portion 22 Device structure 23 Fragile layer 24 Donor wafer 26 Epitaxial layer 27 Functional device 28 Device region 28a First edge 28b Second edge 30 First electrode 31 Second electrode 41 First semiconductor layer 42 Second semiconductor layer 43 Third semiconductor layer 47 Body region 50 Trench electrode structure 59 Interlayer film 61 Source electrode (first electrode) 62 Gate electrode (first electrode) 63 Gate finger electrode (first electrode) 64 Drain electrode (second electrode) 67 Anode electrode (first electrode) 68 Cathode electrode (second electrode) L1 First length L2 Second length S1 Stacked wafer preparation step S2 Device structure formation step S3 Bevel portion formation step S4 Dicing step S5 Base wafer reuse step S6 Receiver wafer preparation step S8 Base wafer preparation step S10 Fragile layer formation step S11 Bonding step S12 Donor wafer formation step S13 Donor wafer polishing step S14 Epitaxial layer formation step S15 Functional device formation step SM First semiconductor device SM1 First semiconductor device SM2 Second semiconductor device T1 First thickness T2 Second thickness T3 Third thickness

Claims

1. A method for manufacturing a semiconductor device, comprising: a step of preparing a stacked wafer including a receiver wafer and a donor wafer; a step of forming a bevel portion on either or both of a corner of the receiver wafer and a corner of the donor wafer; and a step of forming a device structure on the donor wafer side.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the donor wafer has a different material from the receiver wafer.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the receiver wafer includes SiC, and the donor wafer includes SiC.

4. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the receiver wafer includes a polycrystalline material, and the donor wafer includes a single crystal material.

5. A method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the bevel portion is formed on at least the donor wafer, and the device structure is formed on the donor wafer having the bevel portion.

6. A method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein the donor wafer is thinner than the receiver wafer, and the bevel portion is formed at a corner of the donor wafer that is thinner than the receiver wafer.

7. A method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein the step of preparing the laminated wafers includes a step of preparing the receiver wafer and the base wafer, a step of bonding the receiver wafer and the base wafer, and a step of thinning the base wafer in a bonded state to form the donor wafer, and the bevel portion is formed after the step of forming the donor wafer.

8. The method for manufacturing a semiconductor device according to claim 7, wherein the step of forming the donor wafer includes a step of cutting the base wafer in a horizontal direction along the surface of the base wafer.

9. The method for manufacturing a semiconductor device according to claim 8, wherein the base wafer is cut in the horizontal direction from a region on the receiver wafer side relative to a thickness position of the intermediate portion.

10. A method for manufacturing a semiconductor device as described in claim 8 or 9, wherein the base wafer has a weak portion therein extending along the horizontal direction, and is cut in the horizontal direction starting from the weak portion, and the bevel portion is formed after the donor wafer formation process using the weak portion.

11. The method for manufacturing a semiconductor device according to claim 10, wherein the laminated wafer preparation step includes a step of forming the fragile portion inside the base wafer before the bonding step, and a bonding step of bonding the base wafer having the fragile portion to the receiver wafer.

12. The method for manufacturing a semiconductor device according to any one of claims 1 to 11, wherein the step of forming the device structure includes a step of forming an epitaxial layer using the donor wafer as a growth starting point.

13. A method for manufacturing a semiconductor device, comprising: a step of preparing a stacked wafer including a receiver wafer having a bevel portion and a donor wafer; and a step of forming a device structure on the donor wafer side.

14. The method for manufacturing a semiconductor device according to claim 13, wherein the donor wafer has a different material than the receiver wafer.

15. The method for manufacturing a semiconductor device according to claim 13 or 14, wherein the receiver wafer includes SiC, and the donor wafer includes SiC.

16. The method for manufacturing a semiconductor device according to any one of claims 13 to 15, wherein the receiver wafer includes a polycrystalline material, and the donor wafer includes a single crystal material.

17. The method for manufacturing a semiconductor device according to any one of claims 13 to 16, wherein the receiver wafer is processed by the bevel portion to have an inversely tapered shape relative to the donor wafer.

18. The method for manufacturing a semiconductor device according to any one of claims 13 to 17, wherein the donor wafer has a size equal to or smaller than that of the receiver wafer.

19. The method for manufacturing a semiconductor device according to any one of claims 13 to 18, wherein the donor wafer is thinner than the receiver wafer.

20. A method for manufacturing a semiconductor device according to any one of claims 13 to 19, wherein the step of preparing the laminated wafers includes the steps of preparing the receiver wafer and the base wafer, bonding the receiver wafer and the base wafer together, and thinning the base wafer in the bonded state to form the donor wafer.

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