Sure-starting bandgap reference

Abstract

A bandgap device configured to generate a bandgap reference voltage is disclosed. A bandgap reference core is used to generate a bandgap current. The bandgap current is generated from a sum of at least one scaled Proportional to Absolute Temperature (PTAT) voltage current and at least one Complementary to Absolute Temperature (CTAT) current. A ballast circuit is configured to generate a ballast current that is driven into the bandgap reference core to start up the bandgap reference core and that continues to drive the ballast current into the bandgap reference core throughout the operation of the bandgap reference core. In this manner, the ballast current is used to start up the bandgap reference core but simply becomes a part of the operating current of the bandgap reference core. Thus, there is no need to turn off the current after the bandgap reference core has been turned off.

Description

SURE-STARTING BANDGAP REFERENCERelated Applications

[0001] This application claims the benefit of provisional patent application serial number 63 / 626,314, filed January 29, 2024, the disclosure of which is hereby incorporated herein by reference in its entirety.Field of the Disclosure

[0002] This disclosure relates generally to methods and systems for generating a bandgap voltage.Background

[0003] Voltage references are ubiquitous in electronic systems as they provide a basis for data conversion, voltage regulators, current regulators, and temperature sensors. They provide a stable voltage in the presence of variations in supply voltage, temperature, and process variations. The bandgap technique is the most common reference in integrated circuit (IC) technology.

[0004] Most bandgap reference circuits contain a current source and a current mirror that are cross-coupled or a pair of current mirrors that are cross-coupled. This creates a potential undesirable zero-current state. This state is avoided using startup circuits which are notoriously difficult to design reliably. A further challenge is to prove that the startup circuit works over all conditions. A further problem is in detecting the point at which the startup current should be turned off, which itself varies with temperature and other parameters. These problems present a significant risk as they may not be found in a simulation or perhaps not even after a significant period after production. Most systems that require a reference will not function at all with a failed reference.Summary

[0005] In some embodiments, a bandgap device configured to generate a bandgap reference voltage includes: a bandgap reference core configured togenerate a bandgap current, wherein the bandgap current is a sum of a scaled Proportional to Absolute Temperature, PTAT, current and a Complementary to Absolute Temperature, CTAT, current, the bandgap reference core includes: a first circuit portion including a narrow device, wherein the narrow device is configured to set the CTAT current; a second circuit portion including a wider device, wherein the wider device is configured to set a PTAT current and scale the PTAT current to generate the scaled PTAT current; a reference voltage generation circuit that is configured to generate the bandgap reference voltage from the bandgap current; and a ballast circuit configured to generate a ballast current that is driven into the bandgap reference core to start up the bandgap reference core and that continues to drive the ballast current into the bandgap reference core throughout an operation of the bandgap reference core.

[0006] In some embodiments, the bandgap device further includes an amplifier operably associated with the bandgap reference core, the amplifier being configured to generate a servo current that is driven into the bandgap reference core to regulate the PTAT current and the CTAT current.

[0007] In some embodiments, the amplifier includes a differential transconductance amplifier having a first terminal coupled to detect a first input voltage into the first circuit portion and a second terminal coupled to detect a second input voltage into the second circuit portion, the differential transconductance amplifier is configured to drive the servo current into the first circuit portion in order to drive the first input voltage such that the first input voltage and the second input voltage are maintained at a voltage ratio between the first input voltage and the second input voltage.

[0008] In some embodiments, the voltage ratio is equal to 1 .

[0009] In some embodiments, the amplifier includes a differential transconductance amplifier having a first input terminal coupled to the first circuit portion and a second input terminal coupled to the second circuit portion, the differential transconductance amplifier is configured to drive the servo current into the first circuit portion such that a total first circuit portion current driven into the first circuit portion includes the servo current added to the ballast current; andthe differential transconductance amplifier is configured to maintain a total second circuit portion current and the total first circuit portion current at a current ratio of the total second circuit portion current driven over the total first circuit portion current.

[0010] In some embodiments, the current ratio is equal to 1 .

[0011] In some embodiments, the bandgap device further includes a current mirror configured to mirror the total second circuit portion current into the first circuit portion as a reflected current, wherein: the current mirror has a current ratio of the total second circuit portion current over the reflected current that is greater than one; and the total first circuit portion current includes a sum of the servo current, the ballast current, and the reflected current.

[0012] In some embodiments, the current ratio of the total second circuit portion current over the reflected current is equal to 2.

[0013] In some embodiments, the current mirror includes a cross-coupled current mirror, wherein the cross-coupled current mirror includes: a P-channel metal-oxide semiconductor (PMOS) current mirror having a PMOS input device and a PMOS output device; and an N-channel metal-oxide semiconductor (NMOS) current mirror having an NMOS input device and an NMOS output device, wherein: the NMOS input device is coupled to the PMOS output device; the PMOS input device is coupled to the NMOS output device; the NMOS input device is coupled to the first circuit portion; and the NMOS output device is coupled to the second circuit portion.

[0014] In some embodiments, the ballast current is a first ballast current and wherein the ballast circuit is configured to generate a second ballast current that is input into the amplifier.

[0015] In some embodiments, the amplifier has an input stage and an output stage; the ballast circuit is configured to generate a third ballast current; the second ballast current is input into the input stage of the amplifier; and the third ballast current is input into the output stage of the amplifier.

[0016] In some embodiments, the amplifier includes a differential transconductance amplifier having a first terminal coupled to detect a first inputvoltage into the first circuit portion and a second terminal coupled to detect a second input voltage into the second circuit portion, the differential transconductance amplifier is configured to drive the servo current into the first circuit portion and the second circuit portion in order to drive the first input voltage such that the first input voltage and the second input voltage are maintained at a voltage ratio between the first input voltage and the second input voltage.

[0017] In some embodiments, the ballast current is a first ballast current and wherein the ballast circuit is configured to: generate the first ballast current so that the first ballast current is driven into a first current to start up a first current portion and that continues to drive the first ballast current into the first current portion throughout the operation of the bandgap reference core; and generate a second ballast current that is driven into a second current portion to start up the second current portion and that continues to drive the second ballast current into the second current portion throughout the operation of the bandgap reference core.

[0018] In some embodiments, the voltage ratio is equal to 1 .

[0019] In some embodiments, the ballast circuit is configured to: generate a third ballast current that is driven into the reference voltage generation circuit and that drives the third ballast current into the reference voltage generation circuit throughout the operation of the bandgap reference core.

[0020] In some embodiments, the PTAT current is a first PTAT current; the CTAT current is a first CTAT current; the ballast current is a first ballast current; and a bandgap circuit includes: a first field effect transistor (FET) and a second FET coupled in a feedback configuration, wherein the first FET is configured to receive a power source voltage and the second FET is configured to generate a second ballast current, the first ballast current being based on the second ballast current; a third circuit portion connected to the second FET, wherein the third circuit portion generates a second PTAT current; and a fourth circuit portion connected to the first FET, wherein the fourth circuit portion is configured to generate a second CTAT current.

[0021] In some embodiments, the ballast current includes the second PTAT current and the second CTAT current.

[0022] In some embodiments, the bandgap device further includes a current mirror that generates the first ballast current in response to the second ballast current.

[0023] In some embodiments, a method of generating a ballast voltage includes: generating a ballast current that is driven into a bandgap reference core to start up the bandgap reference core and that continues to drive the ballast current into the bandgap reference core throughout an operation of the bandgap reference core; generating a CTAT current with a first circuit portion of the bandgap reference core, the CTAT current being set by a narrow device in the first circuit portion in response to generating the ballast current; generating a scaled PTAT current with a second circuit portion of the bandgap reference core, wherein a PTAT current is scaled and set by a wider device in the second circuit portion in response to generating the ballast current; generating a bandgap current from a sum of the CTAT current and the scaled PTAT current; and generating a bandgap voltage from the bandgap current.

[0024] In some embodiments, the method further includes generating the servo current that is driven into the bandgap reference core to regulate the PTAT current and the CTAT current.

[0025] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.Brief Description of the Drawing Figures

[0026] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0027] FIG. 1 illustrates a circuit diagram of a bandgap device, in accordance with some embodiments;

[0028] FIG. 2A illustrates a circuit diagram of a differential input, a single- ended output, and a differential transconductance amplifier, in accordance with some embodiments;

[0029] FIG. 2B illustrates a circuit diagram of a differential input, a single- ended output, and a transconductance amplifier, in accordance with some embodiments;

[0030] FIG. 3 illustrates a circuit diagram of a bandgap device, in accordance with some embodiments;

[0031] FIG. 4 illustrates a circuit diagram of a differential input and a single- ended output voltage amplifier, in accordance with some embodiments;

[0032] FIG. 5 illustrates a resistive device, in accordance with some embodiments;

[0033] FIG. 6 illustrates a resistive device, in accordance with some embodiments;

[0034] FIG. 7 illustrates a resistive device, in accordance with some embodiments;

[0035] FIG. 8 is a flow diagram illustrating a method of generating a bandgap voltage, in accordance with some embodiments; and

[0036] FIG. 9 illustrates an example of user elements, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, and like wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, and near field communications.Detailed Description

[0037] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood thatthese concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0038] It should be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0039] It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0040] It should be understood that, although the terms “upper,” “lower,” “bottom,” “intermediate,” “middle,” “top,” and the like may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed an “upper” element and, similarly, a second element could be termed an “upper” element depending on the relative orientations of these elements, without departing from the scope of the present disclosure.

[0041] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude thepresence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0042] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having meanings that are consistent with their meanings in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0043] The techniques and embodiments described herein utilize a baseemitter voltage (VBE) of a diode device, such as a diode connected transistor or a diode to generate a bandgap voltage. The relationship between a VBE and a temperature has a negative temperature slope. The negative temperature slope fluctuates with process and current density. However, positive temperature slopes are produced when a common current is driven through both a narrow device and a wider device, as this creates negative VBE temperature coefficients of different slopes, the difference of which is a positive temperature coefficient. The voltage across a resistive device, in series with the narrow device, has the difference of two VBEs impressed across it and this difference voltage has a positive temperature coefficient. By appropriately summing a current with the negative temperature coefficient and a scaled current with the positive temperature coefficient, a bandgap current that is temperature invariant is generated. A bandgap voltage can be generated with this bandgap current.

[0044] Embodiments of a bandgap device configured to generate a bandgap reference voltage are disclosed. A bandgap reference core is used to generate a bandgap current. The bandgap current is generated from a sum of at least one scaled Proportional to Absolute Temperature (PTAT) current and at least one Complementary to Absolute Temperature (CTAT) current. The bandgap reference core comprises a ballast circuit configured to generate a ballast current that is driven into the bandgap reference core to start up the bandgap reference core and continues to drive the ballast current into the bandgap reference corethroughout the bandgap reference core’s operation. In this manner, the ballast current is used to start up the bandgap reference core and simply becomes a part of the operating current of the bandgap reference core. Thus, there is no need to turn off the current after the bandgap reference core has been started.

[0045] FIG. 1 illustrates a circuit diagram of a bandgap device 100, in accordance with some embodiments.

[0046] In some embodiments, the bandgap device 100 is formed as an integrated circuit (IC) on a semiconductor substrate (not explicitly shown). The bandgap device 100 is configured to generate a bandgap reference voltage VBG. A bandgap voltage is a direct current (DC) voltage that is temperature independent because the bandgap voltage is based on the voltage required for electrons to move from one valence band to another. Accordingly, in some embodiments, the bandgap voltage is a voltage that is based on the bandgap energy Eg in the semiconductor material (e.g., Silicon, Gallium Arsenide).

[0047] The bandgap device 100 includes a bandgap reference core 102 configured to generate a bandgap current 11 and bandgap current I2. The bandgap currents 11 , I2 are temperature stable because they are a correctly proportioned sum of CT AT currents (developed by impressing a VBE across a resistor) and PTAT currents (developed by impressing a AVBE across a resistor). The bandgap reference core 102 includes first circuit portion 104 and a second circuit portion 106.

[0048] The bandgap reference core 102 defines a node N1 in the first circuit portion 104 and a node N2 in the second circuit portion 106. With respect to the first circuit portion 104, a resistor R1 is connected between the node N1 and a node NG. A narrow device D1 is connected in parallel between the node N1 and the node NG. The narrow device D1 is a diode device (the narrow device D1 is also referred to as a diode device D1 throughout this disclosure). In this example, the diode device D1 is a diode, but in other embodiments, the diode device D1 may be a diode connected transistor. With respect to the second circuit portion 106, a resistor R2 is connected between the node N2 and the node NG. The series connection of a wider device D2 and a resistor R3 is connectedin parallel with the resistor R2 between the node N2 and the node NG. The wider device D2 is a diode device (the wider device D2 is also referred to as a diode device D2 throughout this disclosure). In this example, the diode device D2 is a diode, but in other embodiments, may be a diode connected transistor.

[0049] In the bandgap reference core 102 of FIG. 1 , the narrow device D1 has a junction area of 2 X A and the wider device D2 has a junction area of the narrow device (D1 ) and m X A. “A” is a base value for the junction area and “m” is a ratio that is a design choice. In some embodiments, the integer “m” is set between 8 and 24. The resistor R3 is in connected in series with the wider device D2 and has a resistance ra. The resistors R1 , R2 have the same resistive values rb so that, with the same voltage developed at the nodes N1 , N2, the same CTAT current will be contributed to both of the bandgap currents 11 , I2. Further, the same PTAT current will be contributed to both of the bandgap currents 11 , I2.

[0050] As explained in further detail below, the bandgap device 100 operates a feedback loop that maintains the voltage at the node N1 and the voltage at the node N2 to be equal. The VBE is the voltage across the narrow device D1 . As such, the VBE is a CTAT voltage, which is a voltage that is inversely proportional to temperature. Since the resistor R3 is connected in series with the wider device D2 and since the voltages at the nodes N1 , N2 are maintained as equal, this means that the voltage difference between the VBE and the voltage across the wider device D2 is dropped across the resistor R3. As such, this voltage difference is the AVBE, which is a PTAT voltage. The voltage across the narrow device D1 is a CTAT voltage and, therefore, the voltages across both the resistors R1 , R2, along with the current in the resistors R1 , R2 are also CTAT voltages. A ratio between the resistors R1 / R3 sets the scale factor between the CTAT and PTAT currents that is required for temperature stability. This ratio is called the “PTAT gain.” The narrow device D1 is connected between ground and the node N1 while the wider device and the resistor D2-R1 series elements are connected between ground and the node N2.

[0051] The bandgap currents 11 , I2 are constrained to be equal (as explained in further detail below) in order for the voltages at the nodes N1 , N2 to be equal. In FIG. 1 , the current ratio between the bandgap currents 11 , I2 is one. In other embodiments, the current ratio between the bandgap currents 11 , I2 is a value other than one. In FIG. 1 , the voltage ratio between the bandgap voltages at the nodes N1 , N2 is equal to 1 .

[0052] Since the bandgap currents 11 , I2 are equal and the resistors R1 , R2 have the same resistance value rb, currents IR1 , IR2 across the resistors R1 , R2 are equal. The VBE across the narrow device D1 is impressed across the resistors R1 , R2 and thus, the currents IR1 , IR2 across the resistors R1 , R2 are CTAT currents that are equal. A CTAT current is a current that is inversely proportional to temperature. However, the AVBE that appears across the resistor R3 is a PTAT current. Accordingly, a current ID1 through the narrow device D1 and a current ID2 through the resistor R3 and the wider device D2 are both PTAT currents that are equal. A PTAT current is a current that is directly proportional to temperature. As such, if the PTAT currents ID1 , ID2 are scaled appropriately with the CTAT currents IR1 , IR2, then the sum of the scaled PTAT currents ID1 , ID2 with the CTAT currents IR1 , IR2 provides the bandgap currents 11 , I2 that are temperature independent. The scaling is provided by the resistance value ra of the resistor R3 and the resistance value rb of the resistors R1 , R2. The ratio ra / rb determines a PTAT gain of a cell. The ratio of the resistance values ra / rb scales the PTAT currents ID1 , ID2 appropriately with the CTAT currents IR1 , IR2 so that the sum of the scaled PTAT currents ID1 , ID2 with the CTAT currents IR1 , IR2 provides the bandgap currents 11 , I2 that are temperature independent. The first circuit portion 104 has the narrow device D1 , wherein the narrow device D1 is configured to set the PTAT currents ID1 , ID2. The second circuit portion 106 has the wider device D2, wherein the wider device D2 is configured to set the CTAT currents IR1 , IR2.

[0053] An N-channel metal-oxide-semiconductor (NMOS) current mirror 110N includes an NMOS input device NID1 (simply referred to by the reference element identifier NID1 for brevity), an NMOS output device NOD1 (simplyreferred to by the reference element identifier NOD1 for brevity), an NMOS cascode input device NIC1 (simply referred to by the reference element identifier NIC1 for brevity), and an NMOS cascode output device NOC1 (simply referred to by the reference element identifier NOC1 for brevity). A source of the NOC1 is coupled to a drain of the NOD1 . A drain of the NOC1 is coupled to a drain of a P-channel metal-oxide semiconductor (PMOS) device PIC1 (simply referred to by the reference element identifier PIC1 for brevity). A drain of the NIC1 is coupled to a node NF. A source of the NI01 is coupled to a drain of the NID1 . A gate of the NIC1 is coupled to a gate of the NOC1 and a gate of the NID1 is coupled to a gate of the NOD1 . The gate of the NID1 is coupled to the drain of the NIC1 . A source of the NOD1 is coupled to the node N2 and a source of the NID1 is coupled to the node N1 .

[0054] A cross-coupled current mirror is configured to reflect the bandgap current 11 into the bandgap current I2. A PMOS output device POD1 (simply referred to by the reference element identifier POD1 for brevity), a PMOS input device PID1 (simply referred to by the reference element identifier PID1 for brevity), a PMOS device POC1 (simply referred to by the reference element identifier POC1 for brevity), and the PIC1 operate as a current mirror and are field effect transistors (FETs). The PID1 and the PIC1 are inputs to the current mirror and operate to cause a reflection in the corresponding POD1 and the POC1 . The POC1 , the PIC1 , the NIC1 , and the NOC1 operate to provide cascode bias voltages to the POD1 and the PID1 and the NOD1 and the NID1 . The POC1 , the PIC1 , the NIC1 , and the NOC1 increase the output impedance of a PMOS current mirror 1 10P and the NMOS current mirror 1 10N and protect the POD1 , the PID1 , the NOD1 , and the NID1 from over-voltage.

[0055] The gate of the NID1 is connected to the drain of the NIC1 (this is sometime referred to as a “diode-connected transistor”). This connection ensures that the NID1 operates in either a cut-off or a saturation mode. This connection also provides the input of the cross-coupled current mirror. The bandgap current 11 is driven through the NI01 and the NID1 into the NOC1 and the NOD1 . Similarly, the bandgap current I2 is driven into the PIC1 and the PID1is driven into the POC1 and the POD1 . A cross-coupled current mirror is formed by the PMOS current mirror 1 10P and the NMOS current mirror 1 10N. The cross-coupled current mirror is cross-coupled because an output of the PMOS current mirror 110P is coupled to the input of the NMOS current mirror 1 10N and the input of the NMOS current mirror 110N is coupled to the output of the PMOS current mirror 110P. The PMOS current mirror 110P has a current ratio of 2:1 from input to output, while the NMOS current mirror 110N has a current ratio of 1 :1.

[0056] The bandgap device 100 includes a cross-coupled amplifier 110 that includes an amplifier 112, the PMOS current mirror 1 10P, the NMOS current mirror 1 10N, and the PMOS current mirror 1 18. A cross coupled current mirror is formed by the PMOS current mirror 1 10P and the NMOS current mirror 110N. The cross-coupled current mirror operates with the amplifier 112, as explained below.

[0057] The amplifier 112 is operably associated with the bandgap reference core 102. The amplifier 1 12 is configured to generate a servo current IS that is driven into the bandgap reference core 102. The servo current IS is generated by the amplifier 112 in order to maintain the voltage at the node N1 and the voltage at the node N2 at a voltage ratio. In FIG. 1 , the voltage ratio is 1 since the voltage at the node N1 and the voltage at the node N2 are to be maintained as equal. In FIG. 1 , the amplifier 1 12 is configured to drive a T-stable current into the core to balance the bandgap currents 11 , I2 at equal magnitudes and force the nodes N1 , N2 to equal voltages.

[0058] Accordingly, the amplifier 1 12 is a differential transconductance amplifier having one input terminal coupled to detect the voltage at the node N1 into the first circuit portion 104, and another input terminal coupled to detect the voltage at the node N2 into the second circuit portion 106. The amplifier 1 12 is configured to drive the servo current IS into the node NF, which is connected to the first circuit portion 104. The amplifier 1 12 thus drives the servo current IS into the first circuit portion 104. The amplifier 1 12 adjusts a current level of the servo current IS to adjust the current level of the bandgap current 11 . In thismanner, the amplifier 11 maintains the voltage at the node N1 and the voltage at the node N2 as equal.

[0059] A reference voltage generation circuit 1 14 is configured to generate the bandgap reference voltage VBG from a bandgap current IBG. The reference voltage generation circuit 114 includes a PMOS output device POD2 (simply referred to by the reference element identifier POD2 for brevity) and a PMOS complementary device POC2 (simply referred to by the reference element identifier POC2 for brevity). The POD2 has a source connected to a power source node NBAT to receive a power source voltage VBAT. A gate of the POD2 is connected to gates of the PID1 and the POD1 . A drain of the POD2 is connected to a source of the POC2. A drain of the POC2 is connected to a bandgap node NBG. A bandgap resistor RBC is connected to the bandgap node NBG. The POD2 and the POC2 result in the bandgap current I2 being reflected into the reference voltage generation circuit 114 to generate the bandgap current IBG. This results in the bandgap reference voltage VBG being generated at the bandgap node NBG, where the voltage level of the bandgap reference voltage VBG is determined by a resistance value of the bandgap resistor RBC.

[0060] As with other bandgap devices, the cross-coupled current mirror, the reference voltage generation circuit 1 14, the amplifier 112, and the bandgap reference core 102 have a startup problem. Without any additional circuit components , a stable state of the cross-coupled current mirror, the reference voltage generation circuit 114, the amplifier 112, and the bandgap reference core 102 exists where the bandgap currents 11 , I2 and the voltages at the nodes N1 , N2 all have a magnitude of zero amps. With no difference in voltages at the nodes N1 , N2, the input terminals of the amplifier 1 12 are unable to cause the amplifier 112 to drive the bandgap reference core 102 out of the zero-current state. Accordingly, the cross-coupled current mirror, the reference voltage generation circuit 1 14, the amplifier 112, and the bandgap reference core 102 are to be started up to reach a servo point. The servo point is a non-zero point where the bandgap currents 11 , I2 are balanced and have non-zero magnitudesand the voltages at the nodes N1 , N2 of both the first circuit portion 104 and the second current portion 106 are also balanced and have non-zero magnitudes.

[0061] To solve the startup problem, the bandgap device 100 includes a ballast circuit 116. The ballast circuit 1 16 is configured to generate a ballast current IBA1 that is driven into the bandgap reference core 102 to start up the bandgap reference core 102. However, the ballast circuit 1 16 continues to drive the ballast current IBA1 into the bandgap reference core 102 throughout the operation of the bandgap reference core 102. The key to starting up the bandgap reference core 102 is to provide the ballast current IBA1 in the range where the voltages at the nodes N1 , N2 diverge. In response to the voltages at the nodes N1 , N2 diverging, the amplifier 1 12 adjusts for differences until the bandgap currents 11 , I2 are balanced by the amplifier 112 by utilizing the servo current IS. The bandgap current 11 is the sum of the ballast current IBA1 , the servo current IS, and the bandgap current I2 being reflected back onto the POD1 , the POC1 , the NIC1 , and the NID1 . In this embodiment, the current ratio between the bandgap currents 12 / 11 is 2. This means that half of the current value of the bandgap current I2 is reflected onto the bandgap current 11 . The remainder of the bandgap current 11 is provided by the servo current IS and the ballast current IBA1 .

[0062] Thus, unlike other start-up solutions, there is no need to turn off the current used to start up the bandgap reference core 102. Instead, the ballast current IBA1 continues to be injected into the first circuit portion 104 throughout the operation of the bandgap reference core 102 (while the bandgap reference core 102 is turned on to generate the bandgap reference voltage VBG).

[0063] In some embodiments, the ballast current IBA1 is unidirectional, always driving the ballast current IBA1 into the bandgap reference core 102. The amplifier 112 drives the servo current IS into the first circuit portion 104 in a positive feedback region and sinks current out of the bandgap reference core 102 in a negative feedback region. This is advantageous because developing accurate currents in an IC context is problematic. There is no fundamental current reference in electronics, and since IC resistors vary typically by + / -20percent in their resistance value, it is difficult to provide an accurate voltage reference during startup. The amplifier 1 12 is capable of covering this variation. The ballast circuit 1 16 includes a resistor R4, a FET BAL1 , a FET BAL2, a diode device BAL3, a resistor R5, and a resistor R6. In this embodiment, the diode device BAL3 is a diode connected FET (the diode device BAL3, which is the diode connected FET, is also referred to simply as the FET BAL3 below). The resistor R4 is connected in series between the power source node NBAT (that receives the power source voltage VBAT) and a node NBAL1 . The FETs BAL1 , BAL2, BAL3 are each N-channel FETs (NFETs). A drain of the FET BAL1 is coupled to the node NBAL1 . A source of the FET BAL1 is coupled to the node NG. A gate of the FET BAL1 is connected to a node NBAL2. A drain of the FET BAL2 is coupled to a node NBAL3. A drain of the FET BAL3 is coupled to the node NBAL2. The FET BAL3 is coupled in a diode configuration by having a gate of the FET BAL3 connected to the drain of the FET BAL3. Thus, the FET BAL3 is also referred to as the diode device BAL3. The drain of the FET BAL1 is connected to the node NBAL1 . The resistor R6 is connected between the node NBAL2 and an anode of the diode device BAL3. A cathode of the diode device BAL3 is connected to the node NG. The resistor R5 is connected between the node NBAL2 and the node NG. A source of the FET BAL3 is coupled to the node NG.

[0064] The resistor R4 pulls up a gate of the FET BAL2 and the drain of the FET BAL1 . This creates a coarse valued drain current in the FET BAL1 . A gatesource voltage of the FET BAL1 is impressed across the resistor R5, setting the current that is passed through the FET BAL2. This classic circuit is a variation of the Wilson current mirror with one transistor replaced by the resistor R5, as those skilled in the art will appreciate. This creates a feedback loop. An error current flows into the gate of the FET BAL2, which is the difference between a current delivered by the resistor R4 and a current absorbed by the FET BAL1 . If a current of the FET BAL2 is too low, the gate of the FET BAL2 is pulled up, in turn pulling up on the gate of the FET BAL1 and increasing the drain current in theFET BAL1 . If the FET BAL1 current is too high, the FET BAL1 pulls down on the gate of the FET BAL2, causing the loop to operate in the opposite direction.

[0065] Normally, an overdrive of the FET BAL1 (Vgs - VT), which is the difference between a gate-source voltage Vgs and a device threshold voltage VT, is set to be small. So only the device threshold voltage VT of the device appears across the resistor R5. The device threshold voltage VT is also a CTAT voltage, so a CTAT output current is generated across the resistor R6 and the FET BAL3.

[0066] When the FETs BAL1 , BAL2 are operated at low currents, the FETs BAL1 , BAL2 operate in a weak-inversion mode and behave as bipolar transistors. The diode device BAL3 is 8 times larger than the FET BAL1 , so the gate-source voltage Vgs of the diode device BAL3 is smaller and the difference in the gate-source voltage Vgs values results in the CTAT output current across the resistor R6. The PTAT current through the resistor R5 and the CTAT output current through the resistor R6 that are summed at the drain of the FET BAL2 to generate a ballast current IBA2, which is a bandgap current.

[0067] The cross coupled amplifier 110 includes the PMOS current mirror 1 18. The PMOS current mirror 1 18 includes a PMOS input device PIDA (simply referred to by the reference element identifier PIDA for brevity), a PMOS output device PODA (simply referred to by the reference element identifier PODA for brevity), a PMOS complementary input device PICA (simply referred to by the reference element identifier PICA for brevity), and a PMOS complementary output device POCA (simply referred to by the reference element identifier POCA for brevity). A source of the PIDA is coupled to the power source node NBAT. A drain of the PIDA is coupled to a source of the PICA. A source of the PODA is coupled to the power source node NBAT and a drain of the PODA is coupled to a source of the POC1 . A gate of the PODA is coupled to a gate of the PIDA and a gate of the POCA is coupled to a gate of the PIC1 . The gate of the PIDA is coupled to the drain of the PIC1 . A drain of the POCA is coupled to the node NF. The PMOS current mirror 1 18 is configured to reflect the ballast current IBA2 to produce the ballast current IBA1 .

[0068] The ballast circuit 1 16 is self-starting. Since the ballast current IBA2 is a bandgap current, the ballast current IBA1 is temperature stable. This greatly reduces ballast current variation, allowing for a target range current to be achieved and reducing demands in the correction current range of the amplifier 1 12. Note that the gates of the PIDA, the PODA, the PIC1 , the POC1 , and the POC2 are each coupled to one another. The gates of the PIDA, the PODA, the PIC1 , the POC1 , and the POC2 are also configured to receive a voltage VPC. The gates of the NIC1 and the NOC1 are each coupled to one another and are configured to receive a voltage VNC. In some embodiments, the voltage VNC is generated using the cross-coupled current mirror (which is a combination of the PMOS current mirror 1 10P and the NMOS current mirror 110N) and the ballast circuit 1 16.

[0069] FIG. 2A illustrates a circuit diagram of a differential input, a single- ended output, and a differential transconductance amplifier 200A, in accordance with some embodiments.

[0070] The differential transconductance amplifier 200A is configured to generate the servo current IS at an output terminal AO. The output terminal AO is connected to the node NF shown in FIG. 1 . Input terminals IT 1 , IT2 are provided to receive the voltages from the nodes N1 , N2 shown in FIG. 1 . More specifically, the input terminal IT1 is connected to the node N1 shown in FIG. 1 . The input terminal IT2 is connected to the node N2 shown in FIG. 1 .

[0071] The differential transconductance amplifier 200A is configured to generate the servo current IS having a current value that is set in accordance with the difference in the voltages at the input terminals IT1 , IT2. The differential transconductance amplifier 200A has an input stage 202 and an output stage 204. The input stage 202 has a first circuit branch 206 and a second circuit branch 208. The first circuit branch 206 has P-channel FETs (PFETs) PIS1 , PIS2, PIS3 and NFETs NIS1 , NIS2. A source of the PFET PIS1 is connected to a degeneration resistor. A drain of the PFET PIS1 is connected to a source of the PFET PIS2. A drain of the PFET PIS2 is connected a source of the PFET PIS3. A drain of the PFET PIS3 is coupled to a drain of the NFET NIS1 . Asource of the NFET NIS1 is connected to a drain of the NFET NIS2. A source of the NFET NIS2 is coupled to a node NIS. The drain of the PFET PIS3 is coupled to a gate of the PFET PIS2.

[0072] The second circuit branch 208 has PFETs PIS4, PIS5, PIS6 and NFETs NIS3, NIS4. A source of the PFET PIS4 is connected to the degeneration resistor. A drain of the PFET PIS4 connected to a source of the PFET PIS5. A drain of the PFET PIS5 is connected a source of the PFET PIS6. A drain of the PFET PIS6 is coupled to a drain of the NFET NIS3. A source of the NFET NIS3 is connected to a drain of the NFET NIS4. A source of NFET NIS4 is coupled to the node NIS. Gates of the PFETs PIS1 , PIS2, PIS4, PIS5 are coupled to one another. A gate of the PFET PIS3 is coupled to a gate of the PFET PIS6. A gate of the NFET NIS1 is coupled to a gate of the NFET NIS3. A gate of the NFET NIS2 is coupled to the input terminal IT 1 and a gate of the NFET NIS4 is coupled to the input terminal IT2.

[0073] The output stage 204 has a first circuit branch 210 and a second circuit branch 212. The first circuit branch 210 has PFETs POS1 , POS2, POS3, POS7 and NFETs NOS2, NOS3, NOS4. A source of the PFET POS1 is connected to the node NBAT. A drain of the PFET POS1 is connected to a source of the PFET POS2. A drain of the PFET POS2 is connected a source of the PFET POS3. A drain of the PFET POS3 is coupled to a source of the PFET POS7. A drain of the PFET POS7 is connected a drain of the NFET NOS2. A source of the NFET NOS2 is coupled to a drain of the NFET NOS3. A source of the NFET NOS3 is coupled to a drain of the NFET NOS4. A source of the NFET NOS4 is coupled to the node NG.

[0074] The second circuit branch 212 has PFETs POS4, POS5, POS6, and NFETs NOS1 , NOS5, NOS6, NOS7. A source of the PFET POS4 is connected to the power source node NBAT. A drain of the PFET POS4 is connected to a source of the PFET POS5. A drain of the PFET POS5 is connected a source of the PFET POS6. A drain of the PFET POS6 is coupled to a drain of the NFET NOS1 . A source of the NFET NOS1 is connected a drain of the NFET NOS5. A source of the NFET NOS5 is coupled to a drain of the NFET NOS6. A source ofthe NFET NOS6 is coupled to a drain of the NFET NOS7. A source of the NFET NOS7 is coupled to the node NG.

[0075] Gates of each of the NFETs NOS3, NOS4, NOS6, NOS7 and the drain of the NFET NOS2 are coupled to one another. A gate of the NFET NOS2 is coupled to a gate of the NFET NOS5. Each of the gates of the PFETs PIS3, PIS6 and gates of the PFETs POS3, POS6 are coupled to one another. The gates of the PFETs PIS1 , PIS2, PIS4, PIS5 and gates of the PFETs POS1 , POS2 and the drain of the PFET PIS3 are all coupled to one another. Gates of the PFETs POS4, POS5 and the drain of PFET PIS6 are all coupled to one another. Accordingly, the first circuit branch 206 of the input stage 202 and the first circuit branch 210 of the output stage 204 are connected to one another. The second circuit branch 208 of the input stage 202 and the second circuit branch 212 of the output stage 204 are connected to one another.

[0076] The PFETs PIS1 , PS2, PIS3, PIS4, PIS5, and PIS6 form a current mirror so that the servo current IS generated at the output terminal AO is the difference between the current in the first circuit branch 210 and the current in the second circuit branch 212. As shown in FIG. 2A, a ballast current IHEAD is injected into the input stage 202 at the node NIS, and a ballast current ITAIL is injected into the output stage 204 at the sources of the PFETs POS1 , POS4. The ballast current ITAIL is a tail current and also may be referred to as a tail current ITAIL below. The ballast current IHEAD and the ballast current ITAIL are generated by the ballast circuit 1 16 shown in FIG. 1 . The PMOS mirror in the input stage 202 is an active load for a differential pair of the NFETs NIS1 -NIS4 of the input stage 202. The ballast current labeled “IHEAD” is also a “tail” current, the name given to the bias of a source-coupled pair as a holdover from bipolar terminology. The ballast current IHEAD may also be referred to as a tail current IHEAD below. These tail currents IHEAD, ITAIL are normally called “bias” currents. Since the servo current IS causes currents in the bandgap reference core 102 (shown in FIG. 1 ) to balance, this loop causes inputs of the differential transconductance amplifier 200A to drive to the same voltage. This is what the amplifier 112 (shown in FIG. 1 ) responds to. In FIG. 2A, the differentialtransconductance amplifier 200A is called a “transconductance amplifier” because the input is a voltage and the output is a current, therefore the transfer function ratio has units of conductance. The PFETs POS1 - POS6 that are in the output stage 204 (the output stage 204 can also be referred to as an amplifier 204), along with the ballast current ITAIL, also form a source-coupled pair. However, instead of being used for voltage gain, this source-coupled pair is used as a “current steering pair,” the output of which is driven into the NFETs NOS2- NOS7. The NFETs NOS2-NOS7, combined, create an NMOS mirror. The NFETs NOS2-NOS7 provide a differential-to-single-ended conversion to produce, along with the current steering pair, the servo current IS.

[0077] FIG. 2B illustrates a circuit diagram of a differential input, a single- ended output, and a transconductance amplifier 200B, in accordance with some embodiments.

[0078] The transconductance amplifier 200B is the same as the differential transconductance amplifier 200A in FIG. 2A, except that the transconductance amplifier 200B includes an output stage 254 instead of the output stage 204 (also referred to as the amplifier 204). The output stage 254 includes a first circuit branch 260 and a second circuit branch 262. The first circuit branch 260 is the same as the first circuit branch 210 in FIG. 2A, except that the first circuit branch 260 does not include the NFETs NOS2, NOS3, NOS4. Instead, the drain of the PFET POS7 is connected directly to the node NG. The source of the PFET POS7 provides a common mode voltage to the PFET POS3. The second circuit branch 262 is the same as the second circuit branch 212 in FIG. 2A, except that the second circuit branch 262 does not include the NFETs NOS5, NOS6, NOS7. The connection below the output terminal AO is left open and the drain of the PFET POS6 simply connects to the output terminal AO.

[0079] FIG. 3 illustrates a circuit diagram of a bandgap device 300, in accordance with some embodiments.

[0080] In some embodiments, the bandgap device 300 is formed as an IC on a semiconductor substrate (not explicitly shown). The bandgap device 300 is configured to generate the bandgap reference voltage VBG shown in FIG. 1 .The bandgap device 300 is based on the energy required to move an electron from the valence band to a conduction band in a silicon lattice. This energy is quantized and therefore forms the basis for a stable reference. Accordingly, in some embodiments, the bandgap reference voltage VBG is a voltage that is based on the bandgap energy of the semiconductor material (e.g., Silicon, Gallium Arsenide) used to form the bandgap device 300.

[0081] The bandgap device 300 includes a bandgap reference core 302 configured to generate the bandgap current 11 and the bandgap current I2 shown in FIG. 1 . A bandgap current (e.g., one of the bandgap currents 11 , I2) is a DC current that is temperature independent because the bandgap current is based on the voltage required for the electrons to move from one valence band to another. The bandgap reference core 302 includes a first circuit portion 304 and a second circuit portion 306.

[0082] The bandgap reference core 302 defines the node N1 in the first circuit portion 304 and the node N2 in the second circuit portion 306. With respect to the first circuit portion 304, a resistive device R1 ’ is connected between the node N1 and the node NG. A narrow device D1 is connected in parallel between the node N1 and the node NG. The narrow device D1 is a diode device. In this example, the narrow device D1 is a diode, but in other embodiments, the narrow device D1 may be a diode connected transistor. With respect to the second circuit portion 306, a resistive device R2’ is connected between the node N2 and the node NG. The wider device D2 and series connected resistive devices R3A’, R3B’ are connected in parallel between the node N2 and the node NG. The wider device D2 and the series connected resistive devices R3A’, R3B’ are connected in series. The wider device D2 is a diode device. In this example, the wider device D2 is a diode, but in other embodiments, the wider device D2 may be a diode connected transistor.

[0083] In the bandgap reference core 302 of FIG. 3, the narrow device D1 has a junction area of 2 X A and the wider device D2 has a junction area of the narrow device (D1 ) and m X A. “A” is a base value for the junction area and “m” is a ratio that is a design choice. In some embodiments, the integer “m” is setbetween 8 and 24. The resistors R3A’ and R3B’ are in series with the wider device D2 and together have a resistance ra. The resistive device R1 ’ and the resistive device R2’ both have the same resistive values rb, in some embodiments.

[0084] As explained in further detail below, the bandgap device 300 operates a feedback loop that maintains the voltages as equal at nodes N1 and N2. The VBE is the voltage across the narrow device D1 . As such, the VBE is a CTAT voltage, which is a voltage that is inversely proportional to temperature. Since the series connected resistive devices R3A’, R3B’ (the combination of the series connected resistive devices R3A’, R3B’ is referred to as the resistor R3) are connected in series with the wider device D2 and since the voltage at the nodes N1 , N2 are maintained as equal, this means that the voltage difference between the VBE and the voltage across the wider device D2 is dropped across the resistive device R2’. As such, the voltage difference between the devices D1 , D2 is dropped across the resistor R3. The AVBE is a PTAT voltage and the VBE is a CTAT voltage. In FIG. 3, a PTAT gain is set by the ratio of the resistors and the resistive device R17R3 = R27R3. This ratio is called the “PTAT gain.” The narrow device D1 is connected between ground and the node N1 while the wider device and resistors D2-R3A’-R3B’ series elements are connected between ground and the node N2. In other embodiments, the current ratio between the bandgap currents 11 , I2 is a ratio other than one, but usually is an integer ratio for practical implementation considerations.

[0085] The bandgap currents 11 , I2 are constrained to be equal (as explained in further detail below) in order for the voltages at the nodes N1 , N2 to be equal. In FIG. 3, the current ratio between the bandgap currents 11 , I2 is three. In other embodiments, the current ratio between the bandgap currents 11 , I2 is a value other than three. In FIG. 3, the voltage ratio between the bandgap voltages 11 , I2 at the nodes N1 , N2 is equal to 3.

[0086] Since the bandgap currents 11 , I2 are equal and the resistive devices R1 ’, R2’ have the same resistance value rb, the currents IR1 , IR2 across the resistive devices R1 ’, R2’ are equal. The VBE across the narrow device D1 isimpressed across the resistive devices R1 R2’ and thus, the currents IR1 , IR2 across the resistive devices R1 R2’ are CTAT currents that are equal. A CTAT current is a current that is inversely proportional to temperature. However, the AVBE that appears across the series connected resistors R3A’, R3B’ is a PTAT voltage. Accordingly, the current ID1 across the narrow device D1 and the current ID2 across the series connected resistors R3A’, R3B’ and the wider device D2 are both PTAT currents that are equal. A PTAT current is a current that is directly proportional to temperature. As such, if the PTAT currents ID1 , ID2 are scaled appropriately with the CTAT currents IR1 , IR2, then the sum of the scaled PTAT currents ID1 , ID2 with the CTAT currents IR1 , IR2 provide the bandgap currents 11 , I2 that are temperature independent. The CTAT currents IR1 , IR2 through the resistive devices R1 ’, R2’ are equal, in some embodiments. The scaling is provided by the resistance ra of the series connected resistors R3A’, R3B’ and the resistance value rb of the resistive devices R1 ’, R2’. The resistance values ratio rb / ra is a ratio set that determines a PTAT gain of the cell (this is a value greater than one, usually 5 to 10). The ratio of the resistance values rb / ra scales the PTAT currents ID1 , ID2 appropriately with the CTAT currents IR1 , IR2 so that the sum of the scaled PTAT currents ID1 , ID2 with the CTAT currents IR1 , IR2 provide the bandgap currents 11 , I2 that are temperature independent. The first circuit portion 304 has the narrow device D1 , wherein the narrow device D1 is configured to set the PTAT currents ID1 , ID2. The second circuit portion 306 has the wider device D2, wherein the wider device D2 is configured to set the CTAT currents IR1 , IR2.

[0087] The bandgap device 300 includes a current injection circuit 308. The current injection circuit 308 is a current mirror that reflects a fraction of its input current to its output. The current injection circuit 308 includes PMOS devices PINJ1 , PINJ2, PINJ3, PINJ4, PINJ5, PINJ6, PINJ7, PINJ8 (simply referred to by their respective reference element identifier for brevity). A source of the PINJ1 is coupled to the power source node NBAT. The power source node NBAT is configured to receive the power source voltage VBAT, which, in some embodiments, is a battery voltage or a regulated voltage based on a batteryvoltage. A drain of the PINJ1 is coupled to a source of the PINJ2. A drain of the PINJ2 is coupled to a source of the PINJ3. A drain of the PINJ3 is coupled to a source of the PINJ4. A drain of the PINJ4 is coupled to the node N1 . Also, a source of the PINJ5 is coupled to the power source node NBAT. A drain of the PINJ5 is coupled to a source of the PINJ6. A drain of PINJ6 is coupled to a source of the PINJ7. A drain of PINJ7 is coupled to a source of the PINJ8. A drain of the PINJ8 is coupled to the node N2. Gates of the PINJ1 , the PINJ2, the PINJ5, and the PINJ6 are all coupled to each other.

[0088] An amplifier 312 is operably associated with the bandgap reference core 302. The amplifier 312 is configured to generate the servo current IS that is driven into the bandgap reference core 302 to regulate the CTAT current IR1 , the PTAT current ID1 , the CTAT current IR2, and the PTAT current ID2. In this embodiment, the output terminal of the amplifier 312 is connected to the gates of the PINJ1 and the PINJ2 as well as gates of the PINJ3 and the PINJ4. As a result, the servo current IS is injected into both the first circuit portion 304 and the second circuit portion 306. The servo current IS is generated by the amplifier 312 in order to maintain the voltage at the node N1 and the voltage at the node N2 at a voltage ratio. In FIG. 3, the voltage ratio is one since the voltage at the node N1 and the voltage at the node N2 are to be maintained as equal. The amplifier 312 is a voltage amplifier that drives the gates of the PINJ1 , the PINJ2, the PINJ5, and the PINJ6 in turn to convert an amplifier output voltage to the servo current IS, which drives the bandgap reference core 302.

[0089] Accordingly, the amplifier 312, coupled with a PMOS mirror, is a differential transconductance amplifier having one input terminal coupled to detect the voltage at the node N1 into the first circuit portion 304 and another input terminal coupled to detect the voltage at the node N2 into the second circuit portion 306. The amplifier 312 is configured to drive the servo current IS into the gates of the PINJ1 , the PINJ2, the PINJ3 ,and the PINJ4, and thereby drive the servo current IS into both the first circuit portion 304 and the second circuit portion 306. The amplifier 312 thus drives the servo current IS into the first circuit portion 304 and the second circuit portion 306. The amplifier 312 adjustsa current level of the servo current IS to adjust the current level of the bandgap currents 11 , I2. In this manner, the amplifier 312 maintains the voltage at the node N1 and the voltage at the node N2 equal.

[0090] A reference voltage generation circuit 310 is configured to generate the bandgap reference voltage VBG from the bandgap current IBG. The reference voltage generation circuit 310 includes a PMOS output device POD2A, a PMOS output device POD2B, a PMOS cascode device POC2A, and a PMOS cascode device POC2B (simply referred to by their respective reference element identifier for brevity). The POD2A has a source connected to the power source node NBAT to receive the power source voltage VBAT. The POD2A has a drain coupled to a source of the POD2B. A drain of the POD2B is coupled to a source of the POC2A. A drain of the POC2A is coupled to a source of the POC2B. The source of the POC2B is coupled to the bandgap node NBG. A drain of the POC2B is coupled to a resistive device RBG’. The resistive device RBG’ is coupled between the bandgap node NBG and the node NG. Gates of the POD2A and the POD2B are connected to the gates of the PINJ1 , the PINJ2, the PINJ5, and the PINJ6. This results in the bandgap currents 11 , I2 causing the reference voltage generation circuit 310 to generate the bandgap current IBG. This results in the bandgap reference voltage VBG being generated at the bandgap node NBG, where the voltage level of the bandgap reference voltage VBG is determined by a resistance value of the resistive device RBG’.

[0091] The reference voltage generation circuit 310 includes a PMOS output device POD3A, a PMOS output device POD3B, a PMOS complementary device POC3A, and a PMOS complementary device POC3B (simply referred to by their respective reference element identifier for brevity). The POD3A has a source connected to the power source node NBAT to receive the power source voltage VBAT. The POD3A has a drain coupled to a source of the POD3B. A drain of the POD3B is coupled to a source of the POC3A. The POD3A, the POD3B, the POC3A, and the POC3B form another branch for generating another bandgap voltage. Gates of the POD3A and the POD3B are coupled to the gate of the POD2A.

[0092] The reference voltage generation circuit 310 includes a PMOS output device POD4A, a PMOS output device POD4B, a PMOS complementary device POC4A, and a PMOS complementary device POC4B (simply referred to by their respective reference element identifier for brevity). The POD4A has a source connected to the power source node NBAT to receive the power source voltage VBAT. The POD4A has a drain coupled to a source of the POD4B. A drain of the POD4B is coupled to a source of the POC4A. The POD4A, the POD4B, the POC4A, and the POC4B form another branch for generating another bandgap voltage. Gates of the POD4A and the POD4B are coupled to the gate of the POD3A.

[0093] As with other bandgap devices, the current injection circuit 308, the reference voltage generation circuit 310, the amplifier 312, and the bandgap reference core 302 have a startup problem. Without additional circuitry, a stable state of the current injection circuit 308, the reference voltage generation circuit 310, the amplifier 312, and the bandgap reference core 302 exists where the bandgap currents 11 , I2 and the voltages at the nodes N1 , N2 all have a magnitude of zero. With no different voltages at the nodes N1 , N2, the input terminals of the amplifier 312 are unable to cause the amplifier 312 to drive the bandgap reference core 302 out of the zero-current state. Accordingly, the current injection circuit 308, the reference voltage generation circuit 310, the amplifier 312, and the bandgap reference core 302 are to be started up to reach a servo point. The servo point is a non-zero point where the bandgap currents 11 , I2 are balanced and have non-zero magnitudes and the voltages at the nodes N1 , N2 both in the first circuit portion 304 and the second current portion 306 are also balanced and have non-zero magnitudes.

[0094] To solve the startup problem, the bandgap device 300 includes a ballast circuit 316. The ballast circuit 316 is configured to generate the ballast current IBA1 that is driven into the bandgap reference core 302 to start up the bandgap reference core 302. However, the ballast circuit 316 continues to drive the ballast current IBA1 and a ballast current IBA3 into the bandgap reference core 302 throughout the operation of the bandgap reference core 302. The keyto starting up the bandgap reference core 302 is to provide the ballast currents IBA1 , IBA2, IBA3 as well as a ballast current IBA4 in a range where the voltages at the nodes N1 , N2 diverge. In response to voltages at the nodes N1 , N2 diverging, the amplifier 312 adjusts for differences until the PTAT currents ID1 , ID2 are balanced by the amplifier 312 utilizing the servo voltage at the amplifier output of the amplifier 312. (The PMOS gates driven by this servo voltage cause the PINJ1 , the PINJ2, the PINJ3, the PINJ4, the PINJ5, the PINJ6, the PINJ7, and the PINJ8 to produce the appropriate current values).

[0095] Thus, unlike other startup solutions, there is no need to turn off the current used to start up the bandgap reference core 302. Instead, the ballast current IBA1 continues to be injected into the first circuit portion 304 throughout the operation of the bandgap reference core 302 (while the bandgap reference core 302 is turned on to generate the bandgap reference voltage VBG).

[0096] In some embodiments, the ballast currents IBA1 , IBA3 are unidirectional and always driving the ballast currents IBA1 , IBA3 into the bandgap reference core 302. The amplifier 312 drives the servo current IS into the first circuit portion 304 in the positive feedback region and sinks current out of the bandgap reference core 302 in the negative feedback region. This is advantageous because developing accurate currents in an IC context is problematic. There is no fundamental current reference in electronics. Since IC resistors vary typically by + / -20 percent in their resistance value, it is difficult to provide an accurate voltage reference during startup and the amplifier 312 is capable of covering this variation. The amplifier 312 is capable of both sourcing and sinking current. In some embodiments, the amplifier 312 has a limitation on its sink capacity such that it does not reduce the ballast currents IBA1 , IBA2, IBA3, IBA4 beyond the point where it is no longer sufficient to start the circuit.

[0097] The ballast circuit 316 includes series connected resistive devices R4A, R4B, R4C, R4D, the FET BAL1 , the FET BAL2, the diode device BAL3, series connected resistive devices R5A, R5B, R5C, and a resistive device R6’. In this embodiment, the diode device BAL3 is a diode connected FET. The series connected resistive devices R4A, R4B, R4C, R4D are connected in seriesbetween the power source node NBAT (that receives the power source voltage VBAT) and the node NBAL1 shown in FIG. 1 . The FETs BAL1 , BAL2, BAL3 are each NFETs. The drain of the FET BAL1 is coupled to the node NBAL1 . The source of the FET BAL1 is coupled to the node NG. The gate of the FET BAL1 is connected to the node NBAL2 shown in FIG. 1 . The drain of the FET BAL2 is coupled to the node NBAL3 shown in FIG. 1 . The source of the FET BAL3 is coupled to the node NBAL2. The gate of the FET BAL1 is connected to the node NBAL1 . The resistive device R6’ is connected between the node NBAL2 to the anode of the diode device BAL3. The cathode (also referred as a source in this embodiment) of the diode device BAL3 is connected to the node NG. The series connected resistive devices R5A, R5B, R5C are connected between the node NBAL2 and the node NG.

[0098] The series connected resistive devices R4A, R4B, R4C, R4D pull up the gate of the FET BAL2 and the drain of the FET BAL1 . This creates the coarse valued drain current in the FET BAL1 . The gate-source voltage of the FET BAL1 is impressed across the series connected resistive devices R5A, R5B, R5C, setting the ballast current IBA2 that is passed through the FET BAL2. This classic circuit is a variation of the Wilson current mirror with one transistor replaced by the series connected resistive devices R5A, R5B, R5C, as those skilled in the art will appreciate. This creates a feedback loop. An error current flows into the gate of the FET BAL2, which is the difference between a current that is delivered by the series connected resistive devices R4A, R4B, R4C, R4D and that absorbed by the FET BAL1 . If the FET BAL2 current is too low, the gate of the FET BAL2 is pulled up, in turn pulling up on the gate of the the FET BAL1 and increasing the drain current of the FET BAL1 . If the FET BAL1 current is too high, the FET BAL1 pulls down on the gate of the FET BAL2, causing the loop to operate in the opposite direction.

[0099] Normally, the overdrive of the FET BAL1 (Vgs - VT), which is the difference between the gate-source voltage Vgs and the device threshold voltage VT, is set to be small. So only the device threshold voltage VT of the device appears across the series connected resistive devices R5A, R5B, R5C. Thedevice threshold voltage VT is also a CTAT voltage, so a CTAT output current is generated across the resistive device R6’ and the FET BAL3.

[0100] When the FETs BAL1 , BAL2 are operated at low currents, the FETs BAL1 , BAL2 operate in weak-inversion mode and behave as bipolar transistors. The diode device BAL3 is 8 times larger than the FET BAL1 , so the gate-source voltage Vgs of the diode device BAL3 is smaller and the difference in the gatesource voltage Vgs values results in the CTAT current IR1 across the resistive device R1 We have a CTAT current through the series connected resistive devices R5A, R5B, R5C and the PTAT current through the resistive device R6’ that are summed at the drain of the FET BAL2 to generate the coarse ballast current IBA2, which is the bandgap current IBG. In some embodiments, the current developed by the ballast circuit 316 is the ballast current IBA2 (which is a coarse bandgap current and may be referred to as a coarse bandgap current IBA2) as currents in the FETs BAL1 , BAL2 are not constrained to be equal or at a fixed ratio. Although the bandgap device 300 reduces temperature variation significantly, the bandgap device 300 is not restrained to operate classically as a “bandgap” current.

[0101] The bandgap device 300 includes a PMOS current mirror 318. The PMOS current mirror 318 includes a pair of cascoded PMOS input devices PIN1 A, PIN1 B; a pair of cascoded complementary PMOS devices PIC1 A, PIC1 B; a pair of cascoded PMOS output devices PIN2A, PIN2B; a complementary PMOS device PIC2A; a pair of cascoded PMOS output devices PIN3A, PIN3B; a complementary PMOS device PIC3A; a pair of cascoded PMOS output devices PIN4A, PIN4B; a complementary PMOS device PIC4A; a pair of cascoded PMOS output devices PIN5A, PIN5B; and a pair of cascoded complementary PMOS devices PIC5A, PIC5B (simply referred to by their respective reference element identifier for brevity).

[0102] A source of the PIN1 A is coupled to the power source node NBAT. A drain of the PIN1 A is coupled to a source of the PIN1 B. A drain of the PIN1 B is coupled to a source of the PIC1 A. A drain of the PIC1 A is coupled to a source of the PIC1 B. A drain of the PIC1 B is coupled to the drain of the FET BAL2.

[0103] A source of the PIN2A is coupled to the power source node NBAT. A drain of the PIN2A is coupled to a source of the PIN2B. A drain of the PIN2B is coupled to a source of the PIC2A. A drain of the PIC2A is coupled to the drain of the PINJ3.

[0104] A source of the PIN3A is coupled to the power source node NBAT. A drain of the PIN3A is coupled to a source of the PIN3B. A drain of the PIN3B is coupled to a source of the PIC3A. A drain of the PIC3A is coupled to the drain of the PINJ7.

[0105] A source of the PIN4A is coupled to the power source node NBAT. A drain of the PIN4A is coupled to a source of the PIN4B. A drain of the PIN4B is coupled to a source of the PIC4A. A drain of the PIC4A is coupled to the drain of the POC2A.

[0106] A source of the PIN5A is coupled to the power source node NBAT. A drain of the PIN5A is coupled to a source of the PIN5B. A drain of the PIN5B is coupled to a source of the PIC5A. A drain of the PIC5A is coupled to a source of the PIC5B. A drain of the PIC5B is coupled to a drain of the amplifier 312.

[0107] Gates of the PIN2A, the PIN2B, the PIN5A, the PIN5B, the PIN1 A, the PIN1 B, the PIN3A, the PIN3B, the PIN4A, and the PIN4B are coupled to one another. The drain of the PIC1 A is coupled to the gates of the PIN1 A and the PIN1 B and, thus, this is the input of the PMOS current mirror 318. The gates of the PIN5A and the POC4A as well as gates of the PIC1 A, the PIC2A, the PIC3A, the PIC4A, the POC2A, the POC3A are all coupled to one another. The PMOS current mirror 318 is configured to reflect the ballast current IBA2 to produce the ballast current IBA1 .

[0108] The ballast circuit 316 is self-starting. Since the ballast current IBA2 is the bandgap current IBG, the ballast current IBA1 is temperature stable. This greatly reduces ballast current variation, allowing for the target range current to be arrived at and reducing demands in the correction current range of the amplifier 312.

[0109] The PMOS current mirror 318 operates so that the ballast current IBA2 is reflected onto the PIN2A, the PIN2B, and the PIC2A to generate the ballastcurrent I BA1 . The ballast current IBA1 is driven into the first circuit portion 304. Also, the PMOS current mirror 318 operates so that the ballast current IBA2 is reflected onto the PIN3A, the PIN3B, and the PIC3A to generate the ballast current IBA3. The ballast current IBA3 is driven into the second circuit portion 306. Additionally, the PMOS current mirror 318 operates so that the ballast current IBA2 is reflected onto the PIN4A, the PIN4B, and the PIC4A to generate the ballast current IBA4. The ballast current IBA4 is driven into the bandgap node NBG, where the bandgap reference voltage VBG is generated, as explained above with respect to FIG. 1 . The ballast currents IBA1 , IBA2, IBA3, IBA4 are generated by the ballast circuit 316 at startup and continually are provided throughout the operation of the bandgap reference core 302. In this manner, the ballast currents IBA1 , IBA2, IBA3, IBA4 start up the bandgap reference core 302, but there is no need to know when to turn off the ballast currents IBA1 , IBA2, IBA3, IBA4 as the ballast currents IBA1 , IBA2, IBA3, IBA4 are continually provided throughout the operation of the bandgap reference core 302.

[0110] The PMOS current mirror 318 operates so that the ballast current IBA2 is reflected onto the PIN5A, the PIN5B, the PIC5A, and the PIC5B to generate the ballast currents IBA1 , IBA2, IBA3, IBA4 that are input into the amplifier 312.

[0111] FIG. 4 illustrates a circuit diagram of a differential input and a differential transconductance amplifier 400, in accordance with some embodiments.

[0112] The differential transconductance amplifier 400 is configured to generate the servo current IS at the output terminal AO. In this case, the differential transconductance amplifier 400 is a single-ended output voltage amplifier. The output terminal AO would be connected to the gates of the PINJ1 , the PINJ2, the PINJ5, and the PIN6 shown in FIG. 3. The input terminal IT1 is connected to the node N2 in FIG. 3. The input terminal IT2 is connected to the node N1 in FIG. 3. More specifically, the input terminal IT1 is connected to the node N1 in FIG. 3. The input terminal IT2 is connected to the node N2 in FIG. 3. The differential transconductance amplifier 400 has a current mirror 402 and adifferential pair of FETs ND1 , ND2. In this embodiment, the differential pair of FETs ND1 , ND2 are each NFETs.

[0113] The current mirror 402 is formed by PFETs PAS1 , PAS2, PAS3, PAS4. A source of the PFET PAS1 is coupled to the power source node NBAT to receive the power source voltage VBAT. A drain of the PFET PAS1 is coupled to a source of the PFET PAS2. A complementary NFET NAC1 is coupled between the PFET PAS2 and the differential FET ND1 . A drain of the PFET PAS2 is coupled to a drain of the NFET NAC1 . A source of the NFET NAC1 is coupled to a to the drain of the differential FET ND1 . A source of the differential FET ND1 is coupled to a node INH.

[0114] A source of the PFET PAS3 is coupled to the power source node NBAT to receive the power source voltage VBAT. A drain of the PFET PAS3 is coupled to a source of the PFET PAS4. A complementary NFET NAC2 is coupled between the PFET PAS4 and the differential FET ND2. A drain of the PFET PAS4 is coupled to a drain of the NFET NAC2. A source of the NFET NAC2 is coupled to the to a drain of the differential FET ND2. A source of the differential FET ND2 is coupled to the node INH. Gates of the PFETs PAS1 , PAS3, and the drain of the PFET PAS2 are coupled to each other. Gates of the PFETS PAS2, PAS4 are coupled to each other. Gates of the complementary NFETs NAC1 , NAC2 are coupled to each other. A gate of the differential FET ND1 is coupled to the input terminal IT1 , and a gate of the different FET ND2 is coupled to the input terminal IT2.

[0115] The current mirror 402 is configured to reflect a current that propagates through the PFETs PAS1 , PAS2; the complementary NFET NAC1 ; and the differential FET ND1 onto a current being propagated through the PFETs PAS3, PAS4; the complementary NFET NAC2; and the differential FET ND2. As such, the servo current IS is generated to have a current level that is based on the voltage difference between the voltage at the input terminal IT1 and the voltage at the input terminal IT2.

[0116] In this embodiment, the ballast circuit 316 in FIG. 3 generates the ballast current ITAILN through the PIN1 A, the PIN1 B, the PIC1 A, and the PIC1 Bto the PIN5A, the PIN5B, the PIC5A, and the PIC5B, which is injected into the node INH. The servo current IS is thus partially provided by the ballast current ITAILN. The ballast current ITAILN is provided to start up the feedback loop, but is provided continuously through the operation of the bandgap reference core 302 shown in FIG. 3. The ballast current ITAILN provides bias to the differential transconductance amplifier 400. In this manner, it is not necessary to determine when to stop providing a start-up current.

[0117] FIG. 5 illustrates a resistive device 500, in accordance with some embodiments.

[0118] The resistive device 500 includes a terminal 502 and a terminal 504. The terminal 502 and the terminal 504 connect externally to other components in a circuit. The resistive device 500 includes nine resistive devices 506 connected in series between the terminal 502 and the terminal 504. One or more of the series connected resistive devices R4A, R4B, R4C, R4D, R5A, R5B, R5C or the resistive devices R6’, R2’ or the resistive device R1 ’ may be provided in the same manner as the resistive device 500.

[0119] FIG. 6 illustrates a resistive device 600, in accordance with some embodiments.

[0120] The resistive device 600 includes a terminal 602 and a terminal 604. The terminal 602 and the terminal 604 connect externally to other components in a circuit. The resistive device 600 includes 6 resistive devices 606 connected in series between the terminal 602 and the terminal 604. One or more of the series connected resistive devices R4A, R4B, R4C, R4D, R5A, R5B, R5C or the resistive devices R6’, R2’ or the resistive device R1 ’ may be provided in the same manner as the resistive device 600.

[0121] FIG. 7 illustrates a resistive device 700, in accordance with some embodiments.

[0122] The resistive device 700 includes a terminal 702 and a terminal 704. The terminal 702 and the terminal 704 connect externally to other components in a circuit. The resistive device 700 includes 3 resistive devices 706 connected in series between the terminal 702 and the terminal 704. One or more of the seriesconnected resistive devices R4A, R4B, R4C, R4D, R5A, R5B, R5C or the resistive devices R6’, R2’ or the resistive device R1 ’ may be provided in the same manner as the resistive device 700.

[0123] FIG. 8 is a flow diagram 800 illustrating a method of generating a bandgap voltage, in accordance with some embodiments.

[0124] In some embodiments, the flow diagram 800 is performed by the bandgap device 100 in FIG. 1 and the bandgap device 300 in FIG. 3, in accordance with some embodiments. The flow diagram 800 includes blocks 802-812. Flow begins at block 802.

[0125] At block 802, a ballast current is generated that is driven into a bandgap reference core to start up the bandgap reference core and that continues to drive the ballast current into the bandgap reference core throughout the operation of the bandgap reference core. Examples of the ballast current include the ballast current IBA1 in FIG. 1 and the ballast currents IBA1 , IBA3 in FIG. 3. Examples of the bandgap reference core include the bandgap reference core 102 in FIG. 1 and the bandgap reference core 302 in FIG. 3. Flow then proceeds to block 804.

[0126] At block 804, a CTAT current is generated with a first circuit portion of the bandgap reference core, the CTAT current being set by a narrow device in the first circuit portion in response to generating the ballast current. Examples of the CTAT current are the CTAT currents IR1 , IR2 in FIG. 1 and FIG. 3. An example of the first circuit portion is the first circuit portion 104 in FIG. 1 and the first circuit portion 304 in FIG. 3. An example of the narrow device is the narrow device D1 in FIG. 1 and FIG. 3. Flow then proceeds to block 806.

[0127] At block 806, a scaled PTAT current is generated with a second circuit portion of the bandgap reference core, wherein a PTAT current is scaled and set by a wider device in the second circuit portion in response to generating the ballast current. An example of the scaled PTAT current are the PTAT currents ID1 , ID2 in FIG. 1 and FIG. 3. An example of the second circuit portion is the second circuit portion 106 in FIG. 1 and the second circuit portion 306 in FIG. 3.An example of the wider device is the wider device D2 in FIG. 1 and FIG. 3. Flow then proceeds to block 808.

[0128] At block 808, a bandgap current is generated from a sum of the CTAT current and the scaled PTAT current. An example of the bandgap current is the bandgap current IBG in FIG. 1 and FIG. 3. Flow then proceeds to block 810.

[0129] At block 810, the bandgap voltage is generated from the bandgap current. An example of the bandgap voltage is the bandgap reference voltage VBG in FIG. 1 and FIG. 3. Flow then proceeds to block 812.

[0130] At block 812, a servo current is generated that is driven into the bandgap reference core to regulate the PTAT current and the CTAT current. An example of the servo current is the servo current IS shown in FIG. 1 , FIG. 2A, FIG. 2B, FIG. 3, and FIG. 4.

[0131] FIG. 9 illustrates a user element 900, in accordance with some embodiments.

[0132] With reference to FIG. 9, the concepts described above may be implemented in various types of the user element 900, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, and like wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, and near field communications.

[0133] The user element 900 will generally include a control system 902, a baseband processor 904, transmit circuitry 906, receive circuitry 908, antenna switching circuitry 910, multiple antennas 912, and user interface circuitry 914. In a non-limiting example, the control system 902 may be a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). In this regard, the control system 902 may include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 908 receives radio frequency signals via the antennas 912 and through the antenna switching circuitry 910 from one or more base stations. A low noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitizationcircuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using analog-to-digital converter(s) (ADC).

[0134] The baseband processor 904 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor 904 is generally implemented in one or more digital signal processors (DSPs) and application specific integrated circuits (ASICs).

[0135] For transmission, the baseband processor 904 receives digitized data, which may represent voice, data, or control information, from the control system 902, which it encodes for transmission. The encoded data is output to the transmit circuitry 906, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission and deliver the modulated carrier signal to the antennas 912 through the antenna switching circuitry 910. The multiple antennas 912 and the replicated transmit and receive circuitries 906, 908 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0136] The above description outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

[0137] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

ClaimsWhat is claimed is:1 . A bandgap device configured to generate a bandgap reference voltage, comprising: a bandgap reference core configured to generate a bandgap current, wherein the bandgap current is a sum of a scaled Proportional to Absolute Temperature, PTAT, current and a Complementary to Absolute Temperature, CTAT, current, the bandgap reference core comprising: a first circuit portion comprising a narrow device, wherein the narrow device is configured to set the CTAT current; and a second circuit portion comprising a wider device, wherein the wider device is configured to set a PTAT current and scale the PTAT current to generate the scaled PTAT current; a reference voltage generation circuit that is configured to generate the bandgap reference voltage from the bandgap current; and a ballast circuit configured to generate a ballast current that is driven into the bandgap reference core to start up the bandgap reference core and that continues to drive the ballast current into the bandgap reference core throughout an operation of the bandgap reference core.

2. The bandgap device of claim 1 , further comprising an amplifier operably associated with the bandgap reference core, the amplifier being configured to generate a servo current that is driven into the bandgap reference core to regulate the PTAT current and the CTAT current.

3. The bandgap device of claim 2, wherein the amplifier comprises a differential transconductance amplifier having a first terminal coupled to detect a first input voltage into the first circuit portion and a second terminal coupled to detect a second input voltage into the second circuit portion, the differential transconductance amplifier configured to drive the servo current into the firstcircuit portion in order to drive the first input voltage such that the first input voltage and the second input voltage are maintained at a voltage ratio between the first input voltage and the second input voltage.

4. The bandgap device of claim 3, wherein the voltage ratio is equal to 1 .

5. The bandgap device of claim 2, wherein the amplifier comprises a differential transconductance amplifier having a first input terminal coupled to the first circuit portion and a second input terminal coupled to the second circuit portion, the differential transconductance amplifier configured to drive the servo current into the first circuit portion such that a total first circuit portion current driven into the first circuit portion comprises the servo current added to the ballast current; and the differential transconductance amplifier is configured to maintain a total second circuit portion current and the total first circuit portion current at a current ratio of the total second circuit portion current driven over the total first circuit portion current.

6. The bandgap device of claim 5, wherein the current ratio is equal to 1 .

7. The bandgap device of claim 5, further comprising a current mirror configured to mirror the total second circuit portion current into the first circuit portion as a reflected current, wherein: the current mirror has a current ratio of the total second circuit portion current over the reflected current that is greater than one; and the total first circuit portion current comprises a sum of the servo current, the ballast current, and the reflected current.

8. The bandgap device of claim 7, wherein the current ratio of the total second circuit portion current over the reflected current is equal to 2.

9. The bandgap device of claim 7, wherein the current mirror comprises a cross-coupled current mirror, wherein the cross-coupled current mirror comprises: a P-channel metal-oxide semiconductor, PMOS, current mirror having a PMOS input device and a PMOS output device; an N-channel metal-oxide semiconductor, NMOS, current mirror having an NMOS input device and an NMOS output device; and wherein: the NMOS input device is coupled to the PMOS output device; the PMOS input device is coupled to the NMOS output device; the NMOS input device is coupled to the first circuit portion; and the NMOS output device is coupled to the second circuit portion.

10. The bandgap device of claim 2, wherein the ballast current is a first ballast current and wherein the ballast circuit is configured to generate a second ballast current that is input into the amplifier.1 1 . The bandgap device of claim 10, wherein: the amplifier has an input stage and an output stage; the ballast circuit is configured to generate a third ballast current; the second ballast current is input into the input stage of the amplifier; and the third ballast current is input into the output stage of the amplifier.

12. The bandgap device of claim 2, wherein the amplifier comprises a differential transconductance amplifier having a first terminal coupled to detect a first input voltage into the first circuit portion and a second terminal coupled to detect a second input voltage into the second circuit portion, the differential transconductance amplifier configured to drive the servo current into the first circuit portion and the second circuit portion in order to drive the first input voltage such that the first input voltage and the second input voltage aremaintained at a voltage ratio between the first input voltage and the second input voltage.

13. The bandgap device of claim 12, wherein the ballast current is a first ballast current and wherein the ballast circuit is configured to: generate the first ballast current so that the first ballast current is driven into the first circuit portion to start up the first circuit portion and that continues to drive the first ballast current into the first circuit portion throughout the operation of the bandgap reference core; and generate a second ballast current that is driven into the second circuit portion to start up the second circuit portion and that continues to drive the second ballast current into the second circuit portion throughout the operation of the bandgap reference core.

14. The bandgap device of claim 12, wherein the voltage ratio is equal to 1 .

15. The bandgap device of claim 13, wherein the ballast circuit is configured to: generate a third ballast current that is driven into the reference voltage generation circuit and that drives the third ballast current into the reference voltage generation circuit throughout the operation of the bandgap reference core.

16. The bandgap device of claim 1 , wherein: the PTAT current is a first PTAT current; the CTAT current is a first CTAT current; the ballast current is a first ballast current; and the bandgap circuit comprises: a first field effect transistor, FET, and a second FET coupled in a feedback configuration, wherein the first FET is configured to receive a power source voltage and the second FET is configured to generate asecond ballast current, the first ballast current being based on the second ballast current; a third circuit portion connected to the second FET, wherein the third circuit portion generates a second PTAT current; and a fourth circuit portion connected to the first FET, wherein the fourth circuit portion is configured to generate a second CTAT current.

17. The bandgap device of claim 16, wherein the ballast current comprises the second PTAT current and the second CTAT current.

18. The bandgap device of claim 16, further comprising a current mirror that generates the first ballast current in response to the second ballast current.

19. A method of generating a ballast voltage, comprising: generating a ballast current that is driven into a bandgap reference core to start up the bandgap reference core and that continues to drive the ballast current into the bandgap reference core throughout an operation of the bandgap reference core; generating a Complementary to Absolute Temperature, CTAT, current with a first circuit portion of the bandgap reference core, the CTAT current being set by a narrow device in the first circuit portion in response to generating the ballast current; generating a scaled Proportional to Absolute Temperature, PTAT, current with a second circuit portion of the bandgap reference core, wherein a PTAT current is scaled and set by a wider device in the second circuit portion in response to generating the ballast current; generating a bandgap current from a sum of the CTAT current and the scaled PTAT current; and generating a bandgap voltage from the bandgap current.

20. The method of claim 19, further comprising generating a servo current that is driven into the bandgap reference core to regulate the PTAT current and the CTAT current.

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