Semiconductor device, display device, and method for manufacturing semiconductor device

Abstract

Provided is a highly reliable semiconductor device. The present invention has first to fourth switches. The first switch has first and second transistors, the second switch has third and fourth transistors, the third switch has fifth and sixth transistors, and the fourth switch has seventh and eighth transistors. Either one of the sources or the drains of the first to fourth transistors are connected to each other, the gates of the first and second transistors are connected to each other, and the gates of the third and fourth transistors are connected to each other. Either one of the sources or the drains of the fifth to eighth transistors are connected to each other, the gates of the fifth and sixth transistors are connected to each other, and the gates of the seventh and eighth transistors are connected to each other. The other of the sources or the drains of the second and fifth transistors are connected to each other.

Description

Semiconductor device, display device, and method for manufacturing the semiconductor device

[0001] 1. Field of the Invention One embodiment of the present invention relates to a transistor, a semiconductor device, a display device, a display module, and an electronic device. 1. Field of the Invention One embodiment of the present invention relates to a method for manufacturing a transistor, a method for manufacturing a semiconductor device, and a method for manufacturing a display device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), an electronic device including any of these devices, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices and each may have a semiconductor device.

[0004] In recent years, display devices have been used in a variety of applications. Examples of applications of large display devices include home television devices, digital signage, and public information displays (PIDs). Display devices are also widely used in smartphones and tablet devices equipped with touch panels.

[0005] As a display device, a light-emitting device having a light-emitting device (also referred to as a light-emitting element) has been developed. A light-emitting device (also referred to as an EL device or an EL element) utilizing the electroluminescence (hereinafter referred to as EL) phenomenon has characteristics such as being easily thin and lightweight, being capable of responding quickly to an input signal, and being capable of being driven using a DC constant voltage power supply. For example, Patent Document 1 discloses an example of a display device using an organic EL element.

[0006] Furthermore, in order to reduce the production cost and mounting area of ​​the driver IC provided in the display device, Patent Document 2 discloses a technology in which part of the circuit constituting the source driver is formed on a glass substrate, similar to the pixel circuit.

[0007] JP 2002-324673 A JP 2019-20687 A

[0008] A display device is provided with a drive circuit (gate driver) that selects pixels and a drive circuit (source driver) that supplies data to the selected pixels. A display device with a touch panel function is also provided with a drive circuit that drives a touch sensor.

[0009] Some or all of these driver circuits use IC chips. While these IC chips can be mounted on the frame of a substrate on which pixel circuits are formed, mounting a large number of IC chips increases the manufacturing cost of the display device. This also hinders efforts to narrow the frame. To address these issues, it is desirable to form some or all of the driver circuits monolithically on the same substrate as the pixel circuits.

[0010] To form a driver circuit, it is necessary to use a transistor suitable for high-speed operation. In general, it is preferable to use a transistor with a large on-state current in order to improve charge / discharge characteristics.

[0011] One way to increase the on-state current of a transistor is to shorten its channel length. However, shortening the channel length of a transistor is known to make it more susceptible to several adverse effects collectively known as short-channel effects. For example, when a transistor is turned on, electrons (also known as hot carriers or hot electrons) accelerated by a strong electric field between the source and drain are injected into the gate insulating film near the drain, damaging the injection site and causing problems such as a plateau in the on-state current (i.e., the drain current is less likely to increase in response to an increase in gate voltage) (so-called hot carrier degradation).

[0012] Therefore, it is desirable to devise a method for suppressing hot carrier degradation in transistors used in drive circuits.

[0013] Therefore, an object of one embodiment of the present invention is to provide a highly reliable semiconductor device and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device capable of suppressing hot carrier degradation and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device including a micro-sized transistor and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a small-sized semiconductor device and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a display device with a narrow frame. Another object of one embodiment of the present invention is to provide a highly reliable display device. Another object of one embodiment of the present invention is to provide an electronic device including the display device. Another object of one embodiment of the present invention is to provide a novel semiconductor device, display device, or electronic device.

[0014] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0015] One embodiment of the present invention is a semiconductor device including a first switch and a second switch, the first switch including a first transistor and a second transistor, the second switch including a third transistor and a fourth transistor, in which one of a source or a drain of the first transistor is electrically connected to one of a source or a drain of the second transistor, one of a source or a drain of the third transistor, and one of a source or a drain of the fourth transistor, a gate of the first transistor is electrically connected to a gate of the second transistor, and a gate of the third transistor is electrically connected to a gate of the fourth transistor.

[0016] In the above, it is preferable that the transistor includes a third switch and a fourth switch, the third switch includes a fifth transistor and a sixth transistor, the fourth switch includes a seventh transistor and an eighth transistor, one of a source or a drain of the fifth transistor, one of a source or a drain of the sixth transistor, one of a source or a drain of the seventh transistor, and one of a source or a drain of the eighth transistor are electrically connected, the gate of the fifth transistor and the gate of the sixth transistor are electrically connected, the gate of the seventh transistor and the gate of the eighth transistor are electrically connected, and the other of the source or the drain of the second transistor and the other of the source or the drain of the fifth transistor are electrically connected.

[0017] In the above, it is preferable that the other of the source or drain of the first transistor, the other of the source or drain of the third transistor, and the other of the source or drain of the seventh transistor are electrically connected to a first power supply line, the other of the source or drain of the fourth transistor, the other of the source or drain of the sixth transistor, and the other of the source or drain of the eighth transistor are electrically connected to a second power supply line, and the potential supplied to the first power supply line is higher than the potential supplied to the second power supply line.

[0018] In the above, each of the first to eighth transistors preferably includes a metal oxide in a semiconductor layer and has a channel formation region along a side surface of an opening in an insulating layer.

[0019] Another embodiment of the present invention is a display device including a gate driver, and the gate driver includes the above semiconductor device.

[0020] Another embodiment of the present invention includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a first semiconductor layer, a second semiconductor layer, a first insulating layer, a second insulating layer, and a third insulating layer, the first conductive layer and the second conductive layer being provided in different regions on the same layer, the first insulating layer, the third conductive layer, the second insulating layer, and the fourth conductive layer being superimposed in this order over the first conductive layer and the second conductive layer, and the first insulating layer, the third conductive layer, the second insulating layer, and the fourth conductive layer have a first opening reaching the first conductive layer and a second opening reaching the second conductive layer. and a second opening, wherein in the first opening, the first semiconductor layer is in contact with an upper surface of the first conductive layer, a side surface of the first insulating layer, a side surface of the third conductive layer, a side surface of the second insulating layer, and a side surface of the fourth conductive layer; in the second opening, the second semiconductor layer is in contact with an upper surface of the second conductive layer, a side surface of the first insulating layer, a side surface of the third conductive layer, a side surface of the second insulating layer, and a side surface of the fourth conductive layer; the third insulating layer is in contact with upper surfaces of the first semiconductor layer and the second semiconductor layer; the fifth conductive layer overlaps the first opening and is in contact with an upper surface of the third insulating layer; and the sixth conductive layer overlaps the second opening and is in contact with an upper surface of the third insulating layer.

[0021] Another embodiment of the present invention includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a first semiconductor layer, a second semiconductor layer, a first insulating layer, a second insulating layer, and a third insulating layer, in which the first insulating layer, the second conductive layer, and the second insulating layer are provided over the first conductive layer in this order, and the third conductive layer and the fourth conductive layer are provided in different regions over the second insulating layer, and the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer have first openings reaching the first conductive layer, and the first insulating layer, the second conductive layer, the second insulating layer, and the fourth conductive layer are provided over different regions over the second insulating layer. and a second opening reaching the first conductive layer, wherein within the first opening, the first semiconductor layer is in contact with an upper surface of the first conductive layer, a side surface of the first insulating layer, a side surface of the second conductive layer, a side surface of the second insulating layer, and a side surface of the third conductive layer, wherein within the second opening, the second semiconductor layer is in contact with an upper surface of the first conductive layer, a side surface of the first insulating layer, a side surface of the second conductive layer, a side surface of the second insulating layer, and a side surface of the fourth conductive layer, wherein the third insulating layer is in contact with upper surfaces of the first semiconductor layer and the second semiconductor layer, wherein the fifth conductive layer overlaps the first opening and is in contact with an upper surface of the third insulating layer, and wherein the sixth conductive layer overlaps the second opening and is in contact with an upper surface of the third insulating layer.

[0022] In the above, it is preferable that the first semiconductor layer and the second semiconductor layer each contain a metal oxide, and at least one of the first insulating layer and the second insulating layer contains silicon oxide or silicon oxynitride.

[0023] In the above, it is preferable that the metal oxide contains one or more elements selected from indium, an element M, and zinc, and that the element M contains one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium.

[0024] Furthermore, in the above, it is preferable that the first insulating layer has a fourth insulating layer, a fifth insulating layer on the fourth insulating layer, and a sixth insulating layer on the fifth insulating layer, the second insulating layer has a seventh insulating layer, an eighth insulating layer on the seventh insulating layer, and a ninth insulating layer on the eighth insulating layer, and that the fourth insulating layer, the sixth insulating layer, the seventh insulating layer, and the ninth insulating layer each have silicon nitride, silicon nitride oxide, hafnium oxide, or aluminum oxide, and that the fifth insulating layer and the eighth insulating layer each have silicon oxide or silicon oxynitride.

[0025] Another embodiment of the present invention includes forming a first conductive layer and a second conductive layer, forming a first insulating film, a third conductive layer, a second insulating film, and a fourth conductive layer in this order on the first conductive layer and the second conductive layer, removing a portion of each of the first insulating film, the third conductive layer, the second insulating film, and the fourth conductive layer to form a first opening reaching the first conductive layer and a second opening reaching the second conductive layer, and forming a first insulating layer, a fifth conductive layer, a second insulating layer, and a sixth conductive layer from the first insulating film, the third conductive layer, the second insulating film, and the fourth conductive layer, respectively, and forming a first insulating layer, a fifth conductive layer, a second insulating layer, and a sixth conductive layer in the first opening. a first semiconductor layer in contact with a top surface, a side surface of the first insulating layer, a side surface of the fifth conductive layer, a side surface of the second insulating layer, and a side surface of the sixth conductive layer; a second semiconductor layer in contact with a top surface of the second conductive layer, the side surface of the first insulating layer, the side surface of the fifth conductive layer, the side surface of the second insulating layer, and a side surface of the sixth conductive layer in a second opening; a third insulating layer in contact with a top surface of the first semiconductor layer and a top surface of the second semiconductor layer; a seventh conductive layer on the third insulating layer overlapping with the first opening; and an eighth conductive layer on the third insulating layer overlapping with the second opening.

[0026] According to one embodiment of the present invention, a highly reliable semiconductor device and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a semiconductor device capable of suppressing hot carrier degradation and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a semiconductor device including a micro-sized transistor and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a small-sized semiconductor device and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a display device with a narrow frame can be provided. According to one embodiment of the present invention, a highly reliable display device can be provided. According to one embodiment of the present invention, an electronic device including the display device can be provided. According to one embodiment of the present invention, a novel semiconductor device, display device, or electronic device can be provided.

[0027] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0028] FIG. 1 is a circuit diagram showing an example of a semiconductor device. FIGS. 2A to 2D are circuit diagrams illustrating an example of operation of a conventional semiconductor device. FIGS. 3A and 3B are circuit diagrams illustrating an example of operation of the semiconductor device. FIGS. 4A and 4B are circuit diagrams illustrating an example of operation of the semiconductor device. FIGS. 5A and 5B are circuit diagrams illustrating an example of operation of the semiconductor device. FIG. 6 is a circuit diagram illustrating an example of operation of the semiconductor device. FIG. 7 is a circuit diagram illustrating an example of operation of the semiconductor device. FIG. 8 is a circuit diagram illustrating an example of operation of the semiconductor device. FIG. 9 is a circuit diagram illustrating an example of operation of the semiconductor device. FIG. 10 is a circuit diagram illustrating an example of operation of the semiconductor device. FIG. 11 is a circuit diagram illustrating an example of operation of the semiconductor device. FIG. 12 is a circuit diagram showing an example of the configuration of a shift register circuit. FIG. 13A is a block diagram showing an example of the configuration of a sequential circuit. FIGS. 13B and 13C are timing charts illustrating an example of operation of the shift register circuit. FIG. 14A is a plan view showing an example of a semiconductor device. FIG. 14B is a cross-sectional view showing an example of a semiconductor device. FIG. 15A is a cross-sectional view showing an example of a semiconductor device. FIG. 15B is a circuit diagram illustrating a semiconductor device. FIG. 16A is a plan view showing an example of a semiconductor device. FIG. 16B is a cross-sectional view showing an example of a semiconductor device. FIG. 17 is a cross-sectional view showing an example of a semiconductor device. FIG. 18 is a cross-sectional view showing an example of a semiconductor device. FIG. 19 is a circuit diagram illustrating a semiconductor device. FIGS. 20A and 20B are cross-sectional views showing an example of a semiconductor device. FIG. 21A is a plan view showing an example of a method for manufacturing a semiconductor device. FIG. 21B is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. FIG. 22A is a plan view showing an example of a method for manufacturing a semiconductor device. FIG. 22B is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. FIG. 23A is a plan view showing an example of a method for manufacturing a semiconductor device. FIG. 23B is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. FIG. 24A is a plan view showing an example of a method for manufacturing a semiconductor device. FIG. 24B is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. FIG. 25A is a plan view showing an example of a method for manufacturing a semiconductor device. FIG. 25B is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.FIG. 26A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIG. 26B is a cross-sectional view illustrating an example of a manufacturing method of a semiconductor device. FIG. 27A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIG. 27B is a cross-sectional view illustrating an example of a manufacturing method of a semiconductor device. FIG. 28A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIG. 28B is a cross-sectional view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 29A to 29D are diagrams illustrating examples of electronic devices. FIGS. 30A to 30F are diagrams illustrating examples of electronic devices. FIGS. 31A to 31F are diagrams illustrating examples of electronic devices.

[0029] The following description of the preferred embodiments will be given in detail with reference to the accompanying drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various modifications can be made to the modes and details of the present invention without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the preferred embodiments shown below.

[0030] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0031] For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0032] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0033] A transistor is a type of semiconductor element that can realize functions such as amplifying current or voltage, and performing a switching operation to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0034] The functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current changes during circuit operation. For this reason, the terms "source" and "drain" may be used interchangeably in this specification. Note that the names of the source and drain of a transistor may be appropriately changed to the source terminal and drain terminal, or the source electrode and drain electrode, etc., depending on the situation.

[0035] The terms "gate" and "back gate" can be interchanged. Therefore, in this specification and the like, the terms "gate" and "back gate" can be used interchangeably. Note that the names of the gate and back gate of a transistor can be appropriately changed to gate electrode and back gate electrode, etc., depending on the situation.

[0036] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as a physical entity. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

[0037] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an exchange of an electric signal or an interaction of electric potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no exchange of an electric signal or an interaction of electric potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an exchange of an electric signal or an interaction of electric potential occurs between A and B.

[0038] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0039] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0040] Furthermore, even if a circuit diagram shows a single element, that element may be configured as multiple elements as long as there is no functional problem. For example, multiple transistors operating as switches may be connected in series or parallel. Also, a capacitor may be divided and placed in multiple locations.

[0041] Furthermore, one conductor may have multiple functions such as wiring, electrode, and terminal, and in this specification, multiple names may be used for the same element. Also, even when elements are shown as being directly connected to each other on a circuit diagram, in reality, the elements may be connected via one or more conductors, and in this specification, such a configuration is also included in the category of direct connection.

[0042] In this specification and the like, "series connection of transistors" means that the drain of one of two adjacent transistors is connected to the source of the other. Although the conductivity type of the transistors used in the semiconductor device of one embodiment of the present invention is assumed to be n-type, this is not limiting, and p-type transistors can also be used by switching the voltage level of the power supply.

[0043] In this specification, the phrase "top surface shapes generally match" means that at least a portion of the contours of stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes generally match" may also be used.

[0044] In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. Furthermore, a plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0045] Furthermore, in this specification and the like, "approximately the same height" refers to a configuration in which the heights from a reference surface (for example, a flat surface such as a substrate surface) are approximately the same in a cross-sectional view. For example, when a planarization process (typically, a chemical mechanical polishing (CMP) process) is performed, the heights of the processed surfaces are approximately the same. However, even when a planarization process is performed, the heights may not strictly match depending on the film material, etc., but in this specification and the like, this case is also considered to be "approximately the same height."

[0046] Embodiment 1 One embodiment of the present invention is a semiconductor device having a function of suppressing hot carrier degradation of a transistor. The semiconductor device can be used as an element of a driver circuit of a display device, for example.

[0047] A semiconductor device according to one embodiment of the present invention includes first to fourth switches. Each of the first to fourth switches includes a plurality of transistors. The plurality of transistors included in each switch are connected in series. That is, the plurality of transistors included in each switch have a configuration in which, of two adjacent transistors, the drain of one transistor is connected to the source of the other transistor. Furthermore, the gates of the plurality of transistors included in each switch are connected to each other.

[0048] In a semiconductor device according to one embodiment of the present invention, the first switch and the second switch are connected to each other. Specifically, the source of the last transistor in the series-connected transistors included in the first switch is connected to the drain of the first transistor in the series-connected transistors included in the second switch.

[0049] In this specification and the like, of the series-connected transistors, the transistor closest to the high-potential power supply line is referred to as the "front-stage transistor," and the transistor closest to the low-potential power supply line is referred to as the "last-stage transistor." Furthermore, hereinafter, of the source and drain of each series-connected transistor, the terminal that is on the high-potential side when conductive is referred to as the drain, and the terminal that is on the low-potential side when conductive is referred to as the source. Of the series-connected transistors, the drain of the front-stage transistor is connected to the high-potential power supply line, and the source of the last-stage transistor is connected to the low-potential power supply line.

[0050] The third switch is provided in parallel with the first switch. The fourth switch is provided in parallel with the second switch. Here, the number of series-connected transistors in the first switch is equal to the number of series-connected transistors in the third switch. The number of series-connected transistors in the second switch is equal to the number of series-connected transistors in the fourth switch.

[0051] The first switch and the third switch are connected to each other. The second switch and the fourth switch are connected to each other. Specifically, a node (also called a junction) between the series-connected transistors of the first switch and a node between the series-connected transistors of the corresponding third switch are connected to each other. Similarly, a node between the series-connected transistors of the second switch and a node between the series-connected transistors of the corresponding fourth switch are connected to each other.

[0052] This allows a potential of the same magnitude as the potential applied to a node of the third switch connected to the first switch to be supplied to the node. For example, by turning on the third switch and passing a through current through the series-connected transistors of the switch, a potential of a magnitude corresponding to the resistance value of each transistor is supplied to the node between the transistors. Therefore, a potential of the same magnitude can be supplied to the node of the first switch connected to the node of the third switch.

[0053] For example, the step of turning on the third switch is the first step, the step of turning off the third switch is the second step, and the step of turning on the first switch is the third step. In this case, by performing the first step to the third step in this order, the first switch can be operated in a state where a constant potential is always supplied to each node of the first switch. That is, the source-drain voltage (V ｄｓ ) is fixed to a constant value, the switch can be operated. ｄｓ This can prevent the occurrence of a transistor in which the resistance is extremely large and the transistor from being deteriorated by hot carriers.

[0054] In addition, the above description of the first switch and the third switch can be applied to the second switch and the fourth switch by replacing the first switch with the second switch and the third switch with the fourth switch, respectively.

[0055] In the semiconductor device of one embodiment of the present invention, the third switch is provided to suppress deterioration of the first switch, and the fourth switch is provided to suppress deterioration of the second switch. By including the third switch and the fourth switch, a highly reliable semiconductor device can be realized.

[0056] Furthermore, it is preferable to use vertical transistors as the transistors that constitute each switch. Vertical transistors have a channel formation region along the side of an opening in an insulator, and are configured to easily shorten the channel length and increase the channel width, making it easy to increase the on-state current. Therefore, vertical transistors are suitable for circuits that operate at high speed. Furthermore, vertical transistors can reduce the area they occupy, so by applying them to the driver circuit of a display device, they have the advantage of making it easier to narrow the frame of the display device.

[0057] Furthermore, since each switch has a structure including a plurality of transistors connected in series, it is preferable that the transistors be arranged in a stacked configuration. This allows the area occupied by the transistors in the substrate plane to be significantly reduced compared to when the transistors are arranged on the same plane. In this case, by using vertical transistors as described above, the area occupied by the transistors in the substrate plane can be further reduced compared to when, for example, planar transistors are used. As described above, in the semiconductor device of one embodiment of the present invention, reliability is improved by providing a third switch and a fourth switch in addition to the first switch and the second switch. Furthermore, by configuring each switch as a stack of a plurality of vertical transistors, a significant increase in the area occupied by the semiconductor device in the substrate plane can be suppressed.

[0058] Furthermore, for example, when two vertical transistors are stacked, a configuration equivalent to the stacked configuration can be achieved by sharing some of the components of each transistor, rather than simply stacking the two. For example, one of the source electrode or drain electrode (the electrode located on the upper side as viewed from the substrate surface) of a first vertical transistor can be shared with one of the source electrode or drain electrode (the electrode located on the lower side as viewed from the substrate surface) of a second vertical transistor located on the first vertical transistor. Furthermore, the semiconductor layer, gate insulating layer, and gate electrode can also be shared between the two vertical transistors. This reduces the number of steps required for fabricating a semiconductor device.

[0059] Hereinafter, details of a semiconductor device according to one embodiment of the present invention will be described with reference to the drawings.

[0060] 1 is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention. A configuration of the semiconductor device will be described with reference to FIG. 1. The semiconductor device includes a switch SW1, a switch SW2, a switch DSW1, and a switch DSW2. The switch SW1 and the switch SW2 are connected to each other. The switch SW1 and the switch DSW1 are connected to each other. The switch SW2 and the switch DSW2 are connected to each other.

[0061] The switch SW1 includes a transistor M1 and a transistor M2. The transistors M1 and M2 are connected in series. Specifically, the source of the transistor M1 and the drain of the transistor M2 are connected to each other. In FIG. 1, the junction of the source of the transistor M1 and the drain of the transistor M2 is shown as a node N1. The gate of the transistor M1 and the gate of the transistor M2 are also connected to each other.

[0062] The switch SW2 includes a transistor M3 and a transistor M4. The transistors M3 and M4 are connected in series. Specifically, the source of the transistor M3 and the drain of the transistor M4 are connected to each other. In FIG. 1, the junction of the source of the transistor M3 and the drain of the transistor M4 is shown as a node N2. The gate of the transistor M3 and the gate of the transistor M4 are also connected to each other.

[0063] The switches SW1 and SW2 are connected to each other. Specifically, the source of the transistor M2 in the switch SW1 is connected to the drain of the transistor M3 in the switch SW2. In FIG. 1, the node where the switches SW1 and SW2 are connected is shown as a node ND.

[0064] The drain of the transistor M1 in the switch SW1 is connected to a high-potential power supply line and is supplied with a high potential (VDD), while the source of the transistor M4 in the switch SW2 is connected to a low-potential power supply line and is supplied with a low potential (VSS).

[0065] The switch DSW1 includes a transistor DM1 and a transistor DM2. The transistors DM1 and DM2 are connected in series. Specifically, the source of the transistor DM1 and the drain of the transistor DM2 are connected to each other. In FIG. 1, the junction of the source of the transistor DM1 and the drain of the transistor DM2 is shown as a node DN1. The gates of the transistors DM1 and DM2 are also connected to each other.

[0066] The drain of the transistor DM1 included in the switch DSW1 is connected to a high-potential power supply line and is supplied with a high potential (VDD), while the source of the transistor DM2 included in the switch DSW1 is connected to a low-potential power supply line and is supplied with a low potential (VSS).

[0067] The switch SW1 and the switch DSW1 are connected to each other. Specifically, the node N1 of the switch SW1 is connected to the node DN1 of the switch DSW1.

[0068] The switch DSW2 includes a transistor DM3 and a transistor DM4. The transistors DM3 and DM4 are connected in series. Specifically, the source of the transistor DM3 and the drain of the transistor DM4 are connected to each other. In FIG. 1, the node between the source of the transistor DM3 and the drain of the transistor DM4 is shown as a node DN2. The gates of the transistors DM3 and DM4 are also connected to each other.

[0069] The drain of the transistor DM3 included in the switch DSW2 is connected to a high-potential power supply line and is supplied with a high potential (VDD).The source of the transistor DM4 included in the switch DSW2 is connected to a low-potential power supply line and is supplied with a low potential (VSS).

[0070] The switch SW2 and the switch DSW2 are connected to each other. Specifically, the node N2 of the switch SW2 is connected to the node DN2 of the switch DSW2.

[0071] Although FIG. 1 illustrates a configuration in which each switch includes two transistors, this is not limiting. In a semiconductor device according to one embodiment of the present invention, each switch can also include three or more transistors. By configuring each switch to include a plurality of transistors connected in series, leakage current of each switch can be reduced compared to a configuration in which each switch includes only one transistor. Furthermore, the withstand voltage of each switch (voltage resistance, specifically, the withstand voltage between the drain of the first transistor and the source of the last transistor in each switch) can be increased.

[0072] Furthermore, the number of series-connected transistors in switch SW1 and the number of series-connected transistors in switch SW2 do not necessarily have to be the same, and can be different numbers. On the other hand, it is preferable that the number of series-connected transistors in switch SW1 and the number of series-connected transistors in switch DSW1 are the same. This allows all nodes between the transistors in switch SW1 to be connected to the corresponding nodes between the transistors in switch DSW1. For the same reason, it is also preferable that the number of series-connected transistors in switch SW2 and the number of series-connected transistors in switch DSW2 are the same.

[0073] As described above, the switch SW1 is connected to a high-potential power line and can supply a high potential (VDD) to the node ND by being turned on. The switch SW2 is connected to a low-potential power line and can supply a low potential (VSS) to the node ND by being turned on. The semiconductor device of one embodiment of the present invention alternately turns on the switch SW1 and turns off the switch SW2, and turns off the switch SW1 and turns on the switch SW2, depending on the operation of the applied circuit. That is, the potential of the node ND can be either VDD or VSS in a steady state.

[0074] The semiconductor device of one embodiment of the present invention includes a switch DSW1 connected to the switch SW1 and a switch DSW2 connected to the switch SW2, and thereby can suppress hot carrier degradation of the transistors included in the switches SW1 and SW2 during operation of the semiconductor device. Prior to describing an operation example of the semiconductor device of one embodiment of the present invention, an operation example of a semiconductor device that does not include the switches DSW1 and DSW2 (hereinafter, this semiconductor device will be referred to as a "conventional semiconductor device") will be described below.

[0075] 2A to 2D are diagrams illustrating an operation example of a conventional semiconductor device, which has a configuration in which the switches DSW1 and DSW2 are omitted from the semiconductor device of one embodiment of the present invention shown in FIG.

[0076] FIG. 2A shows a potential (V Ｈ ) is supplied to the gates of the transistors M3 and M4, and a potential (V Ｌ ) is supplied to the semiconductor device. That is, the switch SW1 is in a conducting state and the switch SW2 is in a non-conducting state. In the following, an example of the operation of the conventional semiconductor device will be described, with a steady state in which the switch SW1 is in a conducting state and the switch SW2 is in a non-conducting state being defined as a first state, and a steady state in which the switch SW1 is in a non-conducting state and the switch SW2 is in a conducting state being defined as a second state.

[0077] As described above, in the first state, switch SW1 is conductive and switch SW2 is non-conductive, so the potential of node ND is VDD. At this time, in switch SW1, the potential of node N1 between transistors M1 and M2 is also VDD. At this time, in switch SW2, the potential of node N2 between transistors M3 and M4 is VSS.

[0078] For example, when the state immediately before the first state is the second state and both the transistors M3 and M4 are on, the potentials of the nodes ND and N2 are VSS. Therefore, when switching from the second state to the first state (i.e., both the transistors M3 and M4 are off), VSS is held at the node N2.

[0079] Next, the transition period when the first state is switched to the second state will be described with reference to Fig. 2B. Fig. 2B shows the state immediately after the state is switched from the first state to the second state, i.e., immediately after the switch SW2 becomes conductive.

[0080] First, the switch SW1 is turned off, and then the switch SW2 is turned on. At this time, a high potential (V Ｈ ) is supplied, the potential of the node ND is VDD and the potential of the node N2 is VSS. Therefore, the source-drain voltage (V ｄｓ ) becomes VDD-VSS (V of transistor M4 ｄｓ VDD-VSS is the maximum potential difference that can occur in the circuit. Therefore, the transistor M3 is connected to V ｄｓ Current starts to flow when the temperature is high, making it easier for hot carriers to be generated.

[0081] A current flows through the switch SW2 until the potential of the node ND drops to VSS, and then the switch SW2 enters a steady state, which is the second state shown in FIG.

[0082] Next, the transition period when the state switches from the second state to the first state will be described with reference to Fig. 2D. Fig. 2D shows the state immediately after the state switches from the second state to the first state, i.e., immediately after the switch SW1 becomes conductive.

[0083] First, the switch SW2 is turned off, and then the switch SW1 is turned on. Here, a high potential (V Ｈ ) is supplied, the potential of the node ND is VSS and the potential of the node N1 is VDD. Therefore, the source-drain voltage (V ｄｓ ) becomes VDD-VSS (V of transistor M1 ｄｓ is 0 (VDD-VDD). Therefore, the moment the switch SW1 is turned on, V ｄｓ Current starts to flow when the temperature is high, making it easier for hot carriers to be generated.

[0084] A current flows through the switch SW1 until the potential of the node ND rises to VDD, and then the switch SW1 enters a steady state, which is the first state shown in FIG.

[0085] As described above, the semiconductor device according to one embodiment of the present invention operates by alternately turning on and off the switches SW1 and SW2. Therefore, if the semiconductor device is configured only with the switches SW1 and SW2 (i.e., if it has the configuration of a conventional semiconductor device), hot carriers generated in the transistors M2 and M3 are repeatedly injected into the gate insulating films during operation of the semiconductor device, which may cause hot carrier degradation, such as a plateau in the on-state current.

[0086] 3A to 5B are diagrams illustrating an example of the operation of the semiconductor device according to one embodiment of the present invention shown in FIG. 1 . Similar to the operation example of the conventional semiconductor device described above ( FIGS. 2A to 2D ), the semiconductor device according to one embodiment of the present invention alternately turns on and off the switches SW1 and SW2. However, the semiconductor device according to one embodiment of the present invention differs from the conventional semiconductor device in that it includes switches DSW1 and DSW2 in addition to switches SW1 and SW2. Therefore, the semiconductor device according to one embodiment of the present invention includes a step of operating the switches DSW1 and DSW2 in addition to the operation of the conventional semiconductor device described above. By performing this step during operation, the semiconductor device according to one embodiment of the present invention can reduce concerns about hot carrier degradation of the transistors M2 and M3 described above. Below, details of the operation example of the semiconductor device according to one embodiment of the present invention are described.

[0087] FIG. 3A shows a state in which a high potential (V Ｈ ) is supplied to the gates of the transistors M1 and M2, the gates of the transistors M3 and M4, and the gates of the transistors DM3 and DM4, and a low potential (V Ｌ ) is supplied. That is, the switch DSW1 is in a conducting state, and the switches SW1, SW2, and DSW2 are in a non-conducting state.

[0088] In the following, a steady state in which switch DSW1 is conductive and switches SW1, SW2, and DSW2 are non-conductive will be described as a third state. A steady state in which switch SW1 is conductive and switches SW2, DSW1, and DSW2 are non-conductive will be described as a fourth state. A steady state in which switch DSW2 is conductive and switches SW1, SW2, and DSW1 are non-conductive will be described as a fifth state. A steady state in which switch SW2 is conductive and switches SW1, SW2, and DSW1 are non-conductive will be described as a sixth state.

[0089] As described above, in the third state, the switch DSW1 is in a conductive state, and the switches SW1, SW2, and DSW2 are in a non-conductive state, so that the potential of the node DN1 between the transistors DM1 and DM2 in the switch DSW1 is between VDD and VSS (higher than VSS and lower than VDD). Ｍ It is shown as V Ｍ is a potential determined by the magnitude of the resistance of each of the transistors DM1 and DM2 when they are in an on-state. For example, when the magnitude of the resistance of each of the transistors DM1 and DM2 when they are in an on-state is equal, the potential V Ｍ In addition, if the resistance of the transistor DM1 during ON operation is larger than the resistance of the transistor DM2 during ON operation, V Ｍ On the other hand, if the resistance of the transistor DM2 during ON operation is larger than the resistance of the transistor DM1 during ON operation, V Ｍ becomes a potential higher than (VDD+VSS) / 2 (a potential closer to VDD than VSS).

[0090] In the following, the term "potential is divided between VDD and VSS" may be used to mean that the potential of the node between each transistor is automatically determined by the magnitude of the resistance of each series-connected transistor of each switch when it is turned on.

[0091] In addition, the potential of the node DN1 of the switch DSW1 is V Ｍ As a result, the potential of the node N1 of the switch SW1 connected thereto also becomes V Ｍ This becomes:

[0092] At this time (third state), the potential of the node ND, the potential of the node N2 between the transistors M3 and M4 in the switch SW2, and the potential of the node DN2 between the transistors DM3 and DM4 in the switch DSW2 are all VSS.

[0093] For example, when the state immediately before the third state is the sixth state and both the transistors M3 and M4 are on, the potentials of the nodes ND, N2, and DN2 are all VSS. Therefore, when switching from the sixth state to the third state (i.e., both the transistors M3 and M4 are off), the potentials of the nodes ND, N2, and DN2 are held at VSS.

[0094] Next, the transition period when the state switches from the third state to the fourth state will be described with reference to Fig. 3B. Fig. 3B shows the state immediately after the state switches from the third state to the fourth state, i.e., immediately after the switch SW1 becomes conductive.

[0095] First, the switch DSW1 is turned off, and then the switch SW1 is turned on. Ｈ ) is supplied, the potential of the node ND is VSS, and the potential of the node N1 is V Ｍ Therefore, the source-drain voltage of the transistor M2 (V ｄｓ ) is V Ｍ Therefore, the transistor M2 is connected to V ｄｓ Therefore, hot carriers are less likely to be generated in the transistor M2 than when the conventional semiconductor device described above is operating (FIG. 2D).

[0096] At this time, the source-drain voltage (V ｄｓ ) is VDD-V Ｍ Therefore, as with the transistor M2, the moment the switch SW1 becomes conductive, V ｄｓ Therefore, the generation of hot carriers can be suppressed in the transistor M1 as well.

[0097] A current flows through the switch SW1 until the potential of the node ND rises to VDD, and then the switch SW1 enters a steady state. At this time, the potentials of the nodes N1 and DN1 also become VDD. This state is the fourth state shown in FIG. 4A.

[0098] Next, the transition period when the state switches from the fourth state to the fifth state will be described with reference to Fig. 4B. Fig. 4B shows the state immediately after switching from the fourth state to the fifth state, i.e., immediately after the switch DSW2 becomes conductive.

[0099] As described above, in the fifth state, the switch DSW2 is in a conductive state, and the switches SW1, SW2, and DSW1 are in a non-conductive state. Therefore, in the switch DSW2, the potential of the node DN2 between the transistors DM3 and DM4 is V Ｍ This becomes:

[0100] In addition, the potential of the node DN2 of the switch DSW2 is V Ｍ As a result, the potential of the node N2 of the switch SW2 connected thereto also becomes V Ｍ This becomes:

[0101] Next, the transition period when the state switches from the fifth state to the sixth state will be described with reference to Fig. 5A. Fig. 5A shows the state immediately after switching from the fifth state to the sixth state, i.e., immediately after the switch SW2 becomes conductive.

[0102] First, the switch DSW2 is turned off, and then the switch SW2 is turned on. Ｈ ) is supplied, the potential of the node ND is VDD, and the potential of the node N2 is V Ｍ Therefore, the source-drain voltage of the transistor M3 (V ｄｓ ) is VDD-V Ｍ Therefore, the moment the switch SW2 is turned on, the transistor M3 receives V ｄｓTherefore, hot carriers are less likely to be generated in the transistor M3 than when the conventional semiconductor device described above is operating (FIG. 2B).

[0103] At this time, the source-drain voltage (V ｄｓ ) is V Ｍ Therefore, like the transistor M3, the moment the switch SW2 becomes conductive, the transistor M4 also becomes V ｄｓ Therefore, the generation of hot carriers can be suppressed in the transistor M4 as well.

[0104] A current flows through the switch SW2 until the potential of the node ND drops to VSS, and then the switch SW2 enters a steady state. At this time, the potentials of the nodes N2 and DN2 also become VSS. This state is the sixth state shown in FIG. 5B.

[0105] As described above, the semiconductor device according to one embodiment of the present invention has a configuration in which the switches DSW1 and DSW2 are added to a conventional semiconductor device, and thus the source-drain voltages (V ｄｓ ) can be made smaller than VDD-VSS. ｄｓ In other words, the generation of hot carriers can be suppressed, and hot carrier degradation of the transistor can be prevented.

[0106] Next, an example of a semiconductor device in which each switch has three or more series-connected transistors will be described. Figures 6 to 11 are diagrams illustrating an operation example of a semiconductor device in which each switch (switch SW1, switch SW2, switch DSW1, and switch DSW2) has four series-connected transistors.

[0107] The more transistors connected in series in a switch, the higher the channel resistance of the entire transistors, which reduces leakage current. Also, the withstand voltage (specifically, the withstand voltage between the drain of the first-stage transistor and the source of the last-stage transistor in the switch) can be increased. On the other hand, the more transistors connected in series, the smaller the on-current. Therefore, it is preferable to set the number of transistors connected in series according to the circuit to which the switch is applied.

[0108] 1 and 3A to 5B , the configuration example and the operation example of the semiconductor device of one embodiment of the present invention will be mainly described below. For the other aspects, the above description of the semiconductor device can be referred to.

[0109] 6 to 11, the semiconductor device has a switch SW1 that includes transistors M5 and M6 in addition to transistors M1 and M2. The switch SW2 has transistors M7 and M8 in addition to transistors M3 and M4. The switch DSW1 has transistors DM5 and DM6 in addition to transistors DM1 and DM2. The switch DSW2 has transistors DM7 and DM8 in addition to transistors DM3 and DM4.

[0110] In the switch SW1, the drain of the transistor M5 is connected to the source of the transistor M2 at a node N3, and the source of the transistor M5 is connected to the drain of the transistor M6 at a node N4.

[0111] In the switch SW2, the source of the transistor M4 is connected to the drain of the transistor M7 at a node N5. The source of the transistor M7 is connected to the drain of the transistor M8 at a node N6. The source of the transistor M8 is connected to the low-potential power line and is supplied with a low potential (VSS).

[0112] In the switch DSW1, the drain of the transistor DM5 is connected to the source of the transistor DM2 at a node DN3. The source of the transistor DM5 is connected to the drain of the transistor DM6 at a node DN4. The source of the transistor DM6 is connected to the low-potential power line, and a low potential (VSS) is supplied to the source.

[0113] In the switch DSW2, the source of the transistor DM4 is connected to the drain of the transistor DM7 at a node DN5. The source of the transistor DM7 is connected to the drain of the transistor DM8 at a node DN6. The source of the transistor DM8 is connected to the low-potential power supply line, and a low potential (VSS) is supplied to the source.

[0114] An example of the operation of the semiconductor device having the above configuration will be described below with reference to FIGS.

[0115] 6 shows that the gates of the transistors DM1, DM2, DM5, and DM6 are supplied with a high potential (V Ｈ ) is supplied to the gates of the transistors M1, M2, M5, and M6, the gates of the transistors M3, M4, M7, and M8, and the gates of the transistors DM3, DM4, DM7, and DM8, so that the respective transistors are in an off state. Ｌ ) is supplied. That is, the switch DSW1 is in a conducting state, and the switches SW1, SW2, and DSW2 are in a non-conducting state.

[0116] The third to sixth states used below are the same as the third to sixth states described with reference to Figures 3A to 5B. That is, the steady state in which switch DSW1 is conductive and switches SW1, SW2, and DSW2 are non-conductive will be described as the third state. The steady state in which switch SW1 is conductive and switches SW2, DSW1, and DSW2 are non-conductive will be described as the fourth state. The steady state in which switch DSW2 is conductive and switches SW1, SW2, and DSW1 are non-conductive will be described as the fifth state. The steady state in which switch SW2 is conductive and switches SW1, DSW1, and DSW2 are non-conductive will be described as the sixth state.

[0117] As described above, in the third state, the switch DSW1 is in a conductive state, and the switches SW1, SW2, and DSW2 are in a non-conductive state, so that the switch DSW1 divides the potential between VDD and VSS. Then, potentials corresponding to the magnitude of the resistance of the transistors DM1, DM2, DM5, and DM6 when they are in an on-state are supplied to the nodes (nodes DN1, DN3, and DN4) between the transistors DM1, DM2, DM5, and DM6. In FIG. 6, the potential supplied to the node DN1 between the transistors DM1 and DM2 is referred to as V Ｍ１ , the potential supplied to the node DN3 between the transistors DM2 and DM5 is V Ｍ２ , the potential supplied to the node DN4 between the transistors DM5 and DM6 is V Ｍ３ where V Ｍ１ is a potential lower than VDD, and V Ｍ２ is V Ｍ１ is a potential lower than V Ｍ３ is V Ｍ２ VSS is a voltage lower than V Ｍ３ That is, VDD, V Ｍ１ , V Ｍ２ , V Ｍ３ , and VSS is VDD>VＭ１ >V Ｍ２ >V Ｍ３ >VSS has a magnitude relationship.

[0118] In addition, the potential of the node DN1 of the switch DSW1 is V Ｍ１ As a result, the potential of the node N1 of the switch SW1 connected thereto also becomes V Ｍ１ Similarly, when the potential of the node DN3 of the switch DSW1 is V Ｍ２ As a result, the potential of the node N3 of the switch SW1 connected thereto also becomes V Ｍ２ The potential of the node DN4 of the switch DSW1 is V Ｍ３ As a result, the potential of the node N4 of the switch SW1 connected thereto also becomes V Ｍ３ This becomes:

[0119] At this time (third state), the potential of node ND, the potential of node N2 between transistors M3 and M4 in switch SW2, the potential of node N5 between transistors M4 and M7 in switch SW2, the potential of node N6 between transistors M7 and M8 in switch SW2, the potential of node DN2 between transistors DM3 and DM4 in switch DSW2, the potential of node DN5 between transistors DM4 and DM7 in switch DSW2, and the potential of node DN6 between transistors DM7 and DM8 in switch DSW2 are all VSS.

[0120] Next, the transition period when the state switches from the third state to the fourth state will be described with reference to Fig. 7. Fig. 7 shows the state immediately after switching from the third state to the fourth state, i.e., immediately after the switch SW1 becomes conductive.

[0121] First, the switch DSW1 is turned off, and then the switch SW1 is turned on. Here, a high potential (V Ｈ ) is supplied, the potential of the node ND is VSS, and the potential of the node N1 is V Ｍ１ and the potential of the node N3 is VＭ２ and the potential of the node N4 is V Ｍ３ Therefore, the source-drain voltages (V ｄｓ ) are VDD-V Ｍ１ , V Ｍ１ -V Ｍ２ , V Ｍ２ -V Ｍ３ , V Ｍ３ Therefore, the transistors M1, M2, M5, and M6 are each supplied with V ｄｓ Therefore, hot carriers are less likely to be generated in the transistors M1, M2, M5, and M6.

[0122] A current flows through the switch SW1 until the potential of the node ND rises to VDD, and then the switch SW1 enters a steady state. At this time, the potentials of the nodes N1, N3, N4, DN1, DN3, and DN4 also become VDD. This state is the fourth state shown in FIG. 8.

[0123] Next, the transition period when the state switches from the fourth state to the fifth state will be described with reference to Fig. 9. Fig. 9 shows the state immediately after switching from the fourth state to the fifth state, i.e., immediately after the switch DSW2 becomes conductive.

[0124] As described above, in the fifth state, the switch DSW2 is in a conductive state, and the switches SW1, SW2, and DSW1 are in a non-conductive state, so that the switch DSW2 divides the potential between VDD and VSS. Potentials corresponding to the magnitude of the resistance of the transistors DM3, DM4, DM7, and DM8 when they are in an on state are supplied to the nodes (nodes DN2, DN5, and DN6) between the transistors DM3, DM4, DM7, and DM8. In FIG. 9, the potential supplied to the node DN2 between the transistors DM3 and DM4 is V Ｍ１ , the potential supplied to the node DN5 between the transistors DM4 and DM7 is V Ｍ２ , the potential supplied to the node DN6 between the transistors DM7 and DM8 is V Ｍ３ is shown as

[0125] In addition, the potential of the node DN2 of the switch DSW2 is V Ｍ１ As a result, the potential of the node N2 of the switch SW2 connected thereto also becomes V Ｍ１ Similarly, when the potential of the node DN5 of the switch DSW2 is V Ｍ２ As a result, the potential of the node N5 of the switch SW2 connected thereto also becomes V Ｍ２ The potential of the node DN6 of the switch DSW2 is V Ｍ３ As a result, the potential of the node N6 of the switch SW2 connected thereto also becomes V Ｍ３ This becomes:

[0126] Next, the transition period when the state switches from the fifth state to the sixth state will be described with reference to Fig. 10. Fig. 10 shows the state immediately after switching from the fifth state to the sixth state, i.e., immediately after the switch SW2 becomes conductive.

[0127] First, the switch DSW2 is turned off, and then the switch SW2 is turned on. Here, a high potential (V Ｈ) is supplied, the potential of the node ND is VDD, and the potential of the node N2 is V Ｍ１ and the potential of the node N5 is V Ｍ２ and the potential of the node N6 is V Ｍ３ Therefore, the source-drain voltages (V ｄｓ ) are VDD-V Ｍ１ , V Ｍ１ -V Ｍ２ , V Ｍ２ -V Ｍ３ , V Ｍ３ Therefore, the transistors M3, M4, M7, and M8 are each supplied with V ｄｓ Therefore, hot carriers are less likely to be generated in the transistors M3, M4, M7, and M8.

[0128] A current flows through the switch SW2 until the potential of the node ND drops to VSS, and then the switch SW2 enters a steady state. At this time, the potentials of the nodes N2, N5, N6, DN2, DN5, and DN6 also become VSS. This state is the sixth state shown in FIG. 11 .

[0129] As described above, the semiconductor device according to one embodiment of the present invention has a configuration in which the switches DSW1 and DSW2 are added to a conventional semiconductor device, and thus the source-drain voltages (V ｄｓ ) can be made smaller than VDD-VSS. ｄｓ In other words, the generation of hot carriers can be suppressed, and hot carrier degradation of the transistor can be prevented.

[0130] In addition, by increasing the number of series-connected transistors in each switch from two to three or more, the potential division between the transistors in each switch is subdivided, and the source-drain voltage (V ｄｓ Therefore, it can be said that the effect of suppressing hot carrier degradation of the transistors is higher when the number of series-connected transistors in each switch is three or more than when it is two.

[0131] 12 is a circuit diagram illustrating an example in which a semiconductor device of one embodiment of the present invention is used in a shift register circuit, in which the semiconductor device whose operation examples are described with reference to FIGS.

[0132] The shift register circuit SR has a switch SW1a as the first switch SW1 and a switch SW1b as the second switch SW1. It also has a switch SW2a as the first switch SW2 and a switch SW2b as the second switch SW2. It also has a switch DSW1a as the first switch DSW1 and a switch DSW1b as the second switch DSW1. It also has a switch DSW2a as the first switch DSW2 and a switch DSW2b as the second switch DSW2. The switch SW1a is connected to the switch SW2a at a node NC. The switch SW1b is connected to the switch SW2b at a node NB. Details of the nodes will be described later.

[0133] The shift register circuit SR also includes switches SW3, SW4, and SW5, each of which includes a plurality of series-connected transistors, and two capacitance elements (capacitance element Ca and capacitance element Cb).

[0134] 12 shows an example in which four transistors are connected in series to the switches SW3 to SW5, similar to the switches SW1a, etc. However, the number of transistors is not limited to this and may be one or more. By connecting multiple transistors in series, it is possible to reduce leakage current and stabilize circuit operation.

[0135] In the following description, for simplicity, each switch is considered to be a single transistor, and the gate of the multiple series-connected transistors in each switch is referred to as the “gate of the switch.” Furthermore, of the multiple series-connected transistors in each switch, the drain of the end transistor to which a high potential is supplied is referred to as the “drain of the switch,” and the source of the end transistor to which a low potential is supplied is referred to as the “source of the switch.”

[0136] The source of switch SW1a is connected to the drain of switch SW2a and one of the source or drain of switch SW3. The gate of switch SW2a is connected to one electrode of capacitance element Ca, the source of switch SW1b, the drain of switch SW2b, and the gate of switch SW5. The other of the source or drain of switch SW3 is connected to the gate of switch SW4 and one electrode of capacitance element Cb. The source or drain of switch SW4 is connected to the other electrode of capacitance element Cb and the drain of switch SW5.

[0137] A high-potential power supply line is connected to the drains of the switches SW1a, DSW1a, DSW2a, SW1b, DSW1b, DSW2b, and the gate of the switch SW3. A low-potential power supply line is connected to the sources of the switches DSW1a, SW2a, DSW2a, DSW1b, SW2b, DSW2b, SW5, and the other electrode of the capacitance element Ca.

[0138] The gates of the switches SW1a and SW2b function as a signal input unit LIN. The gate of the switch SW1b functions as a signal input unit RIN. The other of the source or drain of the switch SW4 functions as a clock signal input unit CLK. One of the source or drain of the switch SW4, the other electrode of the capacitive element Cb, and the drain of the switch SW5 function as a signal output unit SOUT.

[0139] The gates of the switches DSW1a and DSW2b function as signal input units A. The gates of the switches DSW1b function as signal input units B. The gates of the switches DSW2a function as signal input units C. Here, the signal input unit A is a signal input unit that inputs signals to the gates of the switches DSW1a and DSW2b before signals are input from the signal input unit LIN to the gates of the switches SW1a and SW2b during operation of a sequential circuit in which multiple shift register circuits SR are connected. The signal input unit B is a signal input unit that inputs a signal to the gate of the switch DSW1b before signals are input from the signal input unit RIN to the gate of the switch SW1b during operation of the sequential circuit. The signal input unit C is a signal input unit that inputs a signal to the gate of the switch DSW2a before signals are input from the signal input unit RIN to the gate of the switch SW1b during operation of the sequential circuit. Note that details of a configuration example and an operation example of the sequential circuit will be described with reference to FIGS. 13A to 13C.

[0140] Here, the node where the other of the source or drain of switch SW3, the gate of switch SW4, and one electrode of capacitance element Cb are connected is referred to as node NA. Also, the node where the gate of switch SW2a, one electrode of capacitance element Ca, the source of switch SW1b, the drain of switch SW2b, and the gate of switch SW5 are connected is referred to as node NB. Also, the node where the source of switch SW1a, the drain of switch SW2a, and one of the source or drain of switch SW3 are connected is referred to as node NC.

[0141] As shown in FIG. 13A, n stages (n is an integer equal to or greater than 2) of shift register circuits SR can be cascaded to form a sequential circuit. A start pulse signal (SSP) is input to the signal input terminal LIN of the first-stage shift register circuit SR, and the signal output terminal SOUT[1] is connected to the signal input terminal LIN of the second-stage shift register circuit. The signal output terminal SOUT[2] of the second-stage shift register circuit SR is connected to the signal input terminal RIN of the first-stage shift register circuit SR. An end pulse (SEP) is input to the signal input terminal RIN of the n-th stage shift register circuit SR. A dummy shift register circuit SR may be provided to generate the SEP.

[0142] With this configuration, pulse signals can be sequentially output to the signal output units SOUT[1] to SOUT[n], and the device can be used as a gate driver for selecting pixels of a display device or a driver circuit for a touch sensor.Furthermore, by combining the device with a latch circuit, an amplifier circuit, or the like, the device can be used as a source driver for supplying data to pixels.

[0143] Next, the operation of the sequential circuit shown in Fig. 13A when applied to a gate driver will be described. Fig. 13B is a timing chart illustrating the operation of the shift register circuit SR connected to the gate line in the kth row (k is an odd number equal to or less than n-1). Fig. 13C is a timing chart illustrating the operation of the shift register circuit SR connected to the gate line in the k+1th row.

[0144] As shown in Fig. 13A, the clock signals input to the odd-numbered stages are different from those input to the even-numbered stages, but the basic operations are almost the same, and here, the operation of the shift register circuit SR connected to the gate line in the kth row will be mainly described using Fig. 13B.

[0145] Here, the signal input to the signal input unit LIN is the LIN signal, the signal input to the clock signal input unit CLK is the CLK signal, the signal input to the signal input unit RIN is the RIN signal, the signal output from the signal output unit SOUT is the SOUT signal, the signal input to the signal input unit A is the A signal, the signal input to the signal input unit B is the B signal, and the signal input to the signal input unit C is the C signal.

[0146] In a period T1, a signal A having a high potential is input to the gates of the switches DSW1a and DSW2b, and potential division is performed between the transistors of the switches DSW1a and DSW2b. Accordingly, the potential obtained by the potential division is also supplied to the nodes between the transistors of the switches SW1a connected to the nodes between the transistors of the switches DSW1a and DSW2b, and to the nodes between the transistors of the switches SW2b connected to the nodes between the transistors of the switches DSW2b.

[0147] The period T2 is provided to prevent the operations in the above-described period T1 from overlapping with the operations in the period T3 described below. Note that if the operations in the period T1 and the operations in the period T3 do not overlap, the period T2 does not need to be provided.

[0148] In the period T3, a LIN signal of high level potential is input to the gate of the switch SW1a from the gate line SSP or the n-1th row, the switch SW1a is turned on, the potential of the node NC becomes high level potential (VDD), and the node NA is precharged. At this time, the node between the transistors of the switch SW1a is already supplied with the potential divided as described above, so the source-drain voltage (V ｄｓ ) can be operated in a relatively small state.

[0149] Also, a LIN signal of high level potential is input to the gate of the switch SW2b from the gate line SSP or the n-1th row, and the switch SW2b is turned on, discharging the node NB to low level potential. At this time, the node between the transistors of the switch SW2b is already supplied with the potential divided as described above, and therefore the source-drain voltage (V ｄｓ ) can be operated in a relatively small state.

[0150] Furthermore, since the switch SW4 is in a conductive state due to the precharging of the node NA, the switch SW5 is in a non-conductive state due to the discharging of the node NB, and the CLK signal is at a low level potential (VSS), the SOUT signal is at a low level potential. Furthermore, a charge corresponding to the potential difference between VDD and VSS is stored in the capacitance element Cb.

[0151] In addition, in period T3, a high-level potential signal B is input to the gate of the switch DSW1b, and potential division is performed between the transistors of the switch DSW1b. Accordingly, the potential obtained by the potential division is also supplied to the nodes between the transistors of the switch SW1b connected to the nodes between the transistors of the switch DSW1b.

[0152] Similarly, in period T3, a high-level C signal is input to the gate of the switch DSW2a, and potential division is performed between the transistors of the switch DSW2a. Accordingly, the potential obtained by the potential division is also supplied to the nodes between the transistors of the switch SW2a connected to the nodes between the transistors of the switch DSW2a.

[0153] In period T4, when the CLK signal is switched to a high-level potential (VDD), the switch SW4 is turned on, the switch SW5 is turned off, and the SOUT signal is turned to a high-level potential.

[0154] Furthermore, as the gate line in the kth row is charged, the potential of the node NA rises due to the capacitive coupling of the capacitance element Cb, and the gate voltage of the switch SW4 increases, compensating for the charging of the gate line in the kth row. At this time, since there is a potential difference of VDD-VSS across the capacitance element Cb, the node NA rises to 2×(VDD-VSS).

[0155] Here, the source potential of the switch SW3 becomes higher than the gate potential, and the switch SW3 is in a non-conductive state. Therefore, the potential of the node NC does not become higher than VDD. Therefore, the source-drain voltage (V ｄｓ ) does not increase unnecessarily, and stress on the transistor can be suppressed.

[0156] At this time, the SOUT signal at high level potential is input as the LIN signal to the next-stage shift register circuit SR, and in the next-stage shift register circuit SR, the node NA is precharged and the node NB is discharged.

[0157] In period T5, the CLK signal is switched to a low-level potential. Also, the SOUT signal at a high-level potential in the next-stage shift register circuit SR is input as a RIN signal to the gate of the switch SW1b, causing the switch SW1b to conduct and charging the node NB to a high-level potential. At this time, the node between the transistors of the switch SW1b is already supplied with the potential divided as described above, so the source-drain voltage (V ｄｓ ) can be operated in a relatively small state.

[0158] Furthermore, when the switch SW2a is turned on, the node NC becomes a low level potential. At this time, since the potential obtained by dividing the potential has already been supplied to the node between the transistors of the switch SW2a, the source-drain voltage (V ｄｓ ) can be operated in a relatively small state.

[0159] When node NC becomes low potential, switch SW3 becomes conductive, node NA is discharged to low potential, and switch SW4 becomes non-conductive. Also, switch SW5 becomes conductive, and signal SOUT becomes low potential. Furthermore, capacitance element Ca is charged with a charge corresponding to the potential difference between VDD and VSS.

[0160] The above operation completes the operation of the shift register circuit SR connected to the gate line of the kth row. After that, until operation is performed again in the next frame, the switch SW5 is maintained in a conductive state due to the potential difference held in the capacitance element Ca, and the SOUT signal is maintained at a low potential.

[0161] The above has been a description of a shift register circuit SR to which a semiconductor device according to one embodiment of the present invention is applied. Although the above example shows the shift register circuit SR including both the switches SW1 and DSW1 and the switches SW2 and DSW2 of the semiconductor device, it is also possible to use either one of them. For example, it is also possible to use only the switches SW1a and DSW1a, and to use only the switches SW2a, SW1b, and SW2b in the locations where the switches SW2a and DSW2a are applied, the locations where the switches SW1b and DSW1b are applied, and the locations where the switches SW2b and DSW2b are applied, respectively. By reducing the number of switches applied in the shift register circuit SR, the area occupied by the shift register circuit SR on the substrate surface can be reduced, thereby enabling a narrower frame of the display device.

[0162] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0163] Embodiment 2 In this embodiment, a structural example of a semiconductor device according to one embodiment of the present invention, a manufacturing method of the semiconductor device, and the like will be described.

[0164] As described in Embodiment 1, vertical transistors can be used as transistors that constitute switches included in a semiconductor device according to one embodiment of the present invention. Furthermore, a plurality of transistors that are connected in series and that constitute each switch can be stacked, sharing some components. This allows the area occupied by the semiconductor device within the substrate surface to be significantly reduced compared to, for example, a case where a plurality of planar transistors are arranged on the same plane. Furthermore, the number of steps involved in manufacturing the semiconductor device can be reduced.

[0165] For example, when the semiconductor device of one embodiment of the present invention is used as a gate driver of a display device, a vertical transistor can be used as each of a plurality of series-connected transistors constituting the circuit, and the transistors whose source electrodes and drain electrodes are connected to each other can be stacked, thereby reducing the area occupied by the gate driver and narrowing the frame of the display device.

[0166] Below, specific structural examples of the semiconductor device of one embodiment of the present invention will be described with reference to the drawings.

[0167] <Configuration Example 1 of Semiconductor Device> Fig. 14A shows a plan view (also referred to as a top view) of a semiconductor device 100A. Fig. 14B shows a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 14A, and Fig. 15A shows a cross-sectional view taken along dashed dotted line B1-B2 in Fig. 14A. Fig. 15B shows a circuit diagram illustrating the configuration of the semiconductor device 100A. Note that Fig. 14A omits some of the components of the semiconductor device 100A (insulating layers, etc.). As with Fig. 14A, some of the components will also be omitted in plan views of semiconductor devices and the like in subsequent drawings.

[0168] The semiconductor device 100A is provided over a substrate 102. Although not shown in FIG. 14B and other drawings, an insulating layer functioning as a base film may be provided between the substrate 102 and the semiconductor device 100A. The semiconductor device 100A includes a switch 100A1, a switch 100A2, an insulating layer 110_1 (insulating layer 110a1, insulating layer 110b1, and insulating layer 110c1), and an insulating layer 110_2 (insulating layer 110a2, insulating layer 110b2, and insulating layer 110c2).

[0169] The switch 100A1 and the switch 100A2 share some components and are provided adjacent to each other on the same plane. The switch 100A1 includes transistors 10A1_1 and 10A1_2, and the switch 100A2 includes transistors 10A2_1 and 10A2_2. The transistors 10A1_1 and 10A1_2 share some components and are provided overlapping in this order. The transistors 10A2_1 and 10A2_2 share some components and are provided overlapping in this order.

[0170] That is, in the semiconductor device 100A, a transistor 10A1_1 is provided in the first layer of a switch 100A1, and a transistor 10A1_2 is provided in the second layer. Also, a transistor 10A2_1 is provided in the first layer of a switch 100A2, and a transistor 10A2_2 is provided in the second layer.

[0171] The transistor 10A1_1 includes a conductive layer 104_1, an insulating layer 106, a semiconductor layer 108_1, a conductive layer 112a1, and a conductive layer 112b. A part of the conductive layer 104_1 functions as a gate electrode. A part of the insulating layer 106 functions as a gate insulating layer. The conductive layer 112a1 functions as one of a source electrode and a drain electrode. The conductive layer 112b functions as the other of the source electrode and the drain electrode. A region of the semiconductor layer 108_1 that overlaps with the gate electrode with the gate insulating layer interposed therebetween functions as a channel formation region. A region of the semiconductor layer 108_1 that is in contact with the source electrode functions as a source region, and a region of the semiconductor layer 108_1 that is in contact with the drain electrode functions as a drain region.

[0172] The transistor 10A1_2 includes a conductive layer 104_1, an insulating layer 106, a semiconductor layer 108_1, a conductive layer 112b, and a conductive layer 112c. Another part of the conductive layer 104_1 functions as a gate electrode. Another part of the insulating layer 106 functions as a gate insulating layer. The conductive layer 112b functions as one of a source electrode and a drain electrode. The conductive layer 112c functions as the other of the source electrode and the drain electrode. A region of the semiconductor layer 108_1 that overlaps with the gate electrode with the gate insulating layer interposed therebetween functions as a channel formation region. A region of the semiconductor layer 108_1 that is in contact with the source electrode functions as a source region, and a region of the semiconductor layer 108_1 that is in contact with the drain electrode functions as a drain region.

[0173] That is, in the switch 100A1, the conductive layer 104_1 functions as the gate electrode of the transistor 10A1_1 and also functions as the gate electrode of the transistor 10A1_2. The insulating layer 106 functions as the gate insulating layer of the transistor 10A1_1 and also functions as the gate insulating layer of the transistor 10A1_2. The semiconductor layer 108_1 functions as the semiconductor layer of the transistor 10A1_1 and also functions as the semiconductor layer of the transistor 10A1_2. The conductive layer 112b functions as the other of the source and drain electrodes of the transistor 10A1_1 and also functions as one of the source and drain electrodes of the transistor 10A1_2.

[0174] The above description of switch 100A1 can also be applied to switch 100A2 by replacing transistor 10A1_1, transistor 10A1_2, conductive layer 104_1, semiconductor layer 108_1, and conductive layer 112a1 with transistor 10A2_1, transistor 10A2_2, conductive layer 104_2, semiconductor layer 108_2, and conductive layer 112a2, respectively.

[0175] In the semiconductor device 100A, the insulating layer 106, the conductive layer 112b, and the conductive layer 112c each function as components of the switch 100A1 and also function as components of the switch 100A2. That is, in the semiconductor device 100A, the switch 100A1 and the switch 100A2 can be said to share some components.

[0176] As described above, in the semiconductor device 100A, the transistors 10A1_1 and 10A1_2 are stacked and share some of their components, and the transistors 10A2_1 and 10A2_2 are stacked and share some of their components. The semiconductor device 100A can also be said to have a configuration in which some of the electrodes (one (or the other) of the source electrode or the drain electrode and the gate electrode) of the transistors 10A1_1 and 10A1_2 are connected to each other. The semiconductor device 100A can also be said to have a configuration in which some of the electrodes (one (or the other) of the source electrode or the drain electrode and the gate electrode) of the transistors 10A2_1 and 10A2_2 are connected to each other. The semiconductor device 100A can also be said to have a configuration in which some of the electrodes (one (or the other) of the source electrode or the drain electrode and the gate electrode) of the transistors 10A1_1 and 10A2_1 are connected to each other. Alternatively, some electrodes (one (or the other) of the source electrode and the drain electrode) of the transistor 10A1_2 and the transistor 10A2_2 are connected to each other.

[0177] The detailed configuration of the semiconductor device 100A will be described below.

[0178] On the substrate 102, a conductive layer 112a1 and a conductive layer 112a2 are provided in different regions. In FIGS. 14A and 14B , the conductive layer 112a1 extends to the A1 side of the dashed-dotted line A1-A2, and the conductive layer 112a2 extends to the A2 side of the dashed-dotted line A1-A2. An insulating layer 110a1 is provided on the conductive layer 112a1, the conductive layer 112a2, and the substrate 102. An insulating layer 110b1 is provided on the insulating layer 110a1. An insulating layer 110c1 is provided on the insulating layer 110b1. A conductive layer 112b is provided on the insulating layer 110c1. As shown in FIGS. 14A and 14B , the conductive layer 112b is provided so as to have regions overlapping with the conductive layer 112a1 and the conductive layer 112a2. Note that the insulating layer 110a1, the insulating layer 110b1, and the insulating layer 110c1 may be collectively referred to as the insulating layer 110_1.

[0179] The conductive layer 112a1, the insulating layer 110_1, and the conductive layer 112b have overlapping regions. In this region, the insulating layer 110_1 is sandwiched between the conductive layer 112a1 and the conductive layer 112b. The conductive layer 112a2, the insulating layer 110_1, and the conductive layer 112b also have overlapping regions. In this region, the insulating layer 110_1 is sandwiched between the conductive layer 112a2 and the conductive layer 112b.

[0180] An insulating layer 110a2 is provided on the conductive layer 112b and the insulating layer 110c1. An insulating layer 110b2 is provided on the insulating layer 110a2. An insulating layer 110c2 is provided on the insulating layer 110b2. A conductive layer 112c is provided on the insulating layer 110c2. FIGS. 14A and 14B show a configuration in which the conductive layer 112c has regions overlapping with the conductive layer 112a1, the conductive layer 112a2, and the conductive layer 112b, and extends to the A1 side of the dashed dotted line A1-A2. Note that the insulating layer 110a2, the insulating layer 110b2, and the insulating layer 110c2 may be collectively referred to as the insulating layer 110_2.

[0181] The conductive layer 112b, the insulating layer 110_2, and the conductive layer 112c have a region where they overlap with each other. In this region, the insulating layer 110_2 is sandwiched between the conductive layer 112b and the conductive layer 112c.

[0182] The conductive layer 112a1, the insulating layer 110_1, the conductive layer 112b, the insulating layer 110_2, and the conductive layer 112c overlap with each other in some regions. The conductive layer 112a2, the insulating layer 110_1, the conductive layer 112b, the insulating layer 110_2, and the conductive layer 112c overlap with each other in some regions.

[0183] The insulating layer 110_1, the conductive layer 112b, the insulating layer 110_2, and the conductive layer 112c have an opening 143_1 that reaches the conductive layer 112a1 in a region overlapping with the conductive layer 112a1, and an opening 143_2 that reaches the conductive layer 112a2 in a region overlapping with the conductive layer 112a2.

[0184] The top surface shapes of the openings 143_1 and 143_2 can be, for example, circular or elliptical. The top surface shapes of the openings 143_1 and 143_2 can be polygonal, such as triangular, quadrilateral (including rectangular, rhombic, and square), or pentagonal, or can be polygonal shapes with rounded corners. As shown in FIG. 14A , the top surface shapes of the openings 143_1 and 143_2 are preferably circular. By making the top surface shapes of the openings 143_1 and 143_2 circular, the processing accuracy when forming the openings 143_1 and 143_2 can be improved, and the openings 143_1 and 143_2 can be formed with finer sizes. Note that in this specification, a circle is not limited to a perfect circle.

[0185] 14B and other figures show a configuration in which the thicknesses of the conductive layer 112a1 in the region overlapping with the opening 143_1 and the conductive layer 112a2 in the region overlapping with the opening 143_2 are approximately equal to the thicknesses of the conductive layer 112a1 in the region not overlapping with the opening 143_1 and the conductive layer 112a2 in the region not overlapping with the opening 143_2, respectively, but this is not limited thereto. The thicknesses of the conductive layer 112a1 in the region overlapping with the opening 143_1 and the conductive layer 112a2 in the region not overlapping with the opening 143_2 may also be thinner than the thicknesses of the conductive layer 112a1 in the region not overlapping with the opening 143_1 and the conductive layer 112a2 in the region not overlapping with the opening 143_2, respectively. In this case, the electric field from the conductive layer 104_1 can be applied up to the channel formation region of the transistor 10A1_1 near the conductive layer 112a1. Therefore, the effect of the gate electric field on carriers in the channel formation region of the transistor 10A1_1 can be strengthened in some cases compared to when the conductive layer 112a1 has a uniform thickness. Similarly, the electric field from the conductive layer 104_2 can be applied to the channel formation region of the transistor 10A2_1 near the conductive layer 112a2. Therefore, the effect of the gate electric field on carriers in the channel formation region of the transistor 10A2_1 can be strengthened in some cases compared to when the conductive layer 112a2 has a uniform thickness.

[0186] The semiconductor layer 108_1 is provided in contact with the top surface of the conductive layer 112a1 in the opening 143_1, the side surface of the insulating layer 110_1 in the opening 143_1, the side surface of the conductive layer 112b in the opening 143_1, the side surface of the insulating layer 110_2 in the opening 143_1, the side surface of the conductive layer 112c in the opening 143_1, and part of the top surface of the conductive layer 112c. The semiconductor layer 108_2 is provided in contact with the top surface of the conductive layer 112a2 in the opening 143_2, the side surface of the insulating layer 110_1 in the opening 143_2, the side surface of the conductive layer 112b in the opening 143_2, the side surface of the insulating layer 110_2 in the opening 143_2, the side surface of the conductive layer 112c in the opening 143_2, and another part of the top surface of the conductive layer 112c.

[0187] 14B and the like show a structure in which the semiconductor layer 108_1 has a region in contact with the top surface of the conductive layer 112c, but this is not limited thereto. It is sufficient that the semiconductor layer 108_1 has at least a region in contact with the side surface of the conductive layer 112c in the opening 143_1.

[0188] For example, by configuring the entire semiconductor layer 108_1 to be located within the opening 143_1 and the end portion of the semiconductor layer 108_1 to be in contact only with the side surface of the conductive layer 112c within the opening 143_1, it is possible to prevent the end portion of the semiconductor layer 108_1 from causing a step on the conductive layer 112c, thereby improving the coverage of a film on the top surface of the conductive layer 112c as a formation surface.

[0189] 14B and other figures, the end portion of the semiconductor layer 108_1 extends to the outside of the opening 143_1, and the semiconductor layer 108_1 is in contact with not only the side surface of the conductive layer 112c in the opening 143_1 but also the top surface of the conductive layer 112c. This increases the contact area between the semiconductor layer 108_1 and the conductive layer 112c. This can prevent the semiconductor layer 108_1 from peeling off. Furthermore, the contact resistance between the semiconductor layer 108_1 and the conductive layer 112c is reduced, which may increase the on-state current of the transistor 10A1_2.

[0190] Note that for the semiconductor layer 108_2 and the opening 143_2, the above description of the semiconductor layer 108_1 and the opening 143_1 can be referred to by replacing the semiconductor layer 108_1 with the semiconductor layer 108_2, the opening 143_1 with the opening 143_2, and the transistor 10A1_2 with the transistor 10A2_2, respectively.

[0191] Here, the insulating layer 110b1 of the insulating layer 110_1 is preferably an insulating layer containing oxygen. Furthermore, it is preferably an insulating layer that releases oxygen by heating. Thus, for example, when a metal oxide is used for each of the semiconductor layers 108_1 and 108_2, oxygen contained in the insulating layer 110b1 can be supplied to the metal oxide. This can repair oxygen vacancies in the metal oxide, thereby improving the electrical characteristics and reliability of the transistors 10A1_1 and 10A2_1.

[0192] On the other hand, the insulating layer 110a1 and the insulating layer 110c1 of the insulating layer 110_1 preferably have a blocking property against gases such as oxygen and hydrogen. This can prevent oxygen contained in the insulating layer 110b1 from being released to the outside through the insulating layer 110a1 or the insulating layer 110c1. Furthermore, it can prevent hydrogen from diffusing from the outside of the insulating layer 110_1 into the insulating layer 110b1 through the insulating layer 110a1 or the insulating layer 110c1 and then diffusing into the semiconductor layer 108_1 and the semiconductor layer 108_2. For example, when a metal oxide is used for each of the semiconductor layer 108_1 and the semiconductor layer 108_2, hydrogen in the semiconductor layer 108_1 and the semiconductor layer 108_2 can cause deterioration of the electrical characteristics and reliability of the transistor 10A1_1 and the transistor 10A2_1.

[0193] Note that by replacing the insulating layer 110_1, the insulating layer 110a1, the insulating layer 110b1, and the insulating layer 110c1 with the insulating layer 110_2, the insulating layer 110a2, the insulating layer 110b2, and the insulating layer 110c2, respectively, the description of the transistors 10A1_1 and 10A2_1 can also be applied to the transistors 10A1_2 and 10A2_2.

[0194] An insulating layer 106 is provided over the semiconductor layer 108_1 and the semiconductor layer 108_2. The insulating layer 106 has a region in contact with the top surface and side surfaces of the semiconductor layer 108_1, the top surface and side surfaces of the semiconductor layer 108_2, the top surface and side surfaces of the conductive layer 112c, and the top surface of the insulating layer 110c2.

[0195] A conductive layer 104_1 and a conductive layer 104_2 are provided over the insulating layer 106. The conductive layer 104_1 is provided in contact with the top surface of the insulating layer 106 so as to have a region overlapping with the opening 143_1 in a plan view. The conductive layer 104_2 is provided in contact with the top surface of the insulating layer 106 so as to have a region overlapping with the opening 143_2 in a plan view. In FIG. 14A and other drawings, the conductive layer 104_1 and the conductive layer 104_2 each extend toward the B2 side of the dashed dotted line B1-B2.

[0196] The conductive layer 104_1 has a shape that conforms to the shapes of the semiconductor layer 108_1 and the insulating layer 106 in the opening 143_1. That is, the conductive layer 104_1 has a recessed portion on its upper surface that corresponds to the shape of the opening 143_1. The conductive layer 104_1 has a region that faces the semiconductor layer 108_1 in the opening 143_1 with the insulating layer 106 interposed therebetween. Similarly, the conductive layer 104_2 has a shape that conforms to the shapes of the semiconductor layer 108_2 and the insulating layer 106 in the opening 143_2. That is, the conductive layer 104_2 has a recessed portion on its upper surface that conforms to the shape of the opening 143_2. The conductive layer 104_2 has a region that faces the semiconductor layer 108_2 in the opening 143_2 with the insulating layer 106 interposed therebetween.

[0197] Note that the conductive layer 104_1 can also be formed to fill the opening 143_1. For example, depending on the diameter of the opening 143_1 in a plan view, the conductive layer 104_1 may be formed to fill the opening 143_1. In this case, a step or unevenness formed on the top surface of the conductive layer 104_1 in a region overlapping with the opening 143_1 is reduced, which is preferable because coverage of a layer formed thereon can be improved.

[0198] The above description of the conductive layer 104_1 and the opening 143_1 can also be applied to the conductive layer 104_2 by replacing the conductive layer 104_1 with the conductive layer 104_2 and the opening 143_1 with the opening 143_2.

[0199] In the transistors 10A1_1 and 10A2_1, the source electrode and the drain electrode are located at different heights with respect to the surface of the substrate 102, which is a surface where the transistors are formed, and the drain current flows in a direction perpendicular to or approximately perpendicular to the surface of the substrate 102. Similarly, in the transistors 10A1_2 and 10A2_2, the source electrode and the drain electrode are located at different heights with respect to the surface of the insulating layer 110_1, which is a surface where the transistors are formed, and the drain current flows in a direction perpendicular to or approximately perpendicular to the substantially flat surface of the insulating layer 110_1. That is, in the transistors 10A1_1, 10A2_1, 10A1_2, and 10A2_2, the drain current flows in the vertical direction or approximately vertically. Therefore, the transistors of one embodiment of the present invention can be referred to as vertical transistors, vertical channel transistors, or VFETs (Vertical Field Effect Transistors).

[0200] Since the source electrode and the drain electrode of each of the transistors 10A1_1, 10A2_1, 10A1_2, and 10A2_2 can be overlapped, the transistors can be made smaller than so-called planar transistors in which the source electrode and the drain electrode are arranged on the same plane, and the area occupied by the transistors within the substrate surface can be significantly reduced.

[0201] Furthermore, in the semiconductor device 100A of one embodiment of the present invention, the switch 100A1 is provided over the transistor 10A1_1, sharing some of the components with the transistor 10A1_2, and the switch 100A2 is provided over the transistor 10A2_1, sharing some of the components with the transistor 10A2_2, and the switch 100A2 is provided over the transistor 10A2_1, sharing some of the components with the transistor 10A2_2, and the switch 100A2 is provided over the transistor 10A2_1, sharing some of the components with the transistor 10A2_2, and the switch 100A2_1 is provided over the transistor 10A2_1, sharing some of the components with the transistor 10A2_2, and the switch 100A2_2 is provided over the transistor 10A2_1 ... Furthermore, since the transistors 10A1_1 and 10A1_2, and the transistors 10A2_1 and 10A2_2 share some of their components, the number of steps required to manufacture the entire semiconductor device can be reduced compared to when each transistor is provided separately.

[0202] The channel lengths and channel widths of the transistors 10A1_1, 10A2_1, 10A1_2, and 10A2_2 will be described.

[0203] In the transistor 10A1_1, a region of the semiconductor layer 108_1 in contact with the conductive layer 112a1 functions as one of a source region and a drain region, a region of the semiconductor layer 108_1 in contact with the conductive layer 112b functions as the other of the source region and the drain region, and a region between the source region and the drain region functions as a channel formation region. In the transistor 10A1_2, a region of the semiconductor layer 108_1 in contact with the conductive layer 112b functions as one of the source region and the drain region, a region of the semiconductor layer 108_1 in contact with the conductive layer 112c functions as the other of the source region and the drain region, and a region between the source region and the drain region functions as a channel formation region.

[0204] In the transistor 10A2_1, a region of the semiconductor layer 108_2 in contact with the conductive layer 112a2 functions as one of a source region and a drain region, a region of the semiconductor layer 108_2 in contact with the conductive layer 112b functions as the other of the source region and the drain region, and a region between the source region and the drain region functions as a channel formation region. In the transistor 10A2_2, a region of the semiconductor layer 108_2 in contact with the conductive layer 112b functions as one of the source region and the drain region, a region of the semiconductor layer 108_2 in contact with the conductive layer 112c functions as the other of the source region and the drain region, and a region between the source region and the drain region functions as a channel formation region.

[0205] Note that in the following, the channel length and the channel width of the vertical transistor of one embodiment of the present invention will be described using transistors 10A1_1 and 10A1_2 that constitute switch 100A1 in semiconductor device 100A. However, the following description can also be applied to transistors 10A2_1 and 10A2_2 that constitute switch 100A2 by replacing the corresponding components as appropriate.

[0206] The channel lengths of the transistors 10A1_1 and 10A1_2 are the distances between the source and drain regions of the transistors 10A1_1 and 10A1_2, respectively. In FIG. 15A, the channel length L1 of the transistor 10A1_1 and the channel length L2 of the transistor 10A1_2 are indicated by dashed double-headed arrows. In FIG. 15A, the distance along the semiconductor layer 108_1 in the region between the conductive layers 112a1 and 112b is indicated as the channel length L1 of the transistor 10A1_1. The distance along the semiconductor layer 108_1 in the region between the conductive layers 112b and 112c is indicated as the channel length L2 of the transistor 10A1_2.

[0207] Note that the channel length L1 of the transistor 10A1_1 may be the thickness of the insulating layer 110_1 in a region sandwiched between the top surface of the conductive layer 112a1 and the bottom surface of the conductive layer 112b (in the case of the channel length L2 of the transistor 10A1_2, the thickness of the insulating layer 110_2 in a region sandwiched between the top surface of the conductive layer 112b and the bottom surface of the conductive layer 112c). Alternatively, the channel length L1 of the transistor 10A1_1 may be the thickness of the insulating layer 110b1 (in the case of the channel length L2 of the transistor 10A1_2, the thickness of the insulating layer 110b2). Alternatively, the channel length L1 of the transistor 10A1_1 may be the sum of the thicknesses of the insulating layer 110_1 and the conductive layer 112b (in the case of the channel length L2 of the transistor 10A1_2, the sum of the thicknesses of the insulating layer 110_2 and the conductive layer 112c).

[0208] Here, the channel length L1 of the transistor 10A1_1 is determined by the thickness of the insulating layer 110_1, the thickness of the conductive layer 112b, the angle (angle θ143) between the surface where the semiconductor layer 108_1 is to be formed in the opening 143_1 (here, the side surface of the insulating layer 110_1) and the surface where the insulating layer 110_1 is to be formed (here, the top surface of the conductive layer 112a1), and the like, and is not affected by the performance of an exposure apparatus used to manufacture the transistor. Therefore, the channel length L1 can be made extremely small, thereby achieving a transistor with a micro-sized structure. The channel length L2 of the transistor 10A1_2 can also be determined by replacing the insulating layer 110_1, the conductive layer 112b, and the conductive layer 112a1 with the insulating layer 110_2, the conductive layer 112c, and the conductive layer 112b, respectively, as described above.

[0209] The channel lengths L1 and L2 can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and less than 2.5 μm, 10 nm or more and less than 2 μm, 10 nm or more and less than 1.5 μm, 10 nm or more and less than 1.2 μm, 10 nm or more and less than 1 μm, 10 nm or more and less than 500 nm, 10 nm or more and less than 300 nm, 10 nm or more and less than 200 nm, 10 nm or more and less than 100 nm, 10 nm or more and less than 50 nm, 10 nm or more and less than 30 nm, or 10 nm or more and less than 20 nm. For example, the channel lengths L1 and L2 can be, for example, 100 nm or more and less than 1 μm. By shortening the channel length L1, the on-current of the transistor 10A1_1 can be increased. By shortening the channel length L2, the on-current of the transistor 10A1_2 can be increased.

[0210] The thickness of the insulating layer 110_1 and the thickness of the insulating layer 110_2 can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and less than 2.5 μm, 10 nm or more and less than 2 μm, 10 nm or more and less than 1.5 μm, 10 nm or more and less than 1.2 μm, 10 nm or more and less than 1 μm, 10 nm or more and less than 500 nm, 10 nm or more and less than 300 nm, 10 nm or more and less than 200 nm, 10 nm or more and less than 100 nm, 10 nm or more and less than 50 nm, 10 nm or more and less than 30 nm, or 10 nm or more and less than 20 nm.

[0211] The angle θ143 can be, for example, 30 degrees to 90 degrees, 35 degrees to 85 degrees, 40 degrees to 80 degrees, 45 degrees to 80 degrees, 50 degrees to 80 degrees, 55 degrees to 80 degrees, 60 degrees to 80 degrees, 65 degrees to 80 degrees, or 70 degrees to 80 degrees. The smaller the angle θ143, the better the coverage of the layer (such as the semiconductor layer 108_1) formed along the sidewall of the opening 143_1 can be. On the other hand, the closer the angle θ143 is to 90 degrees, the better the area occupied by the transistor on the substrate surface can be reduced.

[0212] The channel widths of the transistors 10A1_1 and 10A1_2 correspond to the lengths of their source and drain regions in a plan view ( FIG. 14A ). That is, the channel width of the transistor 10A1_1 corresponds to the length of the region where the semiconductor layer 108_1 and the conductive layer 112a1 are in contact with each other or the length of the region where the semiconductor layer 108_1 and the conductive layer 112b are in contact with each other in a plan view (in the case of the channel width of the transistor 10A1_2, the length of the region where the semiconductor layer 108_1 and the conductive layer 112b are in contact with each other or the length of the region where the semiconductor layer 108_1 and the conductive layer 112c are in contact with each other in a plan view). Alternatively, the channel width of transistor 10A1_1 may be an intermediate value between the length of the region where the semiconductor layer 108_1 and the conductive layer 112a1 are in contact in a planar view and the length of the region where the semiconductor layer 108_1 and the conductive layer 112b are in contact in a planar view (in the case of the channel width of transistor 10A1_2, an intermediate value between the length of the region where the semiconductor layer 108_1 and the conductive layer 112b are in contact in a planar view and the length of the region where the semiconductor layer 108_1 and the conductive layer 112c are in contact in a planar view).

[0213] Here, the channel width of the transistor 10A1_1 is described as the perimeter of a region where the semiconductor layer 108_1 and the side surface of the conductive layer 112b on the opening 143_1 side are in contact. The channel width of the transistor 10A1_2 is described as the perimeter of a region where the semiconductor layer 108_1 and the side surface of the conductive layer 112c on the opening 143_1 side are in contact. In FIG. 15A , the channel width W1 of the transistor 10A1_1 and the channel width W2 of the transistor 10A1_2 are each indicated by a dashed double-headed arrow. Of these, the channel width W2 of the uppermost transistor 10A1_2 can also be considered to be the perimeter of the opening 143_1 in a plan view. Note that when the angle θ143 is 90 degrees, the channel width W1 of the lower transistor 10A1_1 can also be considered to be the perimeter of the opening 143_1 in a plan view.

[0214] The channel widths W1 and W2 are determined by the top surface shape of the opening 143_1, etc. In FIGS. 14A and 15A, the width D143 of the opening 143_1 is indicated by a double-headed, two-dot chain line. The width D143 refers to the short side of the smallest rectangle circumscribing the opening 143_1 in a plan view. When the opening 143_1 is formed using photolithography, the width D143 of the opening 143_1 is equal to or greater than the resolution limit of the exposure device. The width D143 is, for example, 0.20 μm or greater and less than 5.0 μm. Note that when the top surface shape of the opening 143_1 is circular, the width D143 corresponds to the diameter of the opening 143_1, and the channel width W2 (and the channel width W1 when the angle θ143 is 90 degrees) can be calculated as "D143 × π."

[0215] [Semiconductor Layer 108_1, Semiconductor Layer 108_2] The semiconductor material that can be used for the semiconductor layer 108_1 and the semiconductor layer 108_2 is not particularly limited. For example, an elemental semiconductor or a compound semiconductor can be used. As the elemental semiconductor, for example, silicon or germanium can be used. As the compound semiconductor, for example, gallium arsenide, silicon germanium, or the like can be used. As the compound semiconductor, an organic substance having semiconductor properties or a metal oxide having semiconductor properties (also referred to as an oxide semiconductor) can be used. Note that these semiconductor materials may contain impurities that function as dopants (for example, when silicon is used as the semiconductor material, typical examples include elements such as phosphorus and boron).

[0216] The crystallinity of the semiconductor material used for the semiconductor layer 108_1 and the semiconductor layer 108_2 is not particularly limited, and any of an amorphous semiconductor and a crystalline semiconductor (a single-crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. The use of a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0217] The semiconductor layer 108_1 and the semiconductor layer 108_2 can be formed using silicon. Examples of silicon include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS).

[0218] A transistor using amorphous silicon for the semiconductor layers 108_1 and 108_2 can be formed over a large glass substrate and can be manufactured at low cost. A transistor using polycrystalline silicon for the semiconductor layers 108_1 and 108_2 has high field-effect mobility and can operate at high speed. A transistor using microcrystalline silicon for the semiconductor layers 108_1 and 108_2 has higher field-effect mobility and can operate at high speed than a transistor using amorphous silicon.

[0219] The semiconductor layer 108_1 and the semiconductor layer 108_2 preferably contain a metal oxide (oxide semiconductor). Examples of metal oxides that can be used for the semiconductor layer 108_1 and the semiconductor layer 108_2 include indium oxide (also referred to as indium oxide), gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains one or more elements selected from indium, an element M, and zinc. The element M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium. In particular, the element M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin. Gallium is more preferred as the element M.

[0220] For the semiconductor layer 108_1 and the semiconductor layer 108_2, for example, indium oxide, indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium aluminum zinc oxide (In—Al—Zn oxide, also referred to as IAZO), indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In—Ga—Sn—Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In—Ga—Al—Zn oxide, also referred to as IGAZO or IAGZO), or the like can be used. Alternatively, indium tin oxide containing silicon can be used.

[0221] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). When forming a metal oxide by sputtering, the atomic ratio of the target may differ from the atomic ratio of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide may be smaller than the atomic ratio of the target. Specifically, the atomic ratio of zinc in the metal oxide may be approximately 40% to 90% of the atomic ratio of zinc contained in the target.

[0222] When the semiconductor layers 108_1 and 108_2 are formed by the ALD method, it is preferable to use a film formation method such as a thermal ALD method or a PEALD (Plasma Enhanced ALD) method. The thermal ALD method is preferable because it exhibits extremely high step coverage. The PEALD method is also preferable because it exhibits high step coverage and allows low-temperature film formation.

[0223] The composition of the metal oxide contained in the semiconductor layer 108_1 and the semiconductor layer 108_2 greatly affects the electrical characteristics and reliability of the transistors 10A1_1 and 10A1_2 and the transistors 10A2_1 and 10A2_2.

[0224] For example, by increasing the content of indium in the metal oxide, a transistor with a large on-state current can be realized. Furthermore, by using a metal oxide that does not contain gallium or has a low content of gallium in the semiconductor layers 108_1 and 108_2, for example, a transistor with high reliability against application of a positive bias can be obtained. Furthermore, by using a metal oxide with a low content of element M in the semiconductor layers 108_1 and 108_2, for example, a transistor with high reliability against application of a positive bias can be obtained. Furthermore, by increasing the content of element M in the metal oxide, for example, a transistor with high reliability against light can be obtained.

[0225] The composition of the metal oxide contained in the semiconductor layer 108_1 and the semiconductor layer 108_2 will be described in detail later.

[0226] It is preferable to use a crystalline metal oxide layer for the semiconductor layer 108_1 and the semiconductor layer 108_2. For example, a metal oxide layer having a CAAC (C-Axis Aligned Crystal) structure, a polycrystalline (poly-crystal) structure, a nanocrystalline (nc: nano-crystal) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer 108_1 and the semiconductor layer 108_2, the defect state density in the semiconductor layer 108_1 and the semiconductor layer 108_2 can be reduced, and a highly reliable transistor can be realized. Note that the CAAC structure is a crystal structure in which multiple microcrystals (typically, multiple IGZO microcrystals) have c-axis orientation and are connected without being oriented in the a-b plane. In the CAAC structure, crystal grain boundaries (grains) are less clearly visible in the a-b plane than in the polycrystalline structure, and therefore a highly reliable transistor can be realized.

[0227] The higher the crystallinity of the metal oxide layers used for the semiconductor layers 108_1 and 108_2, the more the density of defect states in the semiconductor layers 108_1 and 108_2 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0228] The semiconductor layer 108_1 and the semiconductor layer 108_2 may have a stacked structure of two or more metal oxide layers with different crystallinity. For example, a stacked structure of a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer can be used, and the second metal oxide layer can have a region with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer can have a region with lower crystallinity than the first metal oxide layer. The two or more metal oxide layers included in the semiconductor layer 108_1 and the semiconductor layer 108_2 may have the same or approximately the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used to form the layers, thereby reducing manufacturing costs. For example, a stacked structure of two or more metal oxide layers with different crystallinity can be formed by using the same sputtering target and varying the ratio of the flow rate of oxygen gas to the total deposition gas used during formation (hereinafter also referred to as the oxygen flow rate ratio). Note that the two or more metal oxide layers included in the semiconductor layer 108_1 and the semiconductor layer 108_2 may have different compositions.

[0229] The thickness of the semiconductor layer 108_1 and the semiconductor layer 108_2 (film thickness relative to the surface on which they are formed) is preferably 3 nm to 100 nm, more preferably 5 nm to 100 nm, even more preferably 10 nm to 100 nm, even more preferably 10 nm to 70 nm, even more preferably 15 nm to 70 nm, even more preferably 15 nm to 50 nm, even more preferably 20 nm to 50 nm, even more preferably 20 nm to 40 nm, and even more preferably 25 nm to 40 nm.

[0230] Here, oxygen vacancies that can be formed in the semiconductor layer 108_1 and the semiconductor layer 108_2 will be described.

[0231] When an oxide semiconductor is used for the semiconductor layer 108_1 and the semiconductor layer 108_2, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to form water, and oxygen vacancies (V Ｏ Furthermore, defects in which hydrogen enters an oxygen vacancy (hereinafter referred to as VＯ H.) functions as a donor and generates electrons as carriers. Furthermore, some of the hydrogen atoms may bond with oxygen atoms that are bonded to metal atoms to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily mobile due to stresses such as heat and an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be reduced.

[0232] Note that normally-on means that when the gate-source voltage of a transistor is 0V, a current flows between the source and drain.

[0233] V Ｏ H can function as a donor in an oxide semiconductor. However, it is difficult to quantitatively evaluate such defects. Therefore, in an oxide semiconductor, evaluation is sometimes performed using the carrier concentration rather than the donor concentration. Therefore, in this specification and the like, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of the oxide semiconductor, rather than the donor concentration. In other words, the "carrier concentration" described in this specification and the like may be rephrased as the "donor concentration."

[0234] From the above, when an oxide semiconductor is used for the semiconductor layer 108_1 and the semiconductor layer 108_2, V Ｏ It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic. Ｏ To obtain an oxide semiconductor in which H is sufficiently reduced, impurities such as water and hydrogen are removed from the oxide semiconductor (this may be referred to as dehydration or dehydrogenation treatment), and oxygen vacancies (V Ｏ It is important to repair the Ｏ By using an oxide semiconductor in which defects such as H are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained. Ｏ ) is sometimes referred to as oxygenation treatment.

[0235] When an oxide semiconductor is used for the semiconductor layer 108_1 and the semiconductor layer 108_2, the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is 1×10 １８ cm −３ Preferably, it is 1×10 or less. １７ cm −３ More preferably, it is less than 1×10 １６ cm −３ More preferably, it is less than 1×10 １３ cm −３ More preferably, it is less than 1×10 １２ cm −３ Note that the lower limit of the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is not particularly limited, but is preferably 1×10 −９ cm −３ It can be said that:

[0236] A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has significantly higher field-effect mobility than a transistor using amorphous silicon. Furthermore, an OS transistor has significantly lower source-drain leakage current in an off state (hereinafter also referred to as an off-state current) and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, by using an OS transistor in a semiconductor device, the power consumption of the semiconductor device can be reduced.

[0237] OS transistors can be applied to display devices. To increase the light-emission luminance of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since OS transistors have a higher source-drain breakdown voltage than transistors using silicon (hereinafter referred to as Si transistors), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as a driving transistor in a pixel circuit, it is possible to increase the amount of current flowing through the light-emitting device and increase the light-emission luminance of the light-emitting device.

[0238] When a transistor operates in the saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the current flowing between the source and drain can be precisely determined by changing the gate-source voltage, and the amount of current flowing through the light-emitting device can be precisely controlled. This allows for a greater number of gray levels to be displayed in the pixel circuit.

[0239] In terms of saturation characteristics of the current that flows when a transistor operates in a saturation region, an OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be passed through a light-emitting device, even when the current-voltage characteristics of the light-emitting device vary. In other words, when an OS transistor operates in a saturation region, the source-drain current of the OS transistor remains almost unchanged even when the source-drain voltage increases, thereby stabilizing the light-emitting luminance of the light-emitting device.

[0240] As described above, by using an OS transistor for a driving transistor included in a pixel circuit, it is possible to achieve "suppression of black floating," "increase in light emission luminance," "multiple gradations," "suppression of variations in light-emitting devices," and the like.

[0241] Furthermore, an OS transistor can also be applied to, for example, a gate driver of a display device. As described above, an OS transistor has an extremely high field-effect mobility compared to a transistor using amorphous silicon. Therefore, by applying an OS transistor to a gate driver of a display device, a gate driver capable of high-speed operation can be realized.

[0242] Furthermore, OS transistors exhibit little change in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, neutron rays, and proton rays).

[0243] In the transistor of one embodiment of the present invention, and in a switch, a semiconductor device, a display device, or the like to which the transistor of one embodiment of the present invention is applied, an inorganic insulating material or an organic insulating material can be used for the insulating layer (the insulating layer 110_1, the insulating layer 110_2, and the insulating layer 106). Alternatively, the insulating layer may have a stacked structure of an inorganic insulating material and an organic insulating material.

[0244] As the inorganic insulating material, one or more of an oxide, an oxynitride, a nitride oxide, and a nitride can be used.

[0245] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. A nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0246] For example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectrometry (XPS) can be used to analyze the oxygen and nitrogen contents. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., less than 0.5 atomic% or less than 1 atomic%). When comparing the element contents, it is more preferable to perform a combined analysis using both SIMS and XPS analytical techniques.

[0247] Furthermore, for evaluating the film density of an insulating layer or the like, for example, Rutherford Backscattering Spectrometry (RBS) or X-ray Reflection (XRR) can be used. Differences in film density can sometimes be evaluated using cross-sectional transmission electron microscopy (TEM) images. In TEM observation, a high film density results in a dense (dark) transmission electron (TE) image, whereas a low film density results in a pale (bright) transmission electron (TE) image. Even when the same material is used for the insulating layer, if the film densities are different, the boundary between these may be observed as a difference in contrast in a cross-sectional TEM image.

[0248] The nitrogen content of the insulating layer can be confirmed, for example, by energy dispersive X-ray spectrometry (EDX). For example, when silicon nitride, silicon oxynitride, or the like is used for the insulating layer, the nitrogen content can be evaluated using the ratio of the nitrogen peak height to the silicon peak height. In EDX, the peak of a certain element refers to the point at which the count number of the element reaches a maximum in a spectrum where the horizontal axis shows the energy of characteristic X-rays and the vertical axis shows the count number (detection value) of characteristic X-rays. Alternatively, the count number at the energy of characteristic X-rays specific to the element may be used to confirm the difference in nitrogen content by the ratio of the nitrogen count number to the silicon count number. For example, the count number at 1.739 keV (Si-Kα) can be used for silicon, and the count number at 0.392 keV (N-Kα) can be used for nitrogen.

[0249] The hydrogen concentration of the insulating layer can be evaluated by, for example, SIMS.

[0250] When hydrogen diffuses into the semiconductor layer 108_1 and the semiconductor layer 108_2, it reacts with oxygen atoms contained in the oxide semiconductor to form water, and oxygen vacancies (V Ｏ ) may be formed in the semiconductor layer 108_1 and the semiconductor layer 108_2. Ｏ When a blocking film that suppresses hydrogen diffusion is used as an insulating layer in contact with the semiconductor layer 108_1 or the semiconductor layer 108_2 or as an insulating layer located around the semiconductor layer 108_1 or the semiconductor layer 108_2, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0251] Oxygen vacancies (VＯ ) and V Ｏ In particular, when the channel length is short, oxygen vacancies (V Ｏ ) and V Ｏ For example, when VH flows from the source region or drain region to the channel formation region, the influence of VH on the electrical characteristics and reliability of each of the transistors 10A1_1, 10A1_2, 10A2_1, and 10A2_2 increases. Ｏ The diffusion of H increases the carrier concentration in the channel formation region, which may cause fluctuations in the threshold voltages of the transistors 10A1_1, 10A1_2, 10A2_1, and 10A2_2 or reduce the reliability. Ｏ The influence of the diffusion of H on the electrical characteristics and reliability of each of the transistors 10A1_1, 10A1_2, 10A2_1, and 10A2_2 increases as the channel length decreases. Ｏ ) and V Ｏ By reducing H, it is possible to realize a transistor with a short channel length, which has good electrical characteristics and high reliability.

[0252] By using an insulating layer that releases oxygen as an insulating layer in contact with the semiconductor layer 108_1 and the semiconductor layer 108_2 (for example, the insulating layer 106, the insulating layer 110b1, and the insulating layer 110b2), oxygen can be supplied from the insulating layer to the semiconductor layer 108_1 and the semiconductor layer 108_2. By supplying oxygen to the channel formation regions of the semiconductor layer 108_1 and the semiconductor layer 108_2, oxygen vacancies (V Ｏ ) and V Ｏ The H can be reduced, and a highly reliable transistor can be obtained, which has favorable electrical characteristics. Note that other treatments for supplying oxygen to the semiconductor layers 108_1 and 108_2 include heat treatment in an atmosphere containing oxygen, plasma treatment in an atmosphere containing oxygen, and the like.

[0253] It is preferable that an insulating layer in contact with the semiconductor layer 108_1 or 108_2, or an insulating layer located around the semiconductor layer 108_1 or 108_2, emits little impurities (for example, water and hydrogen) from itself. Note that the impurities referred to here are impurities that diffuse into the semiconductor layer 108_1 or 108_2 and cause oxygen vacancies (V Ｏ ) and V Ｏ Impurities refer to substances that can adversely affect the electrical characteristics of a transistor by, for example, generating H. Reducing the release of impurities can suppress the diffusion of the impurities into the semiconductor layers 108_1 and 108_2, thereby enabling a highly reliable transistor to exhibit favorable electrical characteristics.

[0254] Oxygen may be released from the semiconductor layers 108_1 and 108_2 due to heat applied in a process after the formation of the semiconductor layers 108_1 and 108_2. However, oxygen is supplied to the semiconductor layers 108_1 and 108_2 from an insulating layer in contact with the semiconductor layers 108_1 and 108_2, which can cause oxygen vacancies (V Ｏ ) and V Ｏ An increase in H can be suppressed. Furthermore, the degree of freedom in the process temperature can be increased in the processes after the formation of the semiconductor layers 108_1 and 108_2. Specifically, the process temperature can be increased in the processes after the formation of the semiconductor layers 108_1 and 108_2. Therefore, a transistor having good electrical characteristics and high reliability can be formed.

[0255] [Insulating Layer 110_1 and Insulating Layer 110_2] The insulating layer 110_1 (insulating layer 110a1, insulating layer 110b1, and insulating layer 110c1) and the insulating layer 110_2 (insulating layer 110a2, insulating layer 110b2, and insulating layer 110c2) can be formed using an inorganic insulating material or an organic insulating material. The insulating layer 110_1 and the insulating layer 110_2 may have a stacked structure of an inorganic insulating material and an organic insulating material.

[0256] An inorganic insulating material can be suitably used for the insulating layer 110_1 and the insulating layer 110_2. Examples of the inorganic insulating material that can be used include one or more of oxide, oxynitride, nitride oxide, and nitride. Examples of the insulating layer 110_1 and the insulating layer 110_2 that can be used include one or more of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, gallium oxide, tantalum oxide, magnesium oxide, lanthanum oxide, cerium oxide, neodymium oxide, silicon nitride, silicon nitride oxide, and aluminum nitride.

[0257] The insulating layer 110_1 and the insulating layer 110_2 may have a stacked structure of two or more layers. In Fig. 14B and other figures, the insulating layer 110_1 has a stacked structure of an insulating layer 110a1, an insulating layer 110b1 on the insulating layer 110a1, and an insulating layer 110c1 on the insulating layer 110b1, and the insulating layer 110_2 has a stacked structure of an insulating layer 110a2, an insulating layer 110b2 on the insulating layer 110a2, and an insulating layer 110c2 on the insulating layer 110b2. The insulating layers 110a1, 110b1, 110c1, 110a2, 110b2, and 110c2 may be made of the same material or different materials.

[0258] The insulating layers 110_1 and 110_2 preferably release little impurities (for example, water and hydrogen) from themselves.

[0259] The insulating layers 110b1 and 110b2 can be thicker than the insulating layers 110a1 and 110a2 and the insulating layers 110c1 and 110c2. As described above, the insulating layers 110b1 and 110b2 are insulating layers containing oxygen to be supplied to the semiconductor layers 108_1 and 108_2. Therefore, by making the insulating layers 110b1 and 110b2 thickest among the three insulating layers constituting the insulating layer 110_1 (the insulating layer 110a1, the insulating layer 110b1, and the insulating layer 110c1) and the three insulating layers constituting the insulating layer 110_2 (the insulating layer 110a2, the insulating layer 110b2, and the insulating layer 110c2), respectively, the amount of oxygen that can be contained in the entire insulating layer 110_1 and the entire insulating layer 110_2 can be increased. The deposition rate of the insulating layers 110b1 and 110b2 is preferably faster than the deposition rate of the insulating layers 110a1 and 110a2 and the deposition rate of the insulating layers 110c1 and 110c2. By increasing the deposition rate of a thick film, productivity can be improved.

[0260] The insulating layers 110a1 and 110c1, as well as the insulating layers 110a2 and 110c2, function as blocking films that suppress gas (e.g., oxygen) desorption from the insulating layers 110b1 and 110b2, respectively. The insulating layers 110a1 and 110c1, as well as the insulating layers 110a2 and 110c2, are preferably made of materials that are difficult for gas to diffuse through. The insulating layers 110a1 and 110c1, as well as the insulating layers 110a2 and 110c2, preferably have regions with higher film density than the insulating layers 110b1 and 110b2, respectively. Increasing the film density of the insulating layers can improve their blocking properties against gas. Slowing the film formation rate of the insulating layers increases the film density, thereby improving their blocking properties against gas.

[0261] The insulating layers 110b1 and 110b2 are preferably formed using an oxide or an oxynitride. The insulating layers 110b1 and 110b2 are preferably formed using a film that releases oxygen when heated. The insulating layers 110b1 and 110b2 are preferably formed using, for example, silicon oxide or silicon oxynitride.

[0262] When the insulating layers 110b1 and 110b2 release oxygen, oxygen can be supplied from the insulating layers 110b1 and 110b2 to the semiconductor layer 108_1 and the semiconductor layer 108_2, respectively. The insulating layers 110b1 and 110b2 preferably have a high oxygen diffusion coefficient. A high oxygen diffusion coefficient facilitates diffusion of oxygen in the insulating layers 110b1 and 110b2, allowing oxygen to be efficiently supplied to the semiconductor layer 108_1 and the semiconductor layer 108_2, respectively. Furthermore, as described above, by making the insulating layers 110b1 and 110b2 thicker than the insulating layers 110a1 and 110c1 and the insulating layers 110a2 and 110c2, respectively, more oxygen can be supplied to the semiconductor layer 108_1 and the semiconductor layer 108_2.

[0263] The insulating layers 110_1 and 110_2 are preferably formed by a film formation method such as a sputtering method, an ALD method, or a plasma CVD (Chemical Vapor Deposition) method.

[0264] In particular, by using a sputtering method without using a deposition gas containing hydrogen, a film with an extremely low hydrogen content can be obtained. Therefore, hydrogen supply to the semiconductor layer 108_1 and the semiconductor layer 108_2 can be suppressed, and the electrical characteristics of each of the transistors 10A1_1, 10A1_2, 10A2_1, and 10A2_2 can be stabilized. When silicon oxide is deposited by a sputtering method, it can be deposited using a silicon target in an atmosphere containing an oxygen gas, for example. When silicon nitride is deposited by a sputtering method, it can be deposited using a silicon target in an atmosphere containing nitrogen gas, for example. When aluminum oxide is deposited by a sputtering method, it can be deposited using an aluminum target in an atmosphere containing an oxidizing gas, for example.

[0265] Silicon oxide and silicon nitride can be formed by, for example, the PEALD method. Aluminum oxide and hafnium oxide can be formed by, for example, the thermal ALD method. By forming an insulating layer by the PEALD method and the thermal ALD method, a dense insulating film can be formed, and thus the blocking property against oxygen and hydrogen can be improved.

[0266] The insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2 can be made of a material having a higher nitrogen content than the insulating layers 110b1 and 110b2, respectively. Increasing the nitrogen content of the insulating layers can improve the blocking properties against oxygen and hydrogen.

[0267] The insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2 may each have a region with a lower hydrogen concentration than the insulating layer 110b1 and the insulating layer 110b2.

[0268] The insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2 are preferably impermeable to oxygen. Furthermore, the insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2 are preferably impermeable to hydrogen. The insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2 function as blocking films that suppress diffusion of hydrogen from the outside of the transistor to the semiconductor layer 108_1 and the semiconductor layer 108_2 through the insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2, respectively. The film densities of the insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2 are preferably higher than those of the insulating layers 110b1 and 110b2, respectively. Increasing the film density of the insulating layers can improve the blocking properties of oxygen and hydrogen. When silicon oxide or silicon oxynitride is used for the insulating layers 110b1 and 110b2, silicon nitride or silicon nitride oxide can be used for the insulating layers 110a1, 110c1, 110a2, and 110c2, respectively. Furthermore, hafnium oxide or aluminum oxide can be suitably used for the insulating layers 110a1, 110c1, 110a2, and 110c2.

[0269] Furthermore, the insulating layer 110a1, the insulating layer 110c1, the insulating layer 110a2, and the insulating layer 110c2 can each have a structure in which two or more materials selected from silicon nitride, silicon nitride oxide, hafnium oxide, and aluminum oxide are stacked.

[0270] If oxygen contained in the insulating layers 110b1 and 110b2 diffuses downward (toward the substrate 102) from the insulating layers 110b1 and 110b2, the amount of oxygen supplied from the insulating layers 110b1 and 110b2 to the semiconductor layers 108_1 and 108_2 may decrease. By providing the insulating layers 110a1 and 110a2 below the insulating layers 110b1 and 110b2, respectively, it is possible to prevent the oxygen contained in the insulating layers 110b1 and 110b2 from diffusing downward from the insulating layers 110b1 and 110b2. Furthermore, by providing the insulating layers 110c1 and 110c2 above the insulating layers 110b1 and 110b2, it is possible to prevent the oxygen contained in the insulating layers 110b1 and 110b2 from diffusing upward from the insulating layers 110b1 and 110b2. Therefore, the amount of oxygen supplied from the insulating layer 110b1 and the insulating layer 110b2 to the semiconductor layer 108_1 and the semiconductor layer 108_2 increases, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0271] Furthermore, by providing the insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2, diffusion of hydrogen into the semiconductor layers 108_1 and 108_2 is suppressed, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0272] The insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2 preferably have a thickness that functions as a blocking film for oxygen and hydrogen. If the insulating layers are too thin, the blocking film function may be impaired. On the other hand, if the insulating layers are too thick, the regions of the semiconductor layers 108_1 and 108_2 in contact with the insulating layers 110b1 and 110b2 may become narrower, and the amount of oxygen supplied to the semiconductor layers 108_1 and 108_2 may become smaller. The film thickness (film thickness relative to the surface on which the insulating layer 110a1, the insulating layer 110c1, the insulating layer 110a2, and the insulating layer 110c2 are preferably 1 nm or more and 200 nm or less, 1 nm or more and 100 nm or less, 1 nm or more and 60 nm or less, 1 nm or more and 50 nm or less, 1 nm or more and 40 nm or less, 1 nm or more and 30 nm or less, 1 nm or more and 20 nm or less, 1 nm or more and 10 nm or less, 1 nm or more and 5 nm or less, or 2 nm or more and 5 nm or less, respectively.

[0273] [Insulating Layer 106] The insulating layer 106, which functions as a gate insulating layer, preferably has a low defect density. A low defect density in the insulating layer 106 enables a transistor to exhibit favorable electrical characteristics. Furthermore, the insulating layer 106 preferably has a high withstand voltage. A high withstand voltage of the insulating layer 106 enables a highly reliable transistor.

[0274] The insulating layer 106 is preferably an insulating layer containing oxygen. Furthermore, the insulating layer 106 is preferably an insulating layer that releases oxygen by heating. Thus, for example, when a metal oxide is used for the semiconductor layers 108_1 and 108_2, oxygen contained in the insulating layer 106 can be supplied to the metal oxide. This can repair oxygen vacancies in the metal oxide, thereby improving the electrical characteristics and reliability of the transistors 10A1_1, 10A1_2, 10A2_1, and 10A2_2.

[0275] The insulating layer 106 can be formed using, for example, one or more of an oxide, an oxynitride, a nitride oxide, and a nitride having insulating properties. The insulating layer 106 can be formed using, for example, one or more of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga—Zn oxide. The insulating layer 106 can be formed as a single layer or a stacked layer. The insulating layer 106 can be formed as, for example, a stacked layer structure of an oxide and a nitride.

[0276] In a miniaturized transistor, a thin gate insulating layer may result in a large leakage current. By using a material with a high dielectric constant (also referred to as a high-k material) for the gate insulating layer, a low voltage can be achieved during transistor operation while maintaining the physical film thickness. Examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

[0277] The insulating layer 106 preferably releases little impurities (for example, water and hydrogen) from itself. The small amount of impurities released from the insulating layer 106 suppresses the impurities from diffusing into the semiconductor layers 108_1 and 108_2, thereby enabling a highly reliable transistor to exhibit favorable electrical characteristics.

[0278] Because the insulating layer 106 is formed over the semiconductor layers 108_1 and 108_2, it is preferable that the insulating layer 106 be formed under conditions that cause little damage to the semiconductor layers 108_1 and 108_2. For example, it is preferable that the insulating layer 106 be formed under conditions that cause a sufficiently slow film formation rate. For example, when the insulating layer 106 is formed by a plasma CVD method, low power consumption can reduce damage to the semiconductor layers 108_1 and 108_2.

[0279] Here, the insulating layer 106 will be specifically described using an example in which a metal oxide is used for the semiconductor layers 108_1 and 108_2.

[0280] In order to improve the interface characteristics with the semiconductor layer 108_1 and the semiconductor layer 108_2, it is preferable to use one or more of oxide and oxynitride on at least the side of the insulating layer 106 that is in contact with the semiconductor layer 108_1 and the semiconductor layer 108_2. For example, one or more of silicon oxide and silicon oxynitride can be suitably used for the insulating layer 106. It is more preferable to use a film that releases oxygen by heating for the insulating layer 106.

[0281] Note that the insulating layer 106 may have a stacked structure. The insulating layer 106 can have a stacked structure of an oxide film or oxynitride film in contact with the semiconductor layer 108_1 and the semiconductor layer 108_2, and a nitride film in contact with the conductive layer 104_1 and the conductive layer 104_2. As the oxide film or the oxynitride film, for example, one or more of silicon oxide and silicon oxynitride can be preferably used. As the nitride film, silicon nitride can be preferably used.

[0282] The thickness of the insulating layer 106 (thickness relative to the surface where the insulating layer 106 is formed) is preferably 1 nm to 100 nm. At least a part of the insulating layer 106 may have a region with the above thickness.

[0283] [Conductive Layers 112a1, 112a2, 112b, and 112c] The conductive layers 112a1, 112a2, 112b, and 112c, which function as source and drain electrodes, can be formed using one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, or an alloy containing one or more of the above metals. The conductive layers 112a1, 112a2, 112b, and 112c can be formed using a low-resistance conductive material containing one or more of copper, silver, gold, and aluminum. Copper and aluminum are particularly preferred because of their excellent mass productivity.

[0284] The conductive layer 112a1, the conductive layer 112a2, the conductive layer 112b, and the conductive layer 112c can each be formed using a metal oxide film (also referred to as an oxide conductor). Examples of oxide conductors (OC) include In—Sn oxide (ITO), In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Zn oxide, In—Sn—Si oxide (ITSO), and In—Ga—Zn oxide.

[0285] Here, oxide conductors (OC) will be described. For example, when oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes more conductive and becomes an electric conductor. A metal oxide that has become an electric conductor can be called an oxide conductor.

[0286] The conductive layers 112a1, 112a2, 112b, and 112c may each have a stacked structure of a conductive film containing the oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced.

[0287] The conductive layer 112a1, the conductive layer 112a2, the conductive layer 112b, and the conductive layer 112c may each be a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti). By using a Cu-X alloy film, it can be processed by wet etching, which makes it possible to reduce manufacturing costs.

[0288] Note that the conductive layer 112a1, the conductive layer 112a2, the conductive layer 112b, and the conductive layer 112c may be formed using the same material or different materials.

[0289] Here, the conductive layers 112a1, 112a2, 112b, and 112c will be specifically described using an example in which the semiconductor layers 108_1 and 108_2 are formed using metal oxide.

[0290] When an oxide semiconductor is used for the semiconductor layer 108_1 and the semiconductor layer 108_2, the conductive layer 112a1, the conductive layer 112a2, the conductive layer 112b, and the conductive layer 112c are oxidized by oxygen contained in the semiconductor layer 108_1 and the semiconductor layer 108_2, which may result in an increase in resistance. The conductive layer 112a1, the conductive layer 112a2, the conductive layer 112b, and the conductive layer 112c are oxidized by oxygen contained in the insulating layer 110_1 and the insulating layer 110_2, which may result in an increase in resistance. Furthermore, the conductive layer 112a1, the conductive layer 112a2, the conductive layer 112b, and the conductive layer 112c are oxidized by oxygen contained in the semiconductor layer 108_1 and the semiconductor layer 108_2, which may result in an oxygen deficiency (V Ｏ The conductive layers 112a1, 112a2, 112b, and 112c are oxidized by oxygen contained in the insulating layers 110_1 and 110_2, which may reduce the amount of oxygen supplied from the insulating layers 110_1 and 110_2 to the semiconductor layers 108_1 and 108_2.

[0291] The conductive layers 112a1, 112a2, 112b, and 112c are preferably made of a material that is resistant to oxidation. The conductive layers 112a1, 112a2, 112b, and 112c are preferably made of an oxide conductor. For example, In—Sn oxide (ITO) or In—Sn—Si oxide (ITSO) can be suitably used. The conductive layers 112a1, 112a2, 112b, and 112c may each be made of a nitride conductor. Examples of nitride conductors include tantalum nitride and titanium nitride. The conductive layers 112a1, 112a2, 112b, and 112c may each have a stacked structure of the above-mentioned materials.

[0292] By using a material that is difficult to oxidize for the conductive layer 112a1, the conductive layer 112a2, the conductive layer 112b, and the conductive layer 112c, it is possible to prevent oxidation due to oxygen contained in the semiconductor layer 108_1 or the semiconductor layer 108_2 or oxygen contained in the insulating layer 110_1 or the insulating layer 110_2, which can prevent an increase in resistance. Ｏ ) can be suppressed, and the amount of oxygen supplied from the insulating layers 110_1 and 110_2 to the semiconductor layers 108_1 and 108_2 can be increased.

[0293] The conductive layers 104_1 and 104_2, which function as gate electrodes, can be formed using, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, and niobium, or an alloy containing one or more of the above metals. Furthermore, the conductive layers 104_1 and 104_2 may be formed using the same materials as those used for the conductive layers 112a1, 112a2, 112b, and 112c.

[0294] 14B and the like, the conductive layers 104_1 and 104_2 are shown as single-layer structures, but this is not limited thereto. For example, the conductive layers 104_1 and 104_2 may have a stacked structure of two or more layers. For example, when the conductive layers 104_1 and 104_2 have a two-layer stacked structure, a nitride or an oxide can be used as the first conductive layer (the conductive layer on the insulating layer 106 side), and a second conductive layer can be made of one or more of chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, and niobium, or an alloy containing one or more of the above metals. Furthermore, for example, when the conductive layer 104_1 and the conductive layer 104_2 have a three-layer stacked structure, the first conductive layer (the conductive layer on the insulating layer 106 side) can be an alloy containing one or more of the above-mentioned metals as components, or a nitride of the metal or the alloy; the second conductive layer can be an alloy containing one or more of the above-mentioned metals as components; and the third conductive layer can be an alloy containing one or more of the above-mentioned metals as components, or a nitride of the metal or the alloy.

[0295] [Substrate 102] There are no significant limitations on the material of the substrate 102, but it is necessary that the material has at least heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate may be used as the substrate 102. Furthermore, any of these substrates on which semiconductor elements are provided may also be used as the substrate 102. The shape of the semiconductor substrate and the insulating substrate may be circular or rectangular.

[0296] A flexible substrate may be used as the substrate 102, and the semiconductor device 100A or the like may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate 102 and the semiconductor device 100A or the like. The release layer can be used to separate a semiconductor device, after a part or all of the semiconductor device is completed thereon, from the substrate 102 and transfer it to another substrate. In this case, the semiconductor device 100A or the like can also be transferred to a substrate with poor heat resistance or a flexible substrate.

[0297] [Composition of Metal Oxide in Semiconductor Layer 108_1 and Semiconductor Layer 108_2] The composition of metal oxide in the semiconductor layer 108_1 and the semiconductor layer 108_2 will be described below.

[0298] The compositions of the metal oxides in the semiconductor layers 108_1 and 108_2 greatly affect the electrical characteristics and reliability of the transistors 10A1_1 and 10A1_2 and the transistors 10A2_1 and 10A2_2, respectively.

[0299] For example, by increasing the content of indium in the metal oxide, a transistor with a large on-state current can be realized.

[0300] When an In—Zn oxide is used for the semiconductor layers 108_1 and 108_2, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of zinc. For example, a metal oxide in which the atomic ratio of metal elements is In:Zn=1:1, In:Zn=2:1, In:Zn=3:1, In:Zn=4:1, In:Zn=5:1, In:Zn=7:1, or In:Zn=10:1, or a metal oxide in a range of these values, can be used.

[0301] When an In—Sn oxide is used for the semiconductor layers 108_1 and 108_2, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of tin. For example, a metal oxide in which the atomic ratio of metal elements is In:Sn=1:1, In:Sn=2:1, In:Sn=3:1, In:Sn=4:1, In:Sn=5:1, In:Sn=7:1, or In:Sn=10:1, or a ratio close to these, can be used.

[0302] When the semiconductor layer 108_1 and the semiconductor layer 108_2 are made of In-M-Zn oxide, a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is higher than the atomic ratio of the element M can be used. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of the element M. For example, the semiconductor layer 108_1 and the semiconductor layer 108_2 may be made of metal oxides in which the atomic ratio of metal elements is In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=5:1:9, In:M:Zn=5:1:10, In:M:Zn=5:1:11, In:M:Zn=5:1:12, In:M:Zn=5:1:13, In:M:Zn=5:1:14, In:M:Zn=5:1:15, In:M:Zn=5:1:16, In:M:Zn=5:1:17, In:M:Zn=5:1:18, In:M:Zn=5:1:19 ... Metal oxides having a ratio of In:M:Zn=6:1:6, In:M:Zn=10:1:3, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, or metal oxides having a ratio close to these can be used.

[0303] In addition, when the element M has a plurality of metal elements, the sum of the atomic ratios of the metal elements can be taken as the atomic ratio of the element M. For example, in the case of an In-Ga-Al-Zn oxide having gallium and aluminum as the element M, the sum of the atomic ratio of gallium and the atomic ratio of aluminum can be taken as the atomic ratio of the element M. Furthermore, it is preferable that the atomic ratios of indium, the element M, and zinc are within the above-mentioned range. For example, in the case of an In-Ga-Sn-Zn oxide having gallium and tin as the element M, the sum of the atomic ratio of gallium and the atomic ratio of tin can be taken as the atomic ratio of the element M. Furthermore, it is preferable that the atomic ratios of indium, the element M, and zinc are within the above-mentioned range.

[0304] It is preferable to use a metal oxide in which the ratio of the number of indium atoms to the number of atoms of metal elements contained in the metal oxide is 30 atomic % to 100 atomic %, preferably 30 atomic % to 95 atomic %, more preferably 35 atomic % to 95 atomic %, more preferably 35 atomic % to 90 atomic %, more preferably 40 atomic % to 90 atomic %, more preferably 45 atomic % to 90 atomic %, more preferably 50 atomic % to 80 atomic %, more preferably 60 atomic % to 80 atomic %, and more preferably 70 atomic % to 80 atomic %. For example, when an In—Ga—Zn oxide is used for the semiconductor layer 108_1 and the semiconductor layer 108_2, the ratio of the number of indium atoms to the total number of indium, gallium, and zinc atoms is preferably in the above-mentioned range.

[0305] In this specification and the like, the ratio of the number of indium atoms to the number of atoms of the contained metal element may be referred to as the indium content. The same applies to other metal elements.

[0306] By increasing the indium content of the metal oxide, a transistor with a large on-state current can be obtained. By applying the transistor to a transistor that requires a large on-state current, a semiconductor device with excellent electrical characteristics can be obtained.

[0307] The composition of a metal oxide can be analyzed using, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques may be used for analysis. Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, or quantification may be difficult, or element M may not be detected.

[0308] In this specification, a "nearby composition" includes a range of ±30% of the desired atomic ratio. For example, when an atomic ratio is described as In:M:Zn = 4:2:3 or a composition near there, this includes a case where, when the atomic ratio of indium is 4, the atomic ratio of M is 1 to 3 and the atomic ratio of zinc is 2 to 4. Furthermore, when an atomic ratio is described as In:M:Zn = 5:1:6 or a composition near there, this includes a case where, when the atomic ratio of indium is 5, the atomic ratio of M is greater than 0.1 and less than 2 and the atomic ratio of zinc is greater than 5 and less than 7. Furthermore, when an atomic ratio is described as In:M:Zn = 1:1:1 or a composition near there, this includes a case where, when the atomic ratio of indium is 1, the atomic ratio of M is greater than 0.1 and less than 2 and the atomic ratio of zinc is greater than 0.1 and less than 2.

[0309] Here, the reliability of a transistor will be described. One of the indicators for evaluating the reliability of a transistor is a Gate Bias Temperature (GBT) stress test, in which a transistor is held at a high temperature while an electric field is applied to the gate. Among these, a test in which a positive potential (positive bias) is applied to the gate relative to the source potential and the drain potential while the transistor is held at a high temperature is called a Positive Bias Temperature (PBTS) test, and a test in which a negative potential (negative bias) is applied to the gate while the transistor is held at a high temperature is called a Negative Bias Temperature (NBTS) test. The PBTS test and the NBTS test performed under light irradiation are called a PBTIS (Positive Bias Temperature Illumination Stress) test and an NBTIS (Negative Bias Temperature Illumination Stress) test, respectively.

[0310] In an n-channel transistor, a positive potential is applied to the gate when the transistor is turned on (a state in which current flows). Therefore, the amount of change in threshold voltage in the PBTS test is one of the important items to be noted as an index of the reliability of the transistor.

[0311] By using a metal oxide that does not contain gallium or has a low gallium content for the semiconductor layer 108_1 and the semiconductor layer 108_2, a transistor with high reliability against positive bias application can be obtained. That is, a transistor with a small amount of fluctuation in threshold voltage in a PBTS test can be obtained. Furthermore, when a metal oxide containing gallium is used, it is preferable to make the gallium content lower than the indium content. This makes it possible to realize a highly reliable transistor.

[0312] One factor that causes the threshold voltage to fluctuate in the PBTS test is carrier trapping into defect levels at or near the interface between the semiconductor layer and the gate insulating layer. The greater the defect level density, the greater the number of carriers trapped in the defect levels, resulting in significant degradation in the PBTS test. By reducing the gallium content in the region of the semiconductor layer that contacts the gate insulating layer, the generation of the defect levels can be suppressed.

[0313] The following is a possible reason why using a metal oxide containing no gallium or with a low gallium content for the semiconductor layer can suppress fluctuations in threshold voltage in the PBTS test. Gallium contained in the metal oxide has the property of attracting oxygen more easily than other metal elements (e.g., indium or zinc). Therefore, it is presumed that gallium combines with excess oxygen in the gate insulating layer at the interface between the gallium-rich metal oxide and the gate insulating layer, making it easier to generate carrier (here, electron) trap sites. Therefore, when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, which is thought to cause fluctuations in threshold voltage.

[0314] More specifically, when In—Ga—Zn oxide is used for the semiconductor layers 108_1 and 108_2, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of gallium can be used for the semiconductor layers 108_1 and 108_2. It is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium. In other words, it is preferable to use a metal oxide in which the atomic ratios of metal elements satisfy In>Ga and Zn>Ga for the semiconductor layers 108_1 and 108_2.

[0315] For the semiconductor layer 108_1 and the semiconductor layer 108_2, it is preferable to use a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal element is more than 0 atomic % and 50 atomic % or less, preferably 0.1 atomic % to 40 atomic % or less, more preferably 0.1 atomic % to 35 atomic % or less, more preferably 0.1 atomic % to 30 atomic % or less, more preferably 0.1 atomic % to 25 atomic % or less, more preferably 0.1 atomic % to 20 atomic % or less, more preferably 0.1 atomic % to 15 atomic % or less, and more preferably 0.1 atomic % to 10 atomic % or less. By reducing the gallium content in the semiconductor layer, a transistor with high resistance to the PBTS test can be obtained. Note that by including gallium in the metal oxide, oxygen deficiency (V Ｏ ) is less likely to occur.

[0316] A metal oxide that does not contain gallium may be used for the semiconductor layer 108_1 and the semiconductor layer 108_2. For example, In—Zn oxide may be used for the semiconductor layer 108_1 and the semiconductor layer 108_2. In this case, increasing the atomic ratio of indium to the atomic number of metal elements contained in the metal oxide can increase the field-effect mobility of the transistor. On the other hand, increasing the atomic ratio of zinc to the atomic number of metal elements contained in the metal oxide can result in a metal oxide with high crystallinity, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving reliability. Furthermore, a metal oxide that does not contain gallium or zinc, such as indium oxide, may be used for the semiconductor layer 108_1 and the semiconductor layer 108_2. Using a metal oxide that does not contain gallium can significantly reduce fluctuations in threshold voltage, particularly in a PBTS test.

[0317] For example, an oxide containing indium and zinc can be used for the semiconductor layer 108_1 and the semiconductor layer 108_2. In this case, a metal oxide having an atomic ratio of metal elements of In:Zn=2:3 or a ratio close thereto can be used.

[0318] Although gallium has been used as a representative example, the present invention can also be applied to a case where the element M is used instead of gallium. For the semiconductor layers 108_1 and 108_2, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of the element M is preferably used. Also, a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of the element M is preferably used.

[0319] By using a metal oxide having a low content of the element M for the semiconductor layers 108_1 and 108_2, a transistor having high reliability when a positive bias is applied can be obtained. By using the transistor as a transistor that is required to have high reliability when a positive bias is applied, a highly reliable semiconductor device can be obtained.

[0320] Next, the reliability of the transistor against light will be described.

[0321] Light incident on a transistor may cause fluctuations in the electrical characteristics of the transistor. In particular, it is preferable that a transistor applied to a region where light may be incident exhibits small fluctuations in electrical characteristics under light irradiation and has high reliability against light. The reliability against light can be evaluated, for example, by the amount of fluctuation in threshold voltage in an NBTIS test.

[0322] Increasing the content of the element M in the metal oxide can provide a transistor with high reliability against light. That is, a transistor with a small variation in threshold voltage in an NBTIS test can be provided. Specifically, a metal oxide in which the atomic ratio of the element M is equal to or greater than the atomic ratio of indium has a larger band gap, and can reduce the variation in threshold voltage of the transistor in an NBTIS test. The band gap of the metal oxide included in the semiconductor layer 108_1 and the semiconductor layer 108_2 is preferably 2.0 eV or more, more preferably 2.5 eV or more, further preferably 3.0 eV or more, further preferably 3.2 eV or more, further preferably 3.3 eV or more, further preferably 3.4 eV or more, and further preferably 3.5 eV or more.

[0323] For example, the semiconductor layer 108_1 and the semiconductor layer 108_2 can be made of metal oxides having an atomic ratio of metal elements of In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Zn=1:3:3, or In:M:Zn=1:3:4, or metal oxides having an atomic ratio of these metal elements.

[0324] For the semiconductor layer 108_1 and the semiconductor layer 108_2, a metal oxide in which the ratio of the number of atoms of the element M to the number of atoms of the contained metal element is 20 atomic % to 70 atomic %, preferably 30 atomic % to 70 atomic %, more preferably 30 atomic % to 60 atomic %, more preferably 40 atomic % to 60 atomic %, and more preferably 50 atomic % to 60 atomic % can be suitably used.

[0325] When the semiconductor layer 108_1 and the semiconductor layer 108_2 are made of In—Ga—Zn oxide, a metal oxide having an atomic ratio of indium to gallium equal to or less than that of gallium can be used. For example, a metal oxide having an atomic ratio of metal elements of In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:1.2, In:Ga:Zn=1:3:2, In:Ga:Zn=1:3:3, or In:Ga:Zn=1:3:4, or a ratio thereof close to these, can be used.

[0326] For the semiconductor layer 108_1 and the semiconductor layer 108_2, a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal element is 20 atomic % or more and 60 atomic % or less, preferably 30 atomic % or more and 60 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, and more preferably 50 atomic % or more and 60 atomic % or less can be suitably used.

[0327] By using a metal oxide having a high content of element M for the semiconductor layers 108_1 and 108_2, a transistor with high reliability against light can be obtained. By using the transistor as a transistor that is required to have high reliability against light, a highly reliable semiconductor device can be obtained.

[0328] As described above, the electrical characteristics and reliability of a transistor differ depending on the composition of the metal oxide used for the semiconductor layer 108_1 and the semiconductor layer 108_2. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0329] The semiconductor layer 108_1 and the semiconductor layer 108_2 may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 108_1 and the semiconductor layer 108_2 may have the same or approximately the same composition. By using a stacked structure of metal oxide layers having the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs.

[0330] The two or more metal oxide layers included in the semiconductor layer 108_1 and the semiconductor layer 108_2 may have different compositions. For example, a stacked structure of a first metal oxide layer having an atomic ratio of In:M:Zn=1:3:4 or a composition similar thereto and a second metal oxide layer having an atomic ratio of In:M:Zn=1:1:1 or a composition similar thereto provided on the first metal oxide layer can be preferably used. Furthermore, it is particularly preferable to use gallium or aluminum as the element M. For example, a stacked structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and indium tin zinc oxide (In—Sn—Zn oxide, also referred to as ITZO (registered trademark)) can be used.

[0331] As described above, the semiconductor device 100A includes four transistors (transistor 10A1_1, transistor 10A1_2, transistor 10A2_1, and transistor 10A2_2), which share some components with one another. Specifically, the semiconductor layer 108_1 and the conductive layer 104_1 are shared between the transistors 10A1_1 and 10A1_2. The semiconductor layer 108_2 and the conductive layer 104_2 are shared between the transistors 10A2_1 and 10A2_2. The conductive layer 112c is shared between the transistors 10A1_2 and 10A2_2. The conductive layer 112b and the insulating layer 106 are shared among the four transistors. FIG. 15B shows a circuit diagram illustrating the connections among the four transistors.

[0332] 15B , the other of the source or the drain of transistor 10A1_1 provided in the first layer of switch 100A1 is connected to one of the source or the drain of transistor 10A1_2 provided in the second layer. The other of the source or the drain of transistor 10A2_1 provided in the first layer of switch 100A2 is connected to one of the source or the drain of transistor 10A2_2 provided in the second layer. These two connection points (which may also be referred to as nodes) are connected to each other by conductive layer 112b.

[0333] The gates of the transistors 10A1_1 and 10A1_2 are connected to each other and led to the outside as a single wiring (here, a conductive layer 104_1). The gates of the transistors 10A2_1 and 10A2_2 are connected to each other and led to the outside as a single wiring (here, a conductive layer 104_2).

[0334] One of the source and drain of the transistor 10A1_1 is led to the outside by a wiring represented as a conductive layer 112a1. One of the source and drain of the transistor 10A2_1 is led to the outside by a wiring represented as a conductive layer 112a2. The other of the source and drain of the transistor 10A1_2 and the other of the source and drain of the transistor 10A2_2 are connected and led to the outside by a wiring represented as a conductive layer 112c.

[0335] 14A to 15B, the switch 100A1 corresponds to, for example, the switch SW1 of the semiconductor device shown in FIG. 1 and FIGS. 3A to 5B, and the switch 100A2 corresponds to the switch DSW1 of the semiconductor device. In this case, the transistor 10A1_1 in the switch 100A1 corresponds to the transistor M2 in the switch SW1, and the transistor 10A1_2 in the switch 100A1 corresponds to the transistor M1 in the switch SW1. Furthermore, the transistor 10A2_1 in the switch 100A2 corresponds to the transistor DM2 in the switch DSW1, and the transistor 10A2_2 in the switch 100A2 corresponds to the transistor DM1 in the switch DSW1. Note that a configuration in which the switch 100A2 corresponds to the switch SW1 and the switch 100A1 corresponds to the switch DSW1 may also be used.

[0336] 1 and 3A to 5B, the switch 100A1 corresponds to the switch SW2 of the semiconductor device shown in FIG. 1 and 3A to 5B, and the switch 100A2 corresponds to the switch DSW2 of the semiconductor device. In this case, the transistor 10A1_1 in the switch 100A1 corresponds to the transistor M3 in the switch SW2, and the transistor 10A1_2 in the switch 100A1 corresponds to the transistor M4 in the switch SW2. The transistor 10A2_1 in the switch 100A2 corresponds to the transistor DM3 in the switch DSW2, and the transistor 10A2_2 in the switch 100A2 corresponds to the transistor DM4 in the switch DSW2. Note that a configuration in which the switch 100A2 corresponds to the switch SW2 and the switch 100A1 corresponds to the switch DSW2 may also be used.

[0337] 16A and 16B show a configuration example of a semiconductor device 100B having a different configuration from the semiconductor device 100A shown in FIGS. 14A to 15B. Fig. 16A is a plan view of the semiconductor device 100B. Fig. 16B is a cross-sectional view corresponding to the dashed dotted line A1-A2 in the plan view of the semiconductor device 100B shown in Fig. 16A.

[0338] In the following, differences from the semiconductor device 100A described above will be mainly described, and descriptions of parts that overlap with the semiconductor device 100A may be omitted.

[0339] The semiconductor device 100B includes a switch 100B1, a switch 100B2, and insulating layers 110_1 and 110_2. The switch 100B1 includes transistors 10B1_1 and 10B1_2. The switch 100B2 includes transistors 10B2_1 and 10B2_2. The transistors 10B1_1 and 10B1_2 share some components and are overlapped in this order. The transistors 10B2_1 and 10B2_2 share some components and are overlapped in this order.

[0340] The switches 100B1 and 100B2 in the semiconductor device 100B correspond to the switches 100A1 and 100A2 in the semiconductor device 100A, respectively.

[0341] The semiconductor device 100B differs from the semiconductor device 100A in that the transistors 10B1_1 and 10B2_1, which are located in the first layer of the switch 100B1 and the switch 100B2, respectively, share a conductive layer (conductive layer 112a) that functions as one of the source and drain electrodes. The semiconductor device 100B also differs from the semiconductor device 100A in that the transistors 10B1_2, which are located in the second layer of the switch 100B1, and the transistor 10B2_2, which are located in the second layer of the switch 100B2, each share separate conductive layers (conductive layer 112c1 and conductive layer 112c2) that function as the other of the source and drain electrodes.

[0342] That is, in the semiconductor device 100B, the conductive layer 112a, the insulating layer 110_1, the conductive layer 112b, and the insulating layer 110_2 are provided in overlapping order, and the conductive layer 112c1 and the conductive layer 112c2 are provided in different regions over the insulating layer 110_2.

[0343] An opening 143_1 reaching the conductive layer 112a is provided in the insulating layer 110_1, the conductive layer 112b, the insulating layer 110_2, and the conductive layer 112c1, and an opening 143_2 reaching the conductive layer 112a is provided in the insulating layer 110_1, the conductive layer 112b, the insulating layer 110_2, and the conductive layer 112c2.

[0344] The semiconductor layer 108_1 is provided in contact with the top surface of the conductive layer 112a in the opening 143_1, the side surface of the insulating layer 110_1 in the opening 143_1, the side surface of the conductive layer 112b in the opening 143_1, the side surface of the insulating layer 110_2 in the opening 143_1, the side surface of the conductive layer 112c1 in the opening 143_1, and the top surface of the conductive layer 112c1. The semiconductor layer 108_2 is provided in contact with the top surface of the conductive layer 112a in the opening 143_2, the side surface of the insulating layer 110_1 in the opening 143_2, the side surface of the conductive layer 112b in the opening 143_2, the side surface of the insulating layer 110_2 in the opening 143_2, the side surface of the conductive layer 112c2 in the opening 143_2, and the top surface of the conductive layer 112c2.

[0345] An insulating layer 106 is provided over the semiconductor layer 108_1 and the semiconductor layer 108_2. The insulating layer 106 has a region in contact with the top surface and side surfaces of the semiconductor layer 108_1, the top surface and side surfaces of the semiconductor layer 108_2, the top surface and side surfaces of the conductive layer 112c1, the top surface and side surfaces of the conductive layer 112c2, and the top surface of the insulating layer 110c2.

[0346] A conductive layer 104_1 and a conductive layer 104_2 are provided over the insulating layer 106. The conductive layer 104_1 is provided in contact with the top surface of the insulating layer 106 so as to have a region overlapping with the opening 143_1 in a plan view. The conductive layer 104_2 is provided in contact with the top surface of the insulating layer 106 so as to have a region overlapping with the opening 143_2 in a plan view.

[0347] In the semiconductor device 100B, it can be said that the transistor 10B1_1 in the first layer of the switch 100B1 corresponds to the transistor 10A1_2 in the second layer of the switch 100A1 in the semiconductor device 100A, and the transistor 10B1_2 in the second layer of the switch 100B1 corresponds to the transistor 10A1_1 in the first layer of the switch 100A1 in the semiconductor device 100A. It can also be said that the transistor 10B2_1 in the first layer of the switch 100B2 corresponds to the transistor 10A2_2 in the second layer of the switch 100A2 in the semiconductor device 100A, and the transistor 10B2_2 in the second layer of the switch 100B2 corresponds to the transistor 10A2_1 in the first layer of the switch 100A2 in the semiconductor device 100A.

[0348] As described above, in the semiconductor device of one embodiment of the present invention, the conductive layer shared between the two switches can be formed above the insulating layer 110_2 as in the semiconductor device 100A, or can be formed below the insulating layer 110_1 as in the semiconductor device 100B. This increases the degree of freedom in manufacturing the semiconductor device.

[0349] With respect to the semiconductor device 100B, the contents described for the semiconductor device 100A can be referred to for other aspects than those described above.

[0350] <Configuration Example 3 of Semiconductor Device> Figures 17 to 19 show a configuration example of a semiconductor device 100C having a different configuration from the semiconductor device 100A shown in Figures 14A to 15B. Figure 17 is a cross-sectional view of the semiconductor device 100C corresponding to the dashed-dotted line A1-A2 in the plan view of the semiconductor device 100A shown in Figure 14A. Figure 18 is a cross-sectional view of the semiconductor device 100C corresponding to the dashed-dotted line B1-B2 in the plan view of the semiconductor device 100A shown in Figure 14A. Figure 19 is a circuit diagram illustrating the configuration of the semiconductor device 100C.

[0351] The semiconductor device 100C includes a switch 100C1, a switch 100C2, an insulating layer 110_1, an insulating layer 110_2, an insulating layer 110_3 (insulating layer 110a3, insulating layer 110b3, and insulating layer 110c3), and an insulating layer 110_4 (insulating layer 110a4, insulating layer 110b4, and insulating layer 110c4). The switch 100C1 includes a transistor 10C1_1, a transistor 10C1_2, a transistor 10C1_3, and a transistor 10C1_4. The switch 100C2 includes a transistor 10C2_1, a transistor 10C2_2, a transistor 10C2_3, and a transistor 10C2_4. The semiconductor device 100C differs from the semiconductor device 100A in that the number of stacked vertical transistors that share some components is four.

[0352] The transistors 10C1_1, 10C1_2, 10C1_3, and 10C1_4 share some components and are overlapped in this order. The transistors 10C2_1, 10C2_2, 10C2_3, and 10C2_4 share some components and are overlapped in this order.

[0353] That is, in the semiconductor device 100C, a transistor 10C1_1 is provided in the first layer of the switch 100C1, a transistor 10C1_2 is provided in the second layer, a transistor 10C1_3 is provided in the third layer, and a transistor 10C1_4 is provided in the fourth layer. Also, a transistor 10C2_1 is provided in the first layer of the switch 100C2, a transistor 10C2_2 is provided in the second layer, a transistor 10C2_3 is provided in the third layer, and a transistor 10C2_4 is provided in the fourth layer.

[0354] The transistor 10C1_1 includes a conductive layer 104_1, an insulating layer 106, a semiconductor layer 108_1, a conductive layer 112a1, and a conductive layer 112b. The transistor 10C1_2 includes a conductive layer 104_1, an insulating layer 106, a semiconductor layer 108_1, a conductive layer 112b, and a conductive layer 112c. The transistor 10C1_3 includes a conductive layer 104_1, an insulating layer 106, a semiconductor layer 108_1, a conductive layer 112c, and a conductive layer 112d. The transistor 10C1_4 includes a conductive layer 104_1, an insulating layer 106, a semiconductor layer 108_1, a conductive layer 112d, and a conductive layer 112e.

[0355] In the transistor 10C1_1, part of the conductive layer 104_1 functions as a gate electrode. Part of the insulating layer 106 functions as a gate insulating layer. The conductive layer 112a1 functions as one of a source electrode and a drain electrode. The conductive layer 112b functions as the other of the source electrode and the drain electrode. In the semiconductor layer 108_1, an entire region that overlaps with the gate electrode with the gate insulating layer interposed therebetween functions as a channel formation region. In addition, in the semiconductor layer 108_1, a region in contact with the source electrode functions as a source region, and a region in contact with the drain electrode functions as a drain region.

[0356] In the transistor 10C1_2, part of the conductive layer 104_1 (part other than that of the transistor 10C1_1) functions as a gate electrode. Part of the insulating layer 106 (part other than that of the transistor 10C1_1) functions as a gate insulating layer. The conductive layer 112b functions as one of a source electrode and a drain electrode. The conductive layer 112c functions as the other of the source electrode and the drain electrode. In the semiconductor layer 108_1, the entire region that overlaps with the gate electrode with the gate insulating layer interposed therebetween functions as a channel formation region. In addition, in the semiconductor layer 108_1, a region in contact with the source electrode functions as a source region, and a region in contact with the drain electrode functions as a drain region.

[0357] In the transistor 10C1_3, part of the conductive layer 104_1 (part other than the transistors 10C1_1 and 10C1_2) functions as a gate electrode. Part of the insulating layer 106 (part other than the transistors 10C1_1 and 10C1_2) functions as a gate insulating layer. The conductive layer 112c functions as one of a source electrode and a drain electrode. The conductive layer 112d functions as the other of the source electrode and the drain electrode. In the semiconductor layer 108_1, an entire region that overlaps with the gate electrode with the gate insulating layer interposed therebetween functions as a channel formation region. In addition, a region of the semiconductor layer 108_1 that is in contact with the source electrode functions as a source region, and a region that is in contact with the drain electrode functions as a drain region.

[0358] In the transistor 10C1_4, part of the conductive layer 104_1 (part other than the transistors 10C1_1, 10C1_2, and 10C1_3) functions as a gate electrode. Part of the insulating layer 106 (part other than the transistors 10C1_1, 10C1_2, and 10C1_3) functions as a gate insulating layer. The conductive layer 112d functions as one of a source electrode and a drain electrode. The conductive layer 112e functions as the other of the source electrode and the drain electrode. In the semiconductor layer 108_1, an entire region that overlaps with the gate electrode with the gate insulating layer interposed therebetween functions as a channel formation region. In addition, a region of the semiconductor layer 108_1 that is in contact with the source electrode functions as a source region, and a region that is in contact with the drain electrode functions as a drain region.

[0359] That is, in the switch 100C1, the conductive layer 112b functions as the other of the source and drain electrodes of the transistor 10C1_1 and also functions as one of the source and drain electrodes of the transistor 10C1_2. The conductive layer 112c functions as the other of the source and drain electrodes of the transistor 10C1_2 and also functions as one of the source and drain electrodes of the transistor 10C1_3. The conductive layer 112d functions as the other of the source and drain electrodes of the transistor 10C1_3 and also functions as one of the source and drain electrodes of the transistor 10C1_4. The semiconductor layer 108_1 functions as a semiconductor layer having channel formation regions of the transistors 10C1_1 to 10C1_4. The insulating layer 106 functions as a gate insulating layer of the transistors 10C1_1 to 10C1_4. The conductive layer 104_1 functions as a gate electrode of the transistors 10C1_1 to 10C1_4.

[0360] The above description of switch 100C1 can also be applied to switch 100C2 by replacing transistor 10C1_1, transistor 10C1_2, transistor 10C1_3, transistor 10C1_4, conductive layer 104_1, semiconductor layer 108_1, and conductive layer 112a1 with transistor 10C2_1, transistor 10C2_2, transistor 10C2_3, transistor 10C2_4, conductive layer 104_2, semiconductor layer 108_2, and conductive layer 112a2, respectively.

[0361] In the semiconductor device 100C, the insulating layer 106, the conductive layer 112b, the conductive layer 112c, the conductive layer 112d, and the conductive layer 112e each function as components of the switch 100C1 and also function as components of the switch 100C2. That is, in the semiconductor device 100C, the switch 100C1 and the switch 100C2 can be said to share some components.

[0362] The insulating layer 110_1 is provided to include a region sandwiched between the source and drain electrodes of the transistor 10C1_1 and a region sandwiched between the source and drain electrodes of the transistor 10C2_1. The insulating layer 110_2 is provided to include a region sandwiched between the source and drain electrodes of the transistor 10C1_2 and a region sandwiched between the source and drain electrodes of the transistor 10C2_2. The insulating layer 110_3 is provided to include a region sandwiched between the source and drain electrodes of the transistor 10C1_3 and a region sandwiched between the source and drain electrodes of the transistor 10C2_3. The insulating layer 110_4 is provided to include a region sandwiched between the source and drain electrodes of the transistor 10C1_4 and a region sandwiched between the source and drain electrodes of the transistor 10C2_4.

[0363] Of the insulating layers constituting the insulating layer 110_3 and the insulating layer 110_4, the insulating layer 110a3, the insulating layer 110a4, the insulating layer 110c3, and the insulating layer 110c4 can refer to the descriptions of the insulating layer 110a1, the insulating layer 110a2, the insulating layer 110c1, and the insulating layer 110c2. Of the insulating layers constituting the insulating layer 110_3 and the insulating layer 110_4, the insulating layer 110b3 and the insulating layer 110b4 can refer to the descriptions of the insulating layer 110b1 and the insulating layer 110b2.

[0364] The conductive layer 112a1, the insulating layer 110_1, the conductive layer 112b, the insulating layer 110_2, the conductive layer 112c, the insulating layer 110_3, the conductive layer 112d, the insulating layer 110_4, and the conductive layer 112e have overlapping regions. The conductive layer 112a2, the insulating layer 110_1, the conductive layer 112b, the insulating layer 110_2, the conductive layer 112c, the insulating layer 110_3, the conductive layer 112d, the insulating layer 110_4, and the conductive layer 112e have overlapping regions. In FIG. 17 , the conductive layer 112e extends toward the A1 side of the dashed dotted line A1-A2.

[0365] The insulating layer 110_1, the conductive layer 112b, the insulating layer 110_2, the conductive layer 112c, the insulating layer 110_3, the conductive layer 112d, the insulating layer 110_4, and the conductive layer 112e have an opening 144_1 that reaches the conductive layer 112a1 in a region overlapping with the conductive layer 112a1, and an opening 144_2 that reaches the conductive layer 112a2 in a region overlapping with the conductive layer 112a2.

[0366] The semiconductor layer 108_1 is provided in contact with the top surface of the conductive layer 112a1 in the opening 144_1, the side surface of the insulating layer 110_1 in the opening 144_1, the side surface of the conductive layer 112b in the opening 144_1, the side surface of the insulating layer 110_2 in the opening 144_1, the side surface of the conductive layer 112c in the opening 144_1, the side surface of the insulating layer 110_3 in the opening 144_1, the side surface of the conductive layer 112d in the opening 144_1, the side surface of the insulating layer 110_4 in the opening 144_1, the side surface of the conductive layer 112e in the opening 144_1, and the top surface of the conductive layer 112e. In addition, the semiconductor layer 108_2 is provided in contact with the top surface of the conductive layer 112a2 in the opening 144_2, the side surface of the insulating layer 110_1 in the opening 144_2, the side surface of the conductive layer 112b in the opening 144_2, the side surface of the insulating layer 110_2 in the opening 144_2, the side surface of the conductive layer 112c in the opening 144_2, the side surface of the insulating layer 110_3 in the opening 144_2, the side surface of the conductive layer 112d in the opening 144_2, the side surface of the insulating layer 110_4 in the opening 144_2, the side surface of the conductive layer 112e in the opening 144_2, and the top surface of the conductive layer 112e.

[0367] An insulating layer 106 is provided over the semiconductor layer 108_1 and the semiconductor layer 108_2. The insulating layer 106 has a region in contact with the top surface and side surfaces of the semiconductor layer 108_1, the top surface and side surfaces of the semiconductor layer 108_2, the top surface and side surfaces of the conductive layer 112e, and the top surface of the insulating layer 110c4.

[0368] A conductive layer 104_1 and a conductive layer 104_2 are provided over the insulating layer 106. The conductive layer 104_1 is provided in contact with the top surface of the insulating layer 106 so as to have a region overlapping with the opening 144_1 in a plan view. The conductive layer 104_2 is provided in contact with the top surface of the insulating layer 106 so as to have a region overlapping with the opening 144_2 in a plan view.

[0369] 18 shows a configuration in which the conductive layer 104_1 extends to the B2 side of the dashed dotted line B1-B2. The conductive layer 104_1 has a shape that conforms to the shapes of the semiconductor layer 108_1 and the insulating layer 106 within the opening 144_1. That is, the conductive layer 104_1 has a recessed portion on its upper surface that corresponds to the shape of the opening 144_1. The conductive layer 104_1 has a region that faces the semiconductor layer 108_1 with the insulating layer 106 interposed therebetween within the opening 144_1.

[0370] The above description of the conductive layer 104_1 can also be applied to the conductive layer 104_2 by replacing the opening 144_1 with the opening 144_2 and the semiconductor layer 108_1 with the semiconductor layer 108_2.

[0371] 18, the channel length L1 of the transistor 10C1_1, the channel length L2 of the transistor 10C1_2, the channel length L3 of the transistor 10C1_3, and the channel length L4 of the transistor 10C1_4 are indicated by dashed double arrows. 18 , the channel width W1 of the transistor 10C1_1, the channel width W2 of the transistor 10C1_2, the channel width W3 of the transistor 10C1_3, and the channel width W4 of the transistor 10C1_4 are each indicated by a double-headed dashed arrow. Also, in FIG. 18 , the width D144 of the opening 144_1 is indicated by a double-headed dashed arrow. Also, in FIG. 18 , the angle between the surface where the semiconductor layer 108_1 is to be formed (here, the side surface of the insulating layer 110_1) and the surface where the insulating layer 110_1 is to be formed (here, the top surface of the conductive layer 112a1) is indicated as angle θ144.

[0372] As described above, the semiconductor device 100C includes eight transistors (transistor 10C1_1, transistor 10C1_2, transistor 10C1_3, transistor 10C1_4, transistor 10C2_1, transistor 10C2_2, transistor 10C2_3, and transistor 10C2_4), which share some components with one another. Specifically, the semiconductor layer 108_1 and the conductive layer 104_1 are shared by the transistors 10C1_1, 10C1_2, 10C1_3, and 10C1_4. The semiconductor layer 108_2 and the conductive layer 104_2 are shared by the transistors 10C2_1, 10C2_2, 10C2_3, and 10C2_4. The conductive layer 112b is shared by the transistor 10C1_1, the transistor 10C1_2, the transistor 10C2_1, and the transistor 10C2_2. The conductive layer 112c is shared by the transistor 10C1_2, the transistor 10C1_3, the transistor 10C2_2, and the transistor 10C2_3. The conductive layer 112d is shared by the transistor 10C1_3, the transistor 10C1_4, the transistor 10C2_3, and the transistor 10C2_4. The conductive layer 112e is shared by the transistor 10C1_4 and the transistor 10C2_4. The insulating layer 106 is shared by the eight transistors. FIG. 19 shows a circuit diagram illustrating the connections among the eight transistors.

[0373] 19 , the other of the source or the drain of a transistor 10C1_1 provided in the first layer of the switch 100C1 is connected to one of the source or the drain of a transistor 10C1_2 provided in the second layer. The other of the source or the drain of a transistor 10C2_1 provided in the first layer of the switch 100C2 is connected to one of the source or the drain of a transistor 10C2_2 provided in the second layer. These two connection points are connected to each other by a conductive layer 112b.

[0374] The other of the source or the drain of transistor 10C1_2 provided in the second layer of switch 100C1 is connected to one of the source or the drain of transistor 10C1_3 provided in the third layer. The other of the source or the drain of transistor 10C2_2 provided in the second layer of switch 100C2 is connected to one of the source or the drain of transistor 10C2_3 provided in the third layer. The two connection points are connected to each other by conductive layer 112c.

[0375] The other of the source or the drain of transistor 10C1_3 provided in the third layer of switch 100C1 is connected to one of the source or the drain of transistor 10C1_4 provided in the fourth layer. The other of the source or the drain of transistor 10C2_3 provided in the third layer of switch 100C2 is connected to one of the source or the drain of transistor 10C2_4 provided in the fourth layer. The two connection points are connected to each other by conductive layer 112d.

[0376] The gates of the transistors 10C1_1, 10C1_2, 10C1_3, and 10C1_4 are connected to each other and led to the outside as a single wiring (here, a conductive layer 104_1). The gates of the transistors 10C2_1, 10C2_2, 10C2_3, and 10C2_4 are connected to each other and led to the outside as a single wiring (here, a conductive layer 104_2).

[0377] One of the source and drain of the transistor 10C1_1 is led to the outside by a wiring represented as a conductive layer 112a1. One of the source and drain of the transistor 10C2_1 is led to the outside by a wiring represented as a conductive layer 112a2.

[0378] 17 to 19, switch 100C1 corresponds to, for example, switch SW1 of the semiconductor device shown in FIGS. 6 to 11, and switch 100C2 corresponds to switch DSW1 of the semiconductor device. In this case, transistor 10C1_1 in switch 100C1 corresponds to transistor M6 in switch SW1, transistor 10C1_2 in switch 100C1 corresponds to transistor M5 in switch SW1, transistor 10C1_3 in switch 100C1 corresponds to transistor M2 in switch SW1, and transistor 10C1_4 in switch 100C1 corresponds to transistor M1 in switch SW1. Furthermore, transistor 10C2_1 in switch 100C2 corresponds to transistor DM6 in switch DSW1, transistor 10C2_2 in switch 100C2 corresponds to transistor DM5 in switch DSW1, transistor 10C2_3 in switch 100C2 corresponds to transistor DM2 in switch DSW1, and transistor 10C2_4 in switch 100C2 corresponds to transistor DM1 in switch DSW1. Note that a configuration in which switch 100C2 corresponds to switch SW1 and switch 100C1 corresponds to switch DSW1 may also be used.

[0379] 6 to 11, the switch 100C1 corresponds to the switch SW2 of the semiconductor device shown in FIG. 6 to 11, and the switch 100C2 corresponds to the switch DSW2 of the semiconductor device. In this case, the transistor 10C1_1 in the switch 100C1 corresponds to the transistor M3 in the switch SW2, the transistor 10C1_2 in the switch 100C1 corresponds to the transistor M4 in the switch SW2, the transistor 10C1_3 in the switch 100C1 corresponds to the transistor M7 in the switch SW2, and the transistor 10C1_4 in the switch 100C1 corresponds to the transistor M8 in the switch SW2. Furthermore, transistor 10C2_1 in switch 100C2 corresponds to transistor DM3 in switch DSW2, transistor 10C2_2 in switch 100C2 corresponds to transistor DM4 in switch DSW2, transistor 10C2_3 in switch 100C2 corresponds to transistor DM7 in switch DSW2, and transistor 10C2_4 in switch 100C2 corresponds to transistor DM8 in switch DSW2. Note that a configuration in which switch 100C2 corresponds to switch SW2 and switch 100C1 corresponds to switch DSW2 may also be used.

[0380] 20A shows a configuration example of a semiconductor device 100D having a different configuration from the semiconductor device 100A shown in FIGS. 14A to 15B. Fig. 20A is a cross-sectional view of the semiconductor device 100D corresponding to the dashed dotted line B1-B2 in the plan view of the semiconductor device 100A shown in Fig. 14A.

[0381] In the following, differences from the semiconductor device 100A described above will be mainly described, and descriptions of parts that overlap with the semiconductor device 100A may be omitted.

[0382] The semiconductor device 100D includes a switch 100D1, a switch 100D2 (not shown), and insulating layers 110_1 and 110_2. The switch 100D1 includes a transistor 10D1_1 and a transistor 10D1_2. The switch 100D2 includes a transistor 10D2_1 (not shown) and a transistor 10D2_2 (not shown).

[0383] The switches 100D1 and 100D2 in the semiconductor device 100D correspond to the switches 100A1 and 100A2 in the semiconductor device 100A, respectively. That is, the transistors 10D1_1, 10D1_2, 10D2_1, and 10D2_2 in the semiconductor device 100D correspond to the transistors 10A1_1, 10A1_2, 10A2_1, and 10A2_2 in the semiconductor device 100A, respectively.

[0384] Note that the following description will be focused on transistors 10D1_1 and 10D1_2 that constitute switch 100D1 in semiconductor device 100D, but the following description can also be applied to transistors 10D2_1 and 10D2_2 that constitute switch 100D2 by appropriately replacing the corresponding components.

[0385] The semiconductor device 100D differs from the semiconductor device 100A in that an insulating layer 195 is provided so as to fill a recess formed on the semiconductor layer 108_1, the insulating layer 106, and the conductive layer 104_1 formed in the opening 143_1.

[0386] The insulating layer 195 is provided on the conductive layer 104_1 so as to have a region overlapping with the opening 143_1. The upper surface of the insulating layer 195 preferably has a substantially flat shape. This reduces large steps, such as the recesses described above, that exist in the semiconductor device 100D. FIG. 20A illustrates a configuration in which the height of the upper surface of the insulating layer 195 and the height of the highest region of the conductive layer 104_1 as viewed from the substrate surface are substantially equal. By providing the insulating layer 195, the surface on which a layer to be provided on the semiconductor device 100D is to be formed can be substantially flat, thereby improving the coverage of the layer. Note that while FIG. 20A illustrates an example in which the upper surface of the insulating layer 195 has a substantially flat shape, this is not limiting. The upper surface of the insulating layer 195 may also have a convex surface, a convex curved surface, a concave surface, a concave curved surface, or an uneven shape. The height of the upper surface of the insulating layer 195 may be higher or lower than the height of the highest region of the conductive layer 104_1 as viewed from the substrate surface. Even in this case, it is preferable to have the insulating layer 195 because the influence of the recesses formed on the conductive layer 104_1 (such as the coverage of the layer formed on the conductive layer 104_1) can be reduced compared to when the insulating layer 195 is not provided.

[0387] Note that the insulating layer 195 may be provided not only inside the opening 143_1 but also outside the opening 143_1. For example, the insulating layer 195 may also be provided on the insulating layer 106 outside the opening 143_1. In this case, it is preferable that the height of the top surface of the insulating layer 195 located inside the opening 143_1 and the height of the top surface of the insulating layer 195 located outside the opening 143_1 are approximately the same. Alternatively, the entire top surface of the semiconductor device 100D may be covered with the insulating layer 195, and the height of the top surface of the insulating layer 195 may be approximately flat.

[0388] An organic insulating material or an inorganic insulating material, or both, can be used for the insulating layer 195. An organic insulating material is preferably used for the insulating layer 195. For example, by using an organic insulating material for the insulating layer 195, a film with excellent flatness can be easily formed at a relatively low temperature on a formation surface having steps.

[0389] Specific examples of organic insulating materials that can be used for the insulating layer 195 include acrylic resins, polyimide resins, epoxy resins, polyamide resins, polyimideamide resins, siloxane resins, benzocyclobutene-based resins, phenolic resins, and precursors of these resins. Photosensitive materials may also be used as the organic insulating material. Here, photosensitivity refers to the property of being sensitive to ultraviolet light, far ultraviolet light, electron beams, X-rays, and the like. This property is utilized to form a resist pattern by exposure. For exposure of silicon-containing resists, ultraviolet light, and more preferably far ultraviolet light, is primarily used. The raw material monomer used here is preferably aromatic, but to increase sensitivity, it is more desirable for it to have a structure that does not contain an aromatic ring. For example, polyimide resin is preferably used for the insulating layer 195.

[0390] An inorganic insulating material can also be used for the insulating layer 195. Specific examples of the inorganic insulating material that can be used for the insulating layer 195 include the inorganic insulating materials that can be used for the insulating layer 110_1 and the insulating layer 110_2. For example, the insulating layer 195 is preferably made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like.

[0391] With respect to the semiconductor device 100D, the contents described for the semiconductor device 100A can be referred to for other aspects.

[0392] <Configuration Example 5 of Semiconductor Device> Fig. 20B shows a configuration example of a semiconductor device 100E having a different configuration from the semiconductor device 100A shown in Fig. 14A to Fig. 15B. Fig. 20B is a cross-sectional view of the semiconductor device 100E corresponding to the dashed dotted line B1-B2 in the plan view of the semiconductor device 100A shown in Fig. 14A.

[0393] The semiconductor device 100E includes a switch 100E1, a switch 100E2 (not shown), and insulating layers 110_1 and 110_2. The switch 100E1 includes transistors 10E1_1 and 10E1_2. The switch 100E2 includes transistors 10E2_1 and 10E2_2 (not shown).

[0394] The switches 100E1 and 100E2 in the semiconductor device 100E correspond to the switches 100A1 and 100A2 in the semiconductor device 100A, respectively. That is, the transistors 10E1_1, 10E1_2, 10E2_1, and 10E2_2 in the semiconductor device 100E correspond to the transistors 10A1_1, 10A1_2, 10A2_1, and 10A2_2 in the semiconductor device 100A, respectively.

[0395] In the following, the semiconductor device 100E will be described focusing on the transistors 10E1_1 and 10E1_2 that constitute the switch 100E1. However, the following description can also be applied to the transistors 10E2_1 and 10E2_2 that constitute the switch 100E2 by appropriately replacing the corresponding components.

[0396] The semiconductor device 100E differs from the semiconductor device 100A in the shape of the conductive layer 104_1.

[0397] Specifically, in the semiconductor device 100A, the conductive layer 104_1 has a shape that reflects the shape of the opening 143_1, whereas in the semiconductor device 100E, a part of the conductive layer 104_1 is provided to fill the opening 143_1, and another part of the conductive layer 104_1 is located outside the opening 143_1. The height of the top surface of the conductive layer 104_1 is higher than the height of the top surface of the semiconductor layer 108_1. Furthermore, the top surface of the conductive layer 104_1 has a substantially flat shape. This allows recesses formed on the semiconductor layer 108_1 and the insulating layer 106 formed in the opening 143_1 to be filled. Therefore, the formation surfaces of layers provided on the semiconductor device 100E can be made substantially flat, thereby improving the coverage of the layers.

[0398] Note that the top surface of the conductive layer 104_1 in the opening 143_1 is preferably located at a height at least half the depth of the opening 143_1 when viewed from the top surface of the conductive layer 112a1. For example, the top surface of the conductive layer 104_1 in the opening 143_1 is preferably located higher than the upper end of the side surface of the conductive layer 112b facing the opening 143_1. Even in this case, the depth of the recess formed on the conductive layer 104_1 in the opening 143_1 can be reduced compared to the semiconductor device 100A shown in FIG. 15A. Therefore, the coverage of layers provided on the conductive layer 104_1 can be improved compared to the semiconductor device 100A.

[0399] Furthermore, compared to the semiconductor device 100D shown in FIG. 20A, the step of forming the insulating layer 195 is not necessary, so the number of steps involved in the manufacture can be reduced compared to the semiconductor device 100D.

[0400] With respect to the semiconductor device 100E, the contents described for the semiconductor device 100A can be referred to for other aspects than those described above.

[0401] <Example of Manufacturing Method of Semiconductor Device> A method for manufacturing a semiconductor device of one embodiment of the present invention will be described below with reference to the drawings. Here, the semiconductor device 100A shown in FIGS. 14A to 15B is used as an example.

[0402] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by a sputtering method, a CVD method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0403] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source; DC sputtering, which uses a direct current power supply; and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is preferably used for film formation using an insulating target. DC sputtering is mainly used when film formation is performed using a conductive target. In addition to forming conductive films, DC sputtering can also form insulating films by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used when forming films of compounds such as oxides, nitrides, and carbides by reactive sputtering.

[0404] CVD methods can be classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, photo-CVD (photo-CVD) methods that utilize light, etc. Furthermore, CVD methods can be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0405] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can reduce plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, or elements included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0406] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0407] The CVD and ALD methods differ from sputtering methods in that particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio, for example. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0408] Furthermore, the CVD method allows deposition of a film of any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film whose composition changes continuously by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0409] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0410] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by methods such as spin coating, dipping, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife coating, slit coating, roll coating, curtain coating, and knife coating.

[0411] When processing a thin film that constitutes a semiconductor device, it can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0412] There are two typical photolithography methods: one is a method in which a resist mask is formed on a thin film to be processed, the thin film is processed by etching or the like, and the resist mask is then removed; the other is a method in which a photosensitive thin film is formed, and then the thin film is exposed to light and developed to be processed into a desired shape.

[0413] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0414] For etching the thin film, for example, dry etching, wet etching, or sandblasting can be used.

[0415] Typically, a polishing method such as CMP can be suitably used as the planarization treatment of the thin film. Alternatively, a reflow method, in which the conductive layer is subjected to a heat treatment to fluidize it, can be suitably used. Alternatively, a combination of the reflow method and CMP can be used.

[0416] Alternatively, a process may be used in which a planarizing film is formed on an uneven film surface and then highly anisotropically etched (e.g., dry etching) on ​​the planarizing film to form a film with a flat upper surface, or a process may be used in which a planarizing film and a photoresist are formed in that order on the uneven film surface and then highly anisotropically etched on the planarizing film and the photoresist to fill the recesses with only the planarizing film and flatten the entire upper surface (these processes are sometimes referred to as etch-back processes). The etch-back process does not require a high-temperature (e.g., about 800°C) heating process as in the reflow process, and therefore there is no need to worry about damage to the device during fabrication due to the heating process. Furthermore, the etch-back process is suitable because it can be applied to devices on large substrates that are difficult to process using CMP due to the effects of warping, etc.

[0417] Other examples of the planarization treatment for a thin film include dry etching and plasma treatment. The polishing, dry etching, and plasma treatment may be performed multiple times, or a combination of these may be performed. When a combination of these treatments is used, the order of the steps is not particularly limited, and it is preferable to set the order appropriately according to the unevenness of the surface to be treated.

[0418] To precisely process a thin film to a desired thickness, for example, CMP is used. In this case, the thin film is first polished at a constant processing speed until a portion of the top surface of the thin film is exposed. Then, the thin film is polished at a slower processing speed until the thin film reaches the desired thickness, thereby enabling highly precise processing.

[0419] Methods for detecting the end point of polishing include an optical method in which light is irradiated onto the surface of the surface to be treated and changes in the reflected light are detected, a physical method in which changes in the polishing resistance that the processing device receives from the surface to be treated are detected, and a method in which magnetic field lines are applied to the surface to be treated and changes in the magnetic field lines due to the eddy currents that are generated are used.

[0420] After the upper surface of the thin film is exposed, the thickness of the thin film can be controlled with high precision by performing a polishing process at a slow processing speed while monitoring the thickness of the thin film by an optical method such as a laser interferometer. If necessary, the polishing process may be performed multiple times until the thin film reaches the desired thickness.

[0421] 21A to 28B are diagrams illustrating a method for manufacturing the semiconductor device 100A. In each diagram, (A) shows a plan view corresponding to FIG. 14A. In each diagram, (B) shows a cross-sectional view taken along dashed line A1-A2 in the plan view shown in FIG. 14A.

[0422] First, a conductive film to be the conductive layers 112a1 and 112a2 is formed over the substrate 102, and then part of the conductive film is removed to form the conductive layers 112a1 and 112a2 (FIGS. 21A and 21B). The conductive film can be formed by, for example, a sputtering method. The conductive film can be processed by one or both of a wet etching method and a dry etching method.

[0423] Subsequently, an insulating film 110a1f, an insulating film 110b1f, and an insulating film 110c1f are formed in this order on the conductive layer 112a1, the conductive layer 112a2, and the substrate 102.

[0424] The insulating film 110a1f can be made of any of the materials that can be used for the insulating layer 110a1 described above.

[0425] The insulating film 110a1f can be formed using, for example, silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide.

[0426] Specifically, the insulating film 110a1f can be formed by, for example, a silicon nitride film by a sputtering method, a PEALD method, or an aluminum oxide film by a sputtering method.

[0427] Alternatively, for example, a structure in which aluminum oxide and silicon nitride are stacked can be used, for example, a structure in which aluminum oxide formed by sputtering and silicon nitride formed by PEALD are stacked.

[0428] The insulating film 110b1f can be made of any of the materials that can be used for the insulating layer 110b1 described above.

[0429] For example, silicon oxide, silicon oxynitride, or the like can be suitably used as the insulating film 110b1f.

[0430] Specifically, the insulating film 110b1f can be formed by, for example, a silicon oxide film by a sputtering method, a silicon oxide film by a PECVD method, or a silicon oxynitride film by a PECVD method.

[0431] Alternatively, for example, a silicon oxide film formed by sputtering and a silicon oxide or silicon oxynitride film formed by PECVD can be stacked and used.

[0432] After the insulating film 110b1f is formed, heat treatment may be performed. By performing the heat treatment, water and hydrogen can be released from the surface and the interior of the insulating film 110b1f.

[0433] The temperature of the heat treatment is preferably 150° C. or higher and lower than the strain point of the substrate 102, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, and further preferably 350° C. or higher and 400° C. or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA: Clean Dry Air) may be used. Note that the atmosphere preferably contains as little hydrogen, water, or the like as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower. Using an atmosphere containing as little hydrogen, water, or the like as possible can prevent hydrogen, water, or the like from being taken into the insulating film 110b1f as much as possible. The heat treatment can be performed using, for example, an oven or a rapid thermal annealing (RTA) device. By using an RTA device, the heat treatment time can be shortened.

[0434] After the heat treatment, a step of supplying oxygen to the insulating film 110b1f may be performed. For example, after the insulating film 110b1f is formed, a metal oxide layer may be formed over the insulating film 110b1f to supply oxygen to the insulating film 110b1f. Alternatively, heat treatment may be performed after the metal oxide layer is formed. By performing heat treatment after the metal oxide layer is formed, oxygen can be effectively supplied from the metal oxide layer to the insulating film 110b1f, and oxygen can be contained in the insulating film 110b1f. In a later step, the oxygen supplied to the insulating film 110b1f is supplied to the semiconductor layer 108_1 and the semiconductor layer 108_2, thereby reducing oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0435] After the metal oxide layer is formed or after the heat treatment, oxygen may be supplied to the insulating film 110b1f through the metal oxide layer. Examples of a method for supplying oxygen include ion implantation, ion doping, plasma immersion ion implantation, and plasma treatment. For the plasma treatment, an apparatus that converts oxygen gas into plasma using high-frequency power can be preferably used. Examples of apparatus that convert gas into plasma using high-frequency power include a plasma etching apparatus and a plasma ashing apparatus.

[0436] The metal oxide layer may be an insulating layer or a conductive layer, and may be, for example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO).

[0437] The metal oxide layer is preferably formed using an oxide material containing one or more of the same elements as those of the semiconductor layers 108_1 and 108_2. In particular, it is preferable to use an oxide semiconductor material applicable to the semiconductor layers 108_1 and 108_2. This allows the metal oxide layer to be formed using the same sputtering target as that of the semiconductor layers 108_1 and 108_2, thereby reducing manufacturing costs.

[0438] When a metal oxide material containing indium and gallium is used for the metal oxide layer, a material having a higher gallium content than the semiconductor layers 108_1 and 108_2 can be used. By using a material having a higher gallium content for the metal oxide layer, the blocking property against oxygen can be further improved. This is preferable because oxygen contained in the insulating film 110b1f can be prevented from being released to the outside through the metal oxide layer.

[0439] The metal oxide layer is preferably formed in an atmosphere containing oxygen, for example. In particular, it is preferably formed by a sputtering method in an atmosphere containing oxygen. This allows oxygen to be suitably supplied to the insulating film 110b1f during the formation of the metal oxide layer.

[0440] Next, the metal oxide layer is removed, for example, by wet etching.

[0441] The process of supplying oxygen to the insulating film 110b1f is not limited to the above-described method. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, or the like may be supplied to the insulating film 110b1f by ion doping, ion implantation, plasma treatment, or the like. Alternatively, a film that suppresses oxygen desorption may be formed over the insulating film 110b1f, and then oxygen may be supplied to the insulating film 110b1f through the film. The film is preferably removed after supplying oxygen. The film that suppresses oxygen desorption may be a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, or tungsten.

[0442] The insulating film 110c1f can be made of any of the materials that can be used for the insulating layer 110c1 described above.

[0443] For the material and the deposition method that can be used for the insulating film 110c1f, the above description of the material and the deposition method that can be used for the insulating film 110a1f can be referred to.

[0444] Next, a conductive film 112bf is formed over the insulating film 110c1f (FIGS. 22A and 22B). The conductive film 112bf can be formed using any of the materials that can be used for the conductive layer 112b described above. The conductive film 112bf can be formed by, for example, a sputtering method.

[0445] Next, a part of the conductive film 112bf is removed to form a conductive layer 112be (FIGS. 23A and 23B). The conductive layer 112be may be formed by wet etching or dry etching, or both. The conductive layer 112be is formed to have a region overlapping with the conductive layer 112a1 and the conductive layer 112a2.

[0446] Next, the insulating film 110a2f, the insulating film 110b2f, the insulating film 110c2f, and the conductive film 112cf are formed in this order over the conductive layer 112be and the insulating film 110c1f ( FIGS. 24A and 24B ). For materials that can be used for the insulating film 110a2f, the insulating film 110b2f, the insulating film 110c2f, and the conductive film 112cf, as well as their formation methods, refer to the descriptions of the insulating film 110a1f, the insulating film 110b1f, the insulating film 110c1f, and the conductive film 112bf, respectively.

[0447] Next, a part of the conductive film 112cf is removed to form a conductive layer 112ce (FIGS. 25A and 25B). The conductive layer 112ce may be formed by wet etching or dry etching, or both. The conductive layer 112ce is formed to have regions overlapping with the conductive layer 112be, the conductive layer 112a1, and the conductive layer 112a2.

[0448] Next, portions of the conductive layer 112ce, the insulating film 110c2f, the insulating film 110b2f, the insulating film 110a2f, the conductive layer 112be, the insulating film 110c1f, the insulating film 110b1f, and the insulating film 110a1f are removed to form an opening 143_1 reaching the conductive layer 112a1 and an opening 143_2 reaching the conductive layer 112a2. For example, dry etching can be suitably used for this process. As a result of this process, the conductive layer 112c, the insulating layer 110c2, the insulating layer 110b2, the insulating layer 110a2, the conductive layer 112b, the insulating layer 110c1, the insulating layer 110b1, and the insulating layer 110a1, each having an opening, are formed ( FIGS. 26A and 26B ).

[0449] Next, the upper surface of the conductive layer 112a1 in the opening 143_1, the side surface of the insulating layer 110_1 (insulating layer 110a1, insulating layer 110b1, and insulating layer 110c1) in the opening 143_1, the side surface of the conductive layer 112b in the opening 143_1, the side surface of the insulating layer 110_2 (insulating layer 110a2, insulating layer 110b2, and insulating layer 110c2) in the opening 143_1, and the side surface of the conductive layer 112c in the opening 143_1. A semiconductor film to become the semiconductor layer 108_1 and the semiconductor layer 108_2 is formed in contact with the top surface of the conductive layer 112a2 in the opening 143_2, the side surface of the insulating layer 110_1 in the opening 143_2, the side surface of the conductive layer 112b in the opening 143_2, the side surface of the insulating layer 110_2 in the opening 143_2, the side surface of the conductive layer 112c in the opening 143_2, the top surface of the conductive layer 112c, and the top surface of the insulating layer 110c2. Then, portions of the semiconductor film are removed by etching to form the semiconductor layer 108_1 and the semiconductor layer 108_2 ( FIGS. 27A and 27B ). The semiconductor layer 108_1 is provided to have a region overlapping with the opening 143_1. The semiconductor layer 108_2 is provided to have a region overlapping with the opening 143_2. The semiconductor layer 108_1 and the semiconductor layer 108_2 are provided so that their ends have a region in contact with the conductive layer 112c.

[0450] For the semiconductor films to be the semiconductor layers 108_1 and 108_2, the above-described materials that can be used for the semiconductor layers 108_1 and 108_2 can be used as appropriate.

[0451] The semiconductor films to be the semiconductor layers 108_1 and 108_2 can be formed by, for example, a sputtering method. For example, when a metal oxide is used for the semiconductor layers 108_1 and 108_2, they can be formed by a sputtering method using a metal oxide target. The sputtering method is preferable because it allows a film with a low hydrogen content to be formed relatively easily.

[0452] When a metal oxide is used for the semiconductor layer 108_1 and the semiconductor layer 108_2, the semiconductor layer 108_1 and the semiconductor layer 108_2 can be formed by an ALD method using a precursor containing a constituent metal element and an oxidizing agent.

[0453] For example, when forming an In—Ga—Zn oxide, three precursors, i.e., a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used, or two precursors, i.e., a precursor containing indium and a precursor containing gallium and zinc, can be used.

[0454] As the precursor containing indium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, and the like can be used.

[0455] Furthermore, examples of precursors that can be used that contain gallium include trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, and diethylchlorogallium.

[0456] Furthermore, as a precursor containing zinc, dimethyl zinc, diethyl zinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc chloride, etc. can be used.

[0457] As the oxidizing agent, for example, ozone, oxygen, water, etc. can be used.

[0458] Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the source gases, the time for which the source gases are flowed, the order in which the source gases are flowed, etc. By adjusting these, it is also possible to form a film whose composition changes continuously. It is also possible to form films with different compositions successively.

[0459] By using the ALD method to form the semiconductor films to be the semiconductor layers 108_1 and 108_2, the semiconductor layers 108_1 and 108_2 can be formed with uniform thicknesses on the side surfaces of the insulating layer 110_1, the conductive layer 112b, the insulating layer 110_2, and the conductive layer 112c, which is preferable.

[0460] After the semiconductor films to be the semiconductor layers 108_1 and 108_2 are formed, heat treatment may be performed. The heat treatment can reduce water and hydrogen contained in the semiconductor films and supply oxygen to the semiconductor films from the insulating layers 110_1 and 110_2. Note that the heat treatment may be performed after the semiconductor films are processed.

[0461] The substrate temperature during the formation of the semiconductor films to be the semiconductor layers 108_1 and 108_2 is preferably from room temperature (25° C.) to 200° C., more preferably from room temperature to 130° C. By setting the substrate temperature within the above range, bending or distortion of the substrate can be suppressed when a large-area glass substrate is used.

[0462] The higher the substrate temperature (stage temperature) during the formation of the metal oxide layer, the higher the crystallinity of the formed metal oxide layer.Furthermore, the higher the oxygen flow rate ratio, the higher the crystallinity of the formed metal oxide layer.

[0463] Subsequently, the insulating layer 106 is formed to cover the semiconductor layer 108_1, the semiconductor layer 108_2, the conductive layer 112c, and the insulating layer 110c2 (FIGS. 28A and 28B). The insulating layer 106 has regions in contact with the top and side surfaces of the semiconductor layer 108_1, the semiconductor layer 108_2, the conductive layer 112c, and the top surface of the insulating layer 110c2.

[0464] The insulating layer 106 can be formed using any of the materials described above as appropriate.

[0465] The insulating layer 106 can be formed by, for example, an ALD method. The ALD method is preferable because the insulating layer 106 can be formed with good coverage over the semiconductor layer 108_1 formed to cover the opening 143_1 and the semiconductor layer 108_2 formed to cover the opening 143_2. Note that, if the semiconductor layer 108_1 and the semiconductor layer 108_2 can be sufficiently covered, a method other than the ALD method may be used to form the insulating layer 106. For example, a PECVD method, a sputtering method, or the like can be used. This allows the insulating layer 106 to be formed at a higher rate than when the ALD method is used, thereby improving productivity.

[0466] Next, conductive films to be the conductive layers 104_1 and 104_2 are formed over the insulating layer 106. The conductive films to be the conductive layers 104_1 and 104_2 can be formed using any of the materials that can be used for the conductive layers 104_1 and 104_2 described above. The conductive films to be the conductive layers 104_1 and 104_2 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. Here, the conductive films to be the conductive layers 104_1 and 104_2 are preferably formed in contact with the insulating layer 106 facing the side surfaces of the insulating layer 110_1 and the insulating layer 110_2 in the openings 143_1 and 143_2, respectively. Therefore, a method having good coverage or embedding properties is preferably used to form the conductive films to be the conductive layers 104_1 and 104_2, and a CVD method, an ALD method, or the like is more preferable.

[0467] Next, parts of the conductive film that will become the conductive layers 104_1 and 104_2 are removed to form the conductive layers 104_1 and 104_2. The conductive layer 104_1 is formed to have a region that overlaps with the opening 143_1. The conductive layer 104_2 is formed to have a region that overlaps with the opening 143_2. In addition, the top surface of the insulating layer 106 is exposed in the regions where the conductive film that will become the conductive layers 104_1 and 104_2 has been removed. The conductive layers 104_1 and 104_2 may be formed by wet etching or dry etching, or both.

[0468] As a result, a switch 100A1 including the transistors 10A1_1 and 10A1_2 and a switch 100A2 including the transistors 10A2_1 and 10A2_2 are formed.

[0469] Through the above steps, the semiconductor device 100A can be manufactured (FIGS. 14A to 15B).

[0470] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0471] Embodiment 3 In this embodiment, electronic devices of one embodiment of the present invention will be described with reference to FIGS. 29A to 31F.

[0472] The electronic devices of this embodiment include the display device of one embodiment of the present invention in their display portions. The display device of one embodiment of the present invention can easily achieve high definition and high resolution. Therefore, the display device of one embodiment of the present invention can be used in the display portions of various electronic devices.

[0473] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0474] In particular, the display device of one embodiment of the present invention can have high resolution and thus can be suitably used in electronic devices having a relatively small display portion. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), and head-mounted wearable devices such as head-mounted displays for virtual reality (VR), glasses-type devices for augmented reality (AR), and glasses-type devices for mixed reality (MR).

[0475] The display device of one embodiment of the present invention preferably has an extremely high resolution, such as HD (1280 × 720 pixels), FHD (1920 × 1080 pixels), WQHD (2560 × 1440 pixels), WQXGA (2560 × 1600 pixels), 4K (3840 × 2160 pixels), or 8K (7680 × 4320 pixels). A resolution of 4K, 8K, or higher is particularly preferable. Furthermore, the pixel density (resolution) of the display device of one embodiment of the present invention is preferably 100 ppi or higher, more preferably 300 ppi or higher, more preferably 500 ppi or higher, more preferably 1000 ppi or higher, more preferably 2000 ppi or higher, more preferably 3000 ppi or higher, more preferably 5000 ppi or higher, and even more preferably 7000 ppi or higher. By using a display device having either or both of high resolution and high definition, it is possible to further enhance the sense of realism and depth. Furthermore, the screen ratio (aspect ratio) of the display device of one embodiment of the present invention is not particularly limited. For example, the display device can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0476] The electronic device of this embodiment may have a sensor (including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0477] The electronic device of the present embodiment can have various functions, such as a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, time, etc., a function of executing various software (programs), a wireless communication function, a function of reading out programs or data recorded on a recording medium, etc.

[0478] 29A to 29D , examples of wearable devices that can be worn on the head are described. These wearable devices have at least one of the functions of displaying AR content, VR content, and MR content. By having an electronic device with the function of displaying at least one of AR, VR, and MR content, it is possible to enhance the sense of immersion felt by the user.

[0479] The electronic device 700A shown in FIG. 29A and the electronic device 700B shown in FIG. 29B each have a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.

[0480] The display device of one embodiment of the present invention can be applied to the display panel 751. Therefore, the electronic device can provide an extremely high-definition display.

[0481] The electronic device 700A and the electronic device 700B can each project an image displayed on the display panel 751 onto a display area 756 of the optical member 753. Because the optical member 753 is translucent, the user can see the image displayed in the display area superimposed on a transmitted image visually recognized through the optical member 753. Therefore, the electronic device 700A and the electronic device 700B are each electronic devices capable of AR display.

[0482] The electronic device 700A and the electronic device 700B may be provided with a camera capable of capturing an image of the front as an imaging unit. Furthermore, the electronic device 700A and the electronic device 700B may each be provided with an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to that orientation in the display area 756.

[0483] The communication unit has a wireless communication device, and can supply a video signal, etc. Instead of or in addition to the wireless communication device, a connector to which a cable through which a video signal and a power supply potential are supplied may be provided.

[0484] The electronic device 700A and the electronic device 700B are provided with a battery (not shown), which can be charged wirelessly and / or by wire.

[0485] The housing 721 may be provided with a touch sensor module. The touch sensor module has a function of detecting a touch on the outer surface of the housing 721. The touch sensor module can detect a tap operation, a slide operation, or the like by the user and perform various processes. For example, a tap operation can perform a process such as pausing or resuming a video, and a slide operation can perform a process such as fast-forwarding or fast-rewinding. Furthermore, providing a touch sensor module on each of the two housings 721 can broaden the range of operations.

[0486] Various touch sensors can be used as the touch sensor module. For example, various types of touch sensors can be used, such as a capacitance type, a resistive film type, an infrared type, an electromagnetic induction type, a surface acoustic wave type, and an optical type. In particular, it is preferable to use a capacitance type or an optical type sensor in the touch sensor module.

[0487] When an optical touch sensor is used, a photoelectric conversion element can be used as the light receiving element. The active layer of the photoelectric conversion element can be made of either or both of an inorganic semiconductor and an organic semiconductor.

[0488] The electronic device 800A shown in Figure 29C and the electronic device 800B shown in Figure 29D each have a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.

[0489] The display device of one embodiment of the present invention can be applied to the display portion 820. Therefore, an electronic device capable of displaying images with extremely high definition can be provided. This allows a user to feel a high sense of immersion.

[0490] The display unit 820 is provided inside the housing 821 at a position where it can be viewed through the lens 832. Also, by displaying different images on the pair of display units 820, it is possible to perform three-dimensional display using parallax.

[0491] The electronic device 800A and the electronic device 800B can be said to be electronic devices for VR. A user wearing the electronic device 800A or the electronic device 800B can view an image displayed on the display unit 820 through the lens 832.

[0492] It is preferable that the electronic device 800A and the electronic device 800B each have a mechanism for adjusting the left-right positions of the lens 832 and the display unit 820 so that they are optimally positioned according to the position of the user's eyes. It is also preferable that the electronic device 800A and the electronic device 800B each have a mechanism for adjusting the focus by changing the distance between the lens 832 and the display unit 820.

[0493] The mounting unit 823 allows the user to mount the electronic device 800A or the electronic device 800B on the head. Note that, in Fig. 29C and other figures, the mounting unit 823 is shaped like the temples of glasses, but is not limited to this. The mounting unit 823 may be shaped like a helmet or a band, for example, as long as it can be worn by the user.

[0494] The imaging unit 825 has a function of acquiring external information. Data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used for the imaging unit 825. Furthermore, multiple cameras may be provided to support multiple angles of view, such as telephoto and wide-angle.

[0495] Although an example including the imaging unit 825 is shown here, a distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object may be provided. That is, the imaging unit 825 is one aspect of the detection unit. As the detection unit, for example, an image sensor or a range image sensor such as a LIDAR (Light Detection and Ranging) can be used. By using an image obtained by the camera and an image obtained by the range image sensor, more information can be obtained, enabling more accurate gesture operations.

[0496] The electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone. For example, a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, the housing 821, and the wearing unit 823. This allows a user to enjoy video and audio simply by wearing the electronic device 800A, without the need for separate audio equipment such as headphones, earphones, or speakers.

[0497] The electronic device 800A and the electronic device 800B may each have an input terminal to which a cable can be connected for supplying a video signal from a video output device or the like and power for charging a battery provided in the electronic device.

[0498] The electronic device of one embodiment of the present invention may have a function of wirelessly communicating with an earphone 750. The earphone 750 includes a communication unit (not shown) and has a wireless communication function. The earphone 750 can receive information (e.g., audio data) from the electronic device through the wireless communication function. For example, an electronic device 700A shown in FIG. 29A has a function of transmitting information to the earphone 750 through the wireless communication function. Furthermore, for example, an electronic device 800A shown in FIG. 29C has a function of transmitting information to the earphone 750 through the wireless communication function.

[0499] The electronic device may have an earphone unit. Electronic device 700B shown in Fig. 29B has earphone unit 727. For example, earphone unit 727 and the control unit may be configured to be connected to each other by wire. Part of the wiring connecting earphone unit 727 and the control unit may be disposed inside housing 721 or attachment unit 723.

[0500] Similarly, electronic device 800B shown in Fig. 29D has earphone unit 827. For example, earphone unit 827 and control unit 824 can be configured to be connected to each other by wire. Part of the wiring connecting earphone unit 827 and control unit 824 may be disposed inside housing 821 or wearing unit 823. Furthermore, earphone unit 827 and wearing unit 823 may have magnets. This allows earphone unit 827 to be fixed to wearing unit 823 by magnetic force, which is preferable as it makes storage easier.

[0501] The electronic device may have an audio output terminal to which earphones or headphones can be connected. The electronic device may also have one or both of an audio input terminal and an audio input mechanism. For example, a sound collection device such as a microphone can be used as the audio input mechanism. By having the audio input mechanism, the electronic device may be endowed with the functionality of a so-called headset.

[0502] As described above, as electronic devices according to one embodiment of the present invention, both glasses-type devices (such as the electronic device 700A and the electronic device 700B) and goggle-type devices (such as the electronic device 800A and the electronic device 800B) are suitable.

[0503] An electronic device according to one embodiment of the present invention can transmit information to an earphone via a wired or wireless connection.

[0504] The electronic device 6500 shown in FIG. 30A is a portable information terminal that can be used as a smartphone.

[0505] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and the like. The display portion 6502 has a touch panel function.

[0506] The display device of one embodiment of the present invention can be applied to the display portion 6502 .

[0507] FIG. 30B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.

[0508] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0509] A display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by adhesive layers (not shown).

[0510] In a region outside the display portion 6502, a part of the display panel 6511 is folded back, and an FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on a printed circuit board 6517.

[0511] The flexible display of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. Furthermore, since the display panel 6511 is extremely thin, the thickness of the electronic device can be reduced and a large-capacity battery 6518 can be mounted thereon. Furthermore, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the display portion 6502, an electronic device with a narrow frame can be realized.

[0512] 30C shows an example of a television set. A television set 7100 has a display portion 7000 built into a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0513] The display device of one embodiment of the present invention can be applied to the display portion 7000 .

[0514] 30C can be operated using operation switches provided on the housing 7101 and a separate remote control 7111. Alternatively, the display portion 7000 may be provided with a touch sensor, and the television set 7100 may be operated by touching the display portion 7000 with a finger or the like. The remote control 7111 may have a display portion that displays information output from the remote control 7111. Using operation keys or a touch panel provided on the remote control 7111, the channel and volume can be controlled, and an image displayed on the display portion 7000 can be controlled.

[0515] The television device 7100 is configured to include a receiver, a modem, and the like. Ordinary television broadcasts can be received using the receiver. Furthermore, by connecting to a wired or wireless communication network via the modem, it is also possible to perform one-way (from a sender to a receiver) or two-way (between a sender and a receiver, or between receivers, etc.) information communication.

[0516] 30D shows an example of a laptop personal computer 7200. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, and an external connection port 7214. The housing 7211 includes a display portion 7000.

[0517] The display device of one embodiment of the present invention can be applied to the display portion 7000 .

[0518] 30E and 30F show an example of digital signage.

[0519] 30E includes a housing 7301, a display portion 7000, a speaker 7303, and the like. The digital signage 7300 may further include an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0520] 30F shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7000 provided along the curved surface of the pillar 7401.

[0521] 30E and 30F, the display device of one embodiment of the present invention can be applied to the display portion 7000.

[0522] The larger the display unit 7000, the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it attracts people's attention, which can increase the advertising effectiveness of, for example, advertisements.

[0523] Applying a touch panel to the display unit 7000 is preferable because it not only displays images or videos on the display unit 7000 but also allows the user to intuitively operate it. Furthermore, when used to provide information such as route information or traffic information, the intuitive operation can improve usability.

[0524] 30E and 30F , the digital signage 7300 or the digital signage 7400 is preferably capable of wirelessly linking with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. Furthermore, by operating the information terminal 7311 or the information terminal 7411, the display on the display unit 7000 can be switched.

[0525] The digital signage 7300 or the digital signage 7400 can also be made to run a game using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller), thereby allowing an unspecified number of users to simultaneously participate in and enjoy the game.

[0526] Furthermore, the semiconductor device and the display device according to one embodiment of the present invention can be applied to the area around the driver's seat of an automobile, which is a moving object.

[0527] Fig. 31A is a diagram illustrating the area around the windshield in the interior of a vehicle, showing display panels 9001a, 9001b, and 9001c attached to the dashboard, and a display panel 9001d attached to a pillar.

[0528] The display panels 9001a to 9001c can provide various information by displaying navigation information, a speedometer, a tachometer, mileage, a fuel gauge, gear status, air conditioning settings, etc. Furthermore, the display items and layouts displayed on the display panels can be changed as appropriate to suit the user's preferences, thereby improving the design. The display panels 9001a to 9001c can also be used as lighting devices.

[0529] The display panel 9001d can display an image from an imaging device installed on the vehicle body to complement the view blocked by the pillar (blind spot). In other words, by displaying an image from an imaging device installed on the outside of the vehicle, blind spots can be complemented and safety can be improved. Furthermore, by displaying an image that complements the invisible part, safety confirmation can be performed more naturally and without discomfort. The display panel 9001d can also be used as a lighting device.

[0530] FIG. 31B is a perspective view showing a wristwatch-type mobile information terminal 9200. The mobile information terminal 9200 can be used as, for example, a smart watch (registered trademark). The display surface of the display unit 9001 is curved, and display can be performed along the curved display surface. The mobile information terminal 9200 can also perform hands-free calling by communicating with, for example, a wirelessly capable headset. The mobile information terminal 9200 can also perform data transmission and charging with another information terminal through a connection terminal 9006. Note that charging may be performed by wireless power supply.

[0531] The mobile information terminal 9200 shown in Figure 31B has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays), a microphone 9008, etc.

[0532] 31C is a perspective view of a foldable portable information terminal 9201. The portable information terminal 9201 includes a housing 9000a, a housing 9000b, a display portion 9001, and an operation button 9056.

[0533] The housing 9000a and the housing 9000b are joined by a hinge 9055, and the hinge 9055 allows the device to be folded in half.

[0534] A display portion 9001 included in the portable information terminal 9201 is supported by two housings (a housing 9000 a and a housing 9000 b ) connected by a hinge 9055 .

[0535] 31D to 31F are perspective views showing a foldable portable information terminal 9202. Fig. 31D is a perspective view of the portable information terminal 9202 in an unfolded state, Fig. 31F is a perspective view of the portable information terminal 9202 in a folded state, and Fig. 31E is a perspective view of the portable information terminal 9202 in a state in which it is changing from one of Fig. 31D and Fig. 31F to the other. In this way, the portable information terminal 9202 can be folded into three.

[0536] A display portion 9001 of the portable information terminal 9202 is supported by three housings 9000 connected by hinges 9055 .

[0537] 31C to 31F, the display device of one embodiment of the present invention can be applied to the display portion 9001. For example, the display portion 9001 can be bent with a curvature radius of 0.1 mm to 150 mm.

[0538] The portable information terminals 9201 and 9202 are each highly portable when folded, and have a seamless, wide display area when unfolded, allowing for excellent display visibility.

[0539] Note that power consumption can be reduced by applying the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, mainframe computers, space equipment, data centers, and electronic devices. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can reduce carbon dioxide (CO ２Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0540] This embodiment mode can be combined with other embodiment modes as appropriate.

[0541] 10A1_1: transistor, 10A1_2: transistor, 10A2_1: transistor, 10A2_2: transistor, 10B1_1: transistor, 10B1_2: transistor, 10B2_1: transistor, 10B2_2: transistor, 10C1_1: transistor, 10C1_2: transistor, 10C1_3: transistor, 10C1_4: transistor, 10C2_1: transistor, 10C2_2: transistor, 10C2_3: transistor, 10C2_4: transistor, 10D1_1: transistor, 10D1_2: transistor , 10D2_1: transistor, 10D2_2: transistor, 10E1_1: transistor, 10E1_2: transistor, 10E2_1: transistor, 10E2_2: transistor, 100A: semiconductor device, 100A1: switch, 100A2: switch, 100B: semiconductor device, 100B1: switch, 100B2: switch, 100C: semiconductor device, 100C1: switch, 100C2: switch, 100D: semiconductor device, 100D1: switch, 100D2: switch, 100E: semiconductor device, 100E1: switch, 100E2: switch 102: substrate, 104_1: conductive layer, 104_2: conductive layer, 106: insulating layer, 108_1: semiconductor layer, 108_2: semiconductor layer, 110_1: insulating layer, 110_2: insulating layer, 110_3: insulating layer, 110_4: insulating layer, 110a1: insulating layer, 110a1f: insulating film, 110a2: insulating layer, 110a2f: insulating film, 110a3: insulating layer, 110a4: insulating layer, 110b1: insulating layer, 110b1f: insulating film, 110b2: insulating layer, 110b2f: insulating film, 110b3: insulating layer, 110b4: insulating layer, 110c1: insulating layer, 110c1f: insulating film, 110c2: Insulating layer, 110c2f: insulating film, 110c3: insulating layer, 110c4: insulating layer, 112a: conductive layer, 112a1: conductive layer, 112a2: conductive layer, 112b: conductive layer, 112be: conductive layer, 112bf: conductive film, 112c: conductive layer, 112c1: conductive layer, 112c2: conductive layer, 112ce: conductive layer, 112cf: conductive film, 112d: conductive layer, 112e: conductive layer, 143_1: opening, 143_2: opening, 144_1: opening, 144_2: opening, 195: insulating layer, 700A: electronic device, 700B: electronic device, 721: housing, 723: wearing portion, 727: earphone portion,750: earphones, 751: display panel, 753: optical member, 756: display area, 757: frame, 758: nose pads, 800A: electronic device, 800B: electronic device, 820: display unit, 821: housing, 822: communication unit, 823: wearing unit, 824: control unit, 825: imaging unit, 827: earphone unit, 832: lens, 6500: electronic device, 6501: housing, 6502: display unit, 6503: power button, 6504: button, 6505: speaker, 6506: microphone, 6507: camera, 6508: light source, 6510: protective member, 6511: display panel, 6512: optical member, 6513: touch sensor panel, 6515: FPC, 6516: IC, 6517: printed circuit board, 6518: battery, 7000: display unit, 7100: television device, 7101: housing, 7103: stand, 7111: remote control device, 7200: notebook personal computer, 7211: housing, 7212: keyboard, 7213: pointing device, 7214: external connection port, 7300: digital signage, 7301: housing, 7303: speaker, 7311: information terminal, 7400: digital signage, 7401: pillar, 7411: information terminal, 9000: housing, 9000a: housing Body, 9000b: housing, 9001: display unit, 9001a: display panel, 9001b: display panel, 9001c: display panel, 9001d: display panel, 9003: speaker, 9005: operation keys, 9006: connection terminal, 9007: sensor, 9008: microphone, 9055: hinge, 9056: operation button, 9200: mobile information terminal, 9201: mobile information terminal, 9202: mobile information terminal,

Claims

a first switch and a second switch; the first switch includes a first transistor and a second transistor; the second switch includes a third transistor and a fourth transistor; one of a source or a drain of the first transistor, one of a source or a drain of the second transistor, one of a source or a drain of the third transistor, and one of a source or a drain of the fourth transistor are electrically connected to each other; a gate of the first transistor and a gate of the second transistor are electrically connected to each other; a gate of the third transistor and a gate of the fourth transistor are electrically connected to each other; Semiconductor device. 　 In claim 1, a third switch and a fourth switch; the third switch includes a fifth transistor and a sixth transistor; the fourth switch includes a seventh transistor and an eighth transistor; one of a source or a drain of the fifth transistor, one of a source or a drain of the sixth transistor, one of a source or a drain of the seventh transistor, and one of a source or a drain of the eighth transistor are electrically connected to each other; a gate of the fifth transistor and a gate of the sixth transistor are electrically connected to each other; a gate of the seventh transistor and a gate of the eighth transistor are electrically connected to each other; the other of the source or the drain of the second transistor is electrically connected to the other of the source or the drain of the fifth transistor; Semiconductor device. 　 In claim 2, the other of the source or the drain of the first transistor, the other of the source or the drain of the third transistor, and the other of the source or the drain of the seventh transistor are electrically connected to a first power supply line; the other of the source or the drain of the fourth transistor, the other of the source or the drain of the sixth transistor, and the other of the source or the drain of the eighth transistor are electrically connected to a second power supply line; a potential supplied to the first power supply line is higher than a potential supplied to the second power supply line; Semiconductor device. 　 In claim 2, the first to eighth transistors each include a metal oxide in a semiconductor layer and have a channel formation region provided along a side surface of an opening in an insulating layer; Semiconductor device. 　 A gate driver is provided. The gate driver includes the semiconductor device according to claim 2 or 4. Display device. 　 a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a first semiconductor layer, a second semiconductor layer, a first insulating layer, a second insulating layer, and a third insulating layer; the first conductive layer and the second conductive layer are provided in different regions on the same layer, the first insulating layer, the third conductive layer, the second insulating layer, and the fourth conductive layer are provided in this order on the first conductive layer and the second conductive layer, and the first insulating layer, the third conductive layer, the second insulating layer, and the fourth conductive layer have a first opening reaching the first conductive layer and a second opening reaching the second conductive layer; In the first opening, the first semiconductor layer is in contact with an upper surface of the first conductive layer, a side surface of the first insulating layer, a side surface of the third conductive layer, a side surface of the second insulating layer, and a side surface of the fourth conductive layer; In the second opening, the second semiconductor layer contacts an upper surface of the second conductive layer, a side surface of the first insulating layer, a side surface of the third conductive layer, a side surface of the second insulating layer, and a side surface of the fourth conductive layer; the third insulating layer is in contact with upper surfaces of the first semiconductor layer and the second semiconductor layer; the fifth conductive layer overlaps the first opening and contacts an upper surface of the third insulating layer; the sixth conductive layer overlaps the second opening and contacts an upper surface of the third insulating layer; Semiconductor device. 　 a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a first semiconductor layer, a second semiconductor layer, a first insulating layer, a second insulating layer, and a third insulating layer; the first insulating layer, the second conductive layer, and the second insulating layer are provided on the first conductive layer in this order, overlapping each other; the third conductive layer and the fourth conductive layer are provided in different regions on the second insulating layer, the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer have a first opening reaching the first conductive layer; the first insulating layer, the second conductive layer, the second insulating layer, and the fourth conductive layer have a second opening reaching the first conductive layer; In the first opening, the first semiconductor layer is in contact with an upper surface of the first conductive layer, a side surface of the first insulating layer, a side surface of the second conductive layer, a side surface of the second insulating layer, and a side surface of the third conductive layer; In the second opening, the second semiconductor layer contacts an upper surface of the first conductive layer, a side surface of the first insulating layer, a side surface of the second conductive layer, a side surface of the second insulating layer, and a side surface of the fourth conductive layer; the third insulating layer is in contact with upper surfaces of the first semiconductor layer and the second semiconductor layer; the fifth conductive layer overlaps the first opening and contacts an upper surface of the third insulating layer; the sixth conductive layer overlaps the second opening and contacts an upper surface of the third insulating layer; Semiconductor device. 　 In claim 6 or claim 7, the first semiconductor layer and the second semiconductor layer each include a metal oxide; At least one of the first insulating layer and the second insulating layer comprises silicon oxide or silicon oxynitride. Semiconductor device. 　 In claim 8, the metal oxide contains one or more selected from indium, an element M, and zinc; The element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium; Semiconductor device. 　 In claim 6 or claim 7, the first insulating layer includes a fourth insulating layer, a fifth insulating layer on the fourth insulating layer, and a sixth insulating layer on the fifth insulating layer; the second insulating layer includes a seventh insulating layer, an eighth insulating layer on the seventh insulating layer, and a ninth insulating layer on the eighth insulating layer; the fourth insulating layer, the sixth insulating layer, the seventh insulating layer, and the ninth insulating layer each include silicon nitride, silicon oxynitride, hafnium oxide, or aluminum oxide; the fifth insulating layer and the eighth insulating layer each contain silicon oxide or silicon oxynitride; Semiconductor device. 　 forming a first conductive layer and a second conductive layer; forming a first insulating film, a third conductive layer, a second insulating film, and a fourth conductive layer in this order on the first conductive layer and the second conductive layer; removing a portion of each of the first insulating film, the third conductive layer, the second insulating film, and the fourth conductive layer to form a first opening reaching the first conductive layer and a second opening reaching the second conductive layer, and forming a first insulating layer, a fifth conductive layer, a second insulating layer, and a sixth conductive layer from the first insulating film, the third conductive layer, the second insulating film, and the fourth conductive layer, respectively; forming a first semiconductor layer in contact with an upper surface of the first conductive layer, a side surface of the first insulating layer, a side surface of the fifth conductive layer, a side surface of the second insulating layer, and a side surface of the sixth conductive layer in the first opening; and forming a second semiconductor layer in contact with an upper surface of the second conductive layer, a side surface of the first insulating layer, a side surface of the fifth conductive layer, a side surface of the second insulating layer, and a side surface of the sixth conductive layer in the second opening; forming a third insulating layer in contact with an upper surface of the first semiconductor layer and an upper surface of the second semiconductor layer; forming a seventh conductive layer on the third insulating layer to overlap the first opening, and forming an eighth conductive layer on the third insulating layer to overlap the second opening; A method for manufacturing a semiconductor device.

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