Capacitive element, and display device

Abstract

[Problem] To provide a display capacitive element and a display device with which it is possible to minimize any decrease in the accuracy of a control operation resulting from parasitic capacitance. [Solution] According to the present disclosure, there is provided a capacitive element connected to an electronic circuit having a first node that has a first impedance and a second node that has a second impedance that is lower than the first impedance, said capacitive element comprising a substrate, and a first capacitance layer formed in a plane along the upper surface of the substrate, said first capacitance layer having looped metal wiring, pectinate first metal wiring connected to the looped metal wiring and formed within the looped metal wiring, and pectinate second metal wiring formed within the looped metal wiring of the first metal wiring. The first metal wiring is connected to the first node, and the second metal wiring is connected to the second node.

Description

Capacitor element and display device

[0001] The present disclosure relates to a capacitive element and a display device.

[0002] The electronic circuits that make up the display device have capacitive elements, but the parasitic capacitance of the capacitive elements may reduce the accuracy of the control operations of the electronic circuits.

[0003] Japanese Patent Application Laid-Open No. 2006-119404

[0004] Therefore, the present disclosure provides a display capacitive element and a display device that can suppress a reduction in the accuracy of control operations due to parasitic capacitance.

[0005] In order to solve the above problem, according to the present disclosure, there is provided a capacitive element connected to an electronic circuit having a first node having a first impedance and a second node having a second impedance smaller than the first impedance, the capacitive element comprising: a substrate; and a first capacitance layer formed in a plane along an upper surface of the substrate and having a loop-shaped metal wiring, a comb-tooth-shaped first metal wiring connected to the loop-shaped metal wiring and formed within the loop-shaped metal wiring, and a comb-tooth-shaped second metal wiring formed within the loop-shaped metal wiring of the first metal wiring, wherein the first metal wiring is connected to the first node and the second metal wiring is connected to the second node.

[0006] The first capacitance layer may constitute a metal-on-metal (MOM) capacitance.

[0007] The semiconductor device may have a plurality of the first capacitance layers, the plurality of first capacitance layers being stacked on the substrate, the first metal wiring of each of the first capacitance layers being electrically connected, and the second metal wiring of each of the first capacitance layers being electrically connected.

[0008] The spaces between the first capacitance layers may be formed by insulating films.

[0009] The semiconductor device may further include a first metal layer configured between an upper surface of the substrate and lower surfaces of the plurality of first capacitance layers and extending along the upper surface of the substrate, the first metal layer being connected to the first metal wiring.

[0010] The semiconductor device may further include a second metal layer formed along upper surfaces of the plurality of first capacitance layers and connected to the first metal wiring.

[0011] The semiconductor device may further include a semiconductor layer stacked on an upper surface of the first metal layer and configured within the loop-shaped metal wiring in a planar view; and a third metal layer stacked on an upper surface of the semiconductor layer and configured within the loop-shaped metal wiring in a planar view.

[0012] The third metal layer may be connected to the second metal wiring.

[0013] The first metal layer, the semiconductor layer, and the third metal layer may form an MIM capacitor.

[0014] In a planar view, the loop-shaped metal wirings of the plurality of first capacitance layers may be arranged to overlap, and the plurality of loop-shaped metal wirings and the first metal layer may be connected by metal pins located within the loop-shaped metal wirings in a planar view.

[0015] The semiconductor device may further include a well formed on the upper surface of the substrate, the well being connected to the first metal wiring.

[0016] The semiconductor device may further include a shallow trench isolation layer configured between an upper surface of the substrate and lower surfaces of the plurality of first capacitance layers.

[0017] In order to solve the above problem, according to the present disclosure, there is provided a capacitive element connected to an electronic circuit having a first node having a first impedance and a second node having a second impedance smaller than the first impedance, the capacitive element comprising: a substrate; a first metal layer formed on an upper surface of the substrate; a semiconductor layer stacked on the upper surface of the first metal layer and formed within the first metal layer in a planar view; a third metal layer stacked on the upper surface of the semiconductor layer and formed within the first metal layer in a planar view; and a fourth metal layer formed above the third metal layer, facing the first metal layer, and arranged so as to overlap in a planar view, wherein the outer peripheries of the first metal layer and the fourth metal layer are connected by a metal pin.

[0018] the electronic circuit is a display drive circuit, the display drive circuit comprising: a ramp voltage generation circuit that generates a ramp voltage whose voltage level changes over time; and a signal line voltage generation circuit that holds the voltage level of the ramp voltage at a timing according to the signal level of a pixel signal to generate a signal line voltage; the ramp voltage generation circuit comprising: an amplifier that outputs the ramp voltage; a load circuit arranged on a feedback path of the amplifier; a current generation circuit that controls a current flowing to the load circuit according to the ramp voltage and a reference voltage; a comparator that compares the ramp voltage with the reference voltage; and a holding unit that holds a comparison result signal of the comparator; the current generation circuit controls the current flowing to the load circuit based on the comparison result signal; the second node is formed at an inverting terminal of the comparator, the first node is formed at an output terminal of the comparator, and the holding unit is configured between the first node and the second node, and the holding unit may have the capacitive element.

[0019] the electronic circuit is a display drive circuit, the display drive circuit comprising: a ramp voltage generation circuit that generates a ramp voltage whose voltage level changes over time; and a signal line voltage generation circuit that generates a signal line voltage by holding the voltage level of the ramp voltage at a timing according to the signal level of a pixel signal; the ramp voltage generation circuit comprising: an amplifier that outputs the ramp voltage; a load circuit arranged on a feedback path of the amplifier; a correction circuit that corrects an offset potential of a reference potential supplied to a non-inverting terminal of the amplifier; and a current generation circuit that controls a current to be passed to the load circuit according to the ramp voltage and a second reference voltage; the first node is formed at the inverting terminal of the amplifier, and a second node is formed at the non-inverting terminal of the amplifier; the correction circuit is configured between the first node and the second node; and the correction circuit may comprise the capacitive element.

[0020] The electronic circuit may be an operational amplifier, and the first node may be formed at an output terminal of the operational amplifier, and the second node may be formed at a non-inverting terminal of the amplifier.

[0021] The electronic circuit may be a source follower circuit having a field effect transistor and a current source, the first node being formed at a source terminal of the field effect transistor, and the second node being formed at a gate terminal of the field effect transistor.

[0022] The electronic circuit may be a source follower circuit having a field effect transistor and a current source, the drain terminal of the field effect transistor being connected to a potential line and the source terminal being connected to the current source, the first node being formed at the source terminal of the field effect transistor, and the second node being formed at the gate terminal of the field effect transistor.

[0023] The electronic circuit may be a gate circuit, and the first node may be formed at an output terminal of the gate circuit, and the second node may be formed at an input terminal of the gate circuit.

[0024] In order to solve the above problems, according to the present disclosure, there is provided a display device comprising: a ramp voltage generation circuit that generates a ramp voltage whose voltage level changes over time; and a signal line voltage generation circuit that generates a signal line voltage by holding the voltage level of the ramp voltage at a timing according to the signal level of a pixel signal, wherein the ramp voltage generation circuit has: an amplifier that outputs the ramp voltage; a capacitive element arranged on a feedback path of the amplifier; a current generation circuit that controls a current to flow to the capacitive element according to the ramp voltage and a reference voltage; a comparator that compares the ramp voltage with the reference voltage; and a holding unit that holds a comparison result signal of the comparator, wherein the current generation circuit controls the current to flow to the capacitive element based on the comparison result signal; a second node is formed at an inverting terminal of the comparator; a first node is formed at an output terminal of the comparator; and the capacitive element is connected between the first node and the second node, and the capacitive element comprises: a substrate; A display device is provided, comprising: a first capacitance layer formed in a plane along the upper surface of the substrate and having a loop-shaped metal wiring; a comb-tooth-shaped first metal wiring connected to the loop-shaped metal wiring and formed within the loop-shaped metal wiring; and a comb-tooth-shaped second metal wiring formed within the loop-shaped metal wiring of the first metal wiring, wherein the first metal wiring is connected to the first node and the second metal wiring is connected to the second node.

[0025] 1 is a block diagram showing the overall configuration of a display device according to the present disclosure. FIG. 1 is a block diagram showing an example of the internal configuration of a horizontal logic circuit and a horizontal analog circuit. FIG. 2 is a voltage waveform diagram of a ramp voltage, a PWM signal, and a signal line voltage. FIG. 3 is a diagram schematically showing the wiring resistance of wiring connected to an output node of a lamp driving circuit. FIG. 3 is a block diagram showing the configuration of a main part of a display driving circuit. FIG. 4 is a time chart showing an example of operation of the lamp driving circuit for one horizontal line period. FIG. 5 is a diagram schematically showing a current flow when a ramp voltage is generated. FIG. 6 is a diagram schematically showing a current flow when a holding voltage is sampled. FIG. 7 is a diagram showing an example of the configuration of a MOM capacitance according to a comparative example. FIG. 8 is a diagram showing an example of the configuration of a MIM capacitance according to a comparative example. FIG. 9 is a diagram showing an example of the configuration of a first capacitor according to the present embodiment. FIG. 10 is a diagram showing an example of the configuration of a second capacitor according to a first modification of the first embodiment. FIG. 11 is a diagram showing an example of the configuration of a third capacitor according to a second modification of the first embodiment. FIG. 12 is a diagram showing another example of the configuration of the third capacitor. FIG. 13 is a diagram showing an example of the configuration of a fourth capacitor according to a third modification of the first embodiment. FIG. 14 is a block diagram showing the configuration of a main part of a display driving circuit according to a second embodiment. FIG. 15 is a time chart showing an example of operation of the lamp driving circuit according to the second embodiment. 37 is a diagram showing an example of an operating state when a differential current is sampled in a current control circuit. 38 is a diagram showing an example of an operating state when a differential current is cancelled in a current control circuit. 39 is a diagram showing an example of an operating state when a differential voltage is sampled in an output buffer. 39 is a diagram showing an example of an operating state when a differential voltage is cancelled in an output buffer. 40 is a circuit diagram of a circuit configuration according to a first specific example. 41 is a circuit diagram of a circuit configuration according to a second specific example. 42 is a circuit diagram of a third specific example. 43 is a circuit diagram of a fourth specific example. 44 is a diagram showing an example of a configuration of a pixel PIX. 45 is a diagram showing an example of a configuration of a pixel PIX. 46 is a diagram showing an example of a configuration of a pixel PIX. 47 is a diagram showing an example of a configuration of a pixel PIX. 48 is a diagram showing an example of a configuration of a pixel PIX. 49 is a diagram showing an example of a configuration of a pixel PIX. 49 is a diagram showing an example of a configuration of a pixel PIX. 50 is a diagram showing an example of an external appearance of a head mounted display. 51 is a diagram showing an example of an external appearance of another head mounted display. 52 is a diagram showing an example of an external appearance of a digital still camera. 53 is a rear view of FIG. 37. 1 is a diagram illustrating an example of the appearance of a television device, a diagram illustrating an example of the appearance of a smartphone, a diagram illustrating an example of the configuration of a vehicle to which the technology of the present disclosure is applied, and a diagram illustrating an example of the interior of the vehicle as seen from the left rear of the vehicle.

[0026] Hereinafter, embodiments of a display driver circuit and a display device will be described with reference to the drawings. The following description will focus on the main components of the display driver circuit and the display device, but the display driver circuit and the display device may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0027] First Embodiment Fig. 1 is a block diagram showing the overall configuration of a display device 1 according to the present disclosure. The display device 1 in Fig. 1 shows the overall configuration of, for example, a micro OLED (organic light emitting display). Note that, as will be described later, the display device 1 according to the present disclosure is not necessarily limited to a micro OLED, and can be applied to various display devices 1 such as a liquid crystal display device.

[0028] The display device 1 in FIG. 1 includes an input / output interface unit (I / O) 2, a gamma generation circuit 3, a power supply circuit 4, a high-speed interface unit (high-speed I / F) 5, a control circuit 6, a vertical logic circuit 7, a vertical analog circuit 8, a horizontal logic circuit 9, a horizontal analog circuit 10, and a pixel array unit 11.

[0029] 1 , at least the horizontal analog circuit 10 constitutes a display drive circuit 20. The display drive circuit 20 according to the present disclosure includes at least a portion of the configuration including the horizontal analog circuit 10 other than the pixel array unit 11 in the display device 1 of FIG.

[0030] The input / output interface unit 2 inputs and outputs pixel data, various control signals, etc. The gamma generation circuit 3 generates a gamma voltage for correcting the signal line voltage in the pixel array unit 11. The gamma generation circuit 3 is not an essential component and may be omitted.

[0031] The high-speed interface unit 5 inputs and outputs control signals and the like that need to be input and output at high speed, among the signals input and output by the input / output interface unit 2 .

[0032] The control circuit 6 generates various control signals for controlling each section in the display device 1. The control circuit 6 also controls the timing at which each pixel in the pixel array section 11 is driven.

[0033] The vertical logic circuit 7 controls the driving of a plurality of scanning lines arranged at regular intervals in the vertical direction (second direction) in the pixel array unit 11, based on a control signal from the control circuit 6. The vertical logic circuit 7 is composed of digital circuits such as logic gates and flip-flops.

[0034] The vertical analog circuit 8 drives a plurality of scanning lines in synchronization with the signal output from the vertical logic circuit 7. The vertical analog circuit 8 is composed of analog circuits such as transistors.

[0035] The horizontal logic circuit 9 performs control to drive a plurality of signal lines arranged at regular intervals in the horizontal direction (first direction) in the pixel array unit 11, based on a control signal from the control circuit 6. The horizontal logic circuit 9 is composed of digital circuits such as logic gates and flip-flops.

[0036] The horizontal analog circuit 10 drives a plurality of signal lines in synchronization with the signals output from the horizontal logic circuit 9. The horizontal analog circuit 10 is composed of analog circuits such as transistors.

[0037] The pixel array section 11 has a plurality of scanning lines arranged at regular intervals in the vertical direction, a plurality of signal lines arranged at regular intervals in the horizontal direction, and a plurality of pixels arranged at the points where the plurality of scanning lines and the plurality of signal lines intersect.

[0038] 2 is a block diagram showing an example of the internal configuration of the horizontal logic circuit 9 and the horizontal analog circuit 10. The horizontal logic circuit 9 has a shift register (S / R) 13, a plurality of first latches (1st latches) 14, a plurality of second latches (2nd latches) 15, a plurality of digital comparators 16, and a plurality of PWM generation circuits 18. The first latches 14, the second latches 15, the digital comparators 16, and the PWM generation circuits 18 are provided for each signal line.

[0039] The shift register 13 sequentially shifts and outputs externally input video data pixel by pixel. The first latches 14 sequentially hold the pixel data output from the shift register 13. The second latches 15 simultaneously hold the pixel data at the timing when the first latches 14 hold the corresponding pixel data.

[0040] The plurality of digital comparators 16 compare the data held in the plurality of second latches 15 with the count value of the synchronous counter 17 to determine whether or not they match, and output a signal indicating the comparison result.

[0041] The PWM generating circuits 18 start generating pulse signals in response to the PWMST signal, and generate PWM signals having pulse widths until a match is detected by the corresponding digital comparators 16 .

[0042] The horizontal analog circuit 10 includes a plurality of level shifters 19 , a lamp driving circuit 21 , and a signal line voltage generating circuit 22 .

[0043] The plurality of level shifters 19 convert the voltage levels of the plurality of PWM signals.

[0044] The lamp driving circuit 21 generates a ramp voltage whose voltage level changes over time. The lamp driving circuit 21 is a characteristic part of the display device 1 according to the present disclosure, and will be described in detail later.

[0045] The signal line voltage generation circuit 22 generates the signal line voltage by maintaining the voltage level of the ramp voltage at a timing corresponding to the signal level of the pixel signal. More specifically, the signal line voltage generation circuit 22 maintains the voltage level of the ramp voltage at the falling edge of the PWM signal.

[0046] The signal line voltage generation circuit 22 has a plurality of PWM switches 23 connected to a plurality of signal lines. One end of each PWM switch 23 is connected to a corresponding signal line, and a ramp voltage is input to the other end of each PWM switch 23. Each PWM switch 23 is turned on when the corresponding PWM signal is at a high level, and turned off when the corresponding PWM signal is at a low level.

[0047] 3 is a voltage waveform diagram of a ramp voltage, a PWM signal, and a signal line voltage. As shown in FIG. 3, the ramp voltage w1 is a voltage signal whose voltage level changes linearly for each horizontal (1H) line. The voltage level of the ramp voltage w1 in FIG. 3 decreases linearly for each horizontal line, but as will be described later, a ramp voltage whose voltage level increases linearly, a triangular ramp voltage, or a ramp voltage whose voltage level changes nonlinearly can also be applied.

[0048] Each PWM switch 23 in the signal line voltage generation circuit 22 is on while the corresponding PWM signal is at high level, and supplies a ramp voltage to the corresponding signal line. Each PWM switch 23 is turned off at timing t1 or t2 when the PWM signal transitions to low level, and the corresponding signal line maintains the voltage level of the ramp voltage at that timing, which becomes the signal line voltage w3 or w4.

[0049] 4 is a diagram schematically showing wiring resistances 29 of wiring (hereinafter referred to as lamp wiring RL) connected to the output node of the lamp driving circuit 100. As shown in the figure, wiring resistances 29 exist between two connection nodes between two adjacent signal lines and the lamp wiring RL. Therefore, multiple wiring resistances 29 are connected in series on the lamp wiring RL, and voltage drops occur due to these wiring resistances 29, so the voltage of the signal line farther from the lamp driving circuit 100 is lower than the voltage of the signal line closer to the lamp driving circuit 100.

[0050] One way to reduce the wiring resistance 29 on the lamp wiring RL is to make the lamp wiring RL thicker. Fig. 5 is a diagram showing the relationship between the number of signal lines in the pixel array section 11, i.e., the display resolution, and the width of the lamp wiring RL. As shown in the figure, the higher the display resolution, the greater the need to make the lamp wiring RL thicker. If the width of the lamp wiring RL is thicker, the peripheral circuit area will increase.

[0051] The display driver circuit 20 according to the present disclosure aims to solve the above-mentioned problems.

[0052] Fig. 5 is a block diagram showing the configuration of the main parts of a display drive circuit 20 according to the first embodiment. The display drive circuit 20 in Fig. 5 includes at least the horizontal analog circuit 10 in Fig. 1. More specifically, the horizontal analog circuit 10 in Fig. 5 includes a lamp drive circuit 21 and a signal line voltage generation circuit 22.

[0053] The lamp driving circuit 21 includes an output buffer 31, a current generating circuit 32, and a current control circuit .

[0054] The output buffer 31 generates and outputs a ramp voltage. An output node VOUT of the output buffer 31 is connected to a ramp wiring RL, and the ramp wiring RL is connected to a PWM switch 23 that constitutes a signal line voltage generation circuit 22.

[0055] The output buffer 31 includes an amplifier 41 , a load circuit 42 , a PWM switch 33 , and a PCHG switch 44 .

[0056] The amplifier 41 compares the ramp voltage with a precharge voltage (reference voltage) VGO and outputs a ramp voltage that is a comparison result signal. The amplifier 41 is a differential amplifier having a first input node to which the precharge voltage VGO is supplied, a second input node to which a feedback voltage (ramp voltage) is supplied via a load circuit 42, and an output node that outputs a ramp voltage having a voltage level that corresponds to the voltage difference between the reference voltage and the feedback voltage (ramp voltage).

[0057] The load circuit 42 is disposed on the feedback path of the amplifier 41. More specifically, the load circuit 42 is connected between the second input node and the output node. As will be described later, the load circuit 42 is connected between the node nA and the node nB, and includes at least a capacitor 42a and a resistor element 42b. The capacitor 42a is one of the characteristic features of this embodiment, and has a configuration in which one end of the capacitor 42a has a different parasitic capacitance from the other end.

[0058] For example, the parasitic capacitances on the node nA side and the node nB side are different. The node nA side on the variable current source 35 side has a high impedance, and the influence of the parasitic capacitance is suppressed compared to the node nB side. On the other hand, the node nB side has a lower impedance than the node nA side, and the parasitic capacitance affects the output of the signal line voltage generating circuit 22. For this reason, the parasitic capacitance on the node nB side of the capacitor 42a is configured to be lower than the parasitic capacitance on the node nA side. A detailed configuration example of the capacitor 42a will be described later.

[0059] The PCHG switch 44 is turned on / off based on the logic of a precharge (PRCG) signal. The PCHG switch 44 is connected in parallel to the load circuit 42. The PCHG switch 44 is turned on for a predetermined period immediately after one horizontal line period starts, and short-circuits both ends of the load circuit 42, i.e., the second node and the output node of the amplifier 41.

[0060] The PWM switch 33 is turned on / off based on the logic of the RAMPEN signal. The PWM switch 33 is connected between the output node of the current generating circuit 32 and the second input node of the amplifier 41. When the PWM switch 33 is turned on, the current output from the current generating circuit 32 flows to the load circuit 42, and the voltage level of the ramp voltage drops. When the PWM switch 33 is turned off, no current flows from the current generating circuit 32 to the load circuit 42, and the voltage level of the ramp voltage is maintained.

[0061] The current generating circuit 32 includes, for example, a PWM switch 33 and a variable current source 35. The PWM switch 33 is turned on / off based on the logic of a RAMPEN signal. The PWM switch 33 is connected between the output node of the variable current source 35 and a second input node of the amplifier 41. When the PWM switch 33 is turned on, the current output from the variable current source 35 flows to the load circuit 42, and the voltage level of the ramp voltage drops. When the PWM switch 33 is turned off, no current flows from the current generating circuit 32 to the load circuit 42, and the voltage level of the ramp voltage is maintained.

[0062] The variable current source 35 controls the current flowing to the load circuit 42 based on the comparison result signal output from the current control circuit 36. One end of the variable current source 35 is connected to the power supply voltage node, and the other end is connected to one end of the PWM switch 33. The current from the PWM switch 33c of the variable current source 35 flows to the load circuit 42 via the PWM switch 33, and the ramp voltage that is the output voltage of the output buffer 31 decreases over time.

[0063] The PCHG switch 44 is turned on / off based on the logic of a precharge (PRCG) signal. The PCHG switch 44 is connected in parallel to the load circuit 42. The PCHG switch 44 is turned on for a predetermined period immediately after one horizontal line period starts, and short-circuits both ends of the load circuit 42, i.e., the second node and the output node of the amplifier 41.

[0064] The current control circuit 36 ​​controls the current generated by the current generation circuit 32 based on the voltage difference between the ramp voltage and the reference voltage VG255. The current control circuit 36 ​​has an SMPL switch 34, a comparator 36a, a holding unit 37, and an XEN switch 38. When the XEN switch 38 is turned off and the SMPL switch 34 is turned on, the comparator 36a compares the ramp voltage with the reference voltage VG255 and outputs a comparison result signal. The holding unit 37 holds the comparison result signal output from the comparator 36a.

[0065] The holding unit 37 is connected between the node nA1 and the node nB1 and includes at least a capacitor 37 a and a resistive element 38 b. The capacitor 37 a is one of the characteristic features of this embodiment, and has a configuration in which one end of the capacitor 37 a has a different parasitic capacitance from the other end.

[0066] For example, the parasitic capacitances on the node nA side and the node nB1 side are different. The node n1A side of the variable current source 35 has a high impedance, and the influence of the parasitic capacitance is suppressed compared to the node nB1 side. On the other hand, the node nB1 side has a lower impedance than the node nA1 side, and the parasitic capacitance affects the output of the signal line voltage generating circuit 22. For this reason, the parasitic capacitance on the node nB side of the capacitor 37a is configured to be lower than the parasitic capacitance on the node nA side. This suppresses the parasitic capacitance on the non-inverting input terminal (+) side of the comparator 36a, and improves the accuracy of the control operation of the current control circuit 36. A detailed configuration example of the capacitor 37a will be described later.

[0067] An SMPL switch 34 is connected between the output buffer 31 and the comparator 36a via a resistor R2. The SMPL switch 34 turns on / off based on the logic of the SMPL signal. The SMPL switch 34 is on for a predetermined period after the PWM signal transitions from high level to low level within one horizontal line period. When the SMPL switch 34 is on, the ramp voltage output from the output buffer 31 is input to the comparator 36a via the SMPL switch 34. The comparator 36a compares the ramp voltage with a reference voltage VG255 only while the SMPL switch 34 is on and outputs a comparison result signal. While the SMPL switch 34 is off, the holding unit 37 continues to hold the comparison result signal output by the comparator 36a when the SMPL switch 34 was last turned on.

[0068] Fig. 6 is a time chart showing an example of the operation of the lamp driving circuit 21 during one horizontal line period. The horizontal axis represents time, and the vertical axis represents the PCHG signal, PWM signal, SMPL signal, I_PWM current, and RAMP wave voltage. Fig. 7 is a diagram showing a schematic diagram of the current flow when the output buffer 31 generates a RAMP wave voltage (ramp wave voltage). Fig. 8 is a diagram showing a schematic diagram of the current flow when the current control circuit 36 ​​samples the holding voltage.

[0069] 6, at time t3, the PCHG signal goes high, turning on the PCHG switch 44. This short-circuits the second input node and output node of the amplifier 41 in the output buffer 31, causing the ramp voltage to rise from the reference potential VG255 to the precharge voltage VGO.

[0070] Next, at time t4, the PCHG signal goes low, turning off the PCHG switch 44. At the same time, the PWM signal goes high, turning on the PWM switch 33. As a result, as shown in FIG. 7 , the amplifier 41 compares the ramp voltage with the precharge voltage (reference voltage) VGO and outputs a ramp voltage, which is a comparison result signal. The amplifier 41 outputs a ramp voltage, the voltage level of which corresponds to the voltage difference between the reference voltage and the feedback voltage (ramp voltage), to a first input node to which the precharge voltage VGO is supplied and a second input node to which a feedback voltage (ramp voltage) is supplied via a load circuit 42. As a result, the current I from the variable current source 35 flows to the load circuit 42 via the PWM switch 33, and the voltage level of the ramp voltage output from the amplifier 41 decreases over time. Thus, while the PWM switch 33 is on, the voltage level of the ramp voltage changes over time.

[0071] Next, at time t5, the PWM signal goes low, the PWM switch 33 turns off, and the current I of the variable current source 35 that flowed during the period tPWM between times t4 and t5 is cut off. As a result, the ramp wave voltage becomes the reference potential VG255 again.

[0072] Next, at time t5, the SMPL signal goes high, turning on the SMPL switch 34. As a result, as shown in FIG. 8 , the output voltage VOUT is controlled depending on whether the input voltage VIN in the current control circuit 36 ​​is higher or lower than the reference voltage VG255. When the input voltage VIN is higher than the reference voltage VG255, the output voltage VOUT is lowered. When the input voltage VIN is higher than the reference voltage VG255, the output voltage VOUT is lowered. As a result, when the input voltage VIN matches the reference voltage VG255, the output voltage VOUT stabilizes. Then, at time t7, the SMPL switch 34 is turned off. While the SMPL switch 34 is off, the holding unit 37 continues to hold the comparison result signal output by the comparator 36a when the SMPL switch 34 was turned on immediately before. The comparison result signal held in the holding unit 37 is used to determine the current flowing from the variable current source 35 during the next horizontal line period 1H. The same process is repeated during the next horizontal line period.

[0073] In this way, the load circuit 42 is placed on the feedback path of the amplifier 41 that outputs the ramp voltage, and the current flowing through the load circuit 42 is variably controlled based on the voltage difference between the ramp voltage and the reference voltage VG255. As a result, even if fluctuations occur in the coupling capacitance between adjacent signal lines, the current flowing through the load circuit 42 can be adjusted in accordance with the fluctuations in the ramp voltage due to the coupling capacitance, thereby suppressing variations in the ramp voltage. In this operation, the parasitic capacitance on the ramp wiring RL side of 42a is reduced, thereby increasing the accuracy of the processing operation.

[0074] An example of the configuration of a capacitor according to a comparative example will be described with reference to Figures 9 and 10. Figure 9 shows an example of the configuration of a MOM (Metal-Oxide-Metal) capacitor according to a comparative example. Figure 9(a) is a plan view, and Figure 9(b) is a cross-sectional view taken along line AA in Figure 9(a).

[0075] 9A, the MOM capacitor of the comparative example is composed of a first metal wiring Mfa and a second metal wiring Mfb. The first metal wiring Mfa and the second metal wiring Mfb are, for example, metal wirings. In FIG. 9A, metal wirings Msa and Msb and a metal layer Mu are also shown.

[0076] As shown in FIG. 9B, the first metal wiring Mfa and the second metal wiring Mfb are configured with three layers M1, M2, and M3. The MOM capacitor of the comparative example is configured on top of a substrate SUB and a shallow trench isolation STI (shallow trench isolation). The substrate SUB is, for example, a semiconductor substrate. The shallow trench isolation STI is, for example, an example of an element isolation structure.

[0077] The first metal wiring Mfa and the second metal wiring Mfb of each layer are connected by, for example, metal Mpin. Terminal Ta is connected to, for example, nodes nA and nA1 (see FIG. 5), and terminal TB is connected to, for example, nodes nB and nB1. In this embodiment, the metals in the connection relationship are described as being connected by metal Mpin, but this is not limited to this. For example, they may be connected by capacitance wiring, metal vias, etc. Furthermore, the metal Mpin may be configured in a planar shape. In this case, a metal wall surface is formed. Furthermore, the description is also given assuming that an interlayer insulating film is configured between each wiring layer, but this is not limited to this.

[0078] In the MOM capacitance of the comparative example, a parasitic capacitance Cpa(side) occurs between the first metal wiring Mfa and the metal wiring Msa, a parasitic capacitance Cpa(sub) occurs between the first metal wiring Mfa and the substrate SUB, and a parasitic capacitance Cpa(upper) occurs between the first metal wiring Mfa and the metal layer Mu.

[0079] Similarly, in the MOM capacitance of the comparative example, a parasitic capacitance Cpb(side) occurs between the second metal wiring Mfb and the metal wiring Msa. Furthermore, a parasitic capacitance Cpb(sub) occurs between the second metal wiring Mfb and the substrate SUB. Furthermore, a parasitic capacitance Cpb(upper) occurs between the second metal wiring Mfb and the metal layer Mu. These parasitic capacitances Cpb(side), Cpb(sub), and Cpb(upper) occurring on the terminal TB side affect the output of the signal line voltage generating circuit 22. Alternatively, they affect the control operation of the current control circuit 36.

[0080] 10A and 10B are diagrams showing an example of the configuration of a MIM (Metal-Oxide-Metal) capacitor according to a comparative example, in which Fig. 10A is a plan view and Fig. 10B is a cross-sectional view taken along line AA in Fig. 10A.

[0081] As shown in Figure 10(a), the MIM capacitor of the comparative example is composed of a first metal layer Mba, a second metal layer Mbb, and a semiconductor layer Sb. A terminal Ta is connected to the first metal layer Mba, and a terminal Tb is connected to the second metal layer Mbb. Figure 10(a) also shows metal wiring Msa and Msb. The terminal Ta is connected to, for example, nodes nA and nA1 (see Figure 5), and the terminal Tb is connected to, for example, nodes nB and nB1.

[0082] 10B, a first metal layer Mba, a semiconductor layer Sb, and a second metal layer Mbb are stacked. The MIM capacitor of the comparative example is formed above a substrate SUB and a shallow trench isolation STI.

[0083] In the MIM capacitance of the comparative example, a parasitic capacitance Cpa(side) occurs between the first metal layer Mba and the metal wiring Msa. On the other hand, in the MOM capacitance of the comparative example, a parasitic capacitance Cpb(side) occurs between the terminal Tb and the metal wiring Msb. Furthermore, a parasitic capacitance Cpb(sub) occurs between the second metal layer Mbb and the substrate SUB. These parasitic capacitances Cpb(side) and Cpb(sub) occurring on the terminal TB side affect the output of the signal line voltage generating circuit 22, or affect the control operation of the current control circuit 36.

[0084] 11A and 11B are diagrams showing an example of the configuration of a first capacitor 120 according to this embodiment, in which Fig. 11A is a plan view and Fig. 11B is a cross-sectional view taken along line AA in Fig. 11A.

[0085] 11A, the first capacitor 120 is formed on a semiconductor substrate SUB. An electronic circuit, for example, is formed on the semiconductor substrate SUB. For example, at least a part of the configuration of the lamp driving circuit 21 is formed as the electronic circuit.

[0086] The first capacitor 120 is composed of a plurality of first metal wirings Mfa, a plurality of second metal wirings Mfb, a first metal layer Mba, a semiconductor layer Sb, a second metal layer Mbb, and a third metal layer Mba2. The first metal wirings Mfa and the second metal wirings Mfb are, for example, metal wirings.

[0087] The first metal wiring Mfa is formed in a plane along the upper surface of the substrate SUB and is composed of a loop-shaped metal wiring and a comb-shaped metal wiring connected to the loop-shaped metal wiring and formed within the loop-shaped metal wiring. The second metal wiring Mfb is a comb-shaped metal wiring formed within the loop-shaped metal wiring of the first metal wiring Mfa. The first metal wiring Mfa and the second metal wiring Mfb constitute the first capacitance layer ML1. In this way, in the first capacitance layer ML1, the periphery of the second metal wiring Mfb is surrounded by the first metal wiring Mfa within the same plane (XY plane).

[0088] The first metal wiring Mfa and the second metal wiring Mfb are formed of, for example, tungsten (W). The first metal wiring Mfa and the second metal wiring Mfb are not limited to tungsten W. The metal wiring layer M1 can also be formed of materials such as TiN (titanium nitride), Ti / TiN (a laminated film of titanium and titanium nitride), aluminum Al, copper Cu, etc.

[0089] The first metal layer Mba, the second metal layer Mbb, and the third metal layer Mba2 are formed of, for example, tungsten (W), and may also be formed of materials such as TiN (titanium nitride), Ti / TiN (a laminated film of titanium and titanium nitride), aluminum Al, or copper Cu.

[0090] 11B, the first capacitance layer is composed of three layers ML1, ML2, and ML3. Furthermore, a first metal layer Mba1, a semiconductor layer Sb, a second metal layer Mbb, and a third metal layer Mba2 are arranged in this order from the substrate SUB. In this case, the first metal layer Mba1, the semiconductor layer Sb, and the second metal layer Mbb are stacked, and a plurality of first capacitance layers ML1, ML2, and ML3 are arranged between the second metal layer Mbb and the third metal layer Mba2. Furthermore, for example, an interlayer insulating film is arranged between the plurality of first capacitance layers ML1, ML2, and ML3 and the second metal layer Mbb and the third metal layer Mba2.

[0091] More specifically, the semiconductor layer Sb is stacked on the top surface of the first metal layer Mba1 and is configured within the loop-shaped metal wiring of the first metal wiring Mfa in plan view. The second metal layer Mbb is stacked on the top surface of the semiconductor layer Sb and is configured within the loop-shaped metal wiring of the first metal wiring Mfa in plan view.

[0092] As described above, the first metal wiring Mfa is composed of a loop-shaped wiring and a comb-shaped wiring formed within the loop-shaped wiring. The second metal wiring Mfb is formed in the same phase as the first metal wiring Mfa and is composed of a comb-shaped wiring. The comb-shaped wiring of the first metal wiring Mfa and the comb-shaped wiring of the second metal wiring Mfb are opposed to each other in the same phase. Furthermore, the second metal wiring Mfb is formed within the loop-shaped wiring of the first metal wiring Mfa.

[0093] In plan view, the loop-shaped metal wiring of the first metal wiring Mfa in the multiple first capacitance layers ML1, ML2, and ML3 is arranged to overlap. The loop-shaped metal wiring of the first metal wiring Mfa in the multiple first capacitance layers ML1, ML2, and ML3 is connected to the first metal layer Mba1 by a metal pin Mpin located within the loop-shaped metal wiring in plan view. Similarly, the loop-shaped metal wiring of the first metal wiring Mfa in the multiple first capacitance layers ML1, ML2, and ML3 is connected to the third metal layer Mba2 by a metal pin Mpin located within the loop-shaped metal wiring in plan view.

[0094] The first metal wiring Mfa and the second metal wiring Mfb of the first capacitance layer form a MOM capacitance, and the first metal layer Mba, the semiconductor layer Sb, and the second metal layer Mbb form an MIM capacitance.

[0095] The upper sides of the first metal wirings Mfa are connected to the third metal layer Mba2 by metal pins Mpin, and the lower sides are connected to the first metal layer Mba by metal pins Mpin. Similarly, the first metal wirings Mfa are connected to each other by metal pins Mpin.

[0096] On the other hand, the second metal wirings Mfb are connected to the second metal layer Mbb by metal pins Mpin. Similarly, the second metal wirings Mfb are connected to the second metal layer Mbb by metal pins Mpin.

[0097] As can be seen from these, the second metal wirings Mfb and the second metal layer Mbb are surrounded above and below by the third metal layer Mba2 and the first metal layer Mba. In this way, the second metal wirings Mfb and the second metal layer Mbb are surrounded by the first metal wirings Mfa, the first metal layer Mba, and the third metal layer Mba2, and are electromagnetically shielded.

[0098] Terminal TA is connected to any of the plurality of first metal wirings Mfa, the first metal layer Mba, or the third metal layer Mba2, and terminal TB is connected to any of the plurality of second metal wirings Mfb or the second metal layer Mbb, so that the parasitic capacitance on the terminal TB side is reduced more than the parasitic capacitance on the terminal TA side.

[0099] The terminal TA is connected to a node nA of the electronic circuit having a first impedance, and the terminal TB is connected to a node nB of the electronic circuit having a second impedance, the first impedance being higher than the second impedance.

[0100] 5, the capacitor 42a is configured with a first capacitor 120, with a terminal TA connected to the node nA side and a terminal TB connected to the node nB side. This reduces the parasitic capacitance on the node nB side and suppresses the effect on the output of the signal line voltage generating circuit 22. The capacitance of the first capacitor 120 can be changed depending on the purpose.

[0101] Similarly, the capacitor 34a is configured with the first capacitor 120, with the terminal TA connected to the node nA1 side and the terminal TB connected to the node nB1 side, thereby reducing the parasitic capacitance on the node nB1 side and suppressing the influence on the control operation of the current control circuit 36.

[0102] (First Modification of First Embodiment) The second capacitor 122 according to the first modification of the first embodiment differs from the first capacitor 120 in that the second capacitor 122 does not have a plurality of first metal wirings Mfa and a plurality of second metal wirings Mfb. The differences from the display device 1 of the first embodiment will be described below.

[0103] 12 is a diagram showing an example of the configuration of a second capacitor 122 according to Modification 1 of the first embodiment. Fig. 12 is a cross-sectional view. The second capacitor 122 is composed of a first metal layer Mba, a semiconductor layer Sb, a second metal layer Mbb, and a third metal layer Mba2. The second capacitor 122 differs from the first capacitor 120 in that it does not have a plurality of first metal wirings Mfa and a plurality of second metal wirings Mfb.

[0104] Also, a first metal layer Mba1, a semiconductor layer Sb, a second metal layer Mbb, and a third metal layer Mba2 are arranged in this order from the substrate SUB. In this case, the first metal layer Mba, the semiconductor layer Sb, and the second metal layer Mbb are stacked to form an MIM capacitor. The first metal layer Mba, the semiconductor layer Sb, and the second metal layer Mbb are formed, for example, within an interlayer insulating film.

[0105] More specifically, the semiconductor layer Sb is stacked on the top surface of the first metal layer Mba1 and is configured within the first metal layer Mba1 in a planar view. The second metal layer Mbb is stacked on the top surface of the semiconductor layer Sb and is configured within the first metal layer Mba1 in a planar view. The third metal layer Mba2 is configured above the second metal layer Mbb and is arranged opposite the first metal layer Mba1 so as to overlap with it in a planar view. The outer peripheries of the first metal layer Mba1 and the third metal layer Mba2 are connected by metal pins.

[0106] Terminal TA is connected to any of the plurality of first metal wirings Mfa, the first metal layer Mba, or the third metal layer Mba2, and terminal TB is connected to any of the plurality of second metal wirings Mfb or the second metal layer Mbb. As can be seen from this, the parasitic capacitance on the terminal TB side is suppressed more than the parasitic capacitance on the terminal TA side.

[0107] 5, the capacitor 42a is configured with a first capacitor 120, with a terminal TA connected to the node nA side and a terminal TB connected to the node nB side. This reduces the parasitic capacitance on the node nB side and suppresses the effect on the output of the signal line voltage generating circuit 22. The capacitance of the first capacitor 120 can be changed depending on the purpose.

[0108] Similarly, the capacitor 34a is configured with the first capacitor 120, with the terminal TA connected to the node nA1 side and the terminal TB connected to the node nB1 side, thereby reducing the parasitic capacitance on the node nB1 side and suppressing the influence on the control operation of the current control circuit 36.

[0109] (Modification 2 of First Embodiment) A second capacitor 124 according to Modification 2 of the first embodiment differs from the first capacitor 120 in that it does not constitute an MIM capacitance. The differences from the display device 1 of the first embodiment will be described below.

[0110] 13 is a diagram showing an example of the configuration of a third capacitor 124 according to Modification 2 of the first embodiment. FIG. 13 is a cross-sectional view.

[0111] 13, the third capacitor 124 is composed of a plurality of first metal wirings Mfa, a plurality of second metal wirings Mfb, a fourth metal layer Mba3, and a fifth metal layer Mba4. The first metal wirings Mfa are formed in a plane along the upper surface of the substrate SUB and are composed of loop-shaped metal wirings and comb-shaped metal wirings connected to the loop-shaped metal wirings and formed within the loop-shaped metal wirings. The second metal wirings Mfb are comb-shaped metal wirings formed within the loop-shaped metal wirings of the first metal wirings Mfa. The first metal wirings Mfa and second metal wirings Mfb constitute a first capacitance layer ML1.

[0112] 13, the first capacitance layer is composed of three layers ML1, ML2, and ML3. For example, an interlayer insulating film is formed between the plurality of first capacitance layers ML1, ML2, and ML3 and the fourth and fifth metal layers Mba3 and Mba4. In this manner, the fifth metal layer Mba4, the plurality of first capacitance layers ML1, ML2, and ML3, and the fourth metal layer Mba3 are arranged in this order from the substrate SUB. Each of the plurality of first capacitance layers ML1, ML2, and ML3 constitutes a MOM capacitance.

[0113] The upper sides of the plurality of first metal interconnects Mfa are connected to the fourth metal layer Mba3, and the lower sides are connected to the fifth metal layer Mba4. As can be seen from this, the plurality of second metal interconnects Mfb are surrounded above and below by the fourth metal layer Mba3 and the fifth metal layer Mba4. In this way, the plurality of second metal interconnects Mfb are surrounded by the plurality of first metal interconnects Mfa, the fourth metal layer Mba3, and the fifth metal layer Mba4, and are electromagnetically shielded.

[0114] Terminal TA is connected to any of the plurality of first metal wirings Mfa, the fourth metal layer Mba3, or the fifth metal layer Mba4, and terminal TB is connected to any of the plurality of second metal wirings Mfb, thereby reducing the parasitic capacitance on the terminal TB side compared to the parasitic capacitance on the terminal TA side.

[0115] 14 is a configuration diagram of a capacitor 124a showing another configuration example of the third capacitor 124 according to the second modification of the first embodiment. FIG. 14 is a cross-sectional view. As shown in FIG. 14, an insulating layer IL or the like may be formed between the third capacitor 124 and the shallow trench isolation STI. In this manner, the distance between the fifth metal layer Mba4 and the substrate SUB can be changed depending on the purpose.

[0116] 5, the capacitor 42a is configured with a first capacitor 120, with a terminal TA connected to the node nA side and a terminal TB connected to the node nB side. This reduces the parasitic capacitance on the node nB side and suppresses the effect on the output of the signal line voltage generating circuit 22. The capacitance of the first capacitor 120 can be changed depending on the purpose.

[0117] Similarly, the capacitor 34a is configured with the first capacitor 120, with the terminal TA connected to the node nA1 side and the terminal TB connected to the node nB1 side, thereby reducing the parasitic capacitance on the node nB1 side and suppressing the influence on the control operation of the current control circuit 36.

[0118] (Third Modification of First Embodiment) A fourth capacitor 126 according to a third modification of the first embodiment differs from the first capacitor 120 in that it does not constitute an MIM capacitance and is connected to the well WELL. The differences from the display device 1 of the first embodiment will be described below.

[0119] 15 is a cross-sectional view illustrating an example of the configuration of the fourth capacitor 126 according to the third modification of the first embodiment.

[0120] 15, the fourth capacitor 126 is composed of a plurality of first metal wirings Mfa, a plurality of second metal wirings Mfb, a fourth metal layer Mba3, and a well WELL. The first metal wirings Mfa and the second metal wirings Mfb are, for example, metal wirings. Furthermore, within the same plane (XY plane), the periphery of the second metal wiring Mfb is surrounded by the first metal wiring Mfa. The first metal wirings Mfa and the second metal wirings Mfb constitute a MOM capacitance. These first metal wirings Mfa and second metal wirings Mfb constitute a first capacitance layer ML1. The well WELL is a P-type or N-type well.

[0121] The first capacitance layer is composed of three layers ML1, ML2, and ML3. An interlayer insulating film, for example, is formed between the multiple first capacitance layers ML1, ML2, and ML3, the fourth metal layer Mba3, and the insulating layer IL. Also, a well WELL, the insulating layer IL, the multiple first capacitance layers ML1, ML2, and ML3, and the fourth metal layer Mba3 are arranged in this order from the substrate SUB. The first metal wiring Mfa and the second metal wiring Mfb form a MOM capacitance. The first metal wiring Mfa and the well WELL are connected via shallow trench isolation STI and metal pins Mpin.

[0122] The upper sides of the plurality of first metal interconnects Mfa are connected to the fourth metal layer Mba3. As can be seen from these, the plurality of second metal interconnects Mfb are surrounded above and below by the fourth metal layer Mba3 and the well WELL. In this way, the plurality of second metal interconnects Mfb are surrounded by the plurality of first metal interconnects Mfa, the fourth metal layer Mba3, and the well WELL, and are electromagnetically shielded.

[0123] Terminal TA is connected to any of the plurality of first metal wirings Mfa and the fourth metal layer Mba3, and terminal TB is connected to any of the plurality of second metal wirings Mfb, so that the parasitic capacitance on the terminal TB side is reduced more than the parasitic capacitance on the terminal TA side.

[0124] 5, the capacitor 42a is configured with a first capacitor 120, with a terminal TA connected to the node nA side and a terminal TB connected to the node nB side. This reduces the parasitic capacitance on the node nB side and suppresses the effect on the output of the signal line voltage generating circuit 22. The capacitance of the first capacitor 120 can be changed depending on the purpose.

[0125] Similarly, the capacitor 34a is configured with the first capacitor 120, with the terminal TA connected to the node nA1 side and the terminal TB connected to the node nB1 side, thereby reducing the parasitic capacitance on the node nB1 side and suppressing the influence on the control operation of the current control circuit 36.

[0126] Second Embodiment A display device 1 according to a second embodiment differs from the display device 1 of the first embodiment and the first to third modifications of the first embodiment in that the output buffer 31 of the lamp drive circuit 21 and the current control circuit 36 ​​further include an offset correction circuit. The differences from the display device 1 of the first embodiment and the first to third modifications of the first embodiment will be described below.

[0127] Fig. 16 is a block diagram showing the configuration of the main parts of a display drive circuit 20 according to the second embodiment. The display drive circuit 20 in Fig. 16 includes at least the horizontal analog circuit 10 in Fig. 1. More specifically, the horizontal analog circuit 10 in Fig. 16 has a lamp drive circuit 21 and a signal line voltage generation circuit 22. The lamp drive circuit 21 has an output buffer 31, a current generation circuit 32, and a current control circuit 36.

[0128] The current generating circuit 32 according to the second embodiment differs from the current generating circuit 32 according to the first embodiment in that it further includes a first correction circuit 310. This first correction circuit 310 holds and cancels the offset voltage ΔV of the second node (inverting terminal) of the amplifier 41. That is, the correction circuit 310 includes an off-hold switch 43 a, an off-sample switch 43 b, a third capacitor 43 c, and a second off-sample switch 43 d.

[0129] The off-hold switch 43a has one end supplied with a precharge voltage (reference voltage) VGO and the other end connected to the node nA2, and is turned on / off based on the logic of an off-sample (OFS_HOLD) signal.

[0130] The off-sample switch 43b has one end supplied with a precharge voltage (reference voltage) VGO, and the other end connected via a node nB2 to the first node (non-inverting terminal) of the amplifier 41. The off-sample switch 43b is turned on / off based on the logic of an off-sample (OFS_SMPL) signal.

[0131] The third capacitor 43c has one end connected to the node nA2 and the other end connected to the node nB2. The third capacitor 43c has the configuration of any of the capacitors 120, 122, 124, 124a, and 126 (see FIGS. 11 to 15 ) described above. The node nA2 is on the high-impedance side, and the terminal TA is connected to the node nA2, and the terminal TB is connected to the node nB2. This reduces the parasitic capacitance of the first node (non-inverting terminal) of the amplifier 41, and prevents a decrease in the driving accuracy of the lamp driving circuit 21.

[0132] One end of second off sample switch 43d is connected to node nA2, and the other end is connected to the first node (non-inverting terminal) of amplifier 41. Second off sample switch 43d is turned on / off based on the logic of an off sample (OFS_SMPL) signal.

[0133] The current control circuit 36 ​​according to the second embodiment differs from the current control circuit 36 ​​according to the first embodiment in that it further includes a second correction circuit 360. This second correction circuit 360 performs an offset cancellation operation by current sampling of the load current source in order to suppress fluctuations in the input voltage VIN of the current control circuit 36. That is, the second correction circuit 360 includes an XCS switch 39a, a CS switch 39b, a second XCS switch 39c, a second CS switch 39d, and a variable current source 39e.

[0134] One end of the XCS switch 39a is connected to the inverting terminal (-) of the comparator 36a, and the other end is connected to the resistor R2. The XCS switch 39a is turned on and off based on the logic of the CS (CS) signal.

[0135] One end of the CS switch 39b is connected to the non-inverting terminal (+) of the comparator 36a, and the other end is connected to the resistor R2. The CS switch 39b is turned on / off based on the logic of the CS signal.

[0136] The second XCS switch 39c has one end connected to the output terminal of the comparator 36a and the other end connected to the output terminal VOUT. The XCS switch 39c is turned on / off based on the logic of the CS signal.

[0137] The second CS switch 39d has one end connected to the output terminal of the comparator 36a and the other end connected to a variable current source 39e. The CS switch 39d is turned on / off based on the logic of the CS signal.

[0138] The variable current source 39e has one end connected to the output terminal of the comparator 36a and the other end connected to the potential line, and changes its output current in response to the potential supplied from the other end of the second XCS switch 39c.

[0139] Here, an example of the operation of the first correction circuit 310 and the second correction circuit 360 will be described using FIGS. 17 to 20 while referring to FIG.

[0140] 17 is a time chart showing an example of the operation of the lamp drive circuit 21 during one horizontal line period. The horizontal axis represents time, and the vertical axis represents the PCHG signal, CS signal, OFS_SMPL signal, OFS_HOLD signal, PWM signal, SMPL signal, and RAMP wave voltage. Operations equivalent to those described in FIG. 6 may not be described here.

[0141] Fig. 18 is a diagram showing an example of an operating state when the current control circuit 36 ​​samples a differential current. Fig. 19 is a diagram showing an example of an operating state when the current control circuit 36 ​​cancels a differential current. Fig. 20 is a diagram showing an example of an operating state when the output buffer 31 samples a differential voltage. Fig. 21 is a diagram showing an example of an operating state when the output buffer 31 cancels a differential voltage.

[0142] As shown in Fig. 17, at time t3, the PCHG signal and the CS signal go high. As a result, as shown in Fig. 18, the PCHG switch 44, the CS switch 39b, and the second CS switch 39d are turned on, and the XCS switch 39a and the second XCS switch 39c are turned off. As a result, the inverting terminal and the non-inverting terminal of the comparator 36a are at the same potential, and (a part of) the difference current is sampled. In other words, the output current of the variable current source 39e is set when the inverting terminal and the non-inverting terminal of the comparator 36a are at the same potential.

[0143] Next, at time t31, the CS signal goes low. As a result, as shown in FIG. 19, the CS switch 39b and the second CS switch 39d are turned off, and the XCS switch 39a and the second XCS switch 39c are turned on. This completes the offset cancellation process of the current control circuit 36 ​​while maintaining the differential current. This initialization process maintains the offset voltage between the inverting terminal and the non-inverting terminal of the comparator 36a at zero when the XCS switch 39a and the second XCS switch 39c are off.

[0144] The correction circuit 310 includes an off-hold switch 43a, an off-sample switch 43b, a third capacitor 43c, and a second off-sample switch 43d.

[0145] Next, at time t32, the OFS_HOLD signal goes low, and at time t33, the OFS_SMPL signal goes high. As a result, off-hold switch 43a turns off, and off-sample switch 43b and second off-sample switch 43d turn on, as shown in Fig. 20. When the output terminal and inverting terminal of amplifier 41 are at the same potential, and the potential of the inverting terminal is set to reference potential VGO+offset voltage ΔV, a charge corresponding to the offset voltage Δ is held in third capacitor 43c.

[0146] Next, at time t34, the OFS_SMPL signal goes low, and at time t35, the OFS_HOLD signal goes high. As a result, as shown in FIG. 20 , the off-hold switch 43a turns on, and the off-sample switch 43b and the second off-sample switch 43d turn off. In this way, the offset cancellation process of the output buffer 31 ends while maintaining the offset voltage ΔV. This initial process cancels the offset voltage ΔV. In this process, the non-inverting terminal side of the amplifier 41 is the high-impedance side, and the terminal TA of the third capacitor 43c is connected to the non-inverting terminal side of the amplifier 41, and the terminal TB of the third capacitor 43c is connected to the non-inverting terminal side of the amplifier 41. This suppresses the parasitic capacitance on the non-inverting terminal side of the amplifier 41, thereby suppressing a decrease in the driving accuracy of the amplifier 41.

[0147] <Circuit Configuration Having Capacitors According to the Present Embodiment> Various modifications are possible for the circuit configuration having the capacitors 120, 122, 124, 124a, and 126 according to the present embodiment described with reference to Figures 11 to 15. A representative circuit configuration will be described below. In the following description, the terminal Ta side of the capacitors 120, 122, 124, 124a, and 126 is a first impedance, and the terminal Tb side is a second impedance, with the first impedance being greater than the second impedance. In other words, the parasitic capacitance on the second impedance side is suppressed more than the parasitic capacitance on the first impedance side. The terminal Ta is connected to the node na, and the terminal Tb is connected to the node nb.

[0148] (First Specific Example) Fig. 22 is a circuit diagram of a circuit configuration according to a first specific example. The circuit in Fig. 22 is an operational amplifier, and includes an amplifier (amplifier) ​​101 and a capacitor 102 (120, 122, 124, 124a, 126). A terminal Ta of the capacitor is connected to the output terminal of the amplifier 100, and a terminal Tb of the capacitor 102 is connected to the inverting terminal of the amplifier 100. This suppresses the parasitic capacitance on the inverting terminal side of the amplifier 101, and suppresses a decrease in the driving accuracy of the operational amplifier.

[0149] (Second Specific Example) Fig. 23 is a circuit diagram of a circuit configuration according to a second specific example. The circuit in Fig. 23 is a source follower circuit A, and includes a field effect transistor (FET) 103, capacitors 104 (120, 122, 124, 124a, 126), and a current source 105. The drain terminal of the field effect transistor 103 is connected to ground potential, and the source terminal is connected to the current source 105. Furthermore, a terminal Ta of the capacitor 104 is connected to the source terminal of the field effect transistor 103, and a terminal Tb of the capacitor 104 is connected to the gate terminal of the field effect transistor 103. This suppresses parasitic capacitance on the gate side of the field effect transistor 103, and suppresses a decrease in the driving accuracy of the source follower circuit A.

[0150] 24 is a circuit diagram of a circuit configuration according to a third specific example. The circuit in FIG. 24 is a source follower circuit B, and includes a field effect transistor (FET) 106, capacitors 107 (120, 122, 124, 124a, 126), and a current source 108. The drain terminal of the field effect transistor 106 is connected to a potential line, and the source terminal is connected to the current source 108. Furthermore, a terminal Ta of the capacitor 107 is connected to the source terminal of the field effect transistor 106, and a terminal Tb of the capacitor 107 is connected to the gate terminal of the field effect transistor 106. This suppresses parasitic capacitance on the gate side of the field effect transistor 106, and suppresses a decrease in the driving accuracy of the source follower circuit B.

[0151] (Fourth Specific Example) Fig. 25 is a circuit diagram of a circuit configuration according to a fourth specific example. The circuit in Fig. 25 is a logic gate circuit, and includes a gate circuit 109 and capacitors 110a (120, 122, 124, 124a, 126). The gate circuit 109 is, for example, a NAND circuit, but is not limited to this. For example, it may be an AND, OR, NOT, NAND, XOR, XNOR, or a combination of these.

[0152] The terminal Ta of the capacitor 110a is connected to the output terminal of the gate circuit 109, and the terminal Tb of the capacitor 110a is connected to the input terminal of the gate circuit 109. This reduces the parasitic capacitance on the input terminal side of the gate circuit 109, and prevents a decrease in the driving accuracy of the gate circuit 109.

[0153] 1 has a pixel circuit including a light-emitting element such as an organic EL element for each pixel. Various modifications are possible for the specific circuit configuration of the pixel circuit. Representative circuit configurations are described below.

[0154] (First concrete example)

[0155] 26 is a diagram showing an example configuration of a pixel PIX. The pixel PIX has a capacitor C01, transistors MN02 and MN03, and a light-emitting element EL. The transistors MN02 and MN03 are N-type metal oxide semiconductor field effect transistors (MOSFETs). The gate of transistor MN02 is connected to a control line WSL, the drain is connected to a signal line SGL, and the source is connected to the gate of transistor MN03 and capacitor C01. One end of capacitor C01 is connected to the source of transistor MN02 and the gate of transistor MN03, and the other end is connected to the source of transistor MN03 and the anode of the light-emitting element EL. The gate of transistor MN03 is connected to the source of transistor MN02 and one end of capacitor C01, the drain is connected to the power supply line VCCP, and the source is connected to the other end of capacitor C01 and the anode of the light-emitting element EL. The anode of the light-emitting element EL is connected to the source of the transistor MN03 and the other end of the capacitor C01, and the cathode is connected to the power supply line Vcath. The voltage of the power supply line VCCP is appropriately switched between a first voltage and a second voltage lower than the first voltage.

[0156] With this configuration, in pixel PIX, when transistor MN02 is turned on, the voltage across capacitor C01 is set based on the pixel signal supplied from signal line SGL. During a period when the voltage of power supply line VCCP is at a first voltage, transistor MN03 passes a current corresponding to the voltage across capacitor C01 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MN03. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. During a period when the voltage of power supply line VCCP is at a second voltage, light-emitting element EL is turned off.

[0157] (Second Specific Example)

[0158] 27 is a diagram showing another example of the configuration of pixel PIX. This pixel PIX has capacitors C11 and C12, transistors MP12 to MP15, and a light-emitting element EL. Transistors MP12 to MP15 are P-type MOSFETs. The gate of transistor MP12 is connected to a control line WSL, its source is connected to a signal line SGL, and its drain is connected to the gate of transistor MP14 and capacitor C12. One end of capacitor C11 is connected to a power supply line VCCP, and the other end is connected to capacitor C12, the drain of transistor MP13, and the source of transistor MP14. One end of capacitor C12 is connected to the other end of capacitor C11, the drain of transistor MP13, and the source of transistor MP14, and the other end is connected to the drain of transistor MP12 and the gate of transistor MP14. The gate of transistor MP13 is connected to the control line DSL, the source is connected to the power supply line VCCP, and the drain is connected to the source of transistor MP14, the other end of capacitor C11, and one end of capacitor C12. The gate of transistor MP14 is connected to the drain of transistor MP12 and the other end of capacitor C12, the source is connected to the drain of transistor MP13, the other end of capacitor C11, and one end of capacitor C12, and the drain is connected to the anode of the light-emitting element EL and the source of transistor MP15. The gate of transistor MP15 is connected to the control line AZSL, the source is connected to the drain of transistor MP14 and the anode of the light-emitting element EL, and the drain is connected to the power supply line VSS.

[0159] With this configuration, in pixel PIX, when transistor MP12 is turned on, the voltage across capacitor C12 is set based on the pixel signal supplied from signal line SGL. Transistor MP13 is turned on and off based on the signal on control line DSL. While transistor MP13 is on, transistor MP14 passes a current corresponding to the voltage across capacitor C12 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP14. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP15 is turned on and off based on the signal on control line AZSL. While transistor MP15 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0160] The transistors MP12 to MP15 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP12 and MP15 may be a transistor using an oxide semiconductor.

[0161] (Third Specific Example) Figure 28 is a diagram showing another example of the configuration of pixel PIX. This pixel PIX has a capacitor C21, transistors MN22 to MN25, and a light-emitting element EL. Transistors MN22 to MN25 are N-type MOSFETs. The gate of transistor MN22 is connected to a control line WSL, the drain is connected to a signal line SGL, and the source is connected to the gate of transistor MN24 and capacitor C21. One end of capacitor C21 is connected to the source of transistor MN22 and the gate of transistor MN24, and the other end is connected to the source of transistor MN24, the drain of transistor MN25, and the anode of light-emitting element EL. The gate of transistor MN23 is connected to a control line DSL, the drain is connected to a power supply line VCCP, and the source is connected to the drain of transistor MN24. The gate of transistor MN24 is connected to the source of transistor MN22 and one end of capacitor C21, the drain is connected to the source of transistor MN23, the source is connected to the other end of capacitor C21, the drain of transistor MN25, and the anode of light-emitting element EL. The gate of transistor MN25 is connected to control line AZSL, the drain is connected to the source of transistor MN24, the other end of capacitor C21, and the anode of light-emitting element EL, and the source is connected to power supply line VSS.

[0162] With this configuration, in pixel PIX, when transistor MN22 is turned on, the voltage across capacitor C21 is set based on the pixel signal supplied from signal line SGL. Transistor MN23 is turned on and off based on the signal on control line DSL. While transistor MN23 is on, transistor MN24 passes a current corresponding to the voltage across capacitor C21 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MN24. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MN25 is turned on and off based on the signal on control line AZSL. While transistor MN25 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0163] The transistors MN22 to MN25 may be transistors using low temperature polysilicon (LTPS). At least one of the transistors MN22 and MN25 may be a transistor using an oxide semiconductor.

[0164] (Fourth Specific Example) Figure 29 is a diagram showing another example of the configuration of pixel PIX. This pixel PIX has a capacitor C31, transistors MP32 to MP36, and a light-emitting element EL. Transistors MP32 to MP36 are P-type MOSFETs. The gate of transistor MP32 is connected to a control line WSL, its source is connected to a signal line SGL, and its drain is connected to the gate of transistor MP33, the drain of transistor MP34, and capacitor C31. One end of capacitor C31 is connected to a power supply line VCCP, and the other end is connected to the drain of transistor MP32, the gate of transistor MP33, and the drain of transistor MP34. The gate of transistor MP34 is connected to a control line AZSL1, its source is connected to the drain of transistor MP33 and the source of transistor MP35, and its drain is connected to the drain of transistor MP32, the gate of transistor MP33, and the other end of capacitor C31. The gate of transistor MP35 is connected to the control line DSL, the source is connected to the drain of transistor MP33 and the source of transistor MP34, the drain is connected to the source of transistor MP36 and the anode of the light-emitting element EL, the gate of transistor MP36 is connected to the control line AZSL2, the source is connected to the drain of transistor MP35 and the anode of the light-emitting element EL, and the drain is connected to the power supply line VSS.

[0165] With this configuration, in pixel PIX, when transistor MP32 is turned on, the voltage across capacitor C31 is set based on the pixel signal supplied from signal line SGL. Transistor MP35 is turned on and off based on the signal on control line DSL. While transistor MP35 is on, transistor MP33 passes a current corresponding to the voltage across capacitor C31 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP33. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP34 is turned on and off based on the signal on control line AZSL1. While transistor MP34 is on, the drain and gate of transistor MP33 are connected to each other. Transistor MP36 is turned on and off based on the signal on control line AZSL2. While transistor MP36 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0166] The transistors MP32 to MP36 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP32, MP34, and MP36 may be a transistor using an oxide semiconductor.

[0167] 30 is a diagram showing another example of the configuration of pixel PIX. One end of capacitor C48 is connected to signal line SGL1, and the other end is connected to power supply line VSS. One end of capacitor C49 is connected to signal line SGL1, and the other end is connected to signal line SGL2. Transistor MP49 is a P-type MOSFET, and its gate is connected to control line WSL2, its source is connected to signal line SGL1, and its drain is connected to signal line SGL2.

[0168] The pixel PIX includes a capacitor C41, transistors MP42 to MP46, and a light-emitting element EL. Transistors MP42 to MP46 are P-type MOSFETs. The gate of transistor MP42 is connected to a control line WSL1, its source is connected to a signal line SGL2, and its drain is connected to the gate of transistor MP43 and capacitor C41. One end of capacitor C41 is connected to a power supply line VCCP, and the other end is connected to the drain of transistor MP42 and the gate of transistor MP43. The gate of transistor MP43 is connected to the drain of transistor MP42 and the other end of capacitor C41, its source is connected to the power supply line VCCP, and its drain is connected to the sources of transistors MP44 and MP45. The gate of transistor MP44 is connected to a control line AZSL1, its source is connected to the drain of transistor MP43 and the source of transistor MP45, and its drain is connected to signal line SGL2. The gate of transistor MP45 is connected to control line DSL, the source is connected to the drain of transistor MP43 and the source of transistor MP44, the drain is connected to the source of transistor MP46 and the anode of light-emitting element EL, the gate of transistor MP46 is connected to control line AZSL2, the source is connected to the drain of transistor MP45 and the anode of light-emitting element EL, and the drain is connected to power supply line VSS.

[0169] With this configuration, in pixel PIX, when transistor MP42 is turned on, the voltage across capacitor C41 is set based on the pixel signal supplied from signal line SGL1 via capacitor C49. Transistor MP45 is turned on and off based on the signal on control line DSL. While transistor MP45 is on, transistor MP43 passes a current corresponding to the voltage across capacitor C41 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP43. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP44 is turned on and off based on the signal on control line AZSL1. While transistor MP44 is on, the drain of transistor MP43 and signal line SGL2 are connected to each other. Transistor MP46 is turned on and off based on the signal on control line AZSL2. While transistor MP46 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0170] The transistors MP42 to MP46 and MP49 may be transistors using low temperature polysilicon (LTPS). At least one of the transistors MP42, MP46 and MP49 may be a transistor using an oxide semiconductor.

[0171] 31 shows another example of the configuration of the pixel PIX. A plurality of pixels PIX are arranged in a matrix in a display area 100, and the display area 100 is provided between a first control unit 40 and a second control unit 70.

[0172] The first control unit 40 includes transmission gates TG45 and TG46, transistors MP56 and MP57, and a capacitor C61. Transistors MP56 and MP57 are P-type MOSFETs. A pixel signal is supplied to the input terminal of the transmission gate TG45, and the output terminal of the transmission gate TG45 is connected to one end of the signal line 14a. The input terminal of the transmission gate TG46 is connected to the signal line 14b, and the output terminal of the transmission gate TG46 is connected to the power supply line Vorst. One end of the capacitor C61 is connected to the signal line 14a, and the other end is connected to the power supply line VSS1. The gate of the transistor MP56 is connected to the control line INIL, the source is connected to the power supply line Vini, and the drain is connected to the signal line 14b. The gate of the transistor MP57 is connected to the control line ELL, the source is connected to the power supply line Vel, and the drain is connected to the signal line 14b.

[0173] The second control unit 70 has a transmission gate TG72, a transistor MP73, and a capacitor C82. The transistor MP73 is a P-type MOSFET. The input terminal of the transmission gate TG72 is connected to the other end of the signal line 14a, and the output terminal is connected to the drain of the transistor MP73 and one end of the capacitor C82. The gate of the transistor MP73 is connected to the control line REFL, the source is connected to the power supply line Vref, and the drain is connected to the output terminal of the transmission gate TG72 and one end of the capacitor C82. One end of the capacitor C82 is connected to the output terminal of the transmission gate TG72 and the drain of the transistor MP73, and the other end is connected to one end of the signal line 14b.

[0174] The pixel PIX includes a capacitor C132, transistors MP121 to MP125, and a light-emitting element EL. Transistors MP121 to MP125 are P-type MOSFETs. The gate of transistor MP122 is connected to a control line WSL, its source is connected to a signal line 14b, and its drain is connected to the gate of transistor MP121 and capacitor C132. One end of capacitor C132 is connected to a power supply line Vel, and the other end is connected to the drain of transistor MP122 and the gate of transistor MP121. The gate of transistor MP121 is connected to the drain of transistor MP122 and the other end of capacitor C132, its source is connected to the power supply line Vel, and its drain is connected to the sources of transistors MP123 and MP124. The gate of transistor MP123 is connected to a control line AZSL, its source is connected to the drain of transistor MP121 and the source of transistor MP124, and its drain is connected to signal line 14b. The gate of transistor MP124 is connected to the control line DSL, the source is connected to the drain of transistor MP121 and the source of transistor MP123, and the drain is connected to the drain of transistor MP125 and the anode of the light-emitting element 130. The gate of transistor MP125 is connected to the control line AZSL, the source is connected to the power supply line Vorst, and the drain is connected to the drain of transistor MP124 and the anode of the light-emitting element 130.

[0175] With this configuration, in pixel PIX, when transistor MP122 is turned on, the voltage across capacitor C132 is set based on the pixel signal supplied via transmission gate TG45, signal line 14a, transmission gate TG72, capacitor C82, and signal line 14b. Transistor MP124 is turned on and off based on the signal on control line DSL. While transistor MP124 is on, transistor MP121 passes a current corresponding to the voltage across capacitor C132 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP121. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistors MP123 and MP125 are turned on and off based on the signal on control line AZSL. While transistor MP123 is on, the drain of transistor MP121 and the source of transistor MP124 are connected to signal line 14b. During the period when transistor MP125 is in the ON state, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line Vorst. Furthermore, transistor MP56 is turned on and off based on the signal on control line INIL, transistor MP57 is turned on and off based on the signal on control line ELL, and transistor MP73 is turned on and off based on the signal on control line REFL. When transistor MP56 is turned on, signal line 14b is set to the voltage of power supply line Vini, and when transistor MP57 is turned on, signal line 14b is set to the voltage of power supply line Vel. When transistor MP73 is turned on, one end of capacitor C82 is initialized by being set to the voltage of power supply line Vref.

[0176] The transistors MP121 to MP125, MP56, and MP57 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP122 and MP125 may be a transistor using an oxide semiconductor.

[0177] 32 shows another example of the configuration of a pixel PIX. This pixel PIX has a capacitor C51, transistors MP52 to MP60, and a light-emitting element EL. Transistors MP52 to MP60 are P-type MOSFETs. The gate of transistor MP52 is connected to a control line WSL, its source is connected to a signal line SGL, and its drain is connected to the drain of transistor MP53 and the source of transistor MP54. The gate of transistor MP53 is connected to a control line DSL, its source is connected to a power supply line VCCP, and its drain is connected to the drain of transistor MP52 and the source of transistor MP54. The gate of transistor MP54 is connected to the source of transistor MP55, the drain of transistor MP57, and capacitor C51, its source is connected to the drains of transistors MP52 and MP53, and its drain is connected to the sources of transistors MP58 and MP59. One end of capacitor C51 is connected to the power supply line VCCP, and the other end is connected to the gate of transistor MP54, the source of transistor MP55, and the drain of transistor MP57. Capacitor C51 may include two capacitors connected in parallel. Transistor MP55 has a gate connected to control line AZSL1, a source connected to the gate of transistor MP54, the drain of transistor MP57, and the other end of capacitor C51, and a drain connected to the source of transistor MP56. Transistor MP56 has a gate connected to control line AZSL1, a source connected to the drain of transistor MP55, and a drain connected to power supply line VSS. Transistor MP57 has a gate connected to control line WSL, a drain connected to the gate of transistor MP54, the source of transistor MP55, and the other end of capacitor C51, and a source connected to the drain of transistor MP58. The gate of the transistor MP58 is connected to the control line WSL, the drain is connected to the source of the transistor MP57, and the source is connected to the drain of the transistor MP54 and the source of the transistor MP59.The gate of transistor 59 is connected to control line DSL, the source is connected to the drain of transistor MP54 and the source of transistor MP58, the drain is connected to the source of transistor MP60 and the anode of light-emitting element EL, the gate of transistor MP60 is connected to control line AZSL2, the source is connected to the drain of transistor MP59 and the anode of light-emitting element EL, and the drain is connected to power supply line VSS.

[0178] With this configuration, in pixel PIX, transistors MP52, MP54, MP58, and MP57 are turned on, and the voltage across capacitor C51 is set based on the pixel signal supplied from signal line SGL. Transistors MP53 and MP59 are turned on and off based on the signal on control line DSL. While transistors MP53 and MP59 are on, transistor MP54 passes a current corresponding to the voltage across capacitor C51 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP54. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistors MP55 and MP56 are turned on and off based on the signal on control line AZSL1. While transistors MP55 and MP56 are on, the gate voltage of transistor MP54 is initialized by being set to the voltage of power supply line VSS. Transistor MP60 is turned on and off based on the signal on control line AZSL2. During the period in which the transistor MP60 is in the on state, the voltage of the anode of the light-emitting element EL is initialized by being set to the voltage of the power supply line VSS.

[0179] The transistors MP52 to MP60 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP55 to MP58 and MP60 may be a transistor using an oxide semiconductor.

[0180] (Eighth Specific Example)

[0181] 33 is a diagram showing another example of the configuration of the pixel PIX. The signal on the control line WSNL and the signal on the control line WSPL are mutually inverted signals.

[0182] The pixel PIX has capacitors C61 and C62, transistors MN63, MP64, MN65 to MN67, and a light-emitting element EL. The transistors MN63, MN65 to MN67 are N-type MOSFETs, and the transistor MP64 is a P-type MOSFET. The gate of the transistor MN63 is connected to a control line WSNL, the drain is connected to a signal line SGL and the source of the transistor MP64, and the source is connected to the drain of the transistor MP64, the capacitors C61 and C62, and the gate of the transistor MN65. The gate of the transistor MP64 is connected to a control line WSPL, the source is connected to the signal line SGL and the drain of the transistor MN63, and the drain is connected to the source of the transistor MN63, the capacitors C61 and C62, and the gate of the transistor MN65. The capacitor C61 is configured using, for example, a metal oxide metal (MOM) capacitor, with one end connected to the source of transistor MN63, the drain of transistor MP64, capacitor C62, and the gate of transistor MN65, and the other end connected to the power supply line VSS2. The capacitor C61 may be configured using, for example, a metal oxide semiconductor (MOS) capacitor or a metal insulator metal (MIM) capacitor. The capacitor C62 is configured using, for example, a MOS capacitor, with one end connected to the source of transistor MN63, the drain of transistor MP64, one end of capacitor C61, and the gate of transistor MN65, and the other end connected to the power supply line VSS2. The capacitor C62 may be configured using, for example, a MOM capacitor or a MIM capacitor. The other end of the capacitor C62 may be connected to the power supply line VSS3 (not shown). The gate of transistor MN65 is connected to the source of transistor MN63, the drain of transistor MP64, and one end of capacitors C61 and C62, the drain is connected to the power supply line VCCP, and the source is connected to the drains of transistors MN66 and MN67. The gate of transistor MN66 is connected to control line AZL, the drain is connected to the source of transistor MN65 and the drain of transistor MN67, and the source is connected to power supply line VSS1.The gate of transistor MN67 is connected to the control line DSL, the drain is connected to the source of transistor MN65 and the drain of transistor MN66, and the source is connected to the anode of the light-emitting element EL. Note that the transistor MN67 and the control line DSL may be omitted, and the source of transistor MN65 may be connected to the drain of transistor MN66 and the anode of the light-emitting element EL.

[0183] With this configuration, in pixel PIX, when at least one of transistors MN63 and MP64 is turned on, the voltage across capacitors C61 and C62 is set based on the pixel signal supplied from signal line SGL. Transistor MN67 is turned on and off based on the signal on control line DSL. While transistor MN65 is on, it passes a current corresponding to the voltage across capacitors C61 and C62 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP65. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MN66 may be turned on and off based on the signal on control line AZL. Transistor MN66 may also function as a resistor element having a resistance value corresponding to the signal on control line AZL. In this case, transistors MN65 and MN66 form a so-called source follower circuit.

[0184] The transistors MN63, MP64, and MN65 to MN67 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MN63, MP64, and MN66 may be a transistor using an oxide semiconductor.

[0185] (Ninth Specific Example)

[0186] 34 shows another example of the configuration of pixel PIX. This pixel PIX has a capacitor C71, transistors MN72 to MN77, and a light-emitting element EL. Transistors MN72 to MN77 are N-type MOSFETs. The gate of transistor MN72 is connected to a control line WSL, the drain is connected to a signal line SGL, and the source is connected to the source of transistor MN74 and the drain of transistor MN75. One end of capacitor C71 is connected to the gate of transistor MN74 and the source of transistor MN76, and the other end is connected to the drain of transistor MN77, the source of transistor MN75, and the anode of light-emitting element EL. The gate of transistor MN73 is connected to control line DLS1, the drain is connected to a power supply line VCCP, and the source is connected to the drain of transistor MN74 and the drain of transistor MN76. The gate of transistor MN74 is connected to the source of transistor MN76 and one end of capacitor C71, the drain is connected to the source of transistor MN73 and the drain of transistor MN76, and the source is connected to the source of transistor MN72 and the drain of transistor MN75. The gate of transistor MN75 is connected to control line DSL2, the drain is connected to the source of transistor MN72 and the source of transistor MN74, and the source is connected to the other end of capacitor C71, the drain of transistor MN77, and the anode of light-emitting element EL. The gate of transistor MN76 is connected to control line AZSL, the drain is connected to the source of transistor MN73 and the drain of transistor MN74, and the source is connected to the gate of transistor MN74 and one end of capacitor C71. The gate of transistor MN77 is connected to control line AZSL, the drain is connected to the other end of capacitor C71, the source of transistor MN75, and the anode of light-emitting element EL, and the source is connected to power supply line VSS.

[0187] With this configuration, in pixel PIX, transistors MN72, MN74, and MN76 are turned on, and the voltage across capacitor C71 is set based on the pixel signal supplied from signal line SGL. Transistor MN73 is turned on and off based on the signal on control line DSL1, and transistor MN75 is turned on and off based on the signal on control line DSL2. While transistors MN73 and MN75 are on, transistor MN74 passes a current corresponding to the voltage across capacitor C71 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MN74. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MN77 is turned on and off based on the signal on control line AZSL. While transistor MN77 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0188] The transistors MN72 to MN77 may be transistors using low temperature polysilicon (LTPS), and the transistor MN76 may be a transistor using an oxide semiconductor.

[0189] (Application examples of image display device 1 and electronic device according to the present disclosure) (First application example) The image display device 1 according to the present disclosure can be used for various purposes. Figures 62A and 62B are diagrams showing the internal configuration of vehicle 100, which is a first application example of electronic device 50 equipped with image display device 1 according to the present disclosure. Figure 62A shows the interior of vehicle 100 from the rear to the front of vehicle 100, and Figure 62B shows the interior of vehicle 100 from diagonally rear to diagonally front of vehicle 100.

[0190] 2. Application Examples Next, application examples of the display systems described in the above embodiments and modifications will be described.

[0191] 35 is a diagram showing an example of the appearance of a head-mounted display 110. The head-mounted display 110 has, for example, ear hooks 112 for wearing on the user's head on both sides of a glasses-shaped display unit 111. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 110.

[0192] (Application Example 2) FIG. 36 is a diagram illustrating an example of the appearance of another head-mounted display 120. The head-mounted display 120 is a see-through head-mounted display having a main body 121, an arm 122, and a lens barrel 123. This head-mounted display 120 is attached to eyeglasses 128. The main body 121 has a control board and a display unit for controlling the operation of the head-mounted display 120. The display unit emits image light of a display image. The arm 122 connects the main body 121 to the lens barrel 123 and supports the lens barrel 123. The lens barrel 123 projects the image light supplied from the main body 121 via the arm 122 toward the user's eyes via lenses 129 of the eyeglasses 128. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 120.

[0193] The head-mounted display 120 is a so-called light guide plate type head-mounted display, but is not limited to this and may be, for example, a so-called birdbath type head-mounted display. The birdbath type head-mounted display includes, for example, a beam splitter and a partially transparent mirror. The beam splitter outputs light encoded with image information toward the mirror, and the mirror reflects the light toward the user's eyes. Both the beam splitter and the partially transparent mirror are partially transparent. This allows light from the surrounding environment to reach the user's eyes.

[0194] (Application Example 3) Figures 37 and 38 are diagrams showing an example of the appearance of a digital still camera 130, with Figure 37 showing a front view and Figure 38 showing a rear view. This digital still camera 130 is a single-lens reflex camera with interchangeable lenses, and has a camera main body 131, a photographing lens unit 132, a grip unit 133, a monitor 134, and an electronic viewfinder 135. The photographing lens unit 312 is an interchangeable lens unit and is provided near the center of the front of the camera main body 311. The grip unit 133 is provided on the left side of the front of the camera main body 311, and is held by the photographer. The monitor 134 is provided to the left of the center of the back of the camera main body 131. The electronic viewfinder 135 is provided above the monitor 134 on the back of the camera main body 131. By looking through this electronic viewfinder 135, the photographer can visually confirm the optical image of the subject guided by the photographing lens unit 132 and determine the composition. The techniques according to the above-described embodiments and the like can be applied to the electronic viewfinder 135.

[0195] 39 is a diagram illustrating an example of the appearance of a television device 140. The television device 140 has an image display screen unit 141 including a front panel 142 and a filter glass 143. The techniques according to the above-described embodiments and the like can be applied to this image display screen unit 141.

[0196] 40 is a diagram illustrating an example of the appearance of a smartphone 150. The smartphone 150 has a display unit 151 that displays various information and an operation unit 152 that includes buttons and the like that accept operation inputs by a user. The techniques according to the above-described embodiments and the like can be applied to this display unit 151.

[0197] (Application Example 6) Figures 41 and 42 are diagrams showing an example configuration of a vehicle to which the technology of the present disclosure is applied, where Figure 41 shows an example of the interior of the vehicle as seen from the rear of vehicle 200, and Figure 42 is a diagram showing an example of the interior of the vehicle as seen from the left rear of vehicle 200.

[0198] The vehicle in Figures 41 and 42 has a center display 201, a console display 202, a head-up display 203, a digital rearview mirror 204, a steering wheel display 205, and a rear entertainment display 106.

[0199] The center display 201 is disposed on the dashboard 261 in a position facing the driver's seat 262 and the passenger's seat 263. FIG. 41 shows an example of a horizontally elongated center display 201 extending from the driver's seat 262 side to the passenger's seat 263 side, but the screen size and location of the center display 201 are not limited to this. The center display 201 can display information detected by various sensors. As a specific example, the center display 201 can display an image captured by an image sensor, a distance image to obstacles in front of or to the side of the vehicle measured by a ToF sensor, and the body temperature of an occupant detected by an infrared sensor. The center display 201 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information.

[0200] The safety-related information includes information based on sensor detection results, such as detection of drowsiness, distraction, child mischief, whether a seatbelt is fastened, and whether a passenger is abandoned. The operation-related information includes gesture information related to passenger operations detected using sensors. The gestures may include operations of various in-vehicle equipment, such as air conditioning, navigation, audiovisual (AV) equipment, and lighting. The life log includes life logs of all passengers. For example, the life log includes a record of each passenger's behavior. By acquiring and storing the life log, it is possible to determine the condition of the passengers at the time of an accident. The health-related information includes the passenger's body temperature detected using a temperature sensor and information on the passenger's health condition estimated based on the detected body temperature. Alternatively, the passenger's health condition information may be estimated based on the passenger's face captured by an image sensor. Furthermore, the passenger's health condition information may be estimated based on the passenger's responses obtained through an automated voice conversation with the passenger. The authentication / identification-related information includes information on a keyless entry function that uses a sensor to perform facial authentication, a function that automatically adjusts the seat height and position by facial recognition, etc. The entertainment-related information includes information on AV device operations by occupants detected by the sensor, and information on content to be displayed that is appropriate for the occupants detected and recognized by the sensor.

[0201] The console display 202 can be used to display, for example, life log information. The console display 202 is disposed near a shift lever 265 on a center console 264 between a driver's seat 262 and a passenger seat 263. The console display 202 can also display information detected by various sensors. The console display 202 may also display an image of the vehicle's surroundings captured by an image sensor, or an image showing the distance to an obstacle around the vehicle.

[0202] The head-up display 203 is virtually displayed behind a windshield 266 in front of the driver's seat 262. The head-up display 203 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. Since the head-up display 203 is often virtually disposed in front of the driver's seat 262, it is suitable for displaying information directly related to vehicle operation, such as the vehicle speed, the remaining fuel level, and the remaining battery level.

[0203] The digital rearview mirror 204 can not only display the rear of the vehicle, but also display the state of passengers in the rear seats, and can therefore be used to display life log information of passengers in the rear seats, for example.

[0204] The steering wheel display 205 is disposed near the center of the vehicle's steering wheel 267. The steering wheel display 205 can be used to display at least one of, for example, safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because the steering wheel display 205 is located near the driver's hands, it is suitable for displaying life log information such as the driver's body temperature, and for displaying information related to the operation of AV equipment, air conditioning equipment, etc.

[0205] The rear entertainment display 206 is attached to the back side of the driver's seat 262 and the passenger seat 263 and is intended for viewing by rear seat passengers. The rear entertainment display 206 can be used to display at least one of, for example, safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, since the rear entertainment display 206 is located in front of the rear seat passengers, information related to the rear seat passengers is displayed on the rear entertainment display 206. The rear entertainment display 206 may display, for example, information related to the operation of an AV device or an air conditioning system, or may display the results of measurements of the body temperature of the rear seat passengers by the temperature sensor 5.

[0206] The techniques according to the above-described embodiments can be applied to the center display 201, console display 202, head-up display 203, digital rearview mirror 204, steering wheel display 205, and rear entertainment display 206.

[0207] The present technology may have the following configuration: (1) A capacitive element connected to an electronic circuit having a first node having a first impedance and a second node having a second impedance smaller than the first impedance, the capacitive element comprising: a substrate; and a first capacitance layer formed in a plane along an upper surface of the substrate, the first capacitance layer having a loop-shaped metal wiring, a comb-shaped first metal wiring connected to the loop-shaped metal wiring and formed within the loop-shaped metal wiring, and a comb-shaped second metal wiring formed within the loop-shaped metal wiring of the first metal wiring, wherein the first metal wiring is connected to the first node, and the second metal wiring is connected to the second node.

[0208] (2) The capacitive element according to (1), wherein the first capacitive layer constitutes a metal-on-metal (MOM) capacitor.

[0209] (3) The capacitive element according to (1) or (2), having a plurality of the first capacitance layers, the plurality of first capacitance layers being stacked on the substrate, the first metal wiring of each of the first capacitance layers being electrically connected, and the second metal wiring of each of the first capacitance layers being electrically connected.

[0210] (4) The capacitive element according to any one of (1) to (3), wherein the spaces between the first capacitance layers are formed by insulating films.

[0211] (5) The capacitive element according to any one of (1) to (4), further comprising a first metal layer configured between an upper surface of the substrate and lower surfaces of the plurality of first capacitance layers and extending along the upper surface of the substrate, the first metal layer being connected to the first metal wiring.

[0212] (6) The capacitive element according to (5), further comprising: a second metal layer formed along upper surfaces of the plurality of first capacitance layers and connected to the first metal wiring.

[0213] (7) The capacitor according to (6), further comprising: a semiconductor layer stacked on an upper surface of the first metal layer and configured within the loop-shaped metal wiring in a planar view; and a third metal layer stacked on an upper surface of the semiconductor layer and configured within the loop-shaped metal wiring in a planar view. (8) The capacitor according to (7), wherein the third metal layer is connected to the second metal wiring. (9) The capacitor according to (8), wherein the first metal layer, the semiconductor layer, and the third metal layer configure an MIM capacitor. (10) The capacitor according to (9), wherein the loop-shaped metal wirings of the plurality of first capacitance layers are arranged to overlap in a planar view, and the plurality of loop-shaped metal wirings and the first metal layer are connected by metal pins located within the loop-shaped metal wiring in a planar view. (11) The capacitor according to (2), further comprising a well configured on an upper surface of the substrate, wherein the well is connected to the first metal wiring. (12) The capacitive element according to (2), further comprising a shallow trench isolation layer formed between an upper surface of the substrate and lower surfaces of the plurality of first capacitance layers. (13) A capacitive element connected to an electronic circuit having a first node having a first impedance and a second node having a second impedance smaller than the first impedance, comprising: a substrate; a first metal layer formed on the upper surface of the substrate; a semiconductor layer stacked on the upper surface of the first metal layer and formed within the first metal layer in a plan view; a third metal layer stacked on the upper surface of the semiconductor layer and formed within the first metal layer in a plan view; and a fourth metal layer formed above the third metal layer, facing the first metal layer and arranged so as to overlap with the first metal layer in a plan view, wherein outer peripheries of the first metal layer and the fourth metal layer are connected by a metal pin.

[0214] (14) The capacitive element according to (1) or (13), wherein the electronic circuit is a display drive circuit, the display drive circuit comprises: a ramp voltage generation circuit that generates a ramp voltage whose voltage level changes over time; and a signal line voltage generation circuit that holds the voltage level of the ramp voltage at a timing according to the signal level of a pixel signal to generate a signal line voltage; the ramp voltage generation circuit comprises: an amplifier that outputs the ramp voltage; a load circuit arranged on a feedback path of the amplifier; a current generation circuit that controls a current flowing to the load circuit according to the ramp voltage and a reference voltage; a comparator that compares the ramp voltage with the reference voltage; and a holding unit that holds a comparison result signal of the comparator; the current generation circuit controls the current flowing to the load circuit based on the comparison result signal; the second node is formed at an inverting terminal of the comparator; the first node is formed at an output terminal of the comparator; (15) The capacitive element according to (1) or (13), wherein the electronic circuit is a display drive circuit, the display drive circuit includes: a ramp voltage generation circuit that generates a ramp voltage whose voltage level changes over time; and a signal line voltage generation circuit that generates a signal line voltage by holding the voltage level of the ramp voltage at a timing according to the signal level of a pixel signal; the ramp voltage generation circuit includes: an amplifier that outputs the ramp voltage; a load circuit arranged on a feedback path of the amplifier; a correction circuit that corrects an offset potential of a reference potential supplied to a non-inverting terminal of the amplifier; and a current generation circuit that controls a current flowing in the load circuit according to the ramp voltage and a second reference voltage; the first node is formed at an inverting terminal of the amplifier, and a second node is formed at a non-inverting terminal of the amplifier; the correction circuit is configured between the first node and the second node; and the correction circuit includes the capacitive element. (16) The capacitive element according to (1) or (13), wherein the electronic circuit is an operational amplifier, and the first node is formed at an output terminal of the operational amplifier, and the second node is formed at a non-inverting terminal of the amplifier.(17) The capacitance element according to (1) or (13), wherein the electronic circuit is a source follower circuit comprising a field effect transistor and a current source, wherein the first node is formed at a source terminal of the field effect transistor and the second node is formed at a gate terminal of the field effect transistor. (18) The capacitance element according to (1) or (13), wherein the electronic circuit is a source follower circuit comprising a field effect transistor and a current source, wherein the drain terminal of the field effect transistor is connected to a potential line and the source terminal is connected to the current source, wherein the first node is formed at the source terminal of the field effect transistor and the second node is formed at a gate terminal of the field effect transistor. (19) The capacitance element according to (1) or (13), wherein the electronic circuit is a gate circuit, wherein the first node is formed at an output terminal of the gate circuit and the second node is formed at an input terminal of the gate circuit.(20) A display device comprising: a ramp voltage generation circuit that generates a ramp voltage whose voltage level changes over time; and a signal line voltage generation circuit that holds the voltage level of the ramp voltage at a timing according to the signal level of a pixel signal to generate a signal line voltage, wherein the ramp voltage generation circuit has: an amplifier that outputs the ramp voltage; a capacitive element arranged on a feedback path of the amplifier; a current generation circuit that controls a current flowing to the capacitive element according to the ramp voltage and a reference voltage; a comparator that compares the ramp voltage with the reference voltage; and a holding unit that holds a comparison result signal of the comparator, wherein the current generation circuit controls the current flowing to the capacitive element based on the comparison result signal; a second node is formed at an inverting terminal of the comparator; a first node is formed at an output terminal of the comparator; and the capacitive element is connected between the first node and the second node, and the capacitive element comprises: a substrate; a first capacitance layer having a loop-shaped metal wiring formed in a plane along an upper surface of the substrate, a comb-shaped first metal wiring connected to the loop-shaped metal wiring and formed within the loop-shaped metal wiring, and a comb-shaped second metal wiring formed within the loop-shaped metal wiring of the first metal wiring, wherein the first metal wiring is connected to the first node and the second metal wiring is connected to the second node.

[0215] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents.

[0216] 1: display device, 10: horizontal analog circuit, 18: PWM generating circuit, 19 level shifter, 20 display driving circuit, 21: lamp driving circuit, 31: output buffer, 32: current generating circuit, 33: current control circuit, 35: variable current source, 120, 122, 124, 124a, 126: capacitor (capacitive element), nA, nA1: first node, nB, nB1: second node, Mfa: first metal wiring (first metal wiring), Mfb: second metal wiring (second metal wiring), Mpin: metal pin, SUB: semiconductor substrate, STI: shallow trench isolation, Ta: terminal, Tb: terminal, WELL: well.

Claims

1. A capacitive element connected to an electronic circuit having a first node with a first impedance and a second node with a second impedance smaller than the first impedance, comprising: a substrate; and a first capacitance layer formed in a plane along the top surface of the substrate, the first metal wiring being formed of a loop-shaped metal wiring and a comb-shaped metal wiring connected to the loop-shaped metal wiring and formed within the loop-shaped metal wiring; and a comb-shaped second metal wiring formed within the loop-shaped metal wiring of the first metal wiring, wherein the first metal wiring is connected to the first node and the second metal wiring is connected to the second node.

2. The capacitive element according to claim 1, wherein the first capacitive layer constitutes a metal-on-metal (MOM) capacitor.

3. The capacitive element according to claim 2, comprising a plurality of the first capacitance layers, the plurality of first capacitance layers being stacked on the substrate, the first metal wiring of each of the first capacitance layers being electrically connected, and the second metal wiring of each of the first capacitance layers being electrically connected.

4. The capacitive element according to claim 3, wherein the spaces between the first capacitance layers are made of insulating films.

5. The capacitive element according to claim 4, further comprising a first metal layer arranged between the upper surface of the substrate and the lower surfaces of the plurality of first capacitance layers and extending along the upper surface of the substrate, the first metal layer being connected to the first metal wiring.

6. The capacitive element according to claim 5, further comprising a second metal layer formed along the upper surfaces of the plurality of first capacitance layers and connected to the first metal wiring.

7. The capacitive element according to claim 6, further comprising: a semiconductor layer stacked on an upper surface of the first metal layer and configured within the loop-shaped metal wiring in a planar view; and a third metal layer stacked on an upper surface of the semiconductor layer and configured within the loop-shaped metal wiring in a planar view.

8. The capacitive element according to claim 7, wherein the third metal layer is connected to the second metal wiring.

9. The capacitive element according to claim 8, wherein the first metal layer, the semiconductor layer, and the third metal layer constitute an MIM capacitor.

10. A capacitance element as described in claim 9, wherein, in a plan view, the loop-shaped metal wirings of the plurality of first capacitance layers are arranged to overlap, and the plurality of loop-shaped metal wirings and the first metal layer are connected by metal pins located within the loop-shaped metal wirings in a plan view.

11. The capacitive element according to claim 2, further comprising a well formed on the upper surface of said substrate, said well being connected to said first metal wiring.

12. The capacitive element of claim 2, further comprising a shallow trench isolation layer configured between an upper surface of the substrate and lower surfaces of the plurality of first capacitive layers.

13. A capacitive element connected to an electronic circuit having a first node having a first impedance and a second node having a second impedance smaller than the first impedance, comprising: a substrate; a first metal layer formed on an upper surface of the substrate; a semiconductor layer stacked on the upper surface of the first metal layer and formed within the first metal layer in a planar view; a third metal layer stacked on the upper surface of the semiconductor layer and formed within the first metal layer in a planar view; and a fourth metal layer formed above the third metal layer, facing the first metal layer, and arranged so as to overlap with it in a planar view, wherein the outer peripheries of the first metal layer and the fourth metal layer are connected by a metal pin.

14. The capacitive element according to claim 1, wherein the electronic circuit is a display drive circuit, the display drive circuit comprising: a ramp voltage generation circuit that generates a ramp voltage whose voltage level changes over time; and a signal line voltage generation circuit that holds the voltage level of the ramp voltage at a timing according to the signal level of a pixel signal to generate a signal line voltage; the ramp voltage generation circuit comprising: an amplifier that outputs the ramp voltage; a load circuit arranged on a feedback path of the amplifier; a current generation circuit that controls a current to be flowed to the load circuit according to the ramp voltage and a reference voltage; a comparator that compares the ramp voltage with the reference voltage; and a holding unit that holds a comparison result signal of the comparator; the current generation circuit controls the current to be flowed to the load circuit based on the comparison result signal; the second node is formed at an inverting terminal of the comparator, the first node is formed at an output terminal of the comparator, and the holding unit is configured between the first node and the second node; and the holding unit has the capacitive element.

15. The capacitive element according to claim 1, wherein the electronic circuit is a display drive circuit, the display drive circuit comprising: a ramp voltage generation circuit that generates a ramp voltage whose voltage level changes over time; and a signal line voltage generation circuit that generates a signal line voltage by holding the voltage level of the ramp voltage at a timing according to the signal level of a pixel signal; the ramp voltage generation circuit comprising: an amplifier that outputs the ramp voltage; a load circuit arranged on a feedback path of the amplifier; a correction circuit that corrects an offset potential of a reference potential supplied to a non-inverting terminal of the amplifier; and a current generation circuit that controls a current to be passed through the load circuit according to the ramp voltage and a second reference voltage; the first node is formed at the inverting terminal of the amplifier, and a second node is formed at the non-inverting terminal of the amplifier; the correction circuit is configured between the first node and the second node; and the correction circuit comprises the capacitive element.

16. The capacitive element according to claim 1, wherein the electronic circuit is an operational amplifier, and the first node is formed at an output terminal of the operational amplifier, and the second node is formed at a non-inverting terminal of the amplifier.

17. The capacitive element according to claim 1, wherein the electronic circuit is a source follower circuit having a field effect transistor and a current source, the first node being formed at a source terminal of the field effect transistor, and the second node being formed at a gate terminal of the field effect transistor.

18. The capacitive element according to claim 1, wherein the electronic circuit is a source follower circuit and includes a field effect transistor and a current source, the drain terminal of the field effect transistor is connected to a potential line and the source terminal is connected to the current source, the first node is formed at the source terminal of the field effect transistor, and the second node is formed at the gate terminal of the field effect transistor.

19. The capacitive element according to claim 1, wherein the electronic circuit is a gate circuit, and the first node is formed at an output terminal of the gate circuit, and the second node is formed at an input terminal of the gate circuit.

20. A display device comprising: a ramp voltage generation circuit that generates a ramp voltage whose voltage level changes over time; and a signal line voltage generation circuit that generates a signal line voltage by holding the voltage level of the ramp voltage at a timing according to the signal level of a pixel signal, wherein the ramp voltage generation circuit has: an amplifier that outputs the ramp voltage; a capacitive element arranged on a feedback path of the amplifier; a current generation circuit that controls a current to flow to the capacitive element according to the ramp voltage and a reference voltage; a comparator that compares the ramp voltage with the reference voltage; and a holding unit that holds a comparison result signal of the comparator, wherein the current generation circuit controls the current to flow to the capacitive element based on the comparison result signal; a second node is formed at an inverting terminal of the comparator; a first node is formed at an output terminal of the comparator; and the capacitive element is connected between the first node and the second node, and the capacitive element comprises: a substrate; a first capacitance layer having a loop-shaped metal wiring formed in a plane along an upper surface of the substrate, a comb-shaped first metal wiring connected to the loop-shaped metal wiring and formed within the loop-shaped metal wiring, and a comb-shaped second metal wiring formed within the loop-shaped metal wiring of the first metal wiring, wherein the first metal wiring is connected to the first node and the second metal wiring is connected to the second node.

Images