Semiconductor device

Abstract

This semiconductor device includes: a first metal plate, a semiconductor chip disposed on the first metal plate and having a first electrode electrically connected to the first metal plate; and a second metal plate electrically connected to a second electrode of the semiconductor chip. The second metal plate has a positioning mechanism for positioning with respect to the first metal plate. A first portion of the second metal plate is electrically connected to the second electrode. A second portion of the second metal plate is electrically connected to the first metal plate. The height of the first portion and the height of the second portion are different.

Description

Semiconductor Devices

[0001] This disclosure relates to a semiconductor device. This application claims priority to Japanese Application No. 2024-015974, filed February 5, 2024, and incorporates by reference all of the contents of said Japanese application.

[0002] A technology relating to a semiconductor device including a semiconductor element has been disclosed (see, for example, Patent Document 1). The semiconductor device disclosed in Patent Document 1 includes a ceramic substrate, a semiconductor element bonded to one conductor layer of the ceramic substrate, a frame member disposed on the one conductor layer so as to surround a side surface of the semiconductor element, and an electrode bonded to the upper part of the semiconductor element by an adhesive layer and having a first fitting portion formed on a side surface thereof. The inner wall of the frame member is formed with a second fitting portion that fits into the first fitting portion of the electrode, and a first positioning portion that extends from the inner wall of the frame member to the side surface of the electrode.

[0003] WO2018 / 131473

[0004] A semiconductor device according to the present disclosure includes a first metal plate, a semiconductor chip disposed on the first metal plate and having a first electrode electrically connected to the first metal plate, and a second metal plate electrically connected to a second electrode of the semiconductor chip. The second metal plate has a positioning mechanism for positioning the second metal plate with respect to the first metal plate. A first portion of the second metal plate is electrically connected to the second electrode. A second portion of the second metal plate is electrically connected to the first metal plate. The height of the first portion and the height of the second portion are different.

[0005] FIG. 1 is a schematic perspective view of a semiconductor device in a first embodiment. FIG. 2 is a schematic plan view of the semiconductor device shown in FIG. 1. FIG. 3 is a schematic side view of the semiconductor device shown in FIG. 1. FIG. 4 is a schematic perspective view of the semiconductor device shown in FIG. 1 with a sealing material (described later) removed. FIG. 5 is a schematic plan view of the semiconductor device shown in FIG. 4. FIG. 6 is a schematic side view of the semiconductor device shown in FIG. 4 with a frame (described later) removed. FIG. 7 is a schematic plan view of the semiconductor device shown in FIG. 4 with a second metal plate, a frame, a first main terminal, and the like removed. FIG. 8 is a schematic perspective view of the semiconductor device with a second metal plate arranged. FIG. 9 is a schematic plan view of the semiconductor device shown in FIG. 8. FIG. 10 is a schematic front view of the semiconductor device shown in FIG. 8. FIG. 11 is a schematic perspective view of the semiconductor device shown in FIG. 8, where a region including a first flat portion is enlarged. FIG. 12 is a schematic perspective view of the semiconductor device shown in FIG. 8, where a region including a second flat portion is enlarged. FIG. 13 is a schematic perspective view of a semiconductor device in a second embodiment. FIG. 14 is a schematic plan view of the semiconductor device shown in FIG. 13. Fig. 15 is a schematic side view of the semiconductor device shown in Fig. 13. Fig. 16 is a schematic perspective view showing a state in which the sealing material has been removed from the semiconductor device shown in Fig. 13. Fig. 17 is a schematic plan view of the semiconductor device shown in Fig. 16. Fig. 18 is a schematic side view of the semiconductor device shown in Fig. 16.

[0006] [Problem to be Solved by the Present Disclosure] The semiconductor device disclosed in Patent Document 1 requires many components for alignment when bonding electrodes to a semiconductor element. This results in the accumulation of tolerances among the components, resulting in a decrease in alignment accuracy. In addition, it is necessary to ensure high insulation between the electrodes and the conductor layer to which the semiconductor element is bonded, by avoiding unexpected contact.

[0007] Therefore, one object is to provide a semiconductor device that can ensure high insulation and can be manufactured with high precision.

[0008] Effect of the Present Disclosure According to such a semiconductor device, high insulation properties can be ensured and it can be manufactured with high precision.

[0009] [Description of Embodiments of the Present Disclosure] (1) A semiconductor device according to the present disclosure includes a first metal plate, a semiconductor chip disposed on the first metal plate, a first electrode of which is electrically connected to the first metal plate, and a second metal plate electrically connected to a second electrode of the semiconductor chip. The second metal plate has a positioning mechanism for positioning the second metal plate with respect to the first metal plate. A first portion of the second metal plate is electrically connected to the second electrode. A second portion of the second metal plate is electrically connected to the first metal plate. The height of the first portion and the height of the second portion are different.

[0010] According to the semiconductor device of the present disclosure, the second metal plate has a positioning mechanism for positioning it relative to the first metal plate, thereby preventing misalignment of the second metal plate relative to the first metal plate during manufacturing. In this case, since misalignment between the first metal plate and the second metal plate can be prevented, the accumulation of tolerances between the components can be prevented, allowing for precision manufacturing. Furthermore, since the height of the first portion of the second metal plate connected to the second electrode is different from the height of the second portion electrically connected to the first metal plate, the height difference ensures an insulation distance. Therefore, high insulation can be ensured. As described above, such a semiconductor device can ensure high insulation and can be manufactured with precision.

[0011] (2) In the above (1), the positioning mechanism may include at least one of a positioning hole, a positioning pin that fits into the positioning hole, a positioning notch provided in at least one of the first metal plate and the second metal plate, and a mechanism for matching the outer shape of the second metal plate to the first metal plate, and may be provided in the overlapping portions of the first metal plate and the second metal plate. By adopting the above-described configuration as the positioning mechanism, the second metal plate can be positioned relative to the first metal plate using the outer shape, thereby more reliably suppressing misalignment of the second metal plate relative to the first metal plate. Therefore, more accurate and efficient manufacturing is possible.

[0012] (3) In the above (1) or (2), the second metal plate may include a first surface having a different height from the first portion. By doing so, a long insulation distance can be ensured on the first surface having a different height from the first portion joined to the second electrode, and high insulation can be ensured between the first metal plate and the portion of the second metal plate other than the first portion.

[0013] (4) In any of the above (1) to (3), the first portion may include a first flat portion connected to the second electrode. This allows the second electrode and the second metal plate to be in contact over a wide area while achieving a high degree of flatness in the first flat portion. Therefore, the second electrode and the second metal plate can be more reliably connected.

[0014] (5) In any of the above (1) to (4), the second portion may include a second flat portion connected to the first metal plate. This allows the first metal plate and the second metal plate to be in contact with each other over a wide area while achieving a high degree of flatness in the second flat portion. Therefore, the first metal plate and the second metal plate can be connected more reliably.

[0015] (6) In any of the above (1) to (5), the second metal plate may be provided with at least one of a through hole and a notch penetrating in the thickness direction. This allows the sealing material to flow more easily when the sealing material is injected after the second metal plate is assembled, and also makes it easier for trapped air to escape, reducing the risk of voids remaining in the sealing material. Therefore, productivity can be improved and high insulation properties can be ensured.

[0016] (7) In any of (1) to (6) above, the second metal plate may include a first surface having a different height from the first portion. The thickness of the first flat portion may be thinner than the thickness of the portion where the first surface is provided. This can alleviate stress in the first flat portion and reduce the risk of cracks occurring in the bonding material between the second electrode and the first flat portion near the bonding point with the second electrode due to heat generated by the semiconductor chip during operation. Therefore, the reliability of the semiconductor device can be improved over the long term.

[0017] (8) In any of the above (1) to (7), a plurality of positioning mechanisms may be provided. By doing so, the use of a plurality of positioning mechanisms can more reliably reduce the risk of misalignment of the second metal plate with respect to the first metal plate.

[0018] (9) In any of the above (1) to (8), the positioning mechanism may be provided on the second flat portion. By doing so, the positioning mechanism is provided on the second flat portion that contacts the first metal plate, so that the position where the first metal plate and the second flat portion are electrically connected can be determined with high precision. Furthermore, to bring the second flat portion into contact with the first metal plate, the second flat portion can be pressed to determine the position in the Z direction (described later), and at the same time, the positioning mechanism can be used to determine the positions in the X direction and the Y direction (described later).

[0019] (10) In any of the above (1) to (9), the second metal plate may be integrally formed. That is, the second metal plate does not need to be separated into two or more components. By doing so, it is possible to suppress the accumulation of tolerances of each component compared to when the second metal plate is formed of multiple components for multiple parallel semiconductor chips. Therefore, it is possible to manufacture semiconductor devices with higher precision.

[0020] (11) In any of the above (5) to (10), at least one of the first flat portion and the second flat portion may be formed by drawing. This allows the first flat portion and the second flat portion to be formed relatively easily and accurately. Therefore, it is possible to reduce manufacturing costs and improve accuracy.

[0021] (12) In any of the above (3) to (11), the first surface may be formed by drawing. This allows the first surface to be formed relatively easily and accurately. Therefore, it is possible to reduce manufacturing costs and improve accuracy.

[0022] (13) In any of (1) to (12) above, the semiconductor chip may be a transistor chip. The second electrode may be a source electrode. The second flat portion may be connected to a first metal plate having the same potential as the second electrode. A semiconductor device using such a transistor chip can ensure electrical connection between the transistor chip and the first metal plate by the second metal plate.

[0023] (14) In any of the above (1) to (12), the semiconductor chip may be a diode chip. The second electrode may be a cathode electrode. The second flat portion may be connected to a first metal plate having the same potential as the second electrode. A semiconductor device using such a diode chip can ensure electrical connection between the diode chip and the first metal plate by the second metal plate.

[0024] (15) In any of the above (5) to (14), the second flat portion may be connected by at least one of fusion bonding and liquid phase bonding. This makes it possible to more reliably ensure electrical connection between the second flat portion and the first metal plate. Therefore, the semiconductor device can be driven more reliably, and reliability can be improved.

[0025] [Details of the Embodiments of the Present Disclosure] Next, embodiments of the semiconductor device of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference characters, and description thereof will not be repeated.

[0026] (First Embodiment) A semiconductor device according to a first embodiment of the present disclosure will be described. FIG. 1 is a schematic perspective view of the semiconductor device according to the first embodiment. FIG. 2 is a schematic plan view of the semiconductor device shown in FIG. 1. FIG. 2 is a view from the direction indicated by arrow II in FIG. 1. FIG. 3 is a schematic side view of the semiconductor device shown in FIG. 1. FIG. 3 is a view from the direction indicated by arrow III in FIG. 1. FIG. 4 is a schematic perspective view showing the semiconductor device shown in FIG. 1 with a sealing material, which will be described later, removed. FIG. 5 is a schematic plan view of the semiconductor device shown in FIG. 4. FIG. 5 is a view from the direction indicated by arrow V in FIG. 4. FIG. 6 is a schematic side view showing the semiconductor device shown in FIG. 4 with a frame, which will be described later, removed.

[0027] 1, 2, 3, 4, 5, and 6, semiconductor device 10a according to the first embodiment includes heat sink 11a, base substrate 12a, frame body 13a, first main terminal 14a, second main terminal 15a, first control terminal 16a, second control terminal 17a, and sealing material 18a. In the drawings shown in FIG. 1 and subsequent drawings, the X direction indicates the direction in which first control terminal 16a and second control terminal 17a, which protrude from frame body 13a, are aligned, the Y direction indicates the direction perpendicular to the X direction, and the Z direction indicates the thickness direction of heat sink 11a. The X direction, Y direction, and Z direction are perpendicular to each other.

[0028] The heat sink 11a is rectangular in the thickness direction (Z direction) and is a single plate. The heat sink 11a functions as a heat sink and is made of, for example, a material with good thermal conductivity, specifically, an alloy such as copper (Cu), aluminum (Al), or Al-SiC. The heat sink 11a is made of, for example, a copper plate. Furthermore, the heat sink 11a may be provided with fins.

[0029] The base substrate 12a includes a first metal plate 21a, an insulating plate 22a, and a metal plate 23a. The insulating plate 22a has a rectangular shape when viewed from the Z direction. The insulating plate 22a may be made of, for example, aluminum oxide (Al ２ O ３ Examples of suitable materials include silicon nitride (SiN), silicon nitride (SiN), and aluminum nitride (AlN). The first metal plate 21a is formed on a first main surface 24a located on one side of the insulating plate 22a in the thickness direction. The metal plate 23a is formed on a second main surface 25a located on the opposite side of the insulating plate 22a in the thickness direction from the first main surface 24a. The base substrate 12a has a laminated structure in which the insulating plate 22a is sandwiched between the first metal plate 21a and the metal plate 23a. The base substrate 12a is arranged so that the metal plate 23a of the base substrate 12a faces the heat sink 11a. The base substrate 12a is bonded to the metal plate 23a and the heat sink 11a using solder 26a as a bonding material disposed between the metal plate 23a and the heat sink 11a. Note that a sintered material may be used instead of the solder 26a to bond the metal plate 23a and the heat sink 11a.

[0030] The first metal plate 21a includes a first region 31a, a second region 32a, a third region 33a, a fourth region 34a, a fifth region 35a, and a sixth region 36a. In this embodiment, the first metal plate 21a is composed of the first region 31a, the second region 32a, the third region 33a, the fourth region 34a, the fifth region 35a, and the sixth region 36a, which are arranged on the heat sink 11a with a gap between them. The first region 31a, the second region 32a, the third region 33a, the fourth region 34a, the fifth region 35a, and the sixth region 36a are spaced apart from one another, i.e., are arranged so as not to contact each other on the insulating plate 22a. The first metal plate 21a is formed, for example, by removing only predetermined portions of a metal plate on the insulating plate 22a by etching and patterning it so as to leave the first region 31a and the like.

[0031] The first region 31a and the second region 32a are each rectangular when viewed in the thickness direction and are arranged so as to form a strip-like shape that is elongated in the Y direction. The first region 31a is arranged close to a first wall portion 41a (described later) of the frame body 13a. The second region 32a is arranged close to a second wall portion 42a (described later) of the frame body 13a. The third region 33a and the fourth region 34a are each rectangular when viewed in the thickness direction. The third region 33a is a strip-like shape that is elongated in the Y direction. The fourth region 34a is a square-like shape when viewed in the thickness direction. The third region 33a and the fourth region 34a are arranged between the first region 31a and the second region 32a in the X direction. The third region 33a and the fourth region 34a are arranged adjacent to each other in the Y direction. The third region 33a is arranged on a third wall portion 43a (described later) of the frame body 13a. The fifth region 35a has a strip-like portion that is elongated in the X direction. The fifth region 35a is T-shaped when viewed in the thickness direction. The fifth region 35a is arranged along a fourth wall portion 44a (described later) of the frame body 13a. The fifth region 35a is arranged side by side with the first region 31a, the second region 32a, and the fourth region 34a in the Y direction. The sixth region 36a is square-shaped when viewed in the thickness direction, and its area is smaller than that of the fourth region 34a. The sixth region 36a is arranged adjacent to a strip-shaped portion of the fifth region 35a that is long in the X direction in the Y direction. The sixth region 36a is arranged near the fourth wall portion 44a.

[0032] The frame 13a includes a first wall 41a, a second wall 42a, a third wall 43a, and a fourth wall 44a, each extending from the heat sink 11a. The first wall 41a and the second wall 42a are arranged opposite each other in the X direction. The third wall 43a and the fourth wall 44a are arranged opposite each other in the Y direction. The fourth wall 44a has a protrusion 45a that protrudes outward in the Y direction. The outer shape of the frame 13a is rectangular when viewed in the thickness direction, excluding the portion where the protrusion 45a is provided. On the base substrate 12a, a sealing material 18a is disposed in a space 19a surrounded by the first wall 41a, the second wall 42a, the third wall 43a, and the fourth wall 44a. The first control terminal 16a and the second control terminal 17a are attached to the protrusion 45a of the fourth wall 44a. The first control terminal 16a and the second control terminal 17a are attached to the frame body 13a by insert molding.

[0033] The frame 13a is made of resin. Specifically, examples of the material of the frame 13a include polyphenylene sulfide (PPS) and polybutylene terephthalate (PBT). The frame 13a is manufactured by injection molding, cutting, or three-dimensional shaping. The sealing material 18a is, for example, a thermosetting resin such as silicone gel or epoxy resin. After parts such as transistors and wires are mounted, the sealing material 18a is injected into the space 19a and hardened by heating.

[0034] The semiconductor device 10a includes a transistor chip (first transistor chip) 51a, a transistor chip (second transistor chip) 52a, a diode chip (first diode chip) 53a, and a diode chip (second diode chip) 54a, each of which serves as a semiconductor chip. That is, the semiconductor device 10a includes a plurality of, specifically two, transistor chips and a plurality of, specifically two diode chips.

[0035] The transistor chip 51a and the transistor chip 52a are each a so-called vertical transistor chip. In this embodiment, the transistor chip 51a and the transistor chip 52a are each, for example, a metal-oxide-semiconductor field effect transistor (MOSFET). The transistor chip 51a and the transistor chip 52a are each a switching element.

[0036] The diode chip 53a and the diode chip 54a are each a so-called vertical diode. In this embodiment, the diode chip 53a and the diode chip 54a are each, for example, a Schottky barrier diode (SBD).

[0037] The transistor chip 51a and the diode chip 53a are arranged side by side in the Y direction on the first metal plate 21a. The transistor chip 52a and the diode chip 54a are arranged side by side in the Y direction on the first metal plate 21a. Specifically, the transistor chip 51a and the diode chip 53a are arranged on the first region 31a such that the transistor chip 51a is closer to the fourth wall portion 44a. The transistor chip 52a and the diode chip 54a are arranged on the second region 32a such that the transistor chip 52a is closer to the fourth wall portion 44a.

[0038] The transistor chip 51a includes a drain electrode 71a, a source electrode 72a, and a gate electrode 73a. The drain electrode 71a, which serves as a first electrode, is located on the side facing the first region 31a in the Z direction. The source electrode 72a and the gate electrode 73a, which serve as second electrodes, are both located on the opposite side of the drain electrode 71a in the Z direction. As viewed in the Z direction, the area occupied by the source electrode 72a is larger than the area occupied by the gate electrode 73a. The transistor chip 51a is electrically connected by bonding the drain electrode 71a and the first region 31a of the transistor chip 51a with a conductive bonding material. Examples of bonding materials include solder and a conductive sintered material. The transistor chip 52a, like the transistor chip 51a, includes a drain electrode 71a, a source electrode 72a, and a gate electrode 73a. The transistor chip 52a is electrically connected by bonding the drain electrode 71a and the second region 32a of the transistor chip 52a with a bonding material.

[0039] The diode chip 53a includes a cathode electrode 76a and an anode electrode 77a. The cathode electrode 76a, which serves as a second electrode, is provided on the side facing the first region 31a in the Z direction. The anode electrode 77a, which serves as a first electrode, is provided on the opposite side of the cathode electrode 76a in the Z direction. The diode chip 53a is electrically connected to the first region 31a by bonding the cathode electrode 76a to the first region 31a with a conductive bonding material. The diode chip 54a, like the diode chip 53a, includes a cathode electrode and an anode electrode. The diode chip 54a is electrically connected to the second region 32a by bonding the cathode electrode of the diode chip 54a to the second region 32a with a conductive bonding material.

[0040] Furthermore, the gate electrode 73a of the transistor chip 51a and the fifth region 35a are electrically connected by a wire 55a. The gate electrode 73a of the transistor chip 52a and the fifth region 35a are electrically connected by a wire 56a. The fifth region 35a and the first control terminal 16a are electrically connected by a wire 57a. The fourth region 34a and the sixth region 36a are electrically connected by a wire 58a. The sixth region 36a and the second control terminal 17a are electrically connected by a wire 59a.

[0041] The first main terminal 14a and the second main terminal 15a are each formed by bending a metal plate of a predetermined shape. In this embodiment, the first main terminal 14a is a source terminal, and the second main terminal 15a is a drain terminal. The first main terminal 14a and the second main terminal 15a are each disposed on the third wall portion 43a side in the Y direction. The first main terminal 14a has a first protruding region that is bent and protrudes from the sealing material 18a. The second main terminal 15a has a second protruding region that is bent and protrudes from the sealing material 18a. The first and second protruding regions are attached so that a portion of the first protruding region and a portion of the second protruding region extend beyond the Z-direction end surface of the third wall portion 43a in the Z direction. The first and second protruding regions are arranged side by side with a gap in the X direction. The first protruding region is located closer to the first wall portion 41a than the second protruding region. A circular hole 37a penetrating in the Z direction is provided near the end of the first protruding region. A round hole 38a is provided near the end of the second projecting region, penetrating in the Z direction.

[0042] The first main terminal 14a is joined to the third region 33a. The first main terminal 14a and the third region 33a may be joined via solder or a conductive joining material, or by laser welding or ultrasonic joining. The second main terminal 15a is joined to the first region 31a and the second region 32a. The joining means for the second main terminal 15a is the same as that for the first main terminal 14a.

[0043] The first control terminal 16a and the second control terminal 17a each have a shape formed by bending a thin strip-shaped metal member into an L-shape. In this embodiment, the first control terminal 16a is a gate control terminal, and the second control terminal 17a is an auxiliary source terminal (Kelvin source terminal). Both the first control terminal 16a and the second control terminal 17a are embedded in the frame body 13a, specifically, in the fourth wall portion 44a, so that a portion of each is exposed. The first control terminal 16a and the second control terminal 17a each protrude from the end surface of the fourth wall portion 44a in the Z direction. Furthermore, the first control terminal 16a and the second control terminal 17a each have an exposed region on the inner circumferential surface of the fourth wall portion 44a. In this embodiment, both the first control terminal 16a and the second control terminal 17a are attached and fixed to the frame body 13a by insert molding. The first control terminal 16a is electrically connected to the fifth region 35a by a wire 57a in the region exposed to the space 19a, and the second control terminal 17a is electrically connected to the sixth region 36a by a wire 59a in the region exposed to the space 19a.

[0044] The second metal plate 29a is formed by bending a metal plate of a predetermined shape. The second metal plate 29a is integrally formed. That is, the second metal plate 29a is not separated into two or more components, and is not formed by bonding or joining multiple components together. The second metal plate 29a includes a first portion 61a and a second portion 62a. The first portion 61a includes a first flat portion 63a having a flat surface. The first flat portion 63a is electrically connected to the source electrode 72a of the transistor chip 51a (second electrode) and the source electrode 72a of the transistor chip 52a (second electrode). The first flat portion 63a is also electrically connected to the anode electrode 77a of the diode chip 53a (second electrode) and the anode electrode 77a of the diode chip 54a (second electrode). The second portion 62a includes a second flat portion 64a having a flat surface. The second flat portion 64a is electrically connected to the first metal plate 21a, specifically, to the third region 33a and the fourth region 34a of the first metal plate 21a. That is, the second flat portion 64a is electrically connected to the first metal plate 21a, which has the same potential as the source electrodes 72a, which are the second electrodes of the transistor chips 51a and 52a. The second flat portion 64a is also electrically connected to the anode electrodes 77a, which are the second electrodes of the diode chips 53a and 54a. The second flat portion 64a is connected by at least one of fusion bonding and liquid-phase bonding. In this embodiment, the first flat portion 63a and the second flat portion 64a are each formed by drawing.

[0045] The second metal plate 29a has a first surface 65a that is at a different height from the first portion 61a. The first surface 65a is a surface of the second metal plate 29a that is located in the thickness direction, specifically, a surface that is located on the opposite side of the second surface that faces the base substrate 12a in the thickness direction. The thickness of the first flat portion 63a is thinner than the thickness of the portion where the first surface 65a is provided. Specifically, the thickness of the first flat portion 63a is set to T １ The thickness of the portion where the first surface 65a is provided is T ２ Then, T １ <T ２(See FIG. 6 in particular.) In this embodiment, the first surface 65a is also formed by drawing.

[0046] FIG. 7 is a schematic plan view of the semiconductor device 10a, showing the state in which the second metal plate 29a, the frame 13a, the first main terminals 14a, etc. have been removed. Note that in FIG. 7, the area where the first flat portion 63a is located is indicated by a dashed line for ease of understanding. Also referring to FIG. 7, the second metal plate 29a has a positioning mechanism 66a that positions the second metal plate 29a relative to the first metal plate 21a. In this embodiment, the positioning mechanism 66a is a positioning hole (first positioning hole) 67a and a positioning hole (second positioning hole) 68a provided in the overlapping portions of the first metal plate 21a and the second metal plate 29a, respectively. The positioning holes 67a are provided in multiple locations, two in this embodiment, spaced apart in the Y direction. The positioning holes 68a are provided in multiple locations, two in this embodiment, spaced apart in the Y direction, corresponding to the positioning holes 67a provided in the first metal plate 21a. The positions of the two positioning holes 67a and the two positioning holes 68a in the X direction are aligned. The positioning holes 67a and the positioning holes 68a are circular holes of the same shape that penetrate the respective members in the thickness direction. During assembly, the positions of the second metal plate 29a relative to the first metal plate 21a are adjusted in the X direction and the Y direction so that the positions of the positioning holes 67a in the first metal plate 21a are aligned with the positions of the positioning holes 68a in the second metal plate 29a. In this case, because multiple positioning mechanisms 66a are provided, positioning in the X-Y plane can be performed more reliably.

[0047] The second metal plate 29a has through holes 74a and cutouts 75a that penetrate the plate in the thickness direction. Two through holes 74a are provided spaced apart in the X direction, each of which is a round hole that penetrates the plate in the thickness direction. The cutouts 75a also penetrate the plate in the thickness direction. Specifically, four cutouts 75a recessed in the Y direction and two cutouts 75a recessed in the X direction are provided.

[0048] Next, a brief description of the current flow during operation of the semiconductor device 10a will be given. When the transistor chips 51a and 52a are turned on by control of the first control terminal 16a, which serves as a gate terminal, current flows from the second main terminal 15a, which serves as a drain terminal, to the first region 31a and the second region 32a of the first metal plate 21a. Then, current flows vertically (thicknesswise) from the drain electrodes 71a of the transistor chips 51a and 52a to their source electrodes 72a, passing through the third region 33a of the first metal plate 21a and reaching the first main terminal 14a, which serves as a source terminal electrically connected to the first metal plate 21a. The reference potential of the first control terminal 16a is the reference potential of the second control terminal 17a via the fourth region 34a and the sixth region 36a of the first metal plate 21a.

[0049] Next, a brief description will be given of an example of a method for manufacturing the semiconductor device 10a having the above-described configuration. First, the following components are prepared: the base substrate 12a having the above-described configuration, including the first metal plate 21a having the first region 31a and the positioning hole 67a, the second metal plate 29a having the first flat portion 63a, the second flat portion 64a, the positioning hole 68a, the through-hole 74a, the notch 75a, and the heat sink 11a; and the frame 13a having the first control terminal 16a and the second control terminal 17a incorporated therein by, for example, insert molding. The second metal plate 29a is manufactured, for example, by drawing, as described above.

[0050] Then, solder 26a serving as a bonding material is placed on the prepared heat sink 11a, and the base substrate 12a is placed on top of that. In this case, after the base substrate 12a is placed, bonding material is placed in predetermined positions, and the transistor chip 51a, the transistor chip 52a, the diode chip 53a, and the diode chip 54a are placed on top of them. Bonding material is then placed on the source electrode 72a, etc., serving as the second electrode, which is the top surface of each chip. Next, the second metal plate 29a is positioned relative to the first metal plate 21a using the positioning mechanism 66a, i.e., the positioning hole 68a in the second metal plate 29a and the positioning hole 67a in the first metal plate 21a, and the second metal plate 29a is then placed.

[0051] Fig. 8 is a schematic perspective view of the semiconductor device 10a showing a state in which the second metal plate 29a is arranged. Fig. 9 is a schematic plan view of the semiconductor device 10a shown in Fig. 8. Fig. 9 is a view from the direction indicated by arrow IX in Fig. 8. Fig. 10 is a schematic front view of the semiconductor device 10a shown in Fig. 8. Fig. 10 is a view from the direction indicated by arrow X in Fig. 8. Fig. 11 is a schematic perspective view showing an enlarged view of a region including the first flat portion 63a in the semiconductor device 10a shown in Fig. 8. Fig. 12 is a schematic perspective view showing an enlarged view of a region including the second flat portion 64a in the semiconductor device 10a shown in Fig. 8.

[0052] Referring to Figures 8, 9, 10, 11 and 12, the positioning mechanism 66a, i.e., the positioning hole 67a provided in the first metal plate 21a and the positioning hole 68a provided in the second metal plate 29a, is used to position the second metal plate 29a relative to the first metal plate 21a so that the respective positioning holes 67a and positioning holes 68a are aligned in the thickness direction, and the second metal plate 29a is placed in the desired position.

[0053] Here, the second flat portion 64a of the second metal plate 29a is pressed against the surface of the second metal plate 29a in the direction of the arrow P in FIG. 12 using a jig (not shown). １ As shown in FIG. 1, the second metal plate 29a is pressed in the thickness direction so as to contact the first metal plate 21a. After that, reflow is performed to bond the components together using a bonding material. Next, the second flat portion 64a of the second metal plate 29a and the first metal plate 21a, specifically the third region 33a and the fourth region 34a of the first metal plate 21a, are laser-welded together.

[0054] Thereafter, the frame 13a is fixed to the heat sink 11a using an adhesive. The frame 13a, which has been prepared so as to surround the base substrate 12a, is attached to the heat sink 11a and fixed thereto using an adhesive.

[0055] Next, the respective components are bonded using wires 55a, 56a, 57a, 58a, and 59a. Specifically, the gate electrode 73a of the transistor chip 51a is electrically connected to the fifth region 35a using wire 55a, the gate electrode 73a of the transistor chip 52a is electrically connected to the fifth region 35a using wire 56a, the first control terminal 16a is electrically connected to the fifth region 35a using wire 57a, the third region 33a is electrically connected to the sixth region 36a using wire 58a, and the second control terminal 17a is electrically connected to the sixth region 36a using wire 59a. In this case, the respective components are connected by wire bonding using, for example, a bonding tool.

[0056] Thereafter, uncured liquid sealing material 18a is poured into space 19a surrounded by frame 13a. Next, after air is removed, sealing material 18a is cured by heating, and semiconductor device 10a having the above configuration is obtained.

[0057] In the semiconductor device 10a configured as described above, the second metal plate 29a has a positioning mechanism 66a that positions it relative to the first metal plate 21a, thereby preventing misalignment of the second metal plate 29a relative to the first metal plate 21a during manufacturing. In this case, misalignment between the first metal plate 21a and the second metal plate 29a can be prevented, preventing the accumulation of tolerances between the various components and enabling precision manufacturing. Furthermore, the height of the first portion 61a of the second metal plate 29a, which is connected to the second electrode, is different from the height of the second portion 62a, which is electrically connected to the first metal plate 21a, ensuring an insulation distance due to the height difference. Therefore, high insulation properties can be ensured. As described above, the semiconductor device 10a can ensure high insulation properties and can be manufactured with precision.

[0058] In addition, with the semiconductor device 10a having the above configuration, the second metal plate 29a is not positioned using the frame body 13a as in the semiconductor device disclosed in Patent Document 1, so even if the number of arms is increased to 2 in 1 or 6 in 1, the semiconductor device 10a can be configured while achieving positioning with a relatively simple shape. Also, although reflow is sometimes performed when joining by soldering, with the semiconductor device 10a having the above configuration, there is no need to perform reflow including the frame body 13a, so there is no need to consider the heat resistance required for the frame body 13a.

[0059] In this embodiment, the positioning mechanism 66a includes positioning holes 68a and 67a provided in the overlapping portions of the first metal plate 21a and the second metal plate 29a, respectively. By employing the above-described configuration for the positioning mechanism 66a, the second metal plate 29a can be positioned relative to the first metal plate 21a using the outer shape, thereby more reliably suppressing misalignment of the second metal plate 29a relative to the first metal plate 21a. This allows for more accurate and efficient manufacturing.

[0060] In this embodiment, the second metal plate 29a includes a first surface 65a that is at a different height from the first portion 61a. Therefore, a long insulation distance can be ensured at the first surface 65a that is at a different height from the first portion 61a that is joined to the second electrode, and high insulation can be ensured between the first metal plate 21a and the portion of the second metal plate 29a other than the first portion 61a.

[0061] In this embodiment, the first portion 61a includes a first flat portion 63a connected to the second electrode. Therefore, the first flat portion 63a realizes high flatness, and the second electrode and the second metal plate 29a can be in contact with each other over a wide area. Therefore, the second electrode and the second metal plate 29a can be connected more reliably.

[0062] In this embodiment, the second portion 62a includes a second flat portion 64a that is connected to the first metal plate 21a. Therefore, the second flat portion 64a allows the first metal plate 21a and the second metal plate 29a to be in contact with each other over a wide area while realizing a high degree of flatness. Therefore, the first metal plate 21a and the second metal plate 29a can be connected more reliably.

[0063] In this embodiment, the second metal plate 29a has a through-hole 74a and a notch 75a that penetrate through the second metal plate 29a in the thickness direction. Therefore, after the second metal plate 29a is assembled, when the uncured sealing material 18a is injected, the area of ​​the space 19a covered by the second metal plate 29a can be reduced. This allows the sealing material 18a to flow more easily using the through-hole 74a and the notch 75a, and also facilitates the escape of trapped air, reducing the risk of voids remaining in the sealing material 18a. This improves productivity and ensures high insulation.

[0064] In this embodiment, the thickness of the first flat portion 63a is thinner than the thickness of the portion where the first surface 65a is provided. This allows for stress relief in the first flat portion 63a, reducing the risk of cracks occurring in the bonding material between the second electrode and the first flat portion 63a near the bonding point with the second electrode due to heat generated by the transistor chip 51a during operation. This allows for improved long-term reliability of the semiconductor device 10a.

[0065] In this embodiment, a plurality of positioning mechanisms 66a are provided, and thus, by using the plurality of positioning mechanisms 66a, it is possible to more reliably prevent the second metal plate 29a from being misaligned with respect to the first metal plate 21a.

[0066] In this embodiment, the positioning mechanism 66a is provided on the second flat portion 64a. Therefore, since the positioning mechanism 66a is provided on the second flat portion 64a that contacts the first metal plate 21a, the position where the first metal plate 21a and the second flat portion 64a are electrically connected can be determined with high precision. Furthermore, to bring the first metal plate 21a into contact with the second flat portion 64a, the second flat portion 64a is pressed to determine the position in the Z direction, and at the same time, the positioning mechanism 66a can be used to determine the positions in the X and Y directions.

[0067] In this embodiment, the second metal plate 29a is formed as a single piece. Therefore, compared to when the second metal plate 29a is formed from multiple parts for multiple semiconductor chips arranged in parallel, it is possible to suppress the accumulation of tolerances between the parts. Therefore, the semiconductor device 10a can be manufactured with higher precision.

[0068] In this embodiment, the first flat portion 63 a and the second flat portion 64 a are formed by drawing. This allows the first flat portion 63 a and the second flat portion 64 a to be formed relatively easily and accurately, thereby reducing manufacturing costs and improving accuracy.

[0069] In this embodiment, the first surface 65a is formed by drawing, which allows the first surface 65a to be formed relatively easily and accurately, thereby reducing manufacturing costs and improving accuracy.

[0070] In this embodiment, the semiconductor chips are transistor chips 51a and 52a. The second electrode is a source electrode 72a. The second flat portion 64a is connected to the first metal plate 21a, which has the same potential as the second electrode. In the semiconductor device 10a using such transistor chips 51a and 52a, the second metal plate 29a ensures electrical connection between the transistor chips 51a and 52a and the first metal plate 21a.

[0071] In this embodiment, the second flat portion 64a is connected by fusion welding, which ensures a more reliable electrical connection between the second flat portion 64a and the first metal plate 21a. This allows the semiconductor device 10a to be driven more reliably, thereby improving reliability.

[0072] Second Embodiment A second embodiment, which is another embodiment, will now be described. FIG. 13 is a schematic perspective view of a semiconductor device in the second embodiment. FIG. 14 is a schematic plan view of the semiconductor device shown in FIG. 13. FIG. 14 is a view from the direction indicated by arrow XIV in FIG. 13. FIG. 15 is a schematic side view of the semiconductor device shown in FIG. 13. FIG. 15 is a view from the direction indicated by arrow XV in FIG. 13. FIG. 16 is a schematic perspective view showing the semiconductor device shown in FIG. 13 with the sealing material removed. FIG. 17 is a schematic plan view of the semiconductor device shown in FIG. 16. FIG. 17 is a view from the direction indicated by arrow XVII in FIG. 16. FIG. 18 is a schematic side view of the semiconductor device shown in FIG. 16. FIG. 18 is a view from the direction indicated by arrow XVIII in FIG. The semiconductor device in the second embodiment basically has the same configuration as the first embodiment and achieves the same effects. However, the semiconductor device in the second embodiment differs from the first embodiment in that it does not include a frame body or a heat sink.

[0073] 13 , 14 , 15 , 16 , 17 , and 18 , semiconductor device 10b according to the second embodiment does not include frame body 13a like semiconductor device 10a according to the first embodiment. First main terminal 14b, second main terminal 15b, first control terminal 16b, and second control terminal 17b are each formed by bending a metal plate. That is, first main terminal 14b, second main terminal 15b, first control terminal 16b, and second control terminal 17b also serve as first metal plate 21b. Specifically, first main terminal 14b and the like are configured to include the respective regions included in first metal plate 21b. Two second main terminals 15b are provided spaced apart in the X direction, sandwiching first main terminal 14a. Semiconductor device 10b does not include an insulating plate or a metal plate on the base substrate. Second metal plate 29a has the same configuration as that of the first embodiment.

[0074] The semiconductor device 10b configured as described above does not require a frame, further reducing the number of components. It can also be manufactured using a lead frame made of a single metal plate. In this case, the lead frame is punched into a predetermined shape and then bent. The transistor chip 51a, second metal plate 29a, and other components are then bonded, connected with wires 56a, and sandwiched between upper and lower molds. The encapsulant 18a is then injected into the cavity formed by the molds and allowed to harden. Finally, the outer frame of the lead frame is removed, completing the semiconductor device 10b with the above-described shape. This allows for a simpler manufacturing configuration.

[0075] (Other Embodiments) In the above-described embodiments, the semiconductor chip may be a diode chip. The second electrode may be a cathode electrode. The second flat portion may be connected to a first metal plate having the same potential as the second electrode. A semiconductor device using such a diode chip can ensure electrical connection between the diode chip and the first metal plate by the second metal plate.

[0076] In the above-described embodiments, the positioning mechanism may include at least one of a positioning hole, a positioning pin that fits into the positioning hole, a positioning notch provided in at least one of the first metal plate and the second metal plate, and a mechanism for matching the outer shape of the second metal plate to the first metal plate, and may be provided in the overlapping portions of the first metal plate and the second metal plate. By employing the above-described configuration as the positioning mechanism, the second metal plate can be positioned relative to the first metal plate using the outer shape, thereby more reliably suppressing misalignment of the second metal plate relative to the first metal plate. This allows for more accurate and efficient manufacturing.

[0077] In the above-described embodiments, the transistor chip included in the semiconductor device is not limited to a MOSFET, and may be, for example, an insulated gate bipolar transistor (IGBT). In this case, this can be achieved by replacing the above-described "source" with "emitter" and "drain" with "collector." The diode chip may be a free wheeling diode (FWD).

[0078] In the above-described embodiment, the second metal plate may have at least one of a hole and a notch. This allows the sealing material to flow more easily when the sealing material is injected after the second metal plate is assembled, and also allows trapped air to escape more easily, reducing the risk of voids remaining in the sealing material. This improves productivity and ensures high insulation.

[0079] In the above embodiment, the second flat portion may be connected by at least one of fusion bonding and liquid phase bonding. This makes it possible to more reliably ensure electrical connection between the second flat portion and the first metal plate. This allows the semiconductor device to be driven more reliably, thereby improving reliability.

[0080] It should be understood that the embodiments disclosed herein are illustrative in all respects and are not limiting in any respect. The scope of the present invention is defined not by the above description but by the claims, and it is intended to include all modifications within the meaning and scope of the claims.

[0081] REFERENCE SIGNS LIST 10a, 10b Semiconductor device, 11a Heat sink, 12a Base substrate, 13a Frame, 14a, 14b First main terminal, 15a, 15b Second main terminal, 16a, 16b First control terminal, 17a, 17b Second control terminal, 18a Sealing material, 19a Space, 21a First metal plate, 22a Insulating plate, 23a Metal plate, 24a First main surface, 25a Second main surface, 26a Solder, 29a Second metal plate, 31a First region, 32a Second region, 33a Third region, 34a Fourth region, 35a Fifth region, 36a Sixth region, 37a, 38a Round hole, 41a First wall portion, 42a Second wall portion, 43a Third wall portion, 44a Fourth wall portion, 45a Protrusion, 51a, 52a Transistor chips, 53a, 54a Diode chips, 55a, 56a, 57a, 58a, 59a Wire, 61a First portion, 62a Second portion, 63a First flat portion, 64a Second flat portion, 65a First surface, 66a Positioning mechanism, 67a, 68a Positioning holes, 71a Drain electrode (first electrode), 72a Source electrode (second electrode), 73a Gate electrode, 74a Through hole, 75a Notch, 76a Cathode electrode, 77a Anode electrode.

Claims

1. A semiconductor device comprising: a first metal plate; a semiconductor chip disposed on the first metal plate, the first electrode of which is electrically connected to the first metal plate; and a second metal plate electrically connected to a second electrode of the semiconductor chip, wherein the second metal plate has a positioning mechanism for positioning the second metal plate with respect to the first metal plate; a first portion of the second metal plate is electrically connected to the second electrode; and a second portion of the second metal plate is electrically connected to the first metal plate; and the height of the first portion and the height of the second portion are different.

2. The semiconductor device according to claim 1, wherein the positioning mechanism includes at least one of a positioning hole, a positioning pin that fits into the positioning hole, a positioning notch provided in at least one of the first metal plate and the second metal plate, and a mechanism for matching the outer shape of the second metal plate to the first metal plate, and is provided in the overlapping portions of the first metal plate and the second metal plate.

3. The semiconductor device according to claim 1 or 2, wherein the second metal plate includes a first surface having a different height from the first portion.

4. The semiconductor device according to any one of claims 1 to 3, wherein the first portion includes a first flat portion connected to the second electrode.

5. The semiconductor device according to any one of claims 1 to 4, wherein the second portion includes a second flat portion connected to the first metal plate.

6. The semiconductor device according to any one of claims 1 to 5, wherein the second metal plate is provided with at least one of a through-hole penetrating through the thickness direction and a notch.

7. The semiconductor device according to claim 4, wherein the second metal plate includes a first surface having a different height from the first portion, and the thickness of the first flat portion is thinner than the thickness of the portion where the first surface is provided.

8. The semiconductor device according to any one of claims 1 to 7, wherein a plurality of positioning mechanisms are provided.

9. The semiconductor device according to claim 5, wherein the positioning mechanism is provided on the second flat portion.

10. The semiconductor device according to any one of claims 1 to 9, wherein the second metal plate is integrally formed.

11. The semiconductor device according to claim 5, wherein at least one of the first flat portion and the second flat portion is formed by drawing.

12. The semiconductor device according to claim 3, wherein the first surface is formed by drawing.

13. The semiconductor device according to claim 5, wherein the semiconductor chip is a transistor chip, the second electrode is a source electrode, and the second flat portion is electrically connected to the first metal plate, which has the same potential as the second electrode.

14. The semiconductor device according to claim 5, wherein the semiconductor chip is a diode chip, the second electrode is a cathode electrode, and the second flat portion is electrically connected to the first metal plate which has the same potential as the second electrode.

15. The semiconductor device according to claim 5, wherein the second flat portion is connected by at least one of fusion bonding and liquid phase bonding.

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