Semiconductor device

Abstract

This semiconductor device is provided with a main substrate, a first semiconductor element, a second semiconductor element, a first terminal, and a second conduction member. The main substrate has a first conductive portion and a second conductive portion. The first semiconductor element is mounted on the first conductive portion and has a switching function. The second semiconductor element is mounted on the second conductive portion and has a switching function. The first terminal includes a terminal portion protruding from the main substrate and is in electrical conduction with the second semiconductor element. The second conductive member is interposed between the second semiconductor element and the first terminal. The first terminal is supported by the main substrate.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Conventionally, semiconductor devices including power switching elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) have been known. Such semiconductor devices are installed in a wide variety of electronic devices, from industrial equipment to home appliances, information terminals, and automotive equipment. Patent Document 1 discloses a conventional semiconductor device (power module). The semiconductor device described in Patent Document 1 includes a semiconductor element, a main substrate, and a conductive member. The conductive member is electrically connected to the semiconductor element.

[0003] Japanese Patent Application Laid-Open No. 2023-088629

[0004] [Summary] When a semiconductor device is used, the semiconductor element generates heat, and it is undesirable for the heat from the semiconductor element to be insufficiently dissipated.

[0005] An object of the present disclosure is to provide an improved semiconductor device compared to conventional semiconductor devices. In particular, in view of the above-mentioned circumstances, an object of the present disclosure is to provide a semiconductor device that can promote heat dissipation.

[0006] A semiconductor device provided by a first aspect of the present disclosure comprises a main substrate having a first main surface facing a first side in a thickness direction, a first conductive portion located on a first side in a first direction perpendicular to the thickness direction, and a second conductive portion having a second main surface facing the first side in the thickness direction and located on a second side in the first direction; one or more first semiconductor elements mounted on the first conductive portion and having a switching function; one or more second semiconductor elements mounted on the second conductive portion and having a switching function; a first terminal including a terminal portion protruding to the first side in the first direction relative to the main substrate and conducting to the second semiconductor element; a second conductive member interposed between the second semiconductor element and the first terminal; and a sealing resin covering the one or more first semiconductor elements, the one or more second semiconductor elements, the second conductive member, the main substrate, and a portion of each of the first terminals, wherein the first terminals are supported by the main substrate.

[0007] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0008] FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a partial perspective view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 3 is a partial perspective view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 4 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 5 is a partial plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 6 is a partial side view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 7 is a partial enlarged plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 8 is a partial plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 9 is a partial plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 10 is a side view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 11 is a bottom view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 5. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 5. FIG. 14 is a partial enlarged cross-sectional view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 15 is a partial enlarged cross-sectional view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 16 is a partially enlarged cross-sectional view showing the semiconductor device according to the first embodiment of the present disclosure. FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 5. FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 5. FIG. 19 is a partially enlarged plan view showing the semiconductor device according to the first embodiment of the present disclosure. FIG. 20 is a partially enlarged plan view showing the semiconductor device according to the first embodiment of the present disclosure. FIG. 21 is a configuration diagram showing a vehicle according to the first embodiment of the present disclosure. FIG. 22 is a partially enlarged cross-sectional view showing a first modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 23 is a partially enlarged cross-sectional view showing a second modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 24 is a partially enlarged cross-sectional view showing a third modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 25 is a partially enlarged cross-sectional view showing a fourth modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 26 is a partially enlarged cross-sectional view showing a fifth modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 27 is a partial perspective view showing the semiconductor device according to the second embodiment of the present disclosure. FIG. 28 is a partial side view showing the semiconductor device according to the second embodiment of the present disclosure.29 is a partially enlarged cross-sectional view showing a semiconductor device according to a second embodiment of the present disclosure, and FIG. 30 is a perspective view showing a semiconductor device according to a third embodiment of the present disclosure.

[0009] DETAILED DESCRIPTION Preferred embodiments of the present disclosure will now be described in detail with reference to the drawings.

[0010] The terms "first," "second," "third," etc. in this disclosure are used for identification purposes only and are not intended to impose any ranking on their objects.

[0011] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on a certain object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on a certain object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on a certain object B" includes "a certain object A is located on a certain object B with a certain object A in contact with the certain object B" and "a certain object A is located on a certain object B with another object interposed between the certain object A and the certain object B." Unless otherwise specified, the phrase "an object A overlaps an object B when viewed in a certain direction" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B." In the present disclosure, "a surface A faces in (one side or the other side of) direction B" is not limited to the case where the angle of surface A with respect to direction B is 90°, but also includes the case where surface A is tilted with respect to direction B.

[0012] 1 to 21 show a semiconductor device according to a first embodiment of the present disclosure. The semiconductor device A1 of this embodiment includes a plurality of first semiconductor elements 10A, a plurality of second semiconductor elements 10B, a main substrate 3, a control terminal support 48, two first terminals 41, a second terminal 42, a third terminal 43, a plurality of control terminals 45, a first conductive member 5, a second conductive member 6, and a sealing resin 8.

[0013] FIG. 1 is a perspective view showing the semiconductor device A1. FIG. 2 is a partial perspective view showing the semiconductor device A1. FIG. 3 is a partial perspective view showing the semiconductor device A1. FIG. 4 is a plan view showing the semiconductor device A1. FIG. 5 is a partial plan view showing the semiconductor device A1. FIG. 6 is a partial side view showing the semiconductor device A1. FIG. 7 is a partial enlarged plan view showing the semiconductor device A1. FIG. 8 is a partial plan view showing the semiconductor device A1. FIG. 9 is a partial plan view showing the semiconductor device A1. FIG. 10 is a side view showing the semiconductor device A1. FIG. 11 is a bottom view showing the semiconductor device A1. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 5. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 5. FIG. 14 is a partial enlarged cross-sectional view showing the semiconductor device A1. FIG. 15 is a partial enlarged cross-sectional view showing the semiconductor device A1. FIG. 16 is a partial enlarged cross-sectional view showing the semiconductor device A1. FIG. 17 is a cross-sectional view taken along line XV-XV in FIG. 5. Fig. 18 is a cross-sectional view taken along line XVI-XVI in Fig. 5. Fig. 19 is a partially enlarged plan view showing the semiconductor device A1. Fig. 20 is a partially enlarged plan view showing the semiconductor device A1. Fig. 21 is a configuration diagram showing a vehicle according to the first embodiment of the present disclosure. For ease of understanding, the sealing resin 8 is omitted from Figs. 2, 3, 5 to 9, 19, and 20.

[0014] In these figures, the thickness direction z is an example of the thickness direction in the present disclosure. The first direction x is a direction perpendicular to the thickness direction z. The second direction y is a direction perpendicular to the thickness direction z and the first direction x.

[0015] First semiconductor element 10A, second semiconductor element 10B: One or more first semiconductor elements 10A and one or more second semiconductor elements 10B are electronic components that are central to the functionality of the semiconductor device A1. The constituent material of each first semiconductor element 10A and each second semiconductor element 10B is a semiconductor material primarily composed of, for example, silicon carbide (SiC). This semiconductor material is not limited to silicon carbide (SiC) and may be silicon (Si), gallium nitride (GaN), diamond (C), or the like. Each first semiconductor element 10A and each second semiconductor element 10B is, for example, a power semiconductor chip with switching function, such as a metal oxide semiconductor field effect transistor (MOSFET). In this embodiment, the first semiconductor element 10A and each second semiconductor element 10B are MOSFETs, but are not limited thereto and may be other transistors, such as an insulated gate bipolar transistor (IGBT). The one or more first semiconductor elements 10A and the one or more second semiconductor elements 10B may have different configurations or may have a common configuration. In the following description, the one or more first semiconductor elements 10A and the one or more second semiconductor elements 10B are all the same element. Each of the first semiconductor elements 10A and each of the second semiconductor elements 10B is, for example, an n-channel MOSFET, but may also be a p-channel MOSFET.

[0016] 15 and 16 , the first semiconductor element 10A and the second semiconductor element 10B each have an element main surface 101 and an element back surface 102. In each of the first semiconductor elements 10A and the second semiconductor elements 10B, the element main surface 101 and the element back surface 102 are spaced apart in the thickness direction z. The element main surface 101 faces a first side z1 in the thickness direction z, and the element back surface 102 faces a second side z2 in the thickness direction z.

[0017] The number of one or more first semiconductor elements 10A and the number of one or more second semiconductor elements 10B are changed as appropriate depending on the required performance, such as the current capacity handled by the semiconductor device A1. In this embodiment, as shown in Figures 8 and 9, six first semiconductor elements 10A and six second semiconductor elements 10B are arranged. The number of first semiconductor elements 10A and six second semiconductor elements 10B may be one or two, or seven or more. The number of first semiconductor elements 10A and the number of second semiconductor elements 10B may be equal to or different from each other.

[0018] The semiconductor device A1 is configured, for example, as a half-bridge switching circuit. In this case, a plurality of first semiconductor elements 10A form an upper arm circuit of the semiconductor device A1, and a plurality of second semiconductor elements 10B form a lower arm circuit. In the upper arm circuit, the plurality of first semiconductor elements 10A are connected in parallel with each other, and in the lower arm circuit, the plurality of second semiconductor elements 10B are connected in parallel with each other. The plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B are connected in series to form a bridge layer.

[0019] As shown in Figures 8, 9, and 18, each of the multiple first semiconductor elements 10A is mounted on a first conductive portion 32A of the main substrate 3, which will be described later. In the example shown in Figures 8 and 9, the multiple first semiconductor elements 10A are lined up, for example, in the second direction y and spaced apart from one another. Each first semiconductor element 10A is conductively bonded to the first conductive portion 32A via a first conductive bonding material 19A. The element back surface 102 faces the first conductive portion 32A.

[0020] As shown in Figures 8, 9, and 17, each of the multiple second semiconductor elements 10B is mounted on a second conductive portion 32B of the main substrate 3 (described later). In the example shown in Figures 8 and 9, the multiple second semiconductor elements 10B are aligned, for example, in the second direction y and spaced apart from one another. Each second semiconductor element 10B is conductively bonded to the second conductive portion 32B via a second conductive bonding material 19B. The element back surface 102 faces the second conductive portion 32B. As can be seen from Figure 9, the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B overlap when viewed in the first direction x, but they do not have to overlap.

[0021] The plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B each have a first principal surface electrode 11, a second principal surface electrode 12, a third principal surface electrode 13, and a back surface electrode 15. The configurations of the first principal surface electrode 11, the second principal surface electrode 12, the third principal surface electrode 13, and the back surface electrode 15 described below are common to each of the first semiconductor elements 10A and each of the second semiconductor elements 10B. The first principal surface electrode 11, the second principal surface electrode 12, and the third principal surface electrode 13 are provided on the element main surface 101. The first principal surface electrode 11, the second principal surface electrode 12, and the third principal surface electrode 13 are insulated by an insulating film (not shown). The back surface electrode 15 is provided on the element back surface 102.

[0022] The first principal surface electrode 11 is, for example, a gate electrode, to which a drive signal (for example, a gate voltage) for driving the first semiconductor element 10A (second semiconductor element 10B) is input. In the first semiconductor element 10A (second semiconductor element 10B), the second principal surface electrode 12 is, for example, a source electrode, through which a source current flows. The third principal surface electrode 13 is, for example, a source sense electrode, through which a source current flows. The back surface electrode 15 is, for example, a drain electrode, through which a drain current flows. The back surface electrode 15 covers substantially the entire area of ​​the element back surface 102. The back surface electrode 15 is, for example, formed by Ag (silver) plating.

[0023] When a drive signal (gate voltage) is input to the first principal surface electrode 11 (gate electrode), each first semiconductor element 10A (each second semiconductor element 10B) switches between a conductive state and a cut-off state in response to the drive signal. In the conductive state, current flows from the back surface electrode 15 (drain electrode) to the second principal surface electrode 12 (source electrode), and in the cut-off state, this current does not flow. In other words, each first semiconductor element 10A (each second semiconductor element 10B) performs a switching operation. The semiconductor device A1 converts a DC voltage input between the third terminal 43 and the first terminal 41 into, for example, an AC voltage, using the switching functions of the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B, and outputs the AC voltage from the second terminal 42.

[0024] Main substrate 3: The main substrate 3 supports a plurality of first semiconductor elements 10A and a plurality of second semiconductor elements 10B. The specific configuration of the main substrate 3 is not limited, and may be, for example, a direct bonded copper (DBC) substrate or an active metal brazing (AMB) substrate. The main substrate 3 includes a main insulating layer 31, a first main metal layer 32, and a second main metal layer 33. The first main metal layer 32 includes a first conductive portion 32A and a second conductive portion 32B. The dimension of the main substrate 3 in the thickness direction z is not limited, and may be, for example, 0.4 mm or more and 3.0 mm or less. In the illustrated example, the first main metal layer 32 does not include a plating layer or the like and may be a single layer, or may be a multi-layer structure including a plating layer of Ni or the like.

[0025] The constituent material of the main insulating layer 31 includes, for example, ceramics with excellent thermal conductivity. Examples of such ceramics include SiN (silicon nitride). The constituent material of the main insulating layer 31 is not limited to ceramics and may be an insulating resin sheet or the like. The main insulating layer 31 has, for example, a rectangular shape in a plan view. The dimension of the main insulating layer 31 in the thickness direction z is not limited in any way and is, for example, 0.05 mm or more and 1.0 mm or less.

[0026] As shown in FIGS. 8 , 9 , and 12 , the first conductive portion 32A supports a plurality of first semiconductor elements 10A, and the second conductive portion 32B supports a plurality of second semiconductor elements 10B. The first conductive portion 32A and the second conductive portion 32B are formed on the upper surface of the main insulating layer 31 (the surface facing the first side z1 in the thickness direction z). The first conductive portion 32A and the second conductive portion 32B are formed from a material that includes, for example, Cu (copper). The material may include, for example, Al (aluminum) other than Cu (copper). The first conductive portion 32A and the second conductive portion 32B are spaced apart in the first direction x. The first conductive portion 32A is located on the first side x1 in the first direction x of the second conductive portion 32B. The first conductive portion 32A and the second conductive portion 32B are each, for example, rectangular in plan view. The first conductive portion 32A and the second conductive portion 32B, together with the first conductive member 5 and the second conductive member 6, constitute a path of the main circuit current switched by the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B.

[0027] 9 , the first conductive portion 32A may include a first portion 321A and a second portion 322A. The first portion 321A and the second portion 322A are separated from each other and insulated from each other. The area of ​​the first portion 321A may be larger than the area of ​​the second portion 322A. In the illustrated example, the first conductive portion 32A may include one first portion 321A and two second portions 322A. The two second portions 322A are located near corners of the main insulating layer 31 and are separated from each other in the second direction y.

[0028] The first conductive portion 32A has a first main surface 301A. The first main surface 301A is a flat surface facing a first side z1 in the thickness direction z. A plurality of first semiconductor elements 10A are bonded to the first main surface 301A of the first portion 321A via a first conductive bonding material 19A. The second conductive portion 32B has a second main surface 301B. The second main surface 301B is a flat surface facing the first side z1 in the thickness direction z. A plurality of second semiconductor elements 10B are bonded to the second main surface 301B of the second conductive portion 32B via a second conductive bonding material 19B. The constituent materials of the first conductive bonding material 19A and the second conductive bonding material 19B are not particularly limited and may be, for example, solder, a metal paste material containing a metal such as Ag (silver), or a sintered metal containing a metal such as Ag (silver). The dimensions of first conductive portion 32A and second conductive portion 32B in thickness direction z are not limited in any way and may be, for example, 0.1 mm or more and 1.5 mm or less.

[0029] The second main metal layer 33 is formed on the lower surface (surface facing the second side z2 in the thickness direction z) of the main insulating layer 31. The constituent material of the second main metal layer 33 is, for example, the same as the constituent material of the first main metal layer 32. The second main metal layer 33 has a back surface 302. The back surface 302 is a flat surface facing the second side z2 in the thickness direction z. In the example shown in FIG. 11 , the back surface 302 is exposed from the sealing resin 8, for example. A heat dissipation member (e.g., a heat sink) (not shown) can be attached to the back surface 302. The back surface 302 may be covered by the sealing resin 8 without being exposed from the sealing resin 8. The second main metal layer 33 overlaps both the first conductive portion 32A and the second conductive portion 32B in a plan view.

[0030] First terminal 41, second terminal 42, third terminal 43: The specific configurations of the first terminal 41, second terminal 42, and third terminal 43 are not limited in any way, and in this embodiment, they are made of a plate-shaped metal plate. This metal plate contains, for example, Cu (copper) or a Cu (copper) alloy. In the examples shown in Figures 1 to 6, 8, 9, and 11, the semiconductor device A1 has two first terminals 41, two second terminals 42, and one third terminal 43, but the number of each terminal is not limited in any way.

[0031] A DC voltage to be converted into power is input to the two first terminals 41 and the third terminal 43. For example, the third terminal 43 is a positive electrode (P terminal), and the two first terminals 41 are each a negative electrode (N terminal). An AC voltage converted into power by the first semiconductor element 10A and the second semiconductor element 10B is output from the two second terminals 42. The two first terminals 41, the two second terminals 42, and the third terminal 43 each include a portion covered with the sealing resin 8 and a portion exposed from the sealing resin 8.

[0032] As shown in FIG. 12 , the third terminal 43 is conductively bonded to the first portion 321A of the first conductive portion 32A. The conductive bonding method is not limited, and methods such as ultrasonic bonding, laser bonding, welding, or methods using solder, metal paste, silver sintered body, etc. may be appropriately adopted. The third terminal 43 may be integrally formed with the first conductive portion 32A. As shown in FIGS. 8 and 9 , the third terminal 43 is located on the first side x1 in the first direction x with respect to the multiple first semiconductor elements 10A and the first conductive portion 32A. The third terminal 43 is conductively connected to the first portion 321A and, via the first portion 321A, to the back surface electrode 15 (drain electrode) of each first semiconductor element 10A.

[0033] The two first terminals 41 are electrically connected to the second principal surface electrodes 12 of the plurality of second semiconductor elements 10B. A second conductive member 6 is interposed between the two first terminals 41 and the second principal surface electrodes 12 of the plurality of second semiconductor elements 10B. The two first terminals 41 may be electrically connected to the second conductive member 6 as shown in FIG. 5 . The method of electrically connecting the first terminals 41 is not limited, and methods such as ultrasonic bonding, laser bonding, welding, or methods using solder, metal paste, silver sintered body, etc. may be appropriately adopted. In the illustrated example, the first terminals 41 and the second conductive member 6 may be electrically connected by a conductive bonding material 69 such as solder.

[0034] The two first terminals 41 may be configured to be integrally formed with the second conductive member 6. As shown in Figures 5, 8, etc., the two first terminals 41 are each located on a first side x1 in the first direction x with respect to the multiple first semiconductor elements 10A and the first conductive portions 32A. Each of the two first terminals 41 is electrically connected to the second conductive member 6 and, via the second conductive member 6, is electrically connected to the second main surface electrode 12 (source electrode) of each second semiconductor element 10B.

[0035] 1 to 5 and 11 , in the semiconductor device A1, the two first terminals 41 and the two third terminals 43 each protrude from the sealing resin 8 to the first side x1 in the first direction x. The two first terminals 41 and the two third terminals 43 are spaced apart from each other. The two first terminals 41 are located on opposite sides of the third terminal 43 in the second direction y. The two first terminals 41 and the two third terminals 43 overlap each other when viewed in the second direction y.

[0036] As can be seen from FIGS. 8 , 9 , and 12 , the two second terminals 42 are each conductively bonded to the second conductive portion 32B. The conductive bonding method is not limited to any particular method, and methods such as ultrasonic bonding, laser bonding, and welding, or methods using solder, metal paste, silver sintered body, etc., may be appropriately employed. As shown in FIG. 8 and other figures, the two second terminals 42 are each located on the second side x2 in the first direction x relative to the multiple second semiconductor elements 10B and the second conductive portions 32B. Each second terminal 42 is conductively connected to the second conductive portion 32B and, via the second conductive portion 32B, to the back electrode 15 (drain electrode) of each second semiconductor element 10B. The number of second terminals 42 is not limited to two and may be, for example, one or three or more. For example, when there is one second terminal 42, it is preferably connected to the center portion of the second conductive portion 32B in the second direction y.

[0037] The first terminal 41 is supported by the main substrate 3. In the present embodiment, as shown in Figures 3 to 8, 13, and 14, the first terminal 41 can have a terminal portion 411, a third joint portion 412, a fourth joint portion 413, and a connecting portion 414.

[0038] The terminal portion 411 is a portion that functions as a connection terminal, and protrudes from a resin side surface 832 of the sealing resin 8 to a first side x1 in the first direction x. The terminal portion 411 may have a flat plate shape that is aligned along the first direction x and the second direction y.

[0039] The third joint portion 412 is a portion that is joined to the second conductive member 6. In the illustrated example, the third joint portion 412 is connected to the second side x2 in the first direction x with respect to the terminal portion 411. In the illustrated example, the third joint portion 412 may be located at the same position as the terminal portion 411 in the thickness direction z. The third joint portion 412 may have a shape whose longitudinal direction is, for example, the second direction y.

[0040] The third bonding portion 412 may have a groove portion 4121. The groove portion 4121 has, for example, a frame shape when viewed in the thickness direction z.

[0041] The fourth bonding portion 413 is a portion to be bonded to the main substrate 3, and in the illustrated example, may be bonded to the second portion 322A. The fourth bonding portion 413 may be bonded to the second portion 322A by, for example, laser bonding. The fourth bonding portion 413 is located on the second side z2 in the thickness direction z relative to the third bonding portion 412. In the illustrated example, the area of ​​the third bonding portion 412 may be larger than the area of ​​the fourth bonding portion 413.

[0042] The first terminal 41 may further include an extending portion 415. The extending portion 415 extends from the third bonding portion 412. In the illustrated example, the extending portion 415 may extend from the third bonding portion 412 in the second direction y. The extending portion 415 may have a through hole 4151. The through hole 4151 penetrates the extending portion 415 in the thickness direction z. The number of through holes 4151 is not limited in any way, and in the illustrated example, there are two through holes 4151.

[0043] First sub-substrate 48A, second sub-substrate 48B: The first sub-substrate 48A and the second sub-substrate 48B support a plurality of control terminals 45. The first sub-substrate 48A and the second sub-substrate 48B are interposed between the first main surface 301A and the second main surface 301B and the plurality of control terminals 45 in the thickness direction z. The first sub-substrate 48A and the second sub-substrate 48B may have different configurations or may have a common configuration. The first sub-substrate 48A is disposed on the first conductive portion 32A. The second sub-substrate 48B is disposed on the second conductive portion 32B. In this embodiment, the first sub-substrate 48A and the second sub-substrate 48B have a common configuration and are rotated 180 degrees relative to each other when viewed in the thickness direction z.

[0044] The specific configuration of the first sub-substrate 48A and the second sub-substrate 48B is not limited in any way. Specific examples of the first sub-substrate 48A and the second sub-substrate 48B include an IMS (Insulated Metal Substrate) substrate, a glass epoxy resin substrate, and a metal substrate. In this embodiment, the first sub-substrate 48A and the second sub-substrate 48B are IMS substrates. The first sub-substrate 48A and the second sub-substrate 48B have a sub-insulation layer 481, a first sub-metal layer 482, and a second sub-metal layer 483 stacked on top of each other.

[0045] The sub-insulating layer 481 is made of, for example, ceramics. The sub-insulating layer 481 has, for example, a rectangular shape in plan view. The thickness of the sub-insulating layer 481 is not particularly limited and is, for example, 0.05 mm to 1.0 mm.

[0046] The first sub-metal layer 482 is formed on the upper surface of the sub-insulating layer 481 (the surface facing the first side z1 in the thickness direction z). The first sub-metal layer 482 includes, for example, Cu (copper) or a Cu (copper) alloy. The specific configuration of the first sub-metal layer 482 is not limited in any way. The thickness of the first sub-metal layer 482 is not limited in any way and is, for example, 0.035 mm or more and 2.0 mm or less.

[0047] 19 and 20, the first sub-metal layer 482 includes a plurality of regions 482A, 482B, 482C, 482D, 482E, and 482F. The plurality of regions 482A, 482B, 482C, 482D, 482E, and 482F are separated and insulated from one another.

[0048] In the first sub-substrate 48A, the region 482A is located on a first side x1 in the first direction x with respect to the center in the first direction x of the sub-insulating layer 481. In the second sub-substrate 48B, the region 482A is located on a second side x2 in the first direction x with respect to the center in the first direction x of the sub-insulating layer 481. The connecting portion 4821A may have a rectangular shape that extends elongatedly in the second direction y.

[0049] In the first sub-substrate 48A, the region 482E is located on the second side x2 with respect to the center of the sub-insulating layer 481 in the first direction x. In the second sub-substrate 48B, the region 482E is located on the first side x1 with respect to the center of the sub-insulating layer 481 in the first direction x. The region 482E has an elongated shape in the second direction y and may be approximately the entire length of the sub-insulating layer 481. The region 482A and the region 482E are electrically connected via, for example, a wire 74. The material of the wire 74 is not limited in any way and may include, for example, Au (gold), Al (aluminum), or an Al (aluminum) alloy.

[0050] A plurality of wires 71 are bonded to region 482E. The material of wires 71 is not limited in any way and may include, for example, Au (gold), Al (aluminum), or an Al (aluminum) alloy. Region 482A is electrically connected to first main surface electrodes 11 (gate electrodes) of a plurality of first semiconductor elements 10A or a plurality of second semiconductor elements 10B via the plurality of wires 71, region 482E, and wires 74.

[0051] The region 482B includes a connection portion 4821B and a terminal portion 4822B. In the first sub-substrate 48A, the connection portion 4821B is located on the second side x2 in the first direction x, and the terminal portion 4822B is located on the first side x1 in the first direction x. In the second sub-substrate 48B, the connection portion 4821B is located on the first side x1 in the first direction x, and the terminal portion 4822B is located on the second side x2 in the first direction x. In the first sub-substrate 48A, the region 482B is located on the first side x1 in the first direction x of the connection portion 4821A. In the second sub-substrate 48B, the region 482B is located on the second side x2 in the first direction x of the connection portion 4821A. The connection portion 4821B has a shape that extends elongated in the second direction y. On the first sub-substrate 48A, the terminal portion 4822B is located on the second side y2 in the second direction y of the region 482A. On the second sub-substrate 48B, the terminal portion 4822B is located on the first side y1 in the second direction y of the region 482A.

[0052] A plurality of wires 72 are bonded to the connection portion 4821B. In this embodiment, the wires 72 are bonded to a surface metal layer 4829 of the connection portion 4821B. The constituent material of the wires 72 is not limited in any way and includes, for example, Au (gold), Al (aluminum), or an Al (aluminum) alloy. The region 482B is electrically connected to the third principal surface electrodes 13 (source sense electrodes) of the plurality of first semiconductor elements 10A or the plurality of second semiconductor elements 10B via the plurality of wires 72.

[0053] The region 482C includes a connection portion 4821C and a terminal portion 4822C. In the first sub-substrate 48A, the connection portion 4821C is located on the second side y2 in the second direction y, and the terminal portion 4822C is located on the first side y1 in the second direction y. In the second sub-substrate 48B, the connection portion 4821C is located on the first side y1 in the second direction y, and the terminal portion 4822C is located on the second side y2 in the second direction y. The connection portion 4821C has a bent shape extending in the second direction y. The terminal portion 4822C has a substantially circular shape. In the first sub-substrate 48A, the terminal portion 4822C is located on the first side x1 in the first direction x of the connection portion 4821B. In the second sub-substrate 48B, it is located on the second side x2 in the first direction x of the connection portion 4821B.

[0054] The region 482D includes a connection portion 4821D and a terminal portion 4822D. In the first sub-substrate 48A, the connection portion 4821D is located on the second side y2 in the second direction y, and the terminal portion 4822D is located on the first side y1 in the second direction y. The connection portion 4821D is, for example, rectangular, and the terminal portion 4822D is, for example, approximately circular. In the first sub-substrate 48A, the connection portion 4821D is located on the first side x1 in the first direction x of the connection portion 4821C. In the second sub-substrate 48B, the connection portion 4821D is located on the second side x2 in the first direction x of the connection portion 4821C. In the first sub-substrate 48A, the terminal portion 4822D is located on the second side y2 in the second direction y of the terminal portion 4822C. On the second sub-substrate 48B, the terminal portion 4822D is located on the first side y1 in the second direction y of the terminal portion 4822C.

[0055] The region 482F is located between the terminal portion 4822C and the terminal portion 4822D in the second direction y. The shape of the multiple regions 482F is not limited in any way and may be rectangular, circular, or the like, and in the illustrated example, is rectangular.

[0056] 15 and 16 , the second sub-metal layer 483 is formed on the lower surface (surface on the second side z2 in the thickness direction z) of the sub-insulating layer 481. The constituent material of the second sub-metal layer 483 includes, for example, Cu (copper) or a Cu (copper) alloy. The thickness of the second sub-metal layer 483 is not particularly limited and is, for example, 0.035 mm to 3.0 mm.

[0057] The second sub-metal layer 483 of the first sub-substrate 48A is conductively joined to the first conductive portion 32A. The second sub-metal layer 483 of the second sub-substrate 48B is conductively joined to the second conductive portion 32B. The method for conductively joining the second sub-metal layer 483 to the first conductive portion 32A or the second conductive portion 32B is not limited in any way. Examples of conductive joining methods include a method using a conductive bonding material, a laser bonding method, an ultrasonic bonding method, and a solid-state bonding method. In this embodiment, the second sub-metal layers 483 of the first sub-substrate 48A and the second sub-substrate 48B are conductively joined to the first conductive portion 32A and the second conductive portion 32B via a conductive bonding material 49. For example, solder is used as the conductive bonding material 49.

[0058] In the first sub-substrate 48A, a wire 73 is connected between the connection portion 4821D and the first conductive portion 32A. The material of the wire 73 is not limited in any way and may include, for example, Al (aluminum) or an Al (aluminum) alloy. This provides electrical continuity between the region 482D and the first conductive portion 32A.

[0059] 20 , on the second sub-board 48B, a thermistor 17 is connected to the connection portion 4821C and the connection portion 4821D. The thermistor 17 is used as a temperature detection sensor. In addition to the thermistor 17, for example, a temperature-sensitive diode or the like may be included, or the thermistor 17 or the like may not be included.

[0060] The wires 71, 72, and 74 are not connected to the first main metal layer 32. In other words, the first main metal layer 32 is separated from the plurality of wires 71, 72, and 73.

[0061] Control terminals 45: The multiple control terminals 45 are terminals for controlling each first semiconductor element 10A and each second semiconductor element 10B. The multiple control terminals 45 include multiple first control terminals 46A, 46B, 46E and multiple second control terminals 47A to 47D. The multiple first control terminals 46A, 46B, 46E are used to control each first semiconductor element 10A, etc. The multiple second control terminals 47A to 47D are used to control each second semiconductor element 10B, etc. The multiple first control terminals 46A, 46B, 46E and the multiple second control terminals 47A to 47D are supported by the support body 1 and directly bonded to the support body 1.

[0062] The multiple first control terminals 46A, 46B, 46E are arranged at intervals in the second direction y. The multiple first control terminals 46A, 46B, 46E are supported by the first conductive portion 32A via the first sub-substrate 48A, as shown in Figures 2, 3, 5, 6, 8, 19, etc. The multiple first control terminals 46A, 46B, 46E are located in the first direction x between the multiple first semiconductor elements 10A and the two first terminals 41 and the third terminal 43, as shown in Figure 5.

[0063] 19 , the first control terminal 46A is disposed on the terminal portion 4822A. The first control terminal 46A is a terminal (gate terminal) for inputting drive signals for the plurality of first semiconductor elements 10A. A drive signal for driving the plurality of first semiconductor elements 10A is input to the first control terminal 46A (for example, a gate voltage is applied).

[0064] The first control terminal 46B is disposed on the terminal portion 4822B. The first control terminal 46B is a terminal (source sense terminal) for detecting source signals of the multiple first semiconductor elements 10A. The first control terminal 46B detects a voltage (a voltage corresponding to a source current) applied to each second main surface electrode 12 (source electrode) of the multiple first semiconductor elements 10A.

[0065] The first control terminal 46E is disposed on the terminal portion 4822D. The first control terminal 46E is a terminal (drain sense terminal) for detecting drain signals of the multiple first semiconductor elements 10A. The first control terminal 46E detects the voltage (voltage corresponding to the drain current) applied to each back surface electrode 15 (drain electrode) of the multiple first semiconductor elements 10A.

[0066] The second control terminals 47A to 47D are arranged at intervals in the second direction y. As shown in Figures 2, 3, 5, 6, 8, 20, etc., the second control terminals 47A to 47D are supported by the second conductive portion 32B via the second sub-substrate 48B. As shown in Figure 5, the second control terminals 47A to 47D are located between the second semiconductor elements 10B and the second terminals 42 in the first direction x.

[0067] 20 , the second control terminal 47A is disposed on the terminal portion 4822A. The second control terminal 47A is a terminal (gate terminal) for inputting drive signals for the plurality of second semiconductor elements 10B. A drive signal for driving the plurality of second semiconductor elements 10B is input to the second control terminal 47A (for example, a gate voltage is applied).

[0068] The second control terminal 47B is disposed on the terminal portion 4822B. The second control terminal 47B is a terminal (source sense terminal) for detecting source signals of the plurality of second semiconductor elements 10B. The second control terminal 47B detects a voltage (a voltage corresponding to a source current) applied to each second main surface electrode 12 (source electrode) of the plurality of second semiconductor elements 10B.

[0069] The second control terminal 47C is disposed on the terminal portion 4822C. The second control terminal 47D is disposed on the terminal portion 4822D. The second control terminals 47C and 47D are terminals that are electrically connected to the thermistor 17.

[0070] As shown in FIGS. 12 and 19, each of the plurality of control terminals 45 (the plurality of first control terminals 46A, 46B, 46E and the plurality of second control terminals 47A to 47D) includes a holder 451 and a pin 452.

[0071] The holder 451 is made of a conductive material and is bonded to the first sub-metal layer 482. The holder 451 may be bonded directly to the first sub-metal layer 482 or may be bonded to the first sub-metal layer 482 using a bonding material (not shown).

[0072] The pin 452 is a rod-shaped member extending in the thickness direction z. The pin 452 is supported, for example, by being press-fitted into the holder 451. The pin 452 is electrically connected to the first sub-metal layer 482 at least via the holder 451. As shown in FIGS. 1 and 12 , the pin 452 protrudes from the sealing resin 8 toward a first side z1 in the thickness direction z. In the illustrated example, the pin 452 includes a thick-diameter portion 4521. The thick-diameter portion 4521 is provided near an end of the pin 452 on the first side z1 in the thickness direction z. The thick-diameter portion 4521 has a dimension in a direction perpendicular to the thickness direction z that is larger than that of other portions of the holder 451. The thick-diameter portion 4521 may be press-fitted into a through-hole provided in a control board (not shown) external to the semiconductor device A1 when the pin 452 is connected to the control board.

[0073] First conductive member 5, second conductive member 6: The first conductive member 5 and the second conductive member 6, together with the first conductive portion 32A and the second conductive portion 32B, constitute a path for a main circuit current switched by the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B. The first conductive member 5 and the second conductive member 6 are spaced apart from the first main surface 301A and the second main surface 301B toward the first side z1 in the thickness direction z and overlap the first main surface 301A and the second main surface 301B in a plan view. In this embodiment, the first conductive member 5 and the second conductive member 6 are each made of a metal plate material. The metal includes, for example, Cu (copper) or a Cu (copper) alloy. Specifically, the first conductive member 5 and the second conductive member 6 are made of an appropriately bent metal plate material.

[0074] The first conductive member 5 is connected to the second principal surface electrode 12 (source electrode) of each first semiconductor element 10A and the second conductive portion 32B, and provides electrical continuity between the second principal surface electrode 12 of each first semiconductor element 10A and the second conductive portion 32B. The first conductive member 5 forms a path for a main circuit current switched by the multiple first semiconductor elements 10A. As shown in FIGS. 7 and 8 , the first conductive member 5 includes a main portion 51, multiple joint portions 52 and multiple joint portions 53.

[0075] The main portion 51 is located between the plurality of first semiconductor elements 10A and the second conductive portions 32B in the first direction x and is a strip-shaped portion extending in the second direction y in a plan view. The main portion 51 overlaps both the first conductive portions 32A and the second conductive portions 32B in a plan view and is separated in the thickness direction z from the first main surface 301A and the second main surface 301B to a first side z1 in the thickness direction z. As shown in FIG. 18 and other figures, the main portion 51 is located on a second side z2 in the thickness direction z relative to a first relay portion 63 and a third relay portion 65 of a second conductive member 6 described later and is closer to the first main surface 301A and the second main surface 301B than the first relay portion 63 and the third relay portion 65.

[0076] In this embodiment, the main portion 51 is disposed parallel to the first main surface 301A and the second main surface 301B.

[0077] As shown in FIG. 8 and other figures, the main portion 51 corresponds to an area in the second direction y where multiple first semiconductor elements 10A are arranged. In this embodiment, as shown in FIGS. 7, 8, 12, and other figures, multiple openings 511 are formed in the main portion 51. Each of the multiple openings 511 is, for example, a through-hole penetrating in the thickness direction z (the plate thickness direction of the main portion 51). The multiple openings 511 are arranged at intervals in the second direction y. The multiple openings 511 may be provided corresponding to each of the multiple first semiconductor elements 10A. In this embodiment, six openings 511 are provided in the main portion 51, and these openings 511 and the multiple (six) first semiconductor elements 10A are positioned at the same position in the second direction y.

[0078] 8, 12, etc., in the present embodiment, each opening 511 overlaps with a gap between the first conductive portion 32A and the second conductive portion 32B in a plan view. The openings 511 are formed to facilitate the flow of the resin material between the upper side (first side z1 in the thickness direction z) and the lower side (second side z2 in the thickness direction z) near the main portion 51 (first conductive member 5) when injecting the flowable resin material to form the sealing resin 8.

[0079] As shown in FIG. 8 and other figures, the multiple bonding portions 52 and the multiple bonding portions 53 are connected to the main portion 51 and can be arranged to correspond to the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B. Specifically, each bonding portion 52 is located on a first side x1 in the first direction x relative to the main portion 51. Each bonding portion 53 is located on a second side x2 in the first direction x relative to the main portion 51. As shown in FIG. 15 , the multiple bonding portions 52 are individually bonded to the second principal surface electrodes 12 of the multiple first semiconductor elements 10A via conductive bonding materials 59. The multiple bonding portions 53 and the second conductive portion 32B are bonded to each other via the conductive bonding material 59. The material of the conductive bonding material 59 is not particularly limited and may be, for example, solder, a metal paste material, or a sintered metal. In this embodiment, the bonding portion 52 has two portions spaced apart in the second direction y.

[0080] The second conductive member 6 electrically connects the second main surface electrode 12 (source electrode) of each second semiconductor element 10B to the two first terminals 41. The second conductive member 6 is formed integrally with the two first terminals 41. The second conductive member 6 constitutes a path for a main circuit current that is switched by the multiple second semiconductor elements 10B. As shown in FIGS. 2 and 5 to 7 , the second conductive member 6 may include multiple first joint portions 61, two second joint portions 62, two second relay portions 64, multiple first relay portions 63, a third relay portion 65, two step portions 66, and two ribs 67.

[0081] The multiple first bonding portions 61 are portions that are individually bonded to the multiple second semiconductor elements 10B. Each first bonding portion 61 and the second principal surface electrode 12 of each second semiconductor element 10B can be bonded via a conductive bonding material 69. The constituent material of the conductive bonding material 69 is not particularly limited and may be, for example, solder, a metal paste material, or a sintered metal. In this embodiment, the first bonding portion 61 has two flat portions 611 and two first inclined portions 612.

[0082] The two flat portions 611 are aligned in the second direction y. The two flat portions 611 are spaced apart from each other in the second direction y. The shape of the flat portions 611 is not limited in any way, and in the illustrated example, they are rectangular. The two flat portions are joined to the second principal surface electrode 12 on both sides in the second direction y.

[0083] The two first inclined portions 612 are connected to the outer sides of the two flat portions 611 in the second direction y. That is, the first inclined portion 612 located on the first side y1 in the second direction y is connected to the first side y1 in the second direction y of the flat portion 611 located on the first side y1 in the second direction y. The first inclined portion 612 located on the second side y2 in the second direction y is connected to the second side y2 in the second direction y of the flat portion 611 located on the second side y2 in the second direction y. The first inclined portion 612 is inclined so that the farther it is from the flat portion 611 in the second direction y, the closer it is to the first side z1 in the thickness direction z.

[0084] The two second relay portions 64 are interposed between the plurality of first joint portions 61 and the first terminals 41. In the illustrated example, the second relay portions 64 are connected to the first terminals 41 via the first step portions 602. The second relay portions 64 overlap the first conductive portion 32A in plan view. The second relay portions 64 have a shape that extends overall in the first direction x.

[0085] The two ribs 67 are connected to the outer edges in the second direction y of the two second link portions 64 and the third link portion 65. The rib 67 stands from the second link portion 64 toward the first side z1 in the thickness direction z.

[0086] The two second bonding portions 62 are individually bonded to the two first terminals 41. In the example shown, the second bonding portions 62 can be bonded to the third bonding portion 412. The second bonding portions 62 can be bonded to the third bonding portion 412 via, for example, a conductive bonding material 69. In the example shown, the second bonding portions 62 are located on a second side z2 in the thickness direction z with respect to the second relay portion 64.

[0087] The step portion 66 is interposed between the second joint portion 62 and the second link portion 64. The step portion 66 is a portion that is bent into a curved shape.

[0088] The multiple first relay portions 63 are individually connected to the multiple first bonding portions 61. Each first relay portion 63 has a shape extending in the first direction x and is arranged spaced apart from one another in the second direction y. There is no limitation on the number of multiple first relay portions 63, and in the example shown, five first relay portions 63 are arranged. Each first relay portion 63 is arranged so as to be located between the multiple second semiconductor elements 10B in the second direction y, or so as to be located outward of the multiple second semiconductor elements 10B in the second direction y.

[0089] In this embodiment, one first joint portion 61 is disposed between two first relay portions 63 adjacent to each other in the second direction y. In one first joint portion 61, the first inclined portion 612 located on the first side y1 in the second direction y is connected to the first relay portion 63 located on the first side y1 in the second direction y, of the two first relay portions 63 adjacent to each other in the second direction y. In one first joint portion 61, the first inclined portion 612 located on the second side y2 in the second direction y is connected to the first relay portion 63 located on the second side y2 in the second direction y, of the two first relay portions 63 adjacent to each other in the second direction y.

[0090] The third relay portion 65 is connected to ends of the first side x1 in the first direction x of the multiple first relay portions 63. The third relay portion 65 has a size that covers the entire length of the main board 3 in the second direction y. In the illustrated example, the third relay portion 65 may have multiple openings 651. Each of the multiple openings 651 penetrates the third relay portion 65 in the thickness direction z. In the illustrated example, the arrangement of the multiple openings 651 may correspond to the arrangement of the multiple openings 511. That is, corresponding ones of the multiple openings 651 and the multiple openings 511 overlap each other when viewed in the thickness direction z. In the illustrated example, all of the openings 511 may be located inside the openings 651.

[0091] 2 , 5 , 13 , and 14 , the second relay portion 64 of the second conductive member overlaps with the fourth joint portion 413 of the first terminal 41 in the thickness direction z. The entire fourth joint portion 413 may overlap with the second relay portion 64 in the thickness direction z.

[0092] Sealing resin 8: The sealing resin 8 covers the multiple first semiconductor elements 10A, the multiple second semiconductor elements 10B, the main substrate 3 (excluding the back surface 302), the two first terminals 41, the multiple second terminals 42, a portion of each of the third terminals 43, a portion of each of the multiple control terminals 45, the first sub-substrate 48A, the second sub-substrate 48B, the first conductive member 5, the second conductive member 6, and the multiple wires 71 to 73. The sealing resin 8 is made of, for example, black epoxy resin. The sealing resin 8 is formed, for example, by molding. The size of the sealing resin 8 is not limited in any way, and may be, for example, approximately 35 mm to 60 mm in the first direction x, approximately 35 mm to 50 mm in the second direction y, and approximately 4 mm to 15 mm in the thickness direction z. These dimensions are the sizes of the largest portions along each direction. The sealing resin 8 has a resin main surface 81, a resin back surface 82, and a plurality of resin side surfaces 831 to 834.

[0093] As shown in FIGS. 10 , 12 , and 17 , the resin main surface 81 and the resin back surface 82 are spaced apart in the thickness direction z. The resin main surface 81 faces a first side z1 in the thickness direction z, and the resin back surface 82 faces a second side z2 in the thickness direction z. A plurality of control terminals 45 (a plurality of first control terminals 46A, 46B, and 46E and a plurality of second control terminals 47A to 47D) protrude from the resin main surface 81. As shown in FIG. 11 , the resin back surface 82 has a frame shape that surrounds a back surface 302 (the lower surface of the second main metal layer 33) of the main substrate 3 in a plan view. The back surface 302 of the main substrate 3 is exposed from the resin back surface 82 and is, for example, flush with the resin back surface 82.

[0094] Each of the multiple resin side surfaces 831 to 834 is connected to both the resin main surface 81 and the resin back surface 82 and is sandwiched between them in the thickness direction z. As shown in FIG. 4 and other figures, the resin side surface 831 and the resin side surface 832 are spaced apart in the first direction x. The resin side surface 831 faces a second side x2 in the first direction x, and the resin side surface 832 faces a first side x1 in the first direction x. Two second terminals 42 protrude from the resin side surface 831, and two first terminals 41 and a third terminal 43 protrude from the resin side surface 832. As shown in FIG. 4 and other figures, the resin side surface 833 and the resin side surface 834 are spaced apart in the second direction y. The resin side surface 833 faces a second side y2 in the second direction y, and the resin side surface 834 faces a first side y1 in the second direction y.

[0095] As shown in FIG. 4 , a plurality of recesses 832 a are formed in the resin side surface 832. Each recess 832 a is a portion recessed in the first direction x in a plan view. The plurality of recesses 832 a include those formed between the first terminal 41 and the third terminal 43 and those formed between the first terminal 41 and the third terminal 43 in a plan view. The plurality of recesses 832 a are provided to increase the creepage distance along the resin side surface 832 between the first terminal 41 and the third terminal 43 and the creepage distance along the resin side surface 832 between the first terminal 41 and the third terminal 43.

[0096] Next, a vehicle B1 equipped with the semiconductor device A1 will be described with reference to Fig. 21. The vehicle B1 is, for example, an electric vehicle (EV).

[0097] As shown in Fig. 21 , vehicle B1 includes an on-board charger 91, a storage battery 92, and a drive system 93. Power is supplied to the on-board charger 91 wirelessly from a power supply facility (not shown) installed outdoors. Alternatively, power may be supplied from the power supply facility to the on-board charger 91 via a wired connection. The on-board charger 91 is configured with a step-up DC-DC converter. The voltage of the power supplied to the on-board charger 91 is stepped up by the converter and then supplied to the storage battery 92. The stepped-up voltage is, for example, 600 V.

[0098] The drive system 93 drives the vehicle B1. The drive system 93 has an inverter 931 and a drive source 932. The semiconductor device A1 constitutes part of the inverter 931. Power stored in the storage battery 92 is supplied to the inverter 931. The power supplied from the storage battery 92 to the inverter 931 is DC power. In addition, unlike the power system shown in FIG. 21 , a step-up DC-DC converter may be further provided between the storage battery 92 and the inverter 931. The inverter 931 converts DC power into AC power. The inverter 931 including the semiconductor device A1 is electrically connected to the drive source 932.

[0099] The drive source 932 includes an AC motor and a transmission. When AC power converted by the inverter 931 is supplied to the drive source 932, the AC motor rotates and the rotation is transmitted to the transmission. The transmission appropriately reduces the rotation speed transmitted from the AC motor and then rotates the drive shaft of the vehicle B1. This drives the vehicle B1. To drive the vehicle B1, it is necessary to freely control the rotation speed of the AC motor based on information such as the amount of fluctuation in the accelerator pedal. The semiconductor device A1 in the inverter 931 is required to output AC power whose frequency has been appropriately changed to correspond to the required rotation speed of the AC motor.

[0100] Next, the operation of the semiconductor device A1 will be described.

[0101] The first terminal 41 is supported by the main substrate 3. Heat generated from one or more second semiconductor elements 10B is transmitted to the first terminal 41 via the second conductive member 6. In the semiconductor device A1, this heat can be dissipated from the first terminal 41 to the main substrate 3. This can promote heat dissipation from the semiconductor device A1.

[0102] The first terminal 41 is supported by the first conductive portion 32A. The first conductive portion 32A contains metal and has excellent thermal conductivity, which is preferable for promoting heat dissipation from the semiconductor device A1.

[0103] The first terminal 41 is supported by the second portion 322A. This prevents the first terminal 41 from being electrically connected to the back surface electrode 15 of the first semiconductor element 10A even when the first terminal 41 is electrically connected to the second portion 322A.

[0104] The fourth joint 413 of the first terminal 41 is joined to the second portion 322A. The fourth joint 413 is located on the second side z2 in the thickness direction z relative to the third joint 412, etc. This provides a heat transfer path that transfers heat to the second side z2 in the thickness direction z via the fourth joint 413, while preventing the current path through the first terminal 41 from unduly detouring around to the second side z2 in the thickness direction z.

[0105] The area of ​​the third joint portion 412 is larger than the area of ​​the fourth joint portion 413, which reduces the resistance of the current path that flows through the second conductive member 6 and the first terminal 41. In addition, the second portion 322A can be made smaller.

[0106] When viewed in the thickness direction z, the fourth joint portion 413 overlaps with the second conductive member 6. This makes it possible to provide the fourth joint portion 413 for being supported by the main board 3 on the first terminal 41 while preventing the semiconductor device A1 from becoming large.

[0107] The first terminal 41 has the extending portion 415, which can reduce the first terminal 41 from slipping out of the sealing resin 8. The extending portion 415 has the through hole 4151, which can more reliably reduce the first terminal 41 from slipping out.

[0108] 22 to 30 show modified examples and other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above-described embodiment are given the same reference numerals. The configurations of the various parts in each modified example and each embodiment can be combined with each other as appropriate within the scope of not causing technical contradictions.

[0109] 22 shows a first modified example of the semiconductor device A1. In the semiconductor device A11 of this modified example, the first terminal 41 is supported on the main substrate 3 via a relay member 418. In the illustrated example, the relay member 418 is interposed between the fourth joint portion 413 and the second portion 322A.

[0110] The material of the relay member 418 is not limited in any way and may be either a conductor or an insulator. Examples of conductors include metals such as Cu (copper) and Ni (nickel) or alloys thereof. Examples of insulators include ceramics and resin. In this modification, the material of the relay member 418 is, for example, a metal.

[0111] The relay member 418 is joined to the fourth bonding portion 413 and the second portion 322A. The relay member 418 may be joined to the fourth bonding portion 413 and the second portion 322A by a bonding material 419, for example.

[0112] According to this modification, heat dissipation can be promoted. As can be understood from this modification, the configuration in which the first terminal 41 is supported by the main board 3 may be a configuration in which another member, such as a relay member 418, is interposed between the first terminal 41 and the main board 3.

[0113] 23 shows a second modified example of the semiconductor device A1. In this modified semiconductor device A12, the first terminal 41 is supported on the main substrate 3 via a relay member 418. In the illustrated example, the first conductive portion 32A is a single member and is not divided into multiple parts. The relay member 418 is interposed between the fourth joint portion 413 and the first conductive portion 32A.

[0114] In this modification, the relay member 418 is made of an insulating material. From the viewpoint of promoting heat dissipation through the relay member 418, the relay member 418 is preferably made of a ceramic material, for example.

[0115] This modification can promote heat dissipation. The insulating material of the relay member 418 insulates the first terminal 41 and the second conductive member 6 from the first conductive portion 32A. This allows the first terminal 41 to be supported by the first conductive portion 32A while electrically connecting a plurality of first semiconductor elements 10A to the first conductive portion 32A without dividing the first conductive portion 32A. This is therefore advantageous for miniaturizing the first conductive portion 32A.

[0116] 24 shows a third modified example of the semiconductor device A1. In the semiconductor device A13 of this modified example, the first terminal 41 is bonded to the main insulating layer 31 of the main substrate 3.

[0117] The first conductive portion 32A may be, for example, cut out to expose a region to which the third bonding portion 412 is to be bonded. The fourth bonding portion 413 is bonded to the main insulating layer 31 by, for example, a bonding material 419.

[0118] According to this modification, heat dissipation can be promoted. As can be understood from this modification, the first terminal 41 may be joined to the main insulating layer 31.

[0119] 25 shows a fourth modification of the semiconductor device A1. In the semiconductor device A14 of this modification, the third bonding portion 412 and the fourth bonding portion 413 are configured as a single portion.

[0120] The portions that function as the third bonding portion 412 and the fourth bonding portion 413 are bonded to the second portion 322A. The second bonding portion 62 is bonded to the portions that function as the third bonding portion 412 and the fourth bonding portion 413 from the first side z1 in the thickness direction z.

[0121] According to this modification, heat dissipation can be promoted. By configuring the third bonding portion 412 and the fourth bonding portion 413 as a single portion, the second portion 322A, the third bonding portion 412, the fourth bonding portion 413, and the second bonding portion 62 overlap one another when viewed in the thickness direction z. This allows for further miniaturization of the semiconductor device A14.

[0122] 26 shows a fifth modified example of the semiconductor device A1. In the semiconductor device A15 of this modified example, the second bonding portion 62 is located on a first side z1 in the thickness direction z relative to the second link portion 64. The step portion 66 is bent in the opposite direction in the thickness direction z compared to the step portion 66 of the semiconductor device A1, for example.

[0123] According to this modification, heat dissipation can be promoted. By appropriately setting the bending direction of the step portion 66, for example, the distance between the resin rear surface 82 or the rear surface 302 and the first terminal 41 in the thickness direction z can be set more freely.

[0124] 27 to 29 show a semiconductor device according to a second embodiment of the present disclosure. In a semiconductor device A2 of this embodiment, the second joint portion 62 and the second link portion 64 of the second conductive member 6 are connected without a step portion 66. The second joint portion 62 and the second link portion 64 are located at the same position in the thickness direction z. The second joint portion 62 and the second link portion 64 form an integrated flat plate-shaped portion.

[0125] The third link portion 65 may include a step portion 652. Due to the provision of the step portion 652, the third link portion 65 has a shape in which a portion on the first side x1 in the first direction x is located closer to the first side z1 in the thickness direction z than a portion on the second side x2 in the first direction x. The rib 67 may extend from the ends of the second link portion 64 and the third link portion 65 in the second direction y toward the second side z2 in the thickness direction z.

[0126] According to this embodiment, heat dissipation can be promoted. Since the second joint portion 62 and the second link portion 64 form an integrated flat plate-shaped portion, the inductance of the second conductive member 6 can be reduced.

[0127] 30 shows a semiconductor device according to a third embodiment of the present disclosure. A semiconductor device A3 of this embodiment differs from the above-described embodiments in the arrangement of a plurality of control terminals 45.

[0128] In this embodiment, the control terminals 45 may be positioned offset toward the second side x2 with respect to the center of the semiconductor device A1 in the first direction x. The control terminals 45 may be arranged in the second direction y.

[0129] This embodiment can promote heat dissipation. As can be seen from this embodiment, the arrangement of the control terminals 45 is not limited in any way.

[0130] The semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure are not limited to the above-described embodiment. The specific configurations of the semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure can be freely modified in various ways.

[0131] Supplementary Note 1. A main substrate (3) having a first conductive portion (32A) having a first main surface (301A) facing a first side (z1) in a thickness direction (z) and located on a first side (x1) in a first direction (x) perpendicular to the thickness direction (z), and a second conductive portion (32B) having a second main surface (301B) facing the first side (z1) in the thickness direction (z) and located on a second side (x2) in the first direction (x), one or more first semiconductor elements (10A) mounted on the first conductive portion (32A) and having a switching function, one or more second semiconductor elements (10B) mounted on the second conductive portion (32B) and having a switching function, and a first terminal (41) including a terminal portion (411) protruding toward the first side (x1) in the first direction (x) with respect to the main substrate (3) and conducting to the second semiconductor element (10B), A semiconductor device (A1) comprising: a second conductive member (6) interposed between the second semiconductor element (10B) and the first terminal (41); and a sealing resin (8) covering one or more of the first semiconductor elements (10A), one or more of the second semiconductor elements (10B), the second conductive member (6), and a portion of each of the main substrate (3) and the first terminal (41), wherein the first terminal (41) is supported by the main substrate (3). Appendix 2. The semiconductor device (A1) according to Appendix 1, wherein the first terminal (41) is supported by the first conductive portion (32A). Appendix 3. The semiconductor device (A1) according to Supplementary Note 2, wherein the first conductive portion (32A) includes a first portion (321A) on which the first semiconductor element (10A) is mounted and a second portion (322A) spaced from the first portion (321A), and the first terminal (41) is supported by the second portion (322A). Supplementary Note 4: The semiconductor device (A1) according to Supplementary Note 3, wherein the first terminal (41) has a third bonding portion (412) to which the second conductive member (6) is bonded and a fourth bonding portion (413) bonded to the main substrate (3). Supplementary Note 5: The semiconductor device (A1) according to Supplementary Note 4, wherein the third bonding portion (412) is located on the first side (z1) in the thickness direction (z) relative to the fourth bonding portion (413). Supplementary Note 6: The semiconductor device (A1) according to Supplementary Note 5, wherein the area of ​​the third bonding portion (412) is larger than the area of ​​the fourth bonding portion (413).Supplementary Note 7. The semiconductor device (A1) according to Supplementary Note 5 or 6, wherein the third bonding portion (412) is located on the first side (x1) in the first direction (x) relative to the fourth bonding portion (413). Supplementary Note 8. The semiconductor device (A1) according to Supplementary Note 7, wherein the fourth bonding portion (413) overlaps with the second conductive member (6) when viewed in the thickness direction (z). Supplementary Note 9. The semiconductor device (A1) according to any one of Supplements 4 to 8, wherein the first terminal (41) has an extension portion (415) extending from the third bonding portion (412). Supplementary Note 10. The semiconductor device (A1) according to Supplementary Note 9, wherein the extension portion (415) has a through hole (4151) penetrating in the thickness direction (z). Supplementary Note 11. The semiconductor device (A11) according to Supplementary Note 1 or 2, further comprising a relay member (418) interposed between the first terminal (41) and the main substrate (3). Appendix 12. The semiconductor device (A11) according to Appendix 11, wherein the relay member (418) is a conductor. Appendix 13. The semiconductor device (A12) according to Appendix 11, wherein the relay member (418) is an insulator. Appendix 14. The semiconductor device (A13) according to Appendix 1, wherein the main substrate (3) further includes a main insulating layer (31) to which the first conductive portion (32A) and the second conductive portion (32B) are fixed and which is located on a second side (z2) in the thickness direction (z) relative to the first conductive portion (32A) and the second conductive portion (32B), and the first terminal (41) is supported by the main insulating layer (31). Appendix 15. The semiconductor device (A1) according to any one of Appendixes 1 to 14, further including a first conductive member (5) that electrically connects one or more of the first semiconductor elements (10A) and the second conductive portion (32B). Appendix 16. The semiconductor device (A1) according to any one of Supplementary Notes 1 to 15, wherein the second conductive member (6) includes a first bonding portion (61) bonded to the second semiconductor element (10B) and a second bonding portion (62) bonded to the first terminal (41).Supplementary Note 17. The semiconductor device (A1) according to Supplementary Note 16, wherein the second conductive member (6) further includes a second relay portion (64) interposed between the first bonding portion (61) and the second bonding portion (62).Supplementary Note 18. The semiconductor device A1 according to Supplementary Note 17, wherein the second conductive member (6) further includes a step portion (66) interposed between the second joint portion (62) and the second relay portion (64), and the second joint portion (62) and the second relay portion (64) are located at different positions in the thickness direction (z). Supplementary Note 19. The semiconductor device A2 according to Supplementary Note 17, wherein the second joint portion (62) and the second relay portion (64) are directly connected, and the second joint portion (62) and the second relay portion (64) are located at the same position in the thickness direction (z). Supplementary Note 20. The semiconductor device (A1) according to any one of Supplementary Notes 1 to 19, further comprising a plurality of control terminals (45) for driving and controlling the first semiconductor element (10A) and the second semiconductor element (10B), the plurality of control terminals (45) protruding from the sealing resin (8) toward the first side (z1) in the thickness direction z. Supplementary Note 21. The semiconductor device (A1) according to Supplementary Note 20, wherein the plurality of control terminals (45) are located separately on both sides in the first direction (x). Supplementary Note 22. The semiconductor device (A1) according to Supplementary Note 20, wherein the plurality of control terminals (45) are located biased toward the second side (x2) in the first direction (x). Supplementary Note 23. The semiconductor device (A1) according to any one of Supplementary Notes 20 to 22, wherein each of the first semiconductor element (10A) and the second semiconductor element (10B) has a first principal surface electrode (11) to which a drive signal is input, the plurality of control terminals (45) includes a first control terminal (46A) and a second control terminal (47A), the first control terminal (46A) is connected to the first principal surface electrode (11) of the first semiconductor element (10A) via a first wire (71), and the second control terminal (47A) is connected to the first principal surface electrode (11) of the second semiconductor element (10B) via a second wire (71).Supplementary Note 24. The semiconductor device (A1) according to any one of Supplementary Notes 20 to 23, further comprising: a control terminal support (48) interposed between the first principal surface (301A) and the back surface (302)A and the plurality of control terminals (45), the control terminal support (48) including a sub-insulating layer (481).Supplementary Note 25. The semiconductor device (A1) according to Supplementary Note 24, wherein the control terminal support (48) includes a first sub-metal layer (482) stacked on the first side (z1) in the thickness direction (z) of the sub-insulating layer (481), and a second sub-metal layer (483) stacked on the second side (z2) in the thickness direction (z) of the sub-insulating layer (481) and joined to the first conductive portion (32A) or the second conductive portion (32B) so as to face the first main surface (301A) or the second main surface (301B). Supplementary Note 26. A vehicle (B1) comprising: a drive system; and the semiconductor device (A1) according to any one of claims 1 to 25, wherein the semiconductor device (A1) is electrically connected to the drive system.

[0132] A1, A11, A12, A13, A14, A15, A2, A3: semiconductor device 1: support 3: main substrate 5: first conductive member 6: second conductive member 8: sealing resin 10A: first semiconductor element 10B: second semiconductor element 11: first principal surface electrode 12: second principal surface electrode 13: third principal surface electrode 15: back surface electrode 17: thermistor 19A: first conductive bonding material 19B: second conductive bonding material 31: main insulating layer 32: first main metal layer 32A: first conductive portion 32B: second conductive portion 33: second main metal layer 41: first terminal 42: second terminal 43: third terminal 45: control terminal 46A, 46B, 46E: first control terminal 47A, 47B, 47C, 47D: Second control terminal 48: Control terminal support 48A: First sub-board 48B: Second sub-board 49: Conductive bonding material 51: Main portion 52, 53: Bonding portion 59: Conductive bonding material 61: First bonding portion 62: Second bonding portion 63: First relay portion 64: Second relay portion 65: Third relay portion 66: Step portion 67: Rib 69: Conductive bonding material 71, 72, 73, 74: Wire 81: Resin main surface 82: Resin back surface 91: On-board charger 92: Storage battery 93: Drive system 101: Element main surface 102: Element back surface 301A: First main surface 301B: Second main surface 302: Back surface 321A: First portion 322A: Second portion 411: Terminal portion 412: Third bonding portion 413: Fourth bonding portion 414: Linking portion 415: Extension portion 418: Relay member 419: Bonding material 451: Holder 452: Pin 481: Sub-insulating layer 482: First sub-metal layer 482A, 482B, 482C, 482D, 482E, 482F: Region 483: Second sub-metal layer 511: Opening 602: First step portion 611: Flat portion 612: First inclined portion 651: Opening 652: Step portion 831: Resin side surface 832: Resin side surface 832a: Recess 833: Resin side surface 834: Resin side surface 931: Inverter 932: Driving source 4121: Groove portion 4151: Through hole 4521: Large diameter portion 4821A, 4821B, 4821C, 4821D: Connection parts 4822A, 4822B, 4822C,4822D: Terminal portion 4829: Surface metal layer B1: Vehicle x: First direction x1: First side x2: Second side y: Second direction y1: First side y2: Second side z: Thickness direction z1: First side z2: Second side

Claims

1. A semiconductor device comprising: a main substrate having a first main surface facing a first side in a thickness direction, a first conductive portion located on a first side in a first direction perpendicular to the thickness direction, and a second conductive portion having a second main surface facing the first side in the thickness direction and located on a second side in the first direction; one or more first semiconductor elements mounted on the first conductive portion and having a switching function; one or more second semiconductor elements mounted on the second conductive portion and having a switching function; a first terminal including a terminal portion protruding to the first side in the first direction relative to the main substrate and conducting to the second semiconductor element; a second conductive member interposed between the second semiconductor element and the first terminal; and a sealing resin covering the one or more first semiconductor elements, the one or more second semiconductor elements and the second conductive member, and a portion of the main substrate and the first terminal, wherein the first terminal is supported by the main substrate.

2. The semiconductor device according to claim 1, wherein said first terminal is supported by said first conductive portion.

3. The semiconductor device according to claim 2, wherein the first conductive portion includes a first portion on which the first semiconductor element is mounted and a second portion spaced apart from the first portion, and the first terminal is supported by the second portion.

4. The semiconductor device according to claim 3, wherein the first terminal has a third joint portion to which the second conductive member is joined and a fourth joint portion to which the main substrate is joined.

5. The semiconductor device according to claim 4, wherein the third bonding portion is located closer to the first side in the thickness direction than the fourth bonding portion.

6. The semiconductor device according to claim 5, wherein the area of said third junction is larger than the area of said fourth junction.

7. The semiconductor device according to claim 5 or 6, wherein the third bonding portion is located on the first side in the first direction relative to the fourth bonding portion.

8. The semiconductor device according to claim 7, wherein the fourth joint portion overlaps the second conductive member when viewed in the thickness direction.

9. The semiconductor device according to claim 4, wherein the first terminal has an extension extending from the third junction.

10. The semiconductor device according to claim 9, wherein the extension portion has a through-hole penetrating in the thickness direction.

11. The semiconductor device according to claim 1 or 2, further comprising a relay member interposed between said first terminal and said main substrate.

12. The semiconductor device according to claim 11, wherein the relay member is a conductor.

13. The semiconductor device according to claim 11, wherein the relay member is an insulator.

14. The semiconductor device described in claim 1, wherein the main substrate further has a main insulating layer to which the first conductive portion and the second conductive portion are fixed and which is located on a second side in the thickness direction relative to the first conductive portion and the second conductive portion, and the first terminal is supported by the main insulating layer.

15. The semiconductor device according to any one of claims 1 to 14, further comprising a first conductive member that provides electrical continuity between one or more of said first semiconductor elements and said second conductive portion.

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