Low-noise amplifier circuit for full-duplex transceiver

Abstract

There is provided a low-noise amplifier circuit (200a:200g) for a full-duplex radio transceiver, the low-noise amplifier circuit (200a:200g) comprising: an input port (Vin) for receiving a signal from an antenna; a first signal path operatively connected to the input port (Vin) and comprising a series impedance (Z1) and a first transistor (M1) operatively connected in series with each other for providing a positive polarity of the received signal at a first differential output (+Vout) of the low-noise amplifier circuit (200a:200g); a second signal path operatively connected to the input port (Vin) and comprising a second transistor (M2) for providing a negative polarity of the received signal at a second differential output (-Vout) of the low-noise amplifier circuit (200a:200g); a cancellation circuit (iC1, iC2) operatively connected to the first signal path for injecting a cancellation current in the first signal path; and a Self- Interference-Signal control circuit configured to receive channel and cross- interference information and to control the cancellation circuit (ic1, ic2) based on the received channel and cross-interference information.

Description

[0001] LOW-NOISE AMPLIFIER CIRCUIT FOR FULL-DUPLEX TRANSCEIVER

[0002] TECHNICAL FIELD

[0003] Embodiments presented herein relate to a low-noise amplifier circuit for a full-duplex radio transceiver and to a full-duplex transceiver comprising such a low-noise amplifier circuit.

[0004] BACKGROUND

[0005] In communications networks, there may be a challenge to obtain good performance and capacity for a given communications protocol, its parameters and the physical environment in which the communications network is deployed.

[0006] For example, in order to improve the spectral efficiency in congested parts of the frequency spectrum, there is an interest in radio circuits able to transmit (Tx) and receive (Rx) signals simultaneously and at the same frequency. This approach is referred to as Full-Duplex (FD) and allows to operate Uplink (UL) and Downlink (DL) on the same time-frequency resource. FD is compared to Time-Division Duplex (TDD) and Frequency-Division Duplex (FDD) in Fig. 1. In more detail, Fig. 1 shows time and frequency allocation for different duplexing schemes; Fig. 1(a) shows an example of TDD, Fig. 1(b) shows an example of FDD, and Fig. 1(c) shows an example of FD.

[0007] One challenge introduced by FD is self-interference, where a portion of the Tx signal is undesirably transmitted to the equipment’s own Rx circuitry. Self-interference can be mitigated, or even resolved, by means of isolation, i.e., by minimizing as much as possible the leakage from the Tx circuitry to the Rx circuitry, and by cancellation (i.e., by Self-Interference (SI) Cancellation; (SIC) where the leaking of the Tx signal is subtracted from the Rx signal. In a single-antenna Transceiver (TRx), isolation can, for example, be obtained by using a circulator at the antenna interface. Cancellation can be performed in the radio frequency (RF) domain, the analog domain, and in the baseband (BB) domain. In an antenna array, isolation can be introduced by connecting the Tx circuitry and the Rx circuitry to split antenna panels. Placing the panels further apart increases the isolation. In this example, the self-interference varies between the different Rx elements according to the steering angle. In an antenna array, the cancellation circuit should address both self-interference and cross-interference (i.e., coupling between the antennas). In some aspects, the complexity of the cancellation circuit grows quadratically with the number of antennas.

[0008] One advantage of performing SIC at the antenna interface is that the cancellation includes some of the Tx impairments, such as the Power Amplifier (PA) nonlinearities. Approaches have been implemented using passive or active balanced duplexers, and circulators. However, the sensitivity to antenna impedance, the inherent 3 dB Noise Figure (NF) degradation and the physical size of these networks remain limiting factors for integration. Considering these limitations, recent attempts at implementing a FD Rx attempts to combine both SIC and noise cancellation (NC).

[0009] In M. Essawy et al., "A Noise-Cancelling Self-Interference Canceller with +7 dBm Self-Interference Power Handling in o.i8p m CMOS,", 2021 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Atlanta, GA, USA, 2021, pp. 95-98, doi: 10.1109 / RFIC51843.2021.9490418 is disclosed a dual-path NC and SIC. The distortion and noise added by the SIC circuit is sensed and also cancelled. A 2odB SI cancellation over a 50MHz bandwidth and 23dB cancellation for +idBm peak SI power while degrading the Rx NF by 3.8dB is claimed. However, the usability in antenna array is limited as cross-interference is not addressed.

[0010] In S. C. Blaakmeer et al., " Wideband Balun- LNA With Simultaneous Output Balancing, Noise-Canceling and Distortion-Canceling," in IEEE Journal of Solid- State Circuits, vol. 43, no. 6, pp. 1341-1350, June 2008, doi:

[0011] 10.1109 / JSSC.2008.922736 is introduced an NC low noise amplifier (LNA) having of a main-path transistor sensing current and an auxiliary-path transistor sensing voltage. The thermal noise on each path has an opposite sign and therefore, can be cancelled.

[0012] In view of the above, there is still a need for an FD LNA that is capable of performing Self- and Cross-Interference Cancellation, with a limited impact on the Rx noise.

[0013] SUMMARY

[0014] An object of embodiments herein is to address the above issues by providing a low- noise amplifier circuit that is capable of performing Self- and Cross-Interference Cancellation, with a limited impact on the Rx noise. A particular object is to provide a low-noise amplifier circuit that is tunable according to the level of cancellation required, to limit the impact on overall power consumption in a large antenna array.

[0015] According to a first aspect there is presented a low-noise amplifier circuit for a full- duplex radio transceiver. The low-noise amplifier circuit comprises an input port for receiving a signal from an antenna. The low-noise amplifier circuit further comprises a first signal path. The first signal path is operatively connected to the input port. The first signal path comprises a series impedance and a first transistor. The series impedance and the first transistor are operatively connected in series with each other for providing a positive polarity of the received signal at a first differential output of the low-noise amplifier circuit. The low-noise amplifier circuit further comprises a second signal path. The second signal path is operatively connected to the input port. The second signal path comprises a second transistor for providing a negative polarity of the received signal at a second differential output of the low-noise amplifier circuit. The low-noise amplifier circuit further comprises a cancellation circuit. The cancellation circuit is operatively connected to the first signal path for injecting a cancellation current in the first signal path. The low-noise amplifier circuit further comprises a Self-Interference-Signal control circuit. The Self-Interference- Signal control circuit is configured to receive channel and cross-interference information and to control the cancellation circuit based on the received channel and cross-interference information.

[0016] According to a second aspect there is presented a full-duplex transceiver. The full- duplex transceiver comprises the low-noise amplifier circuit according to the first aspect.

[0017] Advantageously, this low-noise amplifier circuit and this full-duplex transceiver are capable of performing Self- and Cross-Interference Cancellation, with a limited impact on the Rx noise.

[0018] Advantageously, this low-noise amplifier circuit and this full-duplex transceiver are tunable according to the level of cancellation required, to limit the impact on overall power consumption in a large antenna array. Advantageously, this low-noise amplifier circuit and this full-duplex transceiver can use digital control of the cancellation to enable a tradeoff between power and complexity on the one hand and cancellation on the other hand.

[0019] Advantageously, this low-noise amplifier circuit and this full-duplex transceiver can run in TDD without penalty on the performance.

[0020] Other objectives, features and advantages of the enclosed embodiments will be apparent from the following detailed disclosure, from the attached dependent claims as well as from the drawings.

[0021] Generally, all terms used in the claims are to be interpreted according to their ordinary meaning in the technical field, unless explicitly defined otherwise herein. All references to "a / an / the element, apparatus, component, means, module, step, etc." are to be interpreted openly as referring to at least one instance of the element, apparatus, component, means, module, step, etc., unless explicitly stated otherwise. The steps of any method disclosed herein do not have to be performed in the exact order disclosed, unless explicitly stated.

[0022] BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The inventive concept is now described, by way of example, with reference to the accompanying drawings, in which:

[0024] Fig. 1 is a schematic diagram illustrating TDD, FDD, and FD according to examples;

[0025] Figs. 2, 3, 4, 5, 6, 7, and 8 schematically illustrate low-noise amplifier circuits according to embodiments;

[0026] Figs. 9 and 10 show simulation results according to embodiments; and

[0027] Figs, n, 12, 13, and 14 schematically illustrates full-duplex transceivers according to embodiments.

[0028] DETAILED DESCRIPTION

[0029] The inventive concept will now be described more fully hereinafter with reference to the accompanying drawings, in which certain embodiments of the inventive concept are shown. This inventive concept may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided by way of example so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. Like numbers refer to like elements throughout the description. Any step or feature illustrated by dashed lines should be regarded as optional.

[0030] As noted above, there is still a need for an FD LNA that is capable of performing Self- and Cross-Interference Cancellation, with a limited impact on the Rx noise.

[0031] According to the herein disclosed embodiments, a low-noise amplifier circuit is therefore disclosed for performing Self- and Cross-Interference Cancellation, with a limited impact on the Rx noise. In particular, a low-noise amplifier circuit for a full- duplex radio transceiver as illustrated in Figs. 2, 3, 4, 5, 6, 7, and 8 adapted to perform both noise cancellation (NC) and interference cancellation (IC) will now be disclosed.

[0032] The low- noise amplifier circuit 200a: 200g for a full-duplex radio transceiver. The low-noise amplifier circuit 200a: 200g comprises an input port (Vin) for receiving a signal from an antenna. In some examples, the input port (Vin) is arranged to receive the signal either directly from the antenna or indirectly from the antenna via a frontend filter and / or an isolation device in the full-duplex radio transceiver.

[0033] The low- noise amplifier circuit 200a: 200g further comprises a first signal path. The first signal path is operatively connected to the input port (Vin). The first signal path comprises a series impedance (Zi) and a first transistor (Ml). In some examples, the first transistor (Ml) is a common gate (CG) transistor. The series impedance (Zi) and the first transistor (Ml) are operatively connected in series with each other for providing a positive polarity of the received signal at a first differential output (+Vout) of the low- noise amplifier circuit 200a: 200g. In general terms, a common gate transistor is a transistor that comprises a gate terminal, a source terminal, and a drain terminal. The gate terminal is connected to signal ground (gnd, vdd, or bias voltage). The source terminal is used as a (current) input. The drain terminal is used as a (current) output. The common gate transistor is here represented by a N-channel metal-oxide-semiconductor (NMOS) transistor, but could also be implemented using some other type, e.g. P-channel metal-oxide-semiconductor (PMOS), and / or transistor technology.

[0034] The low- noise amplifier circuit 200a:200g further comprises a second signal path. The second signal path is operatively connected to the input port (Vin). The second signal path comprises a second transistor (M2) for providing a negative polarity of the received signal at a second differential output (-Vout) of the low-noise amplifier circuit 200a:200g. In general terms, the first differential output (+Vout) and the second differential output (-Vout) are linked together so as to form the opposite polarities of one and the same differential output. In some examples, the second transistor (M2) is a common source (CS) transistor. In general terms, a common source transistor is a transistor comprising a gate terminal, a source terminal, and a drain terminal. The gate terminal is used as a (voltage) input. The source terminal is connected to signal ground (gnd, vdd, or bias voltage). The drain terminal is used as a (current) output. The common source transistor is here represented by a N-channel metal-oxide-semiconductor (NMOS) transistor, but could also be implemented using some other type, e.g. P-channel metal-oxide-semiconductor (PMOS), and / or transistor technology.

[0035] The low- noise amplifier circuit 200a:200g further comprises a cancellation circuit (iCi, iC2). The cancellation circuit (iCi, iC2) is operatively connected to the first signal path for injecting a cancellation current in the first signal path (for (self-) interference cancellation). In some examples, the cancellation circuit (iCi, iC2) is operatively connected to the first signal path between the series impedance (Zi) and the first transistor (Ml). In some examples, the cancellation circuit (iCi, iC2) comprises at least one current source (iCi, iC2) with tunable amplitude and phase. The noise introduced by the cancellation circuit can be suppressed by yet an additional current. The cancellation signal can be digitally controlled and set to cancel both self-interference and cross-interference (i.e., coupling between the antennas).

[0036] The low- noise amplifier circuit 200a:200g further comprises a Self-Interference- Signal (SIS) control circuit (SISC). The Self-Interference-Signal control circuit is configured to receive channel and cross-interference information and to control the cancellation circuit (ici, ic2) based on the received channel and cross-interference information. In Figs. 2 to 8 the Self-Interference-Signal control circuit is represented by the Self-Interference-Signal (SIS).

[0037] In some embodiments, the Self-Interference-Signal control circuit (SISC) is configured to tune amplitude and phase of the cancellation current based on the received channel and cross-interference information. In some embodiments, the Self- Interference-Signal control circuit is configured to control the cancellation circuit (iCi, iC2) in accordance with a calibration procedure performed during operation of the low- noise amplifier circuit 2ooa:2oog.

[0038] Fig. 2 shows a low-noise amplifier circuit 200a according to a first embodiment. The low-noise amplifier circuit 200a comprises a first path and second path. The first path comprises an input impedance (Zi), a bias-current source (IDC), a common gate transistor (Mi), a cancellation-current source (Ici), and a load (RLI), which might be an impedance (Zu), to match the input (Vin) of the low-noise amplifier circuit 200a to a nominal impedance. The input could be connected to an antenna, a front-end filter, and / or an isolation-device.

[0039] By matching the first path to the nominal impedance, there is a Noise Figure (NF) penalty of at least 3 dB. One way to reduce this penalty is to utilize the concept of Noise-Canceling (NC). In order to cancel the noise from the first path, an additional second path can be used, by means of which all signals are inverted, such as the wanted received signal and noise. This is possible because the noise at the drain of Mi and the noise at the input (Vin) has opposite phase with respect to each other. This gives a noise voltage at the outputs of the first path and the second path, which are in common mode, whereas the wanted received signal is in differential mode.

[0040] The second path comprises a direct current (DC) blocking capacitor (CDC), a biasresistor (RB), a common source transistor (M2), and a load (RL2) which might be an impedance (ZL2). That is, in some embodiments, the second signal path further comprises a DC blocking capacitor (CDC) operatively connected in series between the input port (Vin) and an input of the second transistor (M2). Further, in some embodiments, the second signal path further comprises a bias resistor (RB) operatively connected between the DC blocking capacitor (CDC) and the input of the second transistor (M2). If the NC is performed correctly, then the NF of the low-noise amplifier circuit 200a is set by the second path and the NF of the second path is inversely proportional to the transconductance (gm) of M2.

[0041] By introducing SIC, in the form of current source ici (as controlled by the SIS signal), to the low-noise amplifier circuit 200a, the impedance Zi is used to electrically differentiate i& and the input Vin, This is needed to enable NC of the SI canceller noise, rather than just placing the SI canceller at the input Vin. The utilization of Zi, even if it is a purely resistive impedance will not affect the overall NF because the second path also cancels the noise from Zi. However, by injecting the cancellation current between the source of Mi and the impedance Zi, a portion of the current injected ends up as drain current of Mi. This portion is the current division between Zi and the source impedance of Mi (i.e., 1 / gm).

[0042] Fig. 3 shows a low-noise amplifier circuit 200b according to a second embodiment. The low-noise amplifier circuit 200b is identical to the low-noise amplifier circuit 200a but further comprises an additional current source (ic2) added at the drain of Mi, which is one of the outputs of the low-noise amplifier circuit 200b. That is, in some embodiments, the cancellation circuit (i&, ic2) comprises a first current source (ici) operatively connected between the series impedance (Zi) and the first transistor (Mi) and a second current source (ic2) operatively connected to an output (e.g., the drain) of the first transistor (Ml). In this way, a second current source allows to further reduce the amount of cancellation current existing at the output (e.g., the drain) of the first transistor (Mi) and can be used to suppress the additional noise introduced by the cancellation. The first current source (ici) and the second current source (ic2) are controlled by the SIS signal.

[0043] The current source ic2 can be used to further improve the SIC by canceling, or at least mitigating, the leaked current from ici, to give additional SIC at the output of the low- noise amplifier circuit 200b and to cancel, or at least mitigate, the noise from the SIC system. Furter, if any signal entity has the same amplitude and phase at the output of the low-noise amplifier circuit 200b, i.e., it is a common mode (CM) signal, then it is canceled by signal balancing. This is because the outputs (RLI and R.L2) are differential, or out-of-phase, with respect to each other. The SI canceller current sources i& and ic2 operate with differential, or out-of-phase, SI replicas and differential, or out-of-phase, noise, but the amplitudes may be tuned differently. In order to reduce, or mitigate, the leakage from ici, the amplitude of ic2 can be set to a value a (alpha), which is scalar in relations to the amplitude of ici. To cancel the leakage from ici, the value of a can be set so that the amplitude of ic2 is equal to the leaked current. This might not achieve a maximum SIC in case there is an amplified residue, amplified by M2, at the other output (RL2). Such an amplified residue might be caused by a non-ideal SIC at the input (Vin) of the low-noise amplifier circuit 200b. This amplified residue might limit the SIC. Conversely, the cancellation at the input is likely to be the limitation of the maximum possible SIC. Furthermore, to achieve more SIC, or to fully utilizes the second current source from a SIC point-of- view, ic2 can be tuned so the residue of the leakage from ici is equal to the residue from the input cancellation, present at RL2.

[0044] Any noise added from the SI canceller system is in general uncanceled, or unmitigated, during the cancellation of the SI. This generally applies for the distortion from the SI canceller system as well. However, for the low-noise amplifier circuit 200b, noise and distortion from the SI canceller system can be canceled or mitigated, in case the noise and / or distortion are differential, or out-of-phase, with respect to each other at the outputs of the current sources ici and ic2. Equation (1) can be used for the setting of the noise and / or distortion amplitudes for ic2, assuming Zi to be resistive.

[0045] Here, iN Mi dis the ici noise current at the drain of Mi, a resistance Ri is used when Zi is purely resistive, Rant is the nominal antenna impedance, gmi is the transconductance of Mi, and iN,iclis the noise current injected by ici. To mitigate the ici noise current at the drain of Mi, the amplitude of ic2 can be set to the i& noise current at the drain of Mi. For a complete cancellation of the noise, the amplitude of ic2 can be set so the output noise current is equal to the i& noise current at the drain of M2.

[0046] By tuning a of ic2, the low-noise amplifier circuit can be configured for three modes of operation. In a first mode, ici is tuned for input SIC and ic2 is tuned to fully cancel the leakage from ici. In a second mode i& is tuned for input SIC and ic2 is tuned to generate a residue at the output of the first transistor (Mi) , which is equal to the residue at the output of the second transistor (M2). Further, additional SIC is introduced by balancing of this differential output. That is, the signals are in CM. In a third mode, ic2 is tuned to generate noise at the output of the first transistor (Ml), which is out-of-phase and has the same magnitude as the noise present at the output of the second transistor (M2). This noise originates from ici and is present at the input of the low-noise amplifier circuit.

[0047] Fig. 4 shows a low-noise amplifier circuit 200c according to a third embodiment. The low-noise amplifier circuit 200c was used for the simulation results that will be disclosed below. The low-noise amplifier circuit 200c is identical to the low-noise amplifier circuit 200b but where the input impedance Zi is purely resistive (and denoted Ri) and that the low-noise amplifier circuit 200c comprises a cascode transistor. In particular, in some embodiments, the low-noise amplifier circuit further comprises a first cascode transistor (M3) operatively connected between an output of the first transistor (Ml) and the first differential output (+Vout) of the low- noise amplifier circuit and a second cascode transistor (M4) operatively connected between an output of the second transistor (M2) and the second differential output (- Vout) of the low-noise amplifier circuit. The cascode transistors provide an improved reverse isolation to prevent local oscillator leakage into the low-noise amplifier circuit 200c and to ensure stability of the low-noise amplifier circuit 200c.

[0048] Fig. 5 and Fig. 6 show low-noise amplifier circuits 2ood, 2ooe according to a fourth embodiment and a fifth embodiments. Both these low-noise amplifier circuits 2ood, 2ooe are identical to the low-noise amplifier circuit 200b except for also comprising a second common gate transistor in the first path, and that the low-noise amplifier circuit 2ooe comprises cascode transistors. The low-noise amplifier circuits 2ood, 2ooe can be used for non-linearity cancellation in a common gate transistor by using derivative superposition. In some embodiments, the first transistor (Ml) is composed of a first first transistor (Mia) and a second first transistor (Mib), wherein the first first transistor (Mia) and the second first transistor (Mib) have mutually different biasing conditions. In this way, a second first transistor (Mib) can be arranged in parallel with the first first transistor (Mia), where the second first transistor (Mib) uses a different bias point than the first first transistor(Mia), which results in a linearization result. Two transistors with different gate-bias voltage (VCG.I, VCG,2) are thus used in the first path. These bias voltages are set so either the second, third, fourth, and so, term in the transconductance (gm) becomes zero, or at least comparatively very low in magnitude. When this condition is meet, the transistorpair generates zero, or at least a comparatively very small amount of for instance third-order harmonic distortion, and therefore a low amount third-order intermodulation (IM3). By this, a further increase in output referred third-order intercept point (OIP3) might be possible.

[0049] Fig. 7 shows a low-noise amplifier circuit 2oof according to a sixth embodiment. The low-noise amplifier circuit 2oof is similar to the low-noise amplifier circuit 200c but where the low-noise amplifier circuit 2oof implements an alternative way of injecting ic2, namely at the output the cascode transistor (M3) of the first path.

[0050] Fig. 8 and shows a low-noise amplifier circuit 200g according to a seventh embodiment. Compared to the low-noise amplifier circuits 200a: 2oof, for the low- noise amplifier circuit 200g the second transistor (M2)has been replaced by an inverter-based transconductor (M2p, M2n, M3p, M3n) and the implementation is also fully differential with differential outputs (Voutp, Voutn). The low-noise amplifier circuit 200g comprises differential inputs (Vinp, Vinn), a first first path, second first path, first second path and second second path. The first first path provides a non-inverting signal from the positive differential input (Vinp) to the positive differential output (Voutp). The second first path provides a non-inverting signal from the negative differential input (Vinn) to the negative differential output (Voutn). The first first path comprises an input impedance (Zip), a bias-current source (IDCP) (depicted as the bias inductor LDCP), a common gate transistor (Mip), a cancellation-current source (Icip), and a load (RLP), which might be an impedance (Zu), to match the positive differential input (Vinp) of the low-noise amplifier circuit 200g to a nominal impedance. The second first path comprises an input impedance (Zm), a bias-current source (IDCH) (depicted as the bias inductor LDCH), a common gate transistor (Mm), a cancellation-current source (Icm), and a load (RLP), which might be an impedance (Zu), to match the negative differential input (Vinn) of the low-noise amplifier circuit 200g to a nominal impedance. The first second path provides an inverting signal from the positive differential input (Vinp) to the negative differential output (Voutn). The second second path provides an inverting signal from the negative differential input (Vinn) to the positive differential output (Voutp). The first second path comprises capacitors (CinP, Cinn), bias-resistors (RBP, RBH), an NMOS common source transistor (M2p), and a PMOS common source transistor (M3P). The second second path comprises capacitors (CinP, Cinn), bias-resistors (RBP, Run), an NMOS common source transistor (M2n), and a PMOS common source transistor (M3n). The cancellation circuits (iciP, icm, ic2p, ic2n) comprises a first current source (iciP) operatively connected between the series impedance (Zip) and the first first path transistor (Mip), a second current source (ic2p) operatively connected to the positive differential output (Voutp), a third current source (icm) operatively connected between the series impedance (Zin) and the second first path transistor (Min), and a fourth current source (ic2n) operatively connected to the negative differential output (Voutn) . All current sources (iciP, icm, ic2p, ic2n) are controlled by the SIS signal.

[0051] Simulation results will be disclosed next with reference to Fig. 9 and Fig. 10. As disclosed above, the low-noise amplifier circuit 200c was used for these simulation results. Further, Table 1 shows component values and parameters used during the simulations.

[0052] Table 1: Parameters to Evaluate the Proposed LNA in GLOBALFOUNDRIES 22 nm Fully Depleted Silicon on Insular (FD-SOI) transistor technology (GF22FDX)

[0053] By selecting the value of Zi to be Ri, which is equal to half the antenna resistance RAnt, this means that the remaining half of RAM is generated with the transconductance gm of Mi, i.e., where gm=40 mS. To keep a good trade-off between the power consumption and the NF, a 1:3 channel width ratio is used between the CG stage (Mi) and the CS stage (M2). This ratio can be further increased if lower NF is required. The current source IDC is implemented by LDC with a radio frequency choke (RFC), assuming the impedance to be much larger than the nominal antenna impedance RAM, to obtain a low-noise amplifier circuit for wideband operation. An inductor can be used to put the input of Mi into resonance for a more narrowband operation of the low-noise amplifier circuit.

[0054] Fig. 9 shows the tuning of a and its effect on the aforementioned modes of operation. The maximum SIC at the input of the CG-stage is 48 dB and the maximum SIC at the output is 58 dB, both at <1=0.535, and the minimum NF is 2.15 dB at a=i. Further, it is noted that the effective SIC is odB at the minimum NF point. Hence there is not any SIC present for this value of a. The maximum of OIP3, 48 dBm, is at <1=0.69, and the SIC in this point is 8.6 dB. Further, the OIP3is 42 dBm at the SIC peak. To test the low-noise amplifier circuit with large SI signal, the SIC at the input and output, the low-noise amplifier circuit gain, and the blocker NF were all simulated with the SIC enabled with an Sl-blocker at 1.9 GHz, an ici setting of 43 mA / V and <1=0.535. In addition, a two-tone test was also performed with SIC enabled, where the first tone was at 1.875 GHZ and the second tone at 1.925 GHz, with both ici and a unchanged.

[0055] Fig. 10 shows the difference in performance between the proposed low-noise amplifier circuit with SIC, a state-of-the-art original low-noise amplifier circuit (as represented by an implementation of the NC-LNA proposed in the aforementioned paper by S. C. Blaakmeer et al.) and the proposed low-noise amplifier circuit without SIC. The improvement in compression point is over 16 dB and the maximum improvement in SI-NF is 6.6 dB, while the NF degradation is 1.2 dB at lower SI powers. This is with a SIC NF contribution of 7 dB (or 10 dB, if all SIC noise is accounted for). For the third-order intercept point (IP3), the improvement is 15 dB with SIC, for input referred third-order intercept point (HP3) / OIP3there is an improvement of 8.7 / 27 dBm for the circuits without SIC, and for IIP3 / OIP3 there is an improvement of 23.7 / 42 dBm with SIC.

[0056] Embodiments of a full-duplex transceiver 1100a: nood comprising a low-noise amplifier circuit 200a: 200g as disclosed above are illustrated in Fig. 11 to Fig. 14. Fig. 11 to Fig. 14 also illustrate different embodiments of the SISC. For this purpose, the low-noise amplifier circuit without the SISC is in Figs. 11 to 14 referred to by reference numerals 2ooa':2oog'. That is, reference numerals 2ooa':22og' in Figs. 11 to 14 refer to the low-noise amplifier circuit 200a: 200g in Figs. 2 to 8 but where SISC has been excluded and instead is illustrated separately. Reference numerals 200a' :200g' thus refer to a schematic illustration of the low- noise amplifier circuit 2ooa:2oog but with the SISC removed.

[0057] Fig. n shows an example of a full-duplex transceiver nooa with analog SIC. Fig. 12 shows an example of a full-duplex transceiver 1100b with digital-assisted SIC system. Figs. 13 and 14 show examples of full-duplex transceivers 1100c, nod with hybrid SIC architectures. That is, in some embodiments, the Self-Interference-Signal control circuit has an analog architecture, a digitally assisted architecture, or a hybrid architecture. As schematically illustrated in Fig. 11 to Fig. 14, in some examples, the full-duplex transceiver nooa:nood is a single antenna transceiver, or comprises an antenna array with a circulator at each input port, or comprises an antenna array with separate antennas for transmission and reception. In some examples, the Self- Interference-Signal (denoted SIS) control circuit (denoted SISC) is operatively connected to the first signal path and the second signal path via delay element (denoted T) and buffer (denoted Buf) and attenuator (denoted Att.). In some embodiments, the full-duplex transceiver 1100a: nood is configured for time-division duplex communication by having the cancellation circuit ici, ic2 turned off. One advantage of the transceivers 1100a: liood is that the SIC system can be disabled without any Rx performance degradation. Further, all buffers are in the current domain nodes, which means that no significant loading is present in the off-state, which is beneficial for Time-Division-Duplex (TDD), Frequency-Division-Duplex (FDD), and FD.

[0058] Further aspects of the full-duplex transceivers nooa:nood will be disclosed next with reference to Fig. 11 to Fig. 14. The Self-Interference-Signal control circuit (SISC) is indicated by dotted lines.

[0059] In these full-duplex transceivers, in order for the SIC to function, a SI replica is created within the transceiver. As will be further disclosed below, the transceiver can implement an analog, digitally-assisted or a hybrid SIC system. The difference between SIC systems in these different implementations is how the required amplitude- and time-alignment are generated for the signal used for the cancellation of SI. In an analog SIC system, all signals and signal processing are performed in the analog domain, but the circuits performing the operations may be digitally controlled. For a digitally-assisted SIC system, the cancellation is performed in the analog domain, but all the signal processing is performed in the digital domain, by converting the analog transmit signal, at the PA output, to a digital signal, processed in the digital domain and then converted back to analog domain. Finally, in the hybrid SIC system, the cancellation is performed in the analog domain, the initial signal processing is performed in the digital domain, the transmit signal is converted to digital domain as well, but after the transmit signal is converted back to the analog domain, analog processing is applied as well. In the example of Fig. 14 (see below), the signal processing is performed first in the analog domain for one SI replica (SIS) but also first in the digital domain for other replicas.

[0060] Fig. 11 is a block diagram of an embodiment of a full-duplex transceiver 1100a implementing an analog SIC system. The SI replica is obtained at the output of the PA, attenuated with the attenuator (Att.) and is fed to a time-varying (delay and / or phase-shifter) block (T), used to time-align the SI from the antenna with the SI replica. Multiple taps might be used here. The thus time-aligned signal is fed to a buffer / current-source (Buf), which has the functionality to generate i& and ic2, and to generate an out-of-phase output-referred noise, or non-ideality, with the correct amplitude for the cancellation of the noise, or non-ideality. In addition, the attenuated SI replica is also fed to a down-converting mixer (Mixersis), converting the SI replica to baseband (BB), in order to for SIC to be applied to the analog baseband (BB) blocks. This is achieved by additional time-aligning (T) and buffer (Buf) blocks. In the present example, buffers (denoted Buf) in the beginning of the NC-Rx, after the mixer MixerRx,i and before the analog baseband (denoted Analog BB) are transconductors. The output is in the current domain and the last buffer between the Analog BB and the Analog-to-Digital Converter (ADC) can be in the voltage- or current-domain. The first buffer, connected between Zi and Mi and connected to Vout (drain of Ml), feeds a first SIS current between Zi and Ml at RF, where it cancels the self-interference at the input (VIn) of the NC-LNA. Further, the second SIS current is feed to Vout at RF, is used to cancel the self-interference residue from the aforementioned SIC at the RF input. For the SIC with this current injection, different delay (T) and signal amplitude might be required, because the delay / phase- shift caused by blocks in the NC-LNA is different from the one used for the SIC at the RF-input. A second SIC tap, provided between the MixerRx and the Analog BB, requires a different delay (T) and signal amplitude in order to cancel the self- interference residue from the SIC circuit in the NC-LNA. Finally, the third SIC tap, provided between the Analog BB and the ADC, requires a different delay (T) and signal amplitude in order to cancel the self-interference residue from the two SIC circuits earlier in the Rx chain. One advantage of the transceiver nooa is that it has the most straight forward approach, where signals are kept in the analog domain.

[0061] Fig. 12 is a block diagram of an embodiment of a full-duplex transceiver noob implementing a digitally-assisted SIC system. The SI replica is collected at the output of the PA and first fed to the Att. block to attenuate the strong transmit signal. The signal is then down-converted to BB by MixersE and fed to an ADC. The digitally converted signal DSE, is fed as an input to the Si-Signal Generator block. The other inputs to the Si-Signal Generator block are the digital transmit baseband signal DTX, the digital receive baseband signal DRX, and a digital control signal DCTRL. That is, in some embodiments, the channel and cross-interference information is based on any, or any combination, of: an analog-to-digital converted version of the received signal, a digital transmission signal, an analog-to-digital converted version of an analog transmission signal, a digital control signal. The output from the Si-Signal Generator block is the digitally signal processed SI replica Dsis. Further, the DSE signal contains the ideal carrier signal and all the non-idealities of the transmit chain, but also the non-idealities from the ADC, which if differential can be canceled, or at least mitigated, by the proposed low-noise amplifier circuit. By also including DTX into the Si-signal generator, all affects from the transmit chain can be correlated to the actual digital data (DTX). By including the digital receive baseband signal (DRX), the time- and amplitude-coefficients can be optimized, or tuned.

[0062] A digital control signal (Dsis) is used to track different surrounding, beamforming angles, etc. The digital output (Dsis) is converted back to analog domain by the DAC. The DAC non-idealities, which if differential can be canceled, or at least mitigated, by the proposed low-noise amplifier circuit. Furthermore, the analog digitally signal processed SI replica is fed to two baseband cancellation circuits (T and Buf) and to an up-converting mixer Mixersis, generating an RF version of the SI replica (SIS). This RF signal is fed to a buffer / current-source (Buf) configured to generate i& and ic2, and to generate an out-of-phase output-referred noise and / or non-ideality of the complete SIC signal chain, while maintaining the correct amplitude for the cancellation of the SI and noise / non-idealities. The two baseband cancellation circuits (T and Buf) are configured to align, or compensate, the SI replica in time to the propagation time from the proposed low-noise amplifier circuit to the injection node, whilst also tuning the amplitude of the SI replicas for the correct SIC. One advantage of the transceiver noob is that more complex SIS operations can be performed in the digital domain with the ability to use Machine Learning (ML) to train of the system. Further, it does not require any complex routing when used in a beamforming antenna array.

[0063] Fig. 13 is a block diagram of an embodiment of a full-duplex transceiver 1100c implementing a (first) hybrid SIC system. The full-duplex transceiver 1100c can be regarded as a combination of the full-duplex transceiver 1100a and the full-duplex transceiver 1100b. The SI replica is retrieved from the PA output and this signal is down-converted in a mixer (Mixersr) to baseband, and then fed to an ADC. The ADC converts the signal into digital domain. However, the hybrid Si-signal generator is different from the digitally-assisted Si-signal generator. In the full-duplex transceiver 1100c the hybrid Si-signal generator is configured to implement longer delays. The hybrid Si-signal generator has lower complexity whilst requiring less hardware and energy than the digitally-assisted Si-signal generator. The high precision requirements of the amplitude- and time-alignment is implemented in the analog domain with analog functionality.

[0064] Fig. 14 is a block diagram of an embodiment of a full-duplex transceiver nood implementing a (second) hybrid SIC system. The full-duplex transceiver nood can be regarded as a combination of the full-duplex transceiver 1100a and the full-duplex transceiver 1100b. The SI replica is retrieved from the PA output. The cancellation within the proposed low-noise amplifier is purely analog and the cancellation points at baseband use a varying degree of a mix of analog and digital implementation. The Si-signal generator can either be of low complexity (such as the same complexity as the full-duplex transceiver 1100c) or be of complexity equivalent to the digitally- assisted SIC system (such as the same complexity as the full-duplex transceiver 1100b).

[0065] The inventive concept has mainly been described above with reference to a few embodiments. However, as is readily appreciated by a person skilled in the art, other embodiments than the ones disclosed above are equally possible within the scope of the inventive concept, as defined by the appended patent claims.

Claims

CLAIMS1. A low-noise amplifier circuit (200a: 200g) for a full-duplex radio transceiver, the low-noise amplifier circuit (200a: 200g) comprising: an input port (Vin) for receiving a signal from an antenna; a first signal path operatively connected to the input port (Vin) and comprising a series impedance (Zi) and a first transistor (Mi) operatively connected in series with each other for providing a positive polarity of the received signal at a first differential output (+Vout) of the low-noise amplifier circuit (200a: 200g); a second signal path operatively connected to the input port (Vin) and comprising a second transistor (M2) for providing a negative polarity of the received signal at a second differential output (-Vout) of the low-noise amplifier circuit (2ooa:2oog); a cancellation circuit (iCi, iC2) operatively connected to the first signal path for injecting a cancellation current in the first signal path; and a Self-Interference-Signal (SIS) control circuit (SISC) configured to receive channel and cross-interference information and to control the cancellation circuit (ici, ic2) based on the received channel and cross-interference information.

2. The low-noise amplifier circuit (200a: 200g) according to claim 1, wherein the first transistor (Ml) is a common gate transistor.

3. The low-noise amplifier circuit (200a: 200g) according to any preceding claim, wherein the second transistor (M2) is a common source transistor.

4. The low-noise amplifier circuit (200a: 200g) according to any preceding claim, wherein the cancellation circuit (iCi, iC2) is operatively connected to the first signal path between the series impedance (Zi) and the first transistor (Mi).

5. The low-noise amplifier circuit (200a: 200g) according to any preceding claim, wherein the cancellation circuit (iCi, iC2) comprises at least one current source (iCi, iC2) with tunable amplitude and phase.

6. The low-noise amplifier circuit (200a: 200g) according to any preceding claim, wherein the cancellation circuit (iCi, iC2) comprises a first current source (iCi) operatively connected between the series impedance (Zi) and the first transistor (Mi) and a second current source (iC2) operatively connected to an output of the first transistor (Ml).

7. The low-noise amplifier circuit (200a: 200g) according to any preceding claim, wherein the low- noise amplifier circuit (200a: 200g) further comprises a first cascode amplifier (M3) operatively connected between an output of the first amplifier (Mi) and the first differential output (+Vout) of the low-noise amplifier circuit(200a: 200g) and a second cascode amplifier (M4) operatively connected between an output of the second amplifier (M2) and the second differential output (-Vout) of the low-noise amplifier circuit (200a: 200g).

8. The low-noise amplifier circuit (200a: 200g) according to any preceding claim, wherein the first transistor (Ml) is composed of a first first transistor (Mia) and a second first transistor (Mib), wherein the first first transistor (Mia) and the second first transistor (Mib) have mutually different biasing conditions.

9. The low-noise amplifier circuit (200a: 200g) according to any preceding claim, wherein the second signal path further comprises a direct current, DC blocking capacitor (CDC) operatively connected in series between the input port (Vin) and an input of the second transistor (M2).

10. The low-noise amplifier circuit (200a: 200g) according to claim 9, wherein the second signal path further comprises a bias resistor (RB) operatively connected between the DC blocking capacitor (CDC) and the input of the second transistor (M2).

11. The low-noise amplifier circuit (200a: 200g) according to any preceding claim, wherein the input port (Vin) is arranged to receive the signal either directly from the antenna or indirectly from the antenna via a front-end filter and / or an isolation device in the full-duplex radio transceiver.

12. The low-noise amplifier circuit (200a: 200g) according to any preceding claim, wherein the Self-Interference-Signal control circuit is configured to tune amplitudeand phase of the cancellation current, and wherein the Self-Interference-Signal control circuit is configured to control the amplitude and phase based on the received channel and cross-interference information.

13. The low-noise amplifier circuit (200a: 200g) according to any preceding claim, wherein the Self-Interference-Signal control circuit is configured to control the cancellation circuit (iCi, iC2) in accordance with a calibration procedure performed during operation of the low-noise amplifier circuit (200a: 200g).

14. The low-noise amplifier circuit (200a: 200g) according to any preceding claim, wherein the Self-Interference-Signal control circuit has an analog architecture, a digitally assisted architecture, or a hybrid architecture.

15. The low-noise amplifier circuit (200a: 200g) according to any preceding claim, wherein the channel and cross-interference information is based on any, or any combination, of: an analog-to-digital converted version of the received signal, a digital transmission signal, an analog-to-digital converted version of an analog transmission signal, a digital control signal.

16. A full-duplex transceiver (1100a: liood), the full-duplex transceiver(1100a: liood) comprising a low-noise amplifier circuit (200a: 200g) according to any of the preceding claims.

17. The full-duplex transceiver (1100a: liood) according to claim 16, wherein the full-duplex transceiver (1100a: liood) is a single antenna transceiver, or comprises an antenna array with a circulator at each antenna port, or comprises an antenna array with separate antennas for transmission and reception.

18. The full-duplex transceiver (1100a: liood) according to claim 16 or 17, wherein the full-duplex transceiver (1100a: liood) is configured for time-division duplex communication by having the cancellation circuit (ici, ic2) turned off.

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