Semiconductor chip and semiconductor device

Abstract

Semiconductor chips (1, 2) are overlapped and joined. The semiconductor chip (1) is provided with electrode pads (e11, e12) disposed on a joint surface (J), and a node (P1) for supplying a first voltage to the electrode pads (e11, e12). The semiconductor chip (2) is provided with electrode pads (e21, e22) disposed on the joint surface (J), and a node (P2) for supplying a second voltage to the electrode pads (e21, e22). The electrode pads (e11, e12) and the electrode pads (e21, e22) are arranged in a row in an X direction in a plan view.

Description

Semiconductor chips and semiconductor devices

[0001] The present disclosure relates to a semiconductor device in which semiconductor chips are stacked and bonded.

[0002] Conventionally, a structure in which multiple semiconductor chips are stacked and bonded (3D structure) has been known for semiconductor devices. As the density of elements integrated on semiconductor chips increases and the area of ​​semiconductor chips decreases accordingly, it is expected that 3D structures will be widely used in the future.

[0003] Patent Document 1 discloses a technique for detecting misalignment that occurs when bonding semiconductor chips in a 3D structure of a semiconductor device.

[0004] International Publication No. 2023 / 145329

[0005] Assuming that 3D structures will be widely used in the future, it will be necessary to detect misalignment during bonding of semiconductor chips using simpler and smaller circuits.

[0006] The present disclosure provides a configuration that can detect misalignment during bonding of semiconductor chips using a simpler and smaller circuit in a 3D structure of a semiconductor device.

[0007] One aspect of the present disclosure is a semiconductor chip that is stacked and bonded to another semiconductor chip to form a semiconductor device, comprising: a plurality of electrode pads provided on a bonding surface with the other semiconductor chip; a voltage supply node connected to the plurality of electrode pads and supplied with a first voltage; and detection pads provided for at least some of the plurality of electrode pads for monitoring the potential of the electrode pads from outside the semiconductor chip, wherein the plurality of electrode pads are arranged side by side in a first direction, each electrode pad has the same size in the first direction, and the spacing in the first direction is constant.

[0008] According to this aspect, the semiconductor chip has electrode pads arranged in a first direction on the bonding surface with another semiconductor chip. In the first direction, the electrode pads have the same size and are spaced apart at a constant interval. A first voltage is applied to the electrode pads from a voltage supply node. When this semiconductor chip is overlaid and bonded to another semiconductor chip, the potential of the electrode pads is monitored from the detection pad, thereby making it possible to detect whether the electrode pads are in contact with the electrode pads of the other semiconductor chip. Whether misalignment occurs during bonding of the semiconductor chips can be determined from the contact / non-contact state of the electrode pads.

[0009] According to the present disclosure, in a 3D structure of a semiconductor device, misalignment during bonding of a semiconductor chip can be detected with a simpler and smaller configuration.

[0010] 6A, 6B, and 6C are schematic diagrams of a semiconductor device in which semiconductor chips are stacked and bonded; and FIG. 6A shows an example of a mechanism for detecting misalignment of the bonding of the semiconductor chips in the first embodiment, where (a) is a cross-sectional view and (b) is a top view. The figure shows a state in which misalignment of the bonding has occurred. The figure shows an example of coding the contact / non-contact state of the electrode pads, where (a) shows no misalignment, (b) shows a misalignment to the left, (c) shows a misalignment to the right, and (d) shows a code. An example of a configuration for detecting the contact / non-contact state of the electrode pads is a configuration in which electrode pads are arranged on four sides of a semiconductor chip; (a), (b), and (c) are examples of misalignment in the configuration of FIG. 6; and an example of coding the contact / non-contact state of the electrode pads on each side. In a modified example of the first embodiment, 1 shows an example of arrangement and coding of electrode pads in a modified example of the second embodiment, where (a) shows no misalignment, (b) shows misalignment to the left, (c) shows misalignment to the right, and (d) shows the code rule. 2 shows an example of a mechanism for detecting misalignment of bonding of a semiconductor chip in the second embodiment, where (a) is a cross-sectional view and (b) is a top view. 3 shows an example of coding of the contact / non-contact state of electrode pads, where (a) shows misalignment to the left, (b) shows misalignment to the right, and (c) shows the code rule. 4 shows an example of arrangement and coding of electrode pads in a modified example of the second embodiment, where (a) shows no misalignment, (b) shows misalignment to the left, (c) shows misalignment to the right, and (d) shows the code rule.

[0011] Hereinafter, embodiments will be described with reference to the drawings. In this specification, the term "plan view" refers to a view of a semiconductor chip or the like from a direction perpendicular to the surface of the semiconductor chip.

[0012] 1 shows an example of the configuration of a semiconductor device according to the present disclosure. The semiconductor device 100 is configured by stacking and bonding a semiconductor chip 1 and a semiconductor chip 2. The semiconductor chips 1 and 2 are bonded with their wiring layers facing each other.

[0013] (First embodiment) Figure 2 is a diagram showing an example of the configuration of a mechanism for detecting misalignment of semiconductor chip bonding in the first embodiment. Figure 2(a) is a cross-sectional view showing an outline of the bonding state of semiconductor chips 1 and 2 and the detection circuit, and (b) is a top view showing an outline of the bonding state of semiconductor chips 1 and 2. Figure 2(a) shows a cross section taken along line II in Figure 2(b).

[0014] The semiconductor chip 1 includes a wiring layer 1a and a substrate layer 1b. The semiconductor chip 2 includes a wiring layer 2a and a substrate layer 2b. The semiconductor chips 1 and 2 are bonded together at a bonding surface J, with the wiring layer 1a and the wiring layer 2a facing each other.

[0015] The semiconductor chip 1 has electrode pads e11 and e12 in the wiring layer 1a that are exposed at the bonding surface J. The electrode pads e11 and e12 are arranged in a row along the side E. The direction along the side E is the X-axis direction, and the direction perpendicular to this is the Y-axis direction. The direction perpendicular to the semiconductor chip surface is the Z-axis direction. The planar shape of the electrode pads e11 and e12 is a rectangle with a width (size in the X-axis direction) w1 and a length (size in the Y-axis direction) l1. The distance between the electrode pads e11 and e12 is d1.

[0016] The semiconductor chip 2 has electrode pads e21 and e22 in the wiring layer 2a that are exposed on the bonding surface J. The electrode pads e21 and e22 are arranged in a row along the side E. The planar shape of the electrode pads e21 and e22 is a rectangle with a width w2 and a length l2. The distance between the electrode pads e21 and e22 is d2. In FIG. 2, the relationship is w1 + d1 = w2 + d2.

[0017] As will be described later, the number of electrode pads arranged on the semiconductor chip may be three or more. The number of electrode pads arranged on the semiconductor chip 1 may differ from that on the semiconductor chip 2.

[0018] 2, the electrode pads e11 and e12 of the semiconductor chip 1 and the electrode pads e21 and e22 of the semiconductor chip 2 are alternately arranged in a line in the X-axis direction in a plan view. That is, the electrode pad e11 is arranged between the electrode pads e21 and e22, and the electrode pad e22 is arranged between the electrode pads e11 and e12. The electrode pad e11 is not in contact with the electrode pads e21 and e22 (w1<d2). The electrode pad e22 is not in contact with the electrode pads e11 and e12 (w2<d1). When there is no misalignment in the bonding of the semiconductor chips, the position of the center point a of the electrode pad e11 coincides with the position of the midpoint b of the electrode pads e21 and e22 in the X-axis direction.

[0019] In semiconductor chip 1, voltage supply node P1 is connected to electrode pads e11 and e12 via resistor R1. In semiconductor chip 2, voltage supply node P2 is connected to electrode pads e21 and e22 via resistor R2. The resistors R1 and R2 are connected to prevent damage caused by a short circuit current flowing between the voltage supply nodes when the electrode pads of both semiconductor chips 1 and 2 come into contact. The resistance values ​​of resistors R1 and R2 should be designed to a value that does not cause damage.

[0020] 2, the operation of detecting misalignment of the bonding of the semiconductor chips 1 and 2 will be described. In this embodiment, contact or non-contact between the electrode pads of the semiconductor chip 1 and the electrode pads of the semiconductor chip 2 is detected, thereby detecting misalignment of the bonding of the semiconductor chips 1 and 2.

[0021] As shown in Figure 3, voltages are supplied to voltage supply nodes P1 and P2. Here, a reference voltage (GND) is supplied to voltage supply node P2, and a high voltage (VDD) is supplied to voltage supply node P1. Alternatively, the opposite may be true, with VDD supplied to voltage supply node P2 and GND supplied to voltage supply node P1. Note that the supply of voltages to voltage supply nodes P1 and P2 may be performed by providing dedicated supply terminals on the semiconductor chip. Alternatively, the supply terminals for the power supply voltage may be shared with other circuits within the semiconductor chip.

[0022] 2(a) shows a state in which misalignment has occurred in the bonding of semiconductor chips 1 and 2. In Fig. 3, because the bonding of semiconductor chips 1 and 2 has been misaligned in the X-axis direction, electrode pad e11 of semiconductor chip 1 is in contact with electrode pad e21 of semiconductor chip 2, and electrode pad e12 of semiconductor chip 1 is in contact with electrode pad e22 of semiconductor chip 2.

[0023] When the electrode pads e11 and e12 of the semiconductor chip 1 are not in contact with the electrode pads e21 and e22 of the semiconductor chip 2, the potential of the electrode pads e11 and e12 of the semiconductor chip 1 is VDD, and the potential of the electrode pads e21 and e22 of the semiconductor chip 2 is GND. On the other hand, in the state shown in Figure 3, the potential of the electrode pads e11 and e12 of the semiconductor chip 1 and the electrode pads e21 and e22 of the semiconductor chip 2 is an intermediate potential between VDD and GND. Therefore, by detecting the potential of an electrode pad, it is possible to detect whether or not the electrode pad in question is in contact with the electrode pads of another semiconductor chip.

[0024] 4 shows an example of coding the contact / non-contact state of the electrode pads of the semiconductor chip 1. Here, when the potential of the electrode pad is VDD, it is set to "1", and when the potential of the electrode pad is an intermediate potential between VDD and GND, it is set to "0". That is, "1" indicates a non-contact state where there is no contact with the electrode pad of the semiconductor chip 2, and "0" indicates a contact state where there is contact with the electrode pad of the semiconductor chip 2. Then, a 2-bit code is generated in which the state of electrode pad e11 is set to the upper bit and the state of electrode pad e12 is set to the lower bit.

[0025] As shown in Fig. 4(a), when there is no misalignment between the semiconductor chips 1 and 2, the electrode pads e11 and e12 are both out of contact, resulting in a code of "11." As shown in Fig. 4(b), when the semiconductor chip 1 is misaligned to the left in the drawing relative to the semiconductor chip 2, the electrode pads e11 and e12 are both in contact, resulting in a code of "00." As shown in Fig. 4(c), when the semiconductor chip 1 is misaligned to the right in the drawing relative to the semiconductor chip 2, the electrode pad e11 is in contact and the electrode pad e12 is in a non-contact state, resulting in a code of "01."

[0026] From the above, we can obtain the code rule shown in Figure 4(d). That is, when the upper bit is "1", it can be determined that there is no misalignment, and when it is "0", there is a misalignment (A). Furthermore, when there is a misalignment, the direction of the misalignment can be determined based on the lower bit (B). That is, when the upper bit is "0", it can be determined that there is a misalignment to the left when the lower bit is "0", and that there is a misalignment to the right when the lower bit is "1".

[0027] The electrode pads of the semiconductor chip 2 can also be coded and determined in the same manner.

[0028] Fig. 5 shows an example of a configuration for detecting the contact / non-contact state of electrode pads. In Fig. 5, detection pads TP11 and TP12 are provided for electrode pads e11 and e12, respectively, on semiconductor chip 1. The potentials of electrode pads e11 and e12 can be monitored from outside semiconductor chip 1 via the detection pads TP11 and TP12. On semiconductor chip 2, detection pads TP21 and TP22 are provided for electrode pads e21 and e22, respectively. The potentials of electrode pads e21 and e22 can be monitored from outside semiconductor chip 2 via the detection pads TP21 and TP22. The detection pads are arranged in the same manner as signal pads that transmit and receive signals to and from the outside of the semiconductor chip.

[0029] To detect the state of the electrode pads e11 and e12 of the semiconductor chip 1, the probes T1 and T2 are brought into contact with the detection pads TP11 and TP12 to detect their potential, and a tester (testing device) determines whether the code is "1" or "0." Alternatively, a buffer circuit may be provided between the electrode pads e11 and e12 and the detection pads TP11 and TP12, so that a high or low logic level is output to the detection pads TP11 and TP12.

[0030] Similarly, to detect the state of the electrode pads e21 and e22 of the semiconductor chip, the probes are brought into contact with the detection pads TP21 and TP22 to detect their potential or logic level. Although Fig. 5 shows a configuration in which detection pads are provided for all the electrode pads, detection pads may be provided only for some of the electrode pads, for example, for electrode pads that measure potential and detect codes.

[0031] 6 shows a configuration in which electrode pads are arranged on the four sides of a semiconductor chip. e1x is an electrode pad arranged on semiconductor chip 1, and e2x is an electrode pad arranged on semiconductor chip 2 (x is an integer from 1 to 8). Semiconductor chips 1 and 2 have two electrode pads arranged on each side. In a plan view, the electrode pads of semiconductor chip 1 and the electrode pads of semiconductor chip 2 are arranged alternately in a row on each side.

[0032] FIG. 7 shows an example of misalignment in the configuration shown in FIG. 6 . In FIG. 7( a), semiconductor chip 1 is misaligned to the right relative to semiconductor chip 2 (pattern A). In this case, misalignment can be detected by the contact / non-contact of the electrode pads arranged on the first and third sides. In FIG. 7( b), semiconductor chip 1 is misaligned to the top relative to semiconductor chip 2 (pattern B). In this case, misalignment can be detected by the contact / non-contact of the electrode pads arranged on the second and fourth sides. In FIG. 7( c), semiconductor chip 1 is misaligned by rotating to the right relative to semiconductor chip 2 (pattern C). In this case, misalignment can be detected by the contact / non-contact of the electrode pads arranged on the first to fourth sides. Note that the contact / non-contact states of the electrode pads shown in FIG. 7 are merely examples, and the contact / non-contact states of the electrode pads may change depending on, for example, the degree of misalignment.

[0033] Figure 8 shows the coded state of the electrode pads on each side in the configuration of Figure 6 and the misalignment of Figure 7. In the configuration of Figure 6, there is no misalignment, and all of the electrode pads on the semiconductor chip 1 are in a non-contact state, so the first to fourth sides are all "11".

[0034] 7A, the electrode pad e11 is in contact with the first side, resulting in "01." The electrode pads e15 and e16 are in contact with the third side, resulting in "00." That is, when the second and fourth sides are "11," the lower-order bit of the first side is "1," and the lower-order bit of the third side is "0," it is possible to detect the occurrence of a positional deviation in the positive direction of the X axis (toward the right in the drawing).

[0035] 7B, the electrode pads e13 and e14 are in contact with each other on the second side, resulting in a value of "00." Also, the electrode pad e17 is in contact with each other on the fourth side, resulting in a value of "01." That is, when the first and third sides are "11," the lower-order bit of the second side is "0," and the lower-order bit of the fourth side is "1," it is possible to detect that a misalignment has occurred in the positive direction of the Y axis (upward in the drawing).

[0036] 7(c), the electrode pad e11 on the first side, the electrode pad e13 on the second side, the electrode pad e15 on the third side, and the electrode pad e17 on the fourth side are in contact with each other, so the first to fourth sides are "01." That is, when the upper bits of all of the first to fourth sides are "0" and the lower bits are "1," it is possible to detect that a positional deviation has occurred in the right rotation direction (clockwise direction).

[0037] According to this embodiment, misalignment during bonding of semiconductor chips can be detected with a simple and small-scale configuration. Furthermore, by displaying the misalignment as a code, it becomes easier to grasp the tendency of misalignment, and therefore the accuracy of alignment can be easily improved. Furthermore, by making the relationship between the spacing and width of the electrode pads between semiconductor chips uniform, a simple regularity can be obtained when extracting codes from the electrode pads of any semiconductor chip. Furthermore, by complying with this relationship, the number of semiconductor chips that can be bonded can be increased.

[0038] For example, for semiconductor devices that fail inspection, the state of misalignment of the semiconductor chip bonding can be detected using a code, and the bonding can be corrected based on the code and re-inspected. Furthermore, if re-inspection is not possible, the bonding positions of subsequent semiconductor chips can be adjusted based on the code. Furthermore, by aggregating the detected codes and understanding the tendency of misalignment, the accuracy of semiconductor chip alignment can be improved.

[0039] (Modification) In the above-described embodiment, two electrode pads are arranged along the sides of the semiconductor chips 1 and 2, but three or more electrode pads may be arranged.

[0040] 9 shows an example in which three electrode pads are arranged on each of semiconductor chips 1 and 2. Electrode pads e11, e12, and e13 are provided on semiconductor chip 1, and electrode pads e21, e22, and e23 are provided on semiconductor chip 2. The coding method is the same as in the above-described embodiment. A 3-bit code is assigned to electrode pads e11, e12, and e13.

[0041] As shown in Fig. 9(a), when there is no misalignment, the electrode pads e11, e12, and e13 are all in a non-contact state, resulting in a code of "111." As shown in Fig. 9(b), when the semiconductor chip 1 is misaligned to the left in the drawing relative to the semiconductor chip 2, the electrode pads e11, e12, and e13 are all in a contact state, resulting in a code of "000." As shown in Fig. 9(c), when the semiconductor chip 1 is misaligned to the right in the drawing relative to the semiconductor chip 2, the electrode pads e11 and e12 are in a contact state, and the electrode pad e13 is in a non-contact state, resulting in a code of "001."

[0042] From the above, we can obtain the code rule shown in Figure 9(d). That is, when the most significant bit is "1", it can be determined that there is no misalignment, and when it is "0", it can be determined that there is a misalignment (A). Furthermore, when the most significant bit is "0", the direction of the misalignment can be determined by the least significant bit (B). That is, when the least significant bit is "0", it can be determined that there is a misalignment to the left, and when it is "1", it can be determined that there is a misalignment to the right.

[0043] The electrode pads of the semiconductor chip 2 can also be coded and determined in the same manner.

[0044] As can be seen from this modification, even if the number of electrode pads is changed, a simple regularity can be obtained for the codes representing the states of the electrode pads, as in the above embodiment. Therefore, it is easier to grasp the tendency of misalignment, and the accuracy of alignment can be easily improved.

[0045] Second Embodiment In a second embodiment, a configuration will be described in which the semiconductor chip 1 and the semiconductor chip 2 have different numbers of electrode pads in the mechanisms for detecting misalignment of bonding.

[0046] 10A and 10B are diagrams showing an example of the configuration of a mechanism for detecting misalignment of semiconductor chip bonding in the second embodiment, in which Fig. 10A is a cross-sectional view showing an outline of the bonding state of semiconductor chips 1 and 2 and the detection circuit, and Fig. 10B is a top view showing an outline of the bonding state of semiconductor chips 1 and 2.

[0047] The semiconductor chip 1 has five electrode pads e31, e32, e33, e34, and e35 in the wiring layer 1a that are exposed on the bonding surface J. The electrode pads e31, e32, e33, e34, and e35 are arranged in a line in the X-axis direction. The planar shape of the electrode pads e31, e32, e33, e34, and e35 is a rectangle with a width w1. The spacing between the electrode pads e31, e32, e33, e34, and e35 is d1.

[0048] The semiconductor chip 2 has electrode pads e21 and e22 in the wiring layer 2a that are exposed on the bonding surface J. The electrode pads e21 and e22 are arranged in a line in the X-axis direction. The planar shape of the electrode pads e21 and e22 is a rectangle with a width w2. The distance between the electrode pads e21 and e22 is d2.

[0049] The electrode pads e31, e32, e33, e34, and e35 of the semiconductor chip 1 have smaller widths and intervals than the electrode pads e21 and e22 of the semiconductor chip 2. That is, there is a relationship of w1<w2 and d1<d2.

[0050] In Figure 10, electrode pad e33 of semiconductor chip 1 is disposed between electrode pads e21 and e22 of semiconductor chip 2. Electrode pad e33 is not in contact with electrode pads e21 and e22 (w1<d2). If there is no misalignment between the semiconductor chips 1 and 2, the position of center point a of electrode pad e33 coincides with the position of midpoint b between electrode pads e21 and e22 in the X-axis direction. Electrode pads e31 and e32 of semiconductor chip 1 are in contact with electrode pad e21 of semiconductor chip 2. Electrode pads e34 and e35 of semiconductor chip 1 are in contact with electrode pad e22 of semiconductor chip 2. Therefore, as shown in Figure 10(b), if there is no misalignment, the code will be "00100".

[0051] 11(a) shows a state in which the semiconductor chip 1 is displaced to the left of the drawing relative to the semiconductor chip 2 in FIG. 10(b). As shown in FIG. 11(a), when a small displacement occurs and the electrode pad e34 is in a non-contact state, the code becomes "00110." When a large displacement occurs and the electrode pad e33 is in a contact state, the code becomes "00010." When an even larger displacement occurs and the electrode pad e35 is in a non-contact state, the code becomes "00011."

[0052] 11(b) shows a state in which the semiconductor chip 1 is displaced to the right in the drawing relative to the semiconductor chip 2 in FIG. 10(b). As shown in FIG. 11(b), when a small displacement occurs and the electrode pad e32 is in a non-contact state, the code becomes "01100." When a large displacement occurs and the electrode pad e33 is in a contact state, the code becomes "01000." When an even larger displacement occurs and the electrode pad e31 is in a non-contact state, the code becomes "11000."

[0053] From the above, the rule shown in Figure 11(c) can be obtained. That is, when the third bit (electrode pad e33) is "0," it can be determined that there is a positional deviation (A). Furthermore, when the third bit is "1" and the second bit (electrode pad e32) is "1," it can be determined that there is a rightward deviation (B). Furthermore, when the third bit is "1" and the fourth bit (electrode pad e34) is "1," it can be determined that there is a leftward deviation (C). In this way, a rightward deviation can be detected by a code change in electrode pad e32, and a leftward deviation can be detected by a code change in electrode pad e34, so the detection accuracy is higher than when determining the code of electrode pad e33 alone.

[0054] Fig. 12 shows an example of a configuration for detecting the state of an electrode pad. In Fig. 12, detection pads TP31, TP32, TP33, TP34, and TP35 are provided for electrode pads e31, e32, e33, e34, and e35 on a semiconductor chip 1, respectively. The potentials of electrode pads e31, e32, e33, e34, and e35 are output to detection pads TP31, TP32, TP33, TP34, and TP35, respectively. The detection pads are arranged in the same manner as signal pads that transmit and receive signals to and from the outside of the semiconductor chip.

[0055] As in the first embodiment, when detecting the states of the electrode pads e31, e32, e33, e34, and e35 of the semiconductor chip 1, probes are brought into contact with the detection pads TP31, TP32, TP33, TP34, and TP35 to detect their potentials, and a tester (testing device) determines the code "1" or "0." Alternatively, buffer circuits may be provided between the electrode pads e31, e32, e33, e34, and e35 and the detection pads TP31, TP32, TP33, TP34, and TP35, so that a high or low logic level is output to the detection pads TP31, TP32, TP33, TP34, and TP35.

[0056] Although FIG. 12 shows a configuration in which detection pads are provided for all electrode pads, detection pads may be provided only for electrode pads that measure potential and detect codes.

[0057] According to this embodiment, misalignment during bonding of semiconductor chips can be detected with a simple and small-scale configuration, as in the first embodiment. Furthermore, even if the number, shape, spacing, etc. of electrode pads arranged on the semiconductor chips differ between semiconductor chips, the misalignment detection accuracy and alignment accuracy can be improved to the same extent as in the first embodiment or even more.

[0058] (Modification) In the above embodiment, the semiconductor chip 1 is provided with five electrode pads. In this modification, the semiconductor chip 1 is provided with four electrode pads.

[0059] 13 shows an example in which four electrode pads are arranged on a semiconductor chip 1. Electrode pads e41, e42, e43, and e44 are provided on the semiconductor chip 1. In FIG. 13, the electrode pads e42 and e43 of the semiconductor chip 1 are arranged between the electrode pads e21 and e22 of the semiconductor chip 2. The electrode pads e42 and e43 are not in contact with the electrode pads e21 and e22. If there is no misalignment in the bonding position of the semiconductor chips 1 and 2, the position of the midpoint a between the electrode pads e42 and e43 in the X-axis direction coincides with the position of the midpoint b between the electrode pads e21 and e22.

[0060] As shown in Fig. 13(a), when there is no misalignment, the code is "0110." As shown in Fig. 13(b), when the semiconductor chip 1 is misaligned to the left in the drawing and the electrode pad e42 comes into contact with the electrode pad e21, the code is "0010." As shown in Fig. 13(c), when the semiconductor chip 1 is misaligned to the right in the drawing and the electrode pad e43 comes into contact with the electrode pad e22, the code is "1100."

[0061] From the above, the rule shown in Figure 13(d) can be obtained. That is, when the second and third bits (electrode pads e42 and e43) are both "1", it can be determined that there is no positional deviation. When the second bit is "0", it can be determined that there is a leftward deviation (A). When the third bit is "0", it can be determined that there is a rightward deviation (B).

[0062] As can be seen from this modification, even if the number of electrode pads is changed, a simple regularity can be obtained for the codes representing the states of the electrode pads, as in the above embodiment. Therefore, it is easier to grasp the tendency of misalignment, and the accuracy of alignment can be easily improved.

[0063] The present disclosure makes it possible to detect misalignment during bonding in a semiconductor device in which semiconductor chips are stacked and bonded using a simple and small-scale configuration, which is useful, for example, for miniaturizing semiconductor devices and improving yields.

[0064] 1, 2 Semiconductor chip 100 Semiconductor device e11, e12, e13, e14, e15, e16, e17, e18 Electrode pads e21, e22, e23, e24, e25, e26, e27, e28 Electrode pads e31, e32, e33, e34, e35 Electrode pads e41, e42, e43, e44 Electrode pads P1, P2 Voltage supply nodes TP11, TP12, TP21, TP22 Detection pads TP31, TP32, TP33, TP34, TP35 Detection pads J Bonding surface

Claims

1. A semiconductor chip that is stacked and bonded with another semiconductor chip to form a semiconductor device, comprising: a plurality of electrode pads provided on the bonding surface with the other semiconductor chip; a voltage supply node connected to the plurality of electrode pads and supplied with a first voltage; and detection pads provided for at least some of the plurality of electrode pads and for monitoring the potential of the electrode pads from outside the semiconductor chip, wherein the plurality of electrode pads are arranged side by side in a first direction, each electrode pad has the same size in the first direction, and the spacing in the first direction is constant.

2. A semiconductor chip according to claim 1, comprising: a plurality of second electrode pads provided on the bonding surface and connected to the voltage supply node; and second detection pads provided for at least some of the second electrode pads for monitoring the potential of the second electrode pads from outside the semiconductor chip, wherein the second electrode pads are arranged side by side in a second direction different from the first direction, the size of each electrode pad in the second direction is the same, and the spacing in the second direction is constant.

3. A semiconductor device in which a first semiconductor chip and a second semiconductor chip are bonded together, wherein the first semiconductor chip comprises: a plurality of first electrode pads provided on a bonding surface with the second semiconductor chip; a first voltage supply node connected to the plurality of first electrode pads and supplied with a first voltage; and first detection pads provided for at least some of the plurality of first electrode pads and for monitoring the potential of the first electrode pads from outside the first semiconductor chip, the plurality of first electrode pads being aligned in a first direction, each having the same size in the first direction and a constant interval in the first direction; and the second semiconductor chip comprises: a plurality of second electrode pads provided on a bonding surface with the first semiconductor chip; a second voltage supply node connected to the plurality of second electrode pads and supplied with a second voltage different from the first voltage; and second detection pads provided for at least some of the plurality of second electrode pads and for monitoring the potential of the second electrode pads from outside the second semiconductor chip. the plurality of second electrode pads are arranged in the first direction, the size of each second electrode pad in the first direction is the same, and the spacing between the second electrode pads in the first direction is constant; and the plurality of first electrode pads and the plurality of second electrode pads are arranged in a line in the first direction in a plan view.

4. A semiconductor device according to claim 3, wherein the size of the first electrode pad in the first direction is smaller than the spacing between the plurality of second electrode pads in the first direction.

5. A semiconductor device according to claim 4, wherein the sum of the size of the first electrode pad in the first direction and the spacing between the plurality of first electrode pads in the first direction is equal to the sum of the size of the second electrode pad in the first direction and the spacing between the plurality of second electrode pads in the first direction.

6. A semiconductor device according to claim 3, wherein the first detection pad provided for the first electrode pad that is not in contact with the second electrode pad outputs the first voltage, and the first detection pad provided for the first electrode pad that is in contact with the second electrode pad outputs a third voltage that is a voltage between the first voltage and the second voltage.

7. A semiconductor device according to claim 3, wherein the first semiconductor chip comprises: a plurality of third electrode pads provided on a bonding surface with the second semiconductor chip and connected to the first voltage supply node; and third detection pads provided for at least some of the third electrode pads for monitoring the potential of the third electrode pads from outside the first semiconductor chip, the third electrode pads being aligned in a second direction different from the first direction, the size of each electrode pad in the second direction being the same, and the spacing in the second direction being constant; the second semiconductor chip comprises: a plurality of fourth electrode pads provided on a bonding surface with the first semiconductor chip and connected to the second voltage supply node; and fourth detection pads provided for at least some of the fourth electrode pads for monitoring the potential of the fourth electrode pads from outside the second semiconductor chip, the fourth electrode pads being aligned in the second direction, the size of each electrode pad in the second direction being the same, and the spacing in the second direction being constant; the third electrode pads and the fourth electrode pads are aligned in a line in the second direction in a plan view.

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