Testing apparatus, testing method, and program

Abstract

The present invention provides a testing apparatus comprising: a reception unit that receives a reception signal sequence including a pseudorandom signal sequence output by a device under test; and a detection unit that detects whether a pseudorandom signal generator that generated the pseudorandom signal sequence within the reception signal sequence was in a prohibited state. The present invention also provides a testing apparatus comprising: a reception unit that receives a reception signal sequence including a pseudorandom signal sequence output by a device under test; an expected-value generation unit that generates an expected-value signal sequence including a pseudorandom signal sequence that is the same as the pseudorandom signal sequence to be output by the device under test; and a detection unit that detects whether a pseudorandom signal generator that generated the pseudorandom signal sequence included in the expected-value signal sequence and / or the reception signal sequence was in a prohibited state.

Description

Testing device, testing method, and program

[0001] The present invention relates to a test device, a test method, and a program.

[0002] In testing a device under test, the quality of the device under test may be determined depending on whether a pseudo-random signal sequence output from the device under test matches an expected signal sequence. General disclosure

[0003] A first aspect of the present invention provides a test apparatus comprising: a receiving section that receives a received signal sequence including a pseudo-random signal sequence output by a device under test; and a detecting section that detects whether a pseudo-random signal generator that generated the pseudo-random signal sequence in the received signal sequence was in a prohibited state.

[0004] In the above test apparatus, the detecting section may detect the inhibited state when a ratio of a predetermined signal value in a pseudo-random signal sequence within the received signal sequence falls outside a reference range.

[0005] Any of the above test apparatuses may include an expected value generating section that generates an expected value signal sequence including a pseudo-random signal sequence that is the same as the pseudo-random signal sequence to be output by the device under test, and a comparing section that compares the pseudo-random signal sequence in the received signal sequence with the pseudo-random signal sequence in the expected value signal sequence.

[0006] Any of the above test devices may include a result determining section that determines a test result based on the comparison result by the comparing section and the detection result by the detecting section.

[0007] Any of the above test apparatuses may include a setting section that uses a portion of a pseudo-random signal sequence in the received signal sequence to set a random number seed for the pseudo-random signal sequence in the expected value signal sequence generated by the expected value generator.

[0008] In any of the above test devices, the detecting section may change the reference range in accordance with the number of bits in a shift register of a pseudorandom signal generator that generates the pseudorandom signal sequence in the received signal sequence.

[0009] In a second aspect of the present invention, a test apparatus is provided that includes a receiving section that receives a received signal sequence including a pseudo-random signal sequence output by a device under test, an expected value generating section that generates an expected signal sequence including a pseudo-random signal sequence that is the same as the pseudo-random signal sequence that should be output by the device under test, and a detecting section that detects whether a pseudo-random signal generator that generated a pseudo-random signal sequence included in at least one of the expected signal sequence or the received signal sequence was in a prohibited state.

[0010] In a third aspect of the present invention, there is provided a testing method comprising receiving a received signal sequence including a pseudo-random signal sequence output by a device under test, and detecting whether a pseudo-random signal generator that generated the pseudo-random signal sequence in the received signal sequence was in a disabled state.

[0011] In a fourth aspect of the present invention, there is provided a testing method comprising: receiving a received signal sequence including a pseudo-random signal sequence output by a device under test; generating an expected signal sequence including a pseudo-random signal sequence identical to the pseudo-random signal sequence to be output by the device under test; and detecting whether a pseudo-random signal generator that generated the pseudo-random signal sequence included in at least one of the expected signal sequence or the received signal sequence was in a prohibited state.

[0012] In a fifth aspect of the present invention, there is provided a program that is executed by a computer and causes the computer to function as a detection unit that detects whether a pseudo-random signal generator that generated a pseudo-random signal sequence included in at least one of a received signal sequence including a pseudo-random signal sequence output by a device under test, or an expected signal sequence including a pseudo-random signal sequence identical to the pseudo-random signal sequence that should be output by the device under test, was in a prohibited state.

[0013] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions.

[0014] 1 shows the configuration of the test apparatus 100 according to the present embodiment together with the DUT 10. FIG. 2 shows an example of the configuration of the setting section 120 and the expected value generating section 130 according to the present embodiment. FIG. 3 shows an example of the configuration of the detection section 150 according to the present embodiment. FIG. 4 shows an example of a reference range according to the present embodiment. FIG. 5 shows a test flow using the test apparatus 100 according to the present embodiment. FIG. 6 shows an example of a computer 2200 in which multiple aspects of the present invention may be embodied in whole or in part.

[0015] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0016] 1 shows the configuration of a test apparatus 100 according to this embodiment together with a DUT 10 (Device Under Test 10, also referred to as "Device Under Test 10"). The DUT 10 includes a transmitting section 20. The transmitting section 20 outputs a signal generated inside the DUT 10 to another device or the like via a wired or wireless connection. In this embodiment, the transmitting section 20 outputs a 1-bit serial signal to the outside of the DUT 10 every cycle. Alternatively, the transmitting section 20 may output a multi-bit parallel signal to the outside of the DUT 10 every cycle.

[0017] The DUT 10 may include a pseudorandom signal generator 30. The pseudorandom signal generator 30 may be a PRBS generator that generates a pseudorandom signal sequence such as a PRBS (Pseudo Random Binary Sequence), and supplies the generated pseudorandom signal sequence to the transmitting section 20. The pseudorandom signal generator 30 may generate a pseudorandom signal sequence to be included in a signal that the transmitting section 20 outputs to the outside of the DUT 10 during testing of the DUT 10.

[0018] In addition to the transmitting section 20 and the pseudo-random signal generator 30, the DUT 10 may include a receiving section that receives signals from outside, a processing section that performs arithmetic processing or signal processing in accordance with the received signals and the internal state of the DUT 10, or various other circuits. In this specification, attention is focused on the configuration in which the test apparatus 100 tests the DUT 10 by inspecting the signals output by the DUT 10, and therefore illustrations and descriptions of the configuration other than the transmitting section 20 and the pseudo-random signal generator 30 are omitted.

[0019] The test apparatus 100 is connected to the DUT 10 and tests the DUT 10. The test apparatus 100 includes a receiving section 110, a setting section 120, an expected value generating section 130, a comparing section 140, a detecting section 150, a result determining section 160, and a control section 170.

[0020] The receiving unit 110 is connected to the DUT 10 so as to be able to receive signals transmitted from the transmitting unit 20. The receiving unit 110 receives a received signal sequence including a pseudo-random signal sequence output by the DUT 10. Here, a "signal sequence" refers to a sequence (sequence) of signal values ​​for multiple cycles, including one signal value per cycle (or one signal period). The DUT 10 may output the pseudo-random signal sequence directly from its terminal (or antenna in the case of a wireless connection). In this case, the receiving unit 110 receives the pseudo-random signal sequence itself output by the DUT 10 as the received signal sequence. Alternatively, the DUT 10 may output a signal sequence such as a packet including a pseudo-random signal sequence in a specific field, such as a data section, from its terminal or the like. In this case, the receiving unit 110 receives a signal sequence such as a packet including the pseudo-random signal sequence output by the DUT 10 in a specific field as the received signal sequence.

[0021] The setting section 120 is connected to the receiving section 110. The setting section 120 sets a random number seed for a pseudo-random signal sequence in the expected value generating section 130, which is capable of generating an expected value signal sequence including a pseudo-random signal sequence that is the same as the pseudo-random signal sequence included in the received signal sequence. The setting section 120 may use a part of the pseudo-random signal sequence in the received signal sequence to set in the expected value generating section 130 a random number seed for the pseudo-random signal sequence in the expected value signal sequence generated by the expected value generating section 130.

[0022] The expected value generating section 130 is connected to the setting section 120. The expected value generating section 130 uses the random number seed of the pseudo-random signal sequence set by the setting section 120 to generate an expected signal sequence including a pseudo-random signal sequence that is the same as the pseudo-random signal sequence to be output by the DUT 10. If the signal sequence output by the DUT 10 is a packet or the like that includes a field other than the pseudo-random signal sequence, the expected value generating section 130 may generate an expected signal sequence by adding a field such as a packet header to the pseudo-random signal sequence in accordance with the format of the signal sequence output by the transmitting section 20.

[0023] The comparing section 140 is connected to the receiving section 110 and the expected value generating section 130. The comparing section 140 compares the received signal sequence with the expected signal sequence. The comparing section 140 may compare the pseudo-random signal sequence in the received signal sequence with the pseudo-random signal sequence in the expected signal sequence.

[0024] The detector 150 is connected to the receiver 110. It detects whether the pseudo-random signal generator 30 that generated the pseudo-random signal sequence in the received signal sequence was in a prohibited state. A pseudo-random signal generator such as the pseudo-random signal generator 30 normally outputs a pseudo-random signal sequence whose signal value changes randomly (or changes in a manner that can be considered random) from cycle to cycle. However, when the internal state of the pseudo-random signal generator becomes special, it always outputs the same value and becomes unable to output a pseudo-random signal sequence. This state in which the pseudo-random signal generator is unable to output a pseudo-random signal sequence is referred to as a "prohibited state."

[0025] The result determining section 160 is connected to the comparing section 140 and the detecting section 150. The result determining section 160 determines the test result based on the comparison result by the comparing section 140 and the detection result by the detecting section 150.

[0026] The control unit 170 is connected to each unit within the test apparatus 100. The control unit 170 may be a computer such as a PC (personal computer), a workstation, a server computer, or a general-purpose computer, or may be a computer system in which multiple computers are connected. Such a computer system is also considered a computer in a broad sense. The control unit 170 may also be implemented as one or more virtual computer environments executable within a computer. Alternatively, the control unit 170 may be a dedicated computer designed for the test apparatus 100, or may be dedicated hardware realized by dedicated circuitry.

[0027] The control unit 170 controls the various units (receiving unit 110, ..., result determining unit 160, etc.) in the test apparatus 100 to control the test of the DUT 10. The control unit 170 may execute a test program created by an engineer for testing the DUT 10, and control the various units in the DUT 10 in accordance with the contents described in the test program, thereby controlling the test of the DUT 10 in accordance with the contents described in the test program.

[0028] The test apparatus 100 according to this embodiment compares an output signal sequence including a pseudo-random signal sequence output from the DUT 10 with an expected signal sequence, thereby making it possible to test internal circuits of the DUT 10, including the transmitter 20 within the DUT 10. Here, since a random number seed is set in the expected value generating section 130 using a pseudo-random signal sequence included in a received signal sequence, if the pseudo-random signal generator 30 is disabled, the pseudo-random signal generator within the expected value generating section 130 will also be disabled. In this case, both the pseudo-random signal sequence included in the received signal and the pseudo-random signal sequence included in the expected signal sequence will always have the same fixed value, leading to a determination that the received signal sequence and the expected signal sequence match.

[0029] According to the test apparatus 100 of this embodiment, the detection section 150 detects whether the pseudo-random signal generator 30 is in a prohibited state. Even if the comparison section 140 determines that the received signal sequence and the expected signal sequence match, it is possible to determine whether there is an abnormality in the DUT 10 itself, an abnormality in the connection between the DUT 10 and the test apparatus 100, or an abnormality in another test, in response to the detection of the prohibited state of the pseudo-random signal generator 30.

[0030] FIG. 2 shows an example of the configuration of the setting unit 120 and the expected value generating unit 130 according to this embodiment. The expected value generating unit 130 has a pseudo-random signal generator including a shift register composed of multiple cascaded flip-flops (D-FFs, etc.) or latches, and a circuit including one or more exclusive OR (XOR) elements that calculates the outputs of two or more D-FFs and feeds the results back to the D-FF in the first stage of the shift register. The expected value generating unit 130 in this figure has an N-bit shift register, and the N stages of flip-flops included in the shift register take values ​​B[N-1] to B[0] (also referred to as B[N-1:0]) from downstream. The flip-flop in the most downstream stage of the shift register outputs the signal value B[N-1] as the next signal value in the pseudo-random signal sequence every clock cycle.

[0031] A feedback circuit including multiple exclusive ORs (XORs) calculates the next value to be input to the shift register based on the value B[N-1:0] output by two or more D-FFs. The arithmetic expression of the feedback circuit is determined in advance so that the signal sequence output by the expected value generating unit 130 can be regarded as pseudo-random numbers.

[0032] This pseudo-random signal generator operates, for each clock cycle, to output the signal values ​​stored in the multiple D-FFs of the shift register in order from downstream to upstream, while replenishing the first-stage D-FF with the next signal value generated by the feedback circuit. If the received signal sequence includes a field other than a pseudo-random signal sequence, the pseudo-random signal generator 30 and the pseudo-random signal generator in the expected value generating unit 130 may stop inputting a clock to stop generating pseudo-random numbers during the transmission period of such a field, or may continue inputting a clock even during the transmission period of such a field to generate pseudo-random numbers for the same number of clock cycles.

[0033] If the received signal sequence may include fields other than the pseudo-random signal sequence, the expected value generating section 130 may further include another expected value generating circuit that outputs expected values ​​of signal values ​​to be included in such fields. The expected value generating section 130 may generate expected value signal sequences from a pseudo-random signal generator for fields in the received signal sequence that include the pseudo-random signal sequence, and may generate expected value signal sequences from another expected value generating circuit for other fields in the received signal sequence.

[0034] The pseudo-random signal generator in the expected value generating section 130 and the pseudo-random signal generator 30 may be designed or configured to use the same number of stages and the same feedback circuit. The test apparatus 100 may be able to change or switch the number of stages of the pseudo-random signal generator provided in the expected value generating section 130 and the configuration of the feedback circuit so as to be able to support testing of various types of DUTs 10.

[0035] The setting unit 120 includes a selector 210 that switches between supplying the output of the feedback circuit of the pseudorandom signal generator or the received signal received by the receiving unit 110 to the first-stage D-FF in the pseudorandom signal generator in the expected value generating unit 130. The setting unit 120 according to this embodiment switches between supplying the output of the feedback circuit or the received signal to the first-stage D-FF in response to a setting instruction signal from the control unit 170. The setting unit 120 can set a random number seed for the pseudorandom signal sequence in the pseudorandom signal generator in the expected value generating unit 130 by supplying the pseudorandom signal sequence in the received signal sequence to the number of stages of the D-FF. Thereafter, the setting unit 120 supplies the output of the feedback circuit of the expected value generating unit 130 to the first-stage D-FF, allowing the expected value generating unit 130 to output a pseudorandom signal sequence using the set random number seed as an initial value.

[0036] According to the expected value generating unit 130 described above, the feedback circuit generates a pseudo-random value as the signal value of the next 1 bit from the signal values ​​of the most recent N bits stored in the shift register in the pseudo-random signal sequence, and feeds this value back to the first-stage D-FF. Here, if the feedback circuit is implemented by combining exclusive ORs (XORs) as illustrated in the figure, 0 XOR 0 = 0, so if all of B[N-1:0] are 0, a signal value of 0 is fed back to the first-stage D-FF, causing the pseudo-random signal generator to always output 0. Therefore, when all bits in the shift register are "0," such a pseudo-random signal generator is in a prohibited state, in which it does not generate a random signal sequence. Depending on the configuration of the feedback circuit in the expected value generating unit 130, a prohibited state may also occur when all bits in the shift register are "1."

[0037] 3 shows an example of the configuration of the detecting unit 150 according to this embodiment. The detecting unit 150 detects whether the pseudo-random signal generator 30 that generated the pseudo-random signal sequence in the received signal sequence was in a prohibited state. The detecting unit 150 according to this embodiment detects the prohibited state when the ratio of predetermined signal values ​​in the pseudo-random signal sequence in the received signal sequence falls outside a reference range.

[0038] In this embodiment, the pseudo-random signal generator 30 and the pseudo-random signal generator in the expected value generating unit 130 enter a prohibited state when the bit values ​​of all bits included in the shift register (i.e., all bit values ​​from B[N-1] to B[0]) are 0, and output a signal sequence whose signal value is always 0. In contrast, if the pseudo-random signal sequence in the received signal sequence is appropriate, the proportion of signal values ​​1, which are signal values ​​that are not generated in the prohibited state, is approximately 50%. Therefore, the detecting unit 150 may detect the prohibited state when the proportion of signal values ​​1 in the pseudo-random signal sequence in the received signal sequence is, for example, less than 40% (i.e., does not satisfy the reference range of 40% or more), or when the proportion of signal values ​​0, which are always generated in the prohibited state, exceeds 60% (i.e., does not satisfy the reference range of 60% or less).

[0039] The detection unit 150 according to this embodiment includes a counter 310, a counter 320, and a prohibition state determination unit 330. The counter 310 is connected to the receiving unit 110. The counter 310 receives a received signal and a clock signal with a cycle corresponding to each signal value of the received signal, and counts the number of predetermined signal values ​​(e.g., "1") included in the received signal. The counter 320 receives the clock signal and counts the number of clocks. The counters 310 and 320 may receive a measurement enable signal from the control unit 170, another trigger circuit, or the like, instructing them to enable measurement during a period (also referred to as a "measurement period") during which at least a portion of a pseudorandom signal sequence is included in the received signal sequence, and may perform a counting operation during the measurement period. Furthermore, the counters 310 and 320 may be initialized to a count value of 0 or the like before starting measurement.

[0040] The inhibit state determination unit 330 is connected to the counter 310 and the counter 320. The inhibit state determination unit 330 calculates the ratio of predetermined signal values ​​in the pseudo-random signal sequence in the received signal sequence based on the number of predetermined signal values ​​included in the received signal sequence counted by the counter 310 during the measurement period and the total number of cycles (total number of clocks) during the measurement period counted by the counter 320. In the example shown in the figure, the inhibit state determination unit 330 calculates the ratio of predetermined signal values ​​(e.g., 1) by dividing the count number of the counter 310 by the count number of the counter 320. The inhibit state determination unit 330 determines whether the calculated ratio is outside a reference range (e.g., less than 40%). If the calculated ratio is outside the reference range, the inhibit state determination unit 330 outputs a detection result indicating a inhibit state.

[0041] The detecting unit 150 described above can use the received signal sequence to detect whether the pseudo-random signal generator 30, which generated the pseudo-random signal sequence included in the received signal sequence, was in a disabled state. The pseudo-random signal generator in the expected value generating unit 130 has the same circuit configuration as the pseudo-random signal generator 30, and generates the same pseudo-random signal sequence as the pseudo-random signal generator 30 by setting a random number seed using at least a portion of the pseudo-random signal sequence included in the received signal sequence. Therefore, instead of or in addition to detecting whether the pseudo-random signal generator 30, which generated the pseudo-random signal sequence included in the received signal sequence, was in a disabled state, the detecting unit 150 may detect whether the pseudo-random signal generator in the expected value generating unit 130, which generated the pseudo-random signal sequence included in the expected value signal sequence, was in a disabled state. For example, the counter 310 in the detecting unit 150 may count the number of times the expected value signal output by the expected value generating unit 130 was a predetermined signal value, instead of counting the number of times the received signal had a predetermined signal value.

[0042] The detection unit 150 may be realized by a hardware circuit or by executing a program on various computers. The detection unit 150 can be realized in a variety of ways other than the configuration shown in this figure.

[0043] For example, instead of counting a signal value (e.g., signal value 1) that is not generated in the prohibited state as the predetermined signal value, counter 310 may count a signal value (e.g., signal value 0) that is always generated in the prohibited state. Detection unit 150 may have a counter that counts signal value 1 that is not generated in the prohibited state and a counter that counts signal value 0 that is always generated in the prohibited state. Detection unit 150 does not need to have counter 320 if the number of cycles in the measurement period is known in advance.

[0044] The test apparatus 100 may also capture the received signal sequence using a capture circuit and store it in a capture memory or the like provided within the test apparatus 100 or external to the test apparatus 100. In this case, the detection section 150 may read out the received signal sequence stored in the capture memory through program processing by a computer and calculate a predetermined ratio of signal values.

[0045] The detection section 150 may be realized as a prohibition state determination circuit added to the pseudorandom signal generator in the expected value generation section 130. Such a prohibition state determination circuit may detect a prohibition state when all bits of a shift register included in the pseudorandom signal generator in the expected value generation section 130 are 0.

[0046] FIG. 4 shows an example of the reference range according to this embodiment. In a pseudorandom signal generator in which the state in which all bits of the shift register are 0 is a prohibited state, the ratio of signal values ​​of 1 can vary depending on the number of bits in the shift register. For example, if the shift register has two bits, there are four possible values ​​for the shift register B[1:0]: 0b00, 0b01, 0b10, and 0b11. Note that "0b" indicates that the following value is expressed in binary notation. Here, since B[1:0] = 0b00 is a prohibited state, a two-bit pseudorandom signal generator can go through three states (2) of 0b01, 0b10, and 0b11 during one cycle of its internal state. ２ A random signal value is generated for each of the prohibited states (states 1-1). The number of times such a signal value will be 1 (a signal value that is not generated in the prohibited state) is 2 ２ / 2 = 2 times. Therefore, the rate at which a 2-bit pseudorandom signal generator generates a signal 1 is 66.7%.

[0047] In the case of an N-bit pseudorandom signal generator, the inhibit state is excluded (2 Ｎ -1), a random signal value is generated for each of the states, and 2 of them have a signal value of 1. Ｎ Therefore, the ratio of signal value 1 contained in the pseudo-random signal sequence generated by the N-bit pseudo-random signal generator is (2 Ｎ / 2) / (2 Ｎ -1).

[0048] If the pseudorandom signal generator 30 is an N-bit pseudorandom signal generator, the pseudorandom signal sequence is 2 Ｎ -1 bit goes around, and then the same 2 Ｎ The pattern is a repeating sequence of one loop of -1 bits. The expected value generator 130 uses the first or middle N bits of the received pseudo-random signal sequence as a random number seed to generate an expected value of a pseudo-random signal received thereafter. In this case, the pseudo-random signal sequence included in the received signal sequence and the pseudo-random signal sequence included in the expected value signal sequence may be longer than N bits in length.

[0049] The pseudorandom signal sequence does not necessarily have to be the number of bits that the internal state of the pseudorandom signal generator 30 completes (i.e., (2 Ｎ The length of the pseudo-random signal generator 30 does not have to be longer than 1 (-1) bits. In this case, the detecting section 150 receives a portion of the pseudo-random signal sequence and detects whether the pseudo-random signal generator 30 was in a prohibited state. The proportion of signal values ​​of 1 within a portion of the pseudo-random signal sequence may deviate to some extent from the proportion of signal values ​​of 1 throughout the entire pseudo-random signal sequence. Furthermore, depending on the structure of the test apparatus 100, it may not be possible to accurately trigger the start and end of the measurement period of the detecting section 150 during a period in which the pseudo-random signal sequence is included in the received signal sequence. In this case, the detecting section 150 may receive a signal value in a field other than the pseudo-random signal sequence in the received signal sequence at the beginning or end of the measurement period.

[0050] Therefore, the detection unit 150 may determine that the pseudo-random signal generator is in a prohibited state if, during a measurement period in a pseudo-random signal sequence generated by the N-bit pseudo-random signal generator, the ratio of a predetermined signal value (e.g., signal value 1) falls outside a reference range that has a margin of ±10% or the like with respect to the ratio of a predetermined signal value (e.g., signal value 1) included in one loop of the pseudo-random signal sequence. When the prohibited state is a state in which all bits of the shift register are 0, the lower limit of the reference range that the ratio of signal value 1 must satisfy may be a value greater than 0%, and may be (½ Ｎ This allows the detection unit 150 to properly detect whether the pseudo-random signal generator is in a prohibited state even when the received signal sequence includes a pseudo-random signal sequence having a length less than one loop, or when the measurement period of the detection unit 150 is slightly off.

[0051] Since the ratio of signal values ​​1 changes when the number of bits of the pseudorandom signal generator changes, the detection section 150 may change the reference range depending on the number of bits of the shift register of the pseudorandom signal generator 30 that generated the pseudorandom signal sequence in the received signal sequence. For example, before executing a test, the control section 170 may set the number of bits of the shift register in the expected value generation section 130 to match the number of bits of the pseudorandom signal generator 30 in the DUT 10 to be tested, and set the reference range in the detection section 150 depending on the number of bits of the pseudorandom signal generator 30. As an example, as shown in this figure, the detection section 150 may use a reference range that adds a positive or negative margin (e.g., a margin of ±10%) to the ratio of a predetermined signal value included in one round of the pseudorandom signal sequence. That is, for example, in the example shown in this figure, when an N-bit pseudorandom signal generator is used, the detection section 150 may change the reference range depending on the number of bits of the shift register of the pseudorandom signal generator 30 (2 Ｎ / 2) / (2 Ｎ -1) A reference range of ±10% may be used.

[0052] Note that the N-bit pseudorandom signal generator may have a maximum length of 2 ＮIt is possible to generate a pseudo-random signal sequence that loops around with fewer bits than -1. However, the feedback circuit of the pseudo-random signal generator is usually determined so that the pseudo-random signal sequence loops around at the maximum length. Therefore, the example in this figure shows a case where the pseudo-random signal generator 30 generates a pseudo-random signal sequence that loops around at the maximum length. Note that the feedback circuit of the pseudo-random signal generator 30 is configured as follows: Ｎ If it is possible to select a circuit that generates a pseudo-random signal sequence that completes a cycle with fewer bits than -1, the reference range shown in Figure 4 may be determined based on the proportion of signal values ​​of 1 in such a pseudo-random signal sequence.

[0053] When the detection unit 150 counts signal values ​​that are always generated in the prohibited state (for example, a signal value of 0), the upper limit of the reference range may be a value smaller than 100%. For example, when a 4-bit pseudorandom signal generator is used, the detection unit 150 may determine that the ratio of signal values ​​of 0 is within the reference range when it is 37.9% (100% - 63.1%) or less.

[0054] The detection unit 150 may change the reference range according to the number of bits when the number of bits in the shift register is equal to or less than a threshold, and may fix the reference range when the number of bits in the shift register exceeds the threshold. For example, the detection unit 150 may set the reference range according to the number of bits as shown in this figure when the number of bits in the shift register is four or less, and may set the reference range to a fixed range such as 40% to 60% when the number of bits in the shift register exceeds four.

[0055] When a state in which all bits of the shift register are 0 is a prohibited state, the detection unit 150 does not need to limit the upper limit of the reference range in which the proportion of signal value 1 should be included. For example, when the shift register has 4 bits, the detection unit 150 may set the reference range in which the proportion of signal value 1 should be included to 43.3% or more (100% or less). Similarly, when a state in which all bits of the shift register are 1 is a prohibited state, the detection unit 150 does not need to limit the upper limit of the reference range in which the proportion of signal value 0 should be included.

[0056] 5 shows a test flow performed by the test apparatus 100 according to this embodiment. Prior to execution of this test flow, the test apparatus 100 connects the DUT 10 to be tested and controls the DUT 10 to output an output signal sequence including a pseudo-random signal sequence.

[0057] In step S500, the receiving unit 110 begins receiving a pseudo-random signal sequence included in the received signal sequence. In S510, the setting unit 120 uses a portion of the received pseudo-random signal sequence (such as the leading portion or a portion close to the leading portion) to set a random number seed for the pseudo-random signal sequence in the pseudo-random signal generator in the expected value generating unit 130. This causes the expected value generating unit 130 to begin outputting an expected value signal sequence including the pseudo-random signal sequence. In S520, the counters 310 and 320 in the detecting unit 150 begin counting predetermined signal values ​​in the pseudo-random signal sequence included in the received signal sequence and the number of clocks during the measurement period.

[0058] In S530, the comparing section 140 compares the received signal sequence with the expected signal sequence. In this comparison, the comparing section 140 compares the pseudo-random signal sequence in the received signal sequence with the pseudo-random signal sequence in the expected signal sequence. If the comparison results in a mismatch between the received signal sequence and the expected signal sequence (YES in S540), the result determining section 160 determines in S580 that the test is abnormal. Depending on the test specifications, the result determining section 160 may determine that the test is abnormal by a condition such as a complete mismatch between the received signal sequence and the expected signal sequence, or the number or ratio of mismatches between the received signal sequence and the expected signal sequence exceeding a threshold. Such test abnormalities may occur due to a defect in the DUT 10, a poor connection between the DUT 10 and the test apparatus 100, a malfunction of the test apparatus 100, etc. If the test apparatus 100 is normal and the connection between the DUT 10 and the test apparatus 100 is considered normal, the result judging section 160 may judge that the DUT 10 is abnormal.

[0059] In S550, the detecting unit 150 detects whether the pseudo-random signal generator 30 that generated the pseudo-random signal sequence in the received signal sequence was in a prohibited state. The detecting unit 150 according to this embodiment detects the prohibited state when the ratio of the predetermined signal values ​​in the pseudo-random signal sequence in the received signal sequence falls outside the reference range (S560: YES), and proceeds to S580. In S580, the result determining unit 160 determines that the test was abnormal, as described above.

[0060] If the received signal sequence and the expected signal sequence match and the pseudo-random signal generator 30 is not in a prohibited state (i.e., if the ratio of the predetermined signal values ​​in the pseudo-random signal sequence is within the reference range), the result determining section 160 determines in S570 that the test was normal. In this case, the result determining section 160 determines that the DUT 10 was normal as a result of the test.

[0061] According to the test apparatus 100 described above, the detecting section 150 can detect whether the pseudo-random signal generator 30 or the pseudo-random signal generator in the expected value generating section 130 is in a disabled state. As a result, even if the comparing section 140 determines that the received signal sequence and the expected signal sequence match, the test apparatus 100 can determine whether there is an abnormality in the DUT 10 itself, an abnormality in the connection between the DUT 10 and the test apparatus 100, or another test abnormality in response to the detection of the disabled state of the pseudo-random signal generator.

[0062] Furthermore, the detecting section 150 according to this embodiment can input a received signal sequence or an expected value signal sequence to determine whether the pseudo-random signal generator is in a disabled state. Therefore, the detecting section 150 can be implemented by inputting the received signal sequence or the expected value signal sequence to a circuit or the like provided separately from the IC, LSI, or FPGA including the expected value generating section 130. Furthermore, if the test apparatus 100 includes a capture circuit that captures the received signal sequence, the detecting section 150 can analyze the captured received signal sequence after completing the test operation between the DUT 10 and the test apparatus 100 to determine whether the pseudo-random signal generator is in a disabled state. Such a detecting section 150 can also be implemented by a computer or the like separate from the test apparatus main body in which the receiving section 110, setting section 120, expected value generating section 130, and comparing section 140 of the test apparatus 100 are provided. A test system including a test device main body having a receiving section 110, a setting section 120, an expected value generating section 130, and a comparing section 140, and a detection section 150 (and a result judgment section 160, if necessary) realized by a computer or the like connected to such a test device main body via a network or the like, can be considered as a test device as a whole.

[0063] Various embodiments of the present invention may be described with reference to flowcharts and block diagrams, where the blocks may represent (1) stages of a process in which operations are performed or (2) sections of apparatus responsible for performing the operations. Particular stages and sections may be implemented by dedicated circuitry, programmable circuitry provided with computer-readable instructions stored on a computer-readable medium, and / or a processor provided with computer-readable instructions stored on a computer-readable medium. Dedicated circuitry may include digital and / or analog hardware circuitry, and may include integrated circuits (ICs) and / or discrete circuits. Programmable circuitry may include reconfigurable hardware circuitry including logical AND, OR, XOR, NAND, NOR, and other logic operations, flip-flops, registers, memory elements such as field programmable gate arrays (FPGAs), programmable logic arrays (PLAs), and the like.

[0064] A computer-readable medium may include any tangible device capable of storing instructions that are executed by an appropriate device, such that the computer-readable medium having instructions stored thereon comprises an article of manufacture containing instructions that can be executed to create means for performing the operations specified in the flowcharts or block diagrams. Examples of computer-readable media may include electronic, magnetic, optical, electromagnetic, and semiconductor storage media. More specific examples of computer-readable media may include floppy disks, diskettes, hard disks, random access memories (RAMs), read-only memories (ROMs), erasable programmable read-only memories (EPROMs or flash memories), electrically erasable programmable read-only memories (EEPROMs), static random access memories (SRAMs), compact disc read-only memories (CD-ROMs), digital versatile discs (DVDs), Blu-ray discs, memory sticks, integrated circuit cards, and the like.

[0065] The computer readable instructions may include either assembler instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or source or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk®, JAVA®, C++, etc., and conventional procedural programming languages ​​such as the “C” programming language or similar programming languages.

[0066] The computer-readable instructions may be provided to a processor or programmable circuitry of a programmable data processing apparatus, such as a general-purpose computer, special-purpose computer, or other computer, either locally or over a local area network (LAN), a wide area network (WAN) such as the Internet, etc., which executes the computer-readable instructions to create means for performing the operations specified in the flowcharts or block diagrams. Examples of processors include computer processors, processing units, microprocessors, digital signal processors, controllers, microcontrollers, etc.

[0067] 6 illustrates an example of a computer 2200 in which aspects of the present invention may be embodied, in whole or in part. Programs installed on the computer 2200 may cause the computer 2200 to function as or perform operations associated with an apparatus or one or more sections of the apparatus according to embodiments of the present invention, and / or to perform a process or steps of a process according to embodiments of the present invention. Such programs may be executed by the CPU 2212 to cause the computer 2200 to perform specific operations associated with some or all of the blocks in the flowcharts and block diagrams described herein.

[0068] A computer 2200 according to this embodiment includes a CPU 2212, a RAM 2214, a graphics controller 2216, and a display device 2218, which are interconnected by a host controller 2210. The computer 2200 also includes input / output units such as a communication interface 2222, a hard disk drive 2224, a DVD-ROM drive 2226, and an IC card drive, which are connected to the host controller 2210 via an input / output controller 2220. The computer also includes legacy input / output units such as a ROM 2230 and a keyboard 2242, which are connected to the input / output controller 2220 via an input / output chip 2240.

[0069] The CPU 2212 operates according to programs stored in the ROM 2230 and RAM 2214, thereby controlling each unit. The graphics controller 2216 acquires image data generated by the CPU 2212 into a frame buffer or the like provided in the RAM 2214 or into the graphics controller 2216 itself, and causes the image data to be displayed on the display device 2218.

[0070] The communication interface 2222 communicates with other electronic devices via a network. The hard disk drive 2224 stores programs and data used by the CPU 2212 in the computer 2200. The DVD-ROM drive 2226 reads programs or data from the DVD-ROM 2201 and provides the programs or data to the hard disk drive 2224 via the RAM 2214. The IC card drive reads programs and data from an IC card and / or writes programs and data to an IC card.

[0071] ROM 2230 stores therein a boot program or the like that is executed by computer 2200 upon activation, and / or programs that depend on the hardware of computer 2200. I / O chip 2240 may also connect various I / O units to I / O controller 2220 via parallel ports, serial ports, keyboard ports, mouse ports, etc.

[0072] The programs are provided by a computer-readable medium such as a DVD-ROM 2201 or an IC card. The programs are read from the computer-readable medium, installed in the hard disk drive 2224, RAM 2214, or ROM 2230, which are also examples of computer-readable media, and executed by the CPU 2212. Information processing described in these programs is read by the computer 2200, and brings about cooperation between the programs and the various types of hardware resources described above. An apparatus or method may be configured by implementing information manipulation or processing in accordance with the use of the computer 2200.

[0073] For example, when communication is performed between computer 2200 and an external device, CPU 2212 may execute a communication program loaded in RAM 2214 and instruct communication interface 2222 to perform communication processing based on the processing described in the communication program. Under the control of CPU 2212, communication interface 2222 reads transmission data stored in a transmission buffer processing area provided in RAM 2214, hard disk drive 2224, DVD-ROM 2201, or a recording medium such as an IC card, and transmits the read transmission data to the network, or writes received data received from the network to a reception buffer processing area or the like provided on the recording medium.

[0074] Furthermore, the CPU 2212 may cause all or a necessary portion of a file or database stored on an external recording medium such as the hard disk drive 2224, the DVD-ROM drive 2226 (DVD-ROM 2201), an IC card, etc. to be read into the RAM 2214, and may perform various types of processing on the data on the RAM 2214. The CPU 2212 then writes back the processed data to the external recording medium.

[0075] Various types of information, such as various types of programs, data, tables, and databases, may be stored on the recording medium and may undergo information processing. The CPU 2212 may perform various types of processing on data read from the RAM 2214, including various types of operations, information processing, conditional judgment, conditional branching, unconditional branching, information search / replacement, etc., as described throughout this disclosure and specified by the instruction sequences of the programs, and write the results back to the RAM 2214. The CPU 2212 may also search for information in a file, database, etc. on the recording medium. For example, if multiple entries each having an attribute value of a first attribute associated with an attribute value of a second attribute are stored on the recording medium, the CPU 2212 may search for an entry that matches a condition specified by the attribute value of the first attribute from among the multiple entries, read the attribute value of the second attribute stored in the entry, and thereby obtain the attribute value of the second attribute associated with the first attribute that satisfies a predetermined condition.

[0076] The above-described programs or software modules may be stored in a computer-readable medium on or near the computer 2200. A recording medium such as a hard disk or RAM provided in a server system connected to a dedicated communication network or the Internet can also be used as a computer-readable medium, thereby providing the programs to the computer 2200 via the network.

[0077] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0078] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order.

[0079] 10 DUT 20 Transmitting section 30 Pseudo-random signal generator 100 Test equipment 110 Receiving section 120 Setting section 130 Expected value generating section 140 Comparing section 150 Detecting section 160 Result determining section 170 Control section 210 Selector 310 Counter 320 Counter 330 Inhibit state determining section 2200 Computer 2201 DVD-ROM 2210 Host controller 2212 CPU 2214 RAM 2216 Graphics controller 2218 Display device 2220 Input / output controller 2222 Communication interface 2224 Hard disk drive 2226 DVD-ROM drive 2230 ROM 2240 Input / output chip 2242 Keyboard

Claims

1. A test apparatus comprising: a receiving section that receives a received signal sequence including a pseudo-random signal sequence output by a device under test; and a detecting section that detects whether a pseudo-random signal generator that generated the pseudo-random signal sequence in the received signal sequence was in a disabled state.

2. The test device according to claim 1, wherein the detection section detects the prohibited state when a ratio of a predetermined signal value in a pseudo-random signal sequence within the received signal sequence falls outside a reference range.

3. The test apparatus according to claim 2, further comprising: an expected value generating section that generates an expected signal sequence including a pseudo-random signal sequence identical to the pseudo-random signal sequence to be output by the device under test; and a comparing section that compares the pseudo-random signal sequence in the received signal sequence with the pseudo-random signal sequence in the expected signal sequence.

4. The test device according to claim 3, further comprising a result determining section that determines a test result based on the comparison result by the comparison section and the detection result by the detection section.

5. The test apparatus according to claim 3, further comprising a setting section that uses a portion of the pseudo-random signal sequence in the received signal sequence to set a random number seed for the pseudo-random signal sequence in the expected value signal sequence generated by the expected value generating section.

6. The test device according to claim 2, wherein the detection section changes the reference range in accordance with the number of bits in a shift register of a pseudorandom signal generator that generates the pseudorandom signal sequence in the received signal sequence.

7. A test apparatus comprising: a receiving section that receives a received signal sequence including a pseudo-random signal sequence output by a device under test; an expected value generating section that generates an expected signal sequence including a pseudo-random signal sequence identical to the pseudo-random signal sequence that should be output by the device under test; and a detecting section that detects whether a pseudo-random signal generator that generated a pseudo-random signal sequence included in at least one of the expected signal sequence or the received signal sequence is in a prohibited state.

8. A testing method comprising: receiving a received signal sequence including a pseudo-random signal sequence output by a device under test; and detecting whether a pseudo-random signal generator that generated the pseudo-random signal sequence in the received signal sequence was in a disabled state.

9. A testing method comprising: receiving a received signal sequence including a pseudo-random signal sequence output by a device under test; generating an expected signal sequence including a pseudo-random signal sequence identical to the pseudo-random signal sequence to be output by the device under test; and detecting whether a pseudo-random signal generator that generated the pseudo-random signal sequence included in at least one of the expected signal sequence or the received signal sequence was in a prohibited state.

10. A program that is executed by a computer and causes the computer to function as a detection unit that detects whether a pseudo-random signal generator that generates a pseudo-random signal sequence included in at least one of a received signal sequence including a pseudo-random signal sequence output by a device under test, or an expected signal sequence including the same pseudo-random signal sequence as the pseudo-random signal sequence to be output by the device under test, is in a prohibited state.

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